1 /*
2  * Copyright 2007-11 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: Dave Airlie
24  *          Alex Deucher
25  */
26 
27 #include <linux/backlight.h>
28 #include <linux/dmi.h>
29 #include <linux/pci.h>
30 
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/drm_file.h>
33 #include <drm/drm_modeset_helper_vtables.h>
34 #include <drm/radeon_drm.h>
35 
36 #include <acpi/video.h>
37 
38 #include "atom.h"
39 #include "radeon_atombios.h"
40 #include "radeon.h"
41 #include "radeon_asic.h"
42 #include "radeon_audio.h"
43 
44 extern int atom_debug;
45 
46 static u8
radeon_atom_get_backlight_level_from_reg(struct radeon_device * rdev)47 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
48 {
49 	u8 backlight_level;
50 	u32 bios_2_scratch;
51 
52 	if (rdev->family >= CHIP_R600)
53 		bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
54 	else
55 		bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
56 
57 	backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
58 			   ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
59 
60 	return backlight_level;
61 }
62 
63 static void
radeon_atom_set_backlight_level_to_reg(struct radeon_device * rdev,u8 backlight_level)64 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
65 				       u8 backlight_level)
66 {
67 	u32 bios_2_scratch;
68 
69 	if (rdev->family >= CHIP_R600)
70 		bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
71 	else
72 		bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
73 
74 	bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
75 	bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
76 			   ATOM_S2_CURRENT_BL_LEVEL_MASK);
77 
78 	if (rdev->family >= CHIP_R600)
79 		WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
80 	else
81 		WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
82 }
83 
84 u8
atombios_get_backlight_level(struct radeon_encoder * radeon_encoder)85 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
86 {
87 	struct drm_device *dev = radeon_encoder->base.dev;
88 	struct radeon_device *rdev = dev->dev_private;
89 
90 	if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
91 		return 0;
92 
93 	return radeon_atom_get_backlight_level_from_reg(rdev);
94 }
95 
96 void
atombios_set_backlight_level(struct radeon_encoder * radeon_encoder,u8 level)97 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
98 {
99 	struct drm_encoder *encoder = &radeon_encoder->base;
100 	struct drm_device *dev = radeon_encoder->base.dev;
101 	struct radeon_device *rdev = dev->dev_private;
102 	struct radeon_encoder_atom_dig *dig;
103 	DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
104 	int index;
105 
106 	if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
107 		return;
108 
109 	if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
110 	    radeon_encoder->enc_priv) {
111 		dig = radeon_encoder->enc_priv;
112 		dig->backlight_level = level;
113 		radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
114 
115 		switch (radeon_encoder->encoder_id) {
116 		case ENCODER_OBJECT_ID_INTERNAL_LVDS:
117 		case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
118 			index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
119 			if (dig->backlight_level == 0) {
120 				args.ucAction = ATOM_LCD_BLOFF;
121 				atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
122 			} else {
123 				args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
124 				atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
125 				args.ucAction = ATOM_LCD_BLON;
126 				atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
127 			}
128 			break;
129 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
130 		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
131 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
132 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
133 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
134 			if (dig->backlight_level == 0)
135 				atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
136 			else {
137 				atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
138 				atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
139 			}
140 			break;
141 		default:
142 			break;
143 		}
144 	}
145 }
146 
radeon_atom_bl_level(struct backlight_device * bd)147 static u8 radeon_atom_bl_level(struct backlight_device *bd)
148 {
149 	u8 level;
150 
151 	/* Convert brightness to hardware level */
152 	if (bd->props.brightness < 0)
153 		level = 0;
154 	else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
155 		level = RADEON_MAX_BL_LEVEL;
156 	else
157 		level = bd->props.brightness;
158 
159 	return level;
160 }
161 
radeon_atom_backlight_update_status(struct backlight_device * bd)162 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
163 {
164 	struct radeon_backlight_privdata *pdata = bl_get_data(bd);
165 	struct radeon_encoder *radeon_encoder = pdata->encoder;
166 
167 	atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
168 
169 	return 0;
170 }
171 
radeon_atom_backlight_get_brightness(struct backlight_device * bd)172 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
173 {
174 	struct radeon_backlight_privdata *pdata = bl_get_data(bd);
175 	struct radeon_encoder *radeon_encoder = pdata->encoder;
176 	struct drm_device *dev = radeon_encoder->base.dev;
177 	struct radeon_device *rdev = dev->dev_private;
178 
179 	return radeon_atom_get_backlight_level_from_reg(rdev);
180 }
181 
182 static const struct backlight_ops radeon_atom_backlight_ops = {
183 	.get_brightness = radeon_atom_backlight_get_brightness,
184 	.update_status	= radeon_atom_backlight_update_status,
185 };
186 
radeon_atom_backlight_init(struct radeon_encoder * radeon_encoder,struct drm_connector * drm_connector)187 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
188 				struct drm_connector *drm_connector)
189 {
190 	struct drm_device *dev = radeon_encoder->base.dev;
191 	struct radeon_device *rdev = dev->dev_private;
192 	struct backlight_device *bd;
193 	struct backlight_properties props;
194 	struct radeon_backlight_privdata *pdata;
195 	struct radeon_encoder_atom_dig *dig;
196 	char bl_name[16];
197 
198 	/* Mac laptops with multiple GPUs use the gmux driver for backlight
199 	 * so don't register a backlight device
200 	 */
201 	if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
202 	    (rdev->pdev->device == 0x6741) &&
203 	    !dmi_match(DMI_PRODUCT_NAME, "iMac12,1"))
204 		return;
205 
206 	if (!radeon_encoder->enc_priv)
207 		return;
208 
209 	if (!rdev->is_atom_bios)
210 		return;
211 
212 	if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
213 		return;
214 
215 	if (!acpi_video_backlight_use_native()) {
216 		drm_info(dev, "Skipping radeon atom DIG backlight registration\n");
217 		return;
218 	}
219 
220 	pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
221 	if (!pdata) {
222 		DRM_ERROR("Memory allocation failed\n");
223 		goto error;
224 	}
225 
226 	memset(&props, 0, sizeof(props));
227 	props.max_brightness = RADEON_MAX_BL_LEVEL;
228 	props.type = BACKLIGHT_RAW;
229 	snprintf(bl_name, sizeof(bl_name),
230 		 "radeon_bl%d", dev->primary->index);
231 	bd = backlight_device_register(bl_name, drm_connector->kdev,
232 				       pdata, &radeon_atom_backlight_ops, &props);
233 	if (IS_ERR(bd)) {
234 		DRM_ERROR("Backlight registration failed\n");
235 		goto error;
236 	}
237 
238 	pdata->encoder = radeon_encoder;
239 
240 	dig = radeon_encoder->enc_priv;
241 	dig->bl_dev = bd;
242 
243 	bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
244 	/* Set a reasonable default here if the level is 0 otherwise
245 	 * fbdev will attempt to turn the backlight on after console
246 	 * unblanking and it will try and restore 0 which turns the backlight
247 	 * off again.
248 	 */
249 	if (bd->props.brightness == 0)
250 		bd->props.brightness = RADEON_MAX_BL_LEVEL;
251 	bd->props.power = FB_BLANK_UNBLANK;
252 	backlight_update_status(bd);
253 
254 	DRM_INFO("radeon atom DIG backlight initialized\n");
255 	rdev->mode_info.bl_encoder = radeon_encoder;
256 
257 	return;
258 
259 error:
260 	kfree(pdata);
261 	return;
262 }
263 
radeon_atom_backlight_exit(struct radeon_encoder * radeon_encoder)264 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
265 {
266 	struct drm_device *dev = radeon_encoder->base.dev;
267 	struct radeon_device *rdev = dev->dev_private;
268 	struct backlight_device *bd = NULL;
269 	struct radeon_encoder_atom_dig *dig;
270 
271 	if (!radeon_encoder->enc_priv)
272 		return;
273 
274 	if (!rdev->is_atom_bios)
275 		return;
276 
277 	if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
278 		return;
279 
280 	dig = radeon_encoder->enc_priv;
281 	bd = dig->bl_dev;
282 	dig->bl_dev = NULL;
283 
284 	if (bd) {
285 		struct radeon_legacy_backlight_privdata *pdata;
286 
287 		pdata = bl_get_data(bd);
288 		backlight_device_unregister(bd);
289 		kfree(pdata);
290 
291 		DRM_INFO("radeon atom LVDS backlight unloaded\n");
292 	}
293 }
294 
radeon_atom_mode_fixup(struct drm_encoder * encoder,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)295 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
296 				   const struct drm_display_mode *mode,
297 				   struct drm_display_mode *adjusted_mode)
298 {
299 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
300 	struct drm_device *dev = encoder->dev;
301 	struct radeon_device *rdev = dev->dev_private;
302 
303 	/* set the active encoder to connector routing */
304 	radeon_encoder_set_active_device(encoder);
305 	drm_mode_set_crtcinfo(adjusted_mode, 0);
306 
307 	/* hw bug */
308 	if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
309 	    && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
310 		adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
311 
312 	/* vertical FP must be at least 1 */
313 	if (mode->crtc_vsync_start == mode->crtc_vdisplay)
314 		adjusted_mode->crtc_vsync_start++;
315 
316 	/* get the native mode for scaling */
317 	if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
318 		radeon_panel_mode_fixup(encoder, adjusted_mode);
319 	} else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
320 		struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
321 		if (tv_dac) {
322 			if (tv_dac->tv_std == TV_STD_NTSC ||
323 			    tv_dac->tv_std == TV_STD_NTSC_J ||
324 			    tv_dac->tv_std == TV_STD_PAL_M)
325 				radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
326 			else
327 				radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
328 		}
329 	} else if (radeon_encoder->rmx_type != RMX_OFF) {
330 		radeon_panel_mode_fixup(encoder, adjusted_mode);
331 	}
332 
333 	if (ASIC_IS_DCE3(rdev) &&
334 	    ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
335 	     (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
336 		struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
337 		radeon_dp_set_link_config(connector, adjusted_mode);
338 	}
339 
340 	return true;
341 }
342 
343 static void
atombios_dac_setup(struct drm_encoder * encoder,int action)344 atombios_dac_setup(struct drm_encoder *encoder, int action)
345 {
346 	struct drm_device *dev = encoder->dev;
347 	struct radeon_device *rdev = dev->dev_private;
348 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
349 	DAC_ENCODER_CONTROL_PS_ALLOCATION args;
350 	int index = 0;
351 	struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
352 
353 	memset(&args, 0, sizeof(args));
354 
355 	switch (radeon_encoder->encoder_id) {
356 	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
357 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
358 		index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
359 		break;
360 	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
361 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
362 		index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
363 		break;
364 	}
365 
366 	args.ucAction = action;
367 
368 	if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
369 		args.ucDacStandard = ATOM_DAC1_PS2;
370 	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
371 		args.ucDacStandard = ATOM_DAC1_CV;
372 	else {
373 		switch (dac_info->tv_std) {
374 		case TV_STD_PAL:
375 		case TV_STD_PAL_M:
376 		case TV_STD_SCART_PAL:
377 		case TV_STD_SECAM:
378 		case TV_STD_PAL_CN:
379 			args.ucDacStandard = ATOM_DAC1_PAL;
380 			break;
381 		case TV_STD_NTSC:
382 		case TV_STD_NTSC_J:
383 		case TV_STD_PAL_60:
384 		default:
385 			args.ucDacStandard = ATOM_DAC1_NTSC;
386 			break;
387 		}
388 	}
389 	args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
390 
391 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
392 
393 }
394 
395 static void
atombios_tv_setup(struct drm_encoder * encoder,int action)396 atombios_tv_setup(struct drm_encoder *encoder, int action)
397 {
398 	struct drm_device *dev = encoder->dev;
399 	struct radeon_device *rdev = dev->dev_private;
400 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
401 	TV_ENCODER_CONTROL_PS_ALLOCATION args;
402 	int index = 0;
403 	struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
404 
405 	memset(&args, 0, sizeof(args));
406 
407 	index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
408 
409 	args.sTVEncoder.ucAction = action;
410 
411 	if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
412 		args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
413 	else {
414 		switch (dac_info->tv_std) {
415 		case TV_STD_NTSC:
416 			args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
417 			break;
418 		case TV_STD_PAL:
419 			args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
420 			break;
421 		case TV_STD_PAL_M:
422 			args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
423 			break;
424 		case TV_STD_PAL_60:
425 			args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
426 			break;
427 		case TV_STD_NTSC_J:
428 			args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
429 			break;
430 		case TV_STD_SCART_PAL:
431 			args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
432 			break;
433 		case TV_STD_SECAM:
434 			args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
435 			break;
436 		case TV_STD_PAL_CN:
437 			args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
438 			break;
439 		default:
440 			args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
441 			break;
442 		}
443 	}
444 
445 	args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
446 
447 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
448 
449 }
450 
radeon_atom_get_bpc(struct drm_encoder * encoder)451 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
452 {
453 	int bpc = 8;
454 
455 	if (encoder->crtc) {
456 		struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
457 		bpc = radeon_crtc->bpc;
458 	}
459 
460 	switch (bpc) {
461 	case 0:
462 		return PANEL_BPC_UNDEFINE;
463 	case 6:
464 		return PANEL_6BIT_PER_COLOR;
465 	case 8:
466 	default:
467 		return PANEL_8BIT_PER_COLOR;
468 	case 10:
469 		return PANEL_10BIT_PER_COLOR;
470 	case 12:
471 		return PANEL_12BIT_PER_COLOR;
472 	case 16:
473 		return PANEL_16BIT_PER_COLOR;
474 	}
475 }
476 
477 union dvo_encoder_control {
478 	ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
479 	DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
480 	DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
481 	DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
482 };
483 
484 void
atombios_dvo_setup(struct drm_encoder * encoder,int action)485 atombios_dvo_setup(struct drm_encoder *encoder, int action)
486 {
487 	struct drm_device *dev = encoder->dev;
488 	struct radeon_device *rdev = dev->dev_private;
489 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
490 	union dvo_encoder_control args;
491 	int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
492 	uint8_t frev, crev;
493 
494 	memset(&args, 0, sizeof(args));
495 
496 	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
497 		return;
498 
499 	/* some R4xx chips have the wrong frev */
500 	if (rdev->family <= CHIP_RV410)
501 		frev = 1;
502 
503 	switch (frev) {
504 	case 1:
505 		switch (crev) {
506 		case 1:
507 			/* R4xx, R5xx */
508 			args.ext_tmds.sXTmdsEncoder.ucEnable = action;
509 
510 			if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
511 				args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
512 
513 			args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
514 			break;
515 		case 2:
516 			/* RS600/690/740 */
517 			args.dvo.sDVOEncoder.ucAction = action;
518 			args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
519 			/* DFP1, CRT1, TV1 depending on the type of port */
520 			args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
521 
522 			if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
523 				args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
524 			break;
525 		case 3:
526 			/* R6xx */
527 			args.dvo_v3.ucAction = action;
528 			args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
529 			args.dvo_v3.ucDVOConfig = 0; /* XXX */
530 			break;
531 		case 4:
532 			/* DCE8 */
533 			args.dvo_v4.ucAction = action;
534 			args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
535 			args.dvo_v4.ucDVOConfig = 0; /* XXX */
536 			args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
537 			break;
538 		default:
539 			DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
540 			break;
541 		}
542 		break;
543 	default:
544 		DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
545 		break;
546 	}
547 
548 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
549 }
550 
551 union lvds_encoder_control {
552 	LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
553 	LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
554 };
555 
556 void
atombios_digital_setup(struct drm_encoder * encoder,int action)557 atombios_digital_setup(struct drm_encoder *encoder, int action)
558 {
559 	struct drm_device *dev = encoder->dev;
560 	struct radeon_device *rdev = dev->dev_private;
561 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
562 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
563 	union lvds_encoder_control args;
564 	int index = 0;
565 	int hdmi_detected = 0;
566 	uint8_t frev, crev;
567 
568 	if (!dig)
569 		return;
570 
571 	if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
572 		hdmi_detected = 1;
573 
574 	memset(&args, 0, sizeof(args));
575 
576 	switch (radeon_encoder->encoder_id) {
577 	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
578 		index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
579 		break;
580 	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
581 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
582 		index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
583 		break;
584 	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
585 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
586 			index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
587 		else
588 			index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
589 		break;
590 	}
591 
592 	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
593 		return;
594 
595 	switch (frev) {
596 	case 1:
597 	case 2:
598 		switch (crev) {
599 		case 1:
600 			args.v1.ucMisc = 0;
601 			args.v1.ucAction = action;
602 			if (hdmi_detected)
603 				args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
604 			args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
605 			if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
606 				if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
607 					args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
608 				if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
609 					args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
610 			} else {
611 				if (dig->linkb)
612 					args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
613 				if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
614 					args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
615 				/*if (pScrn->rgbBits == 8) */
616 				args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
617 			}
618 			break;
619 		case 2:
620 		case 3:
621 			args.v2.ucMisc = 0;
622 			args.v2.ucAction = action;
623 			if (crev == 3) {
624 				if (dig->coherent_mode)
625 					args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
626 			}
627 			if (hdmi_detected)
628 				args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
629 			args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
630 			args.v2.ucTruncate = 0;
631 			args.v2.ucSpatial = 0;
632 			args.v2.ucTemporal = 0;
633 			args.v2.ucFRC = 0;
634 			if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
635 				if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
636 					args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
637 				if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
638 					args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
639 					if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
640 						args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
641 				}
642 				if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
643 					args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
644 					if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
645 						args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
646 					if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
647 						args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
648 				}
649 			} else {
650 				if (dig->linkb)
651 					args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
652 				if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
653 					args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
654 			}
655 			break;
656 		default:
657 			DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
658 			break;
659 		}
660 		break;
661 	default:
662 		DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
663 		break;
664 	}
665 
666 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
667 }
668 
669 int
atombios_get_encoder_mode(struct drm_encoder * encoder)670 atombios_get_encoder_mode(struct drm_encoder *encoder)
671 {
672 	struct drm_device *dev = encoder->dev;
673 	struct radeon_device *rdev = dev->dev_private;
674 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
675 	struct drm_connector *connector;
676 	struct radeon_connector *radeon_connector;
677 	struct radeon_connector_atom_dig *dig_connector;
678 
679 	/* dp bridges are always DP */
680 	if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
681 		return ATOM_ENCODER_MODE_DP;
682 
683 	/* DVO is always DVO */
684 	if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
685 	    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
686 		return ATOM_ENCODER_MODE_DVO;
687 
688 	connector = radeon_get_connector_for_encoder(encoder);
689 	/* if we don't have an active device yet, just use one of
690 	 * the connectors tied to the encoder.
691 	 */
692 	if (!connector)
693 		connector = radeon_get_connector_for_encoder_init(encoder);
694 	radeon_connector = to_radeon_connector(connector);
695 
696 	switch (connector->connector_type) {
697 	case DRM_MODE_CONNECTOR_DVII:
698 	case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
699 		if (radeon_audio != 0) {
700 			if (radeon_connector->use_digital &&
701 			    (radeon_connector->audio == RADEON_AUDIO_ENABLE))
702 				return ATOM_ENCODER_MODE_HDMI;
703 			else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
704 				 (radeon_connector->audio == RADEON_AUDIO_AUTO))
705 				return ATOM_ENCODER_MODE_HDMI;
706 			else if (radeon_connector->use_digital)
707 				return ATOM_ENCODER_MODE_DVI;
708 			else
709 				return ATOM_ENCODER_MODE_CRT;
710 		} else if (radeon_connector->use_digital) {
711 			return ATOM_ENCODER_MODE_DVI;
712 		} else {
713 			return ATOM_ENCODER_MODE_CRT;
714 		}
715 		break;
716 	case DRM_MODE_CONNECTOR_DVID:
717 	case DRM_MODE_CONNECTOR_HDMIA:
718 	default:
719 		if (radeon_audio != 0) {
720 			if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
721 				return ATOM_ENCODER_MODE_HDMI;
722 			else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
723 				 (radeon_connector->audio == RADEON_AUDIO_AUTO))
724 				return ATOM_ENCODER_MODE_HDMI;
725 			else
726 				return ATOM_ENCODER_MODE_DVI;
727 		} else {
728 			return ATOM_ENCODER_MODE_DVI;
729 		}
730 		break;
731 	case DRM_MODE_CONNECTOR_LVDS:
732 		return ATOM_ENCODER_MODE_LVDS;
733 		break;
734 	case DRM_MODE_CONNECTOR_DisplayPort:
735 		dig_connector = radeon_connector->con_priv;
736 		if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
737 		    (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
738 			if (radeon_audio != 0 &&
739 			    drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
740 			    ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
741 				return ATOM_ENCODER_MODE_DP_AUDIO;
742 			return ATOM_ENCODER_MODE_DP;
743 		} else if (radeon_audio != 0) {
744 			if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
745 				return ATOM_ENCODER_MODE_HDMI;
746 			else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
747 				 (radeon_connector->audio == RADEON_AUDIO_AUTO))
748 				return ATOM_ENCODER_MODE_HDMI;
749 			else
750 				return ATOM_ENCODER_MODE_DVI;
751 		} else {
752 			return ATOM_ENCODER_MODE_DVI;
753 		}
754 		break;
755 	case DRM_MODE_CONNECTOR_eDP:
756 		if (radeon_audio != 0 &&
757 		    drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
758 		    ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
759 			return ATOM_ENCODER_MODE_DP_AUDIO;
760 		return ATOM_ENCODER_MODE_DP;
761 	case DRM_MODE_CONNECTOR_DVIA:
762 	case DRM_MODE_CONNECTOR_VGA:
763 		return ATOM_ENCODER_MODE_CRT;
764 		break;
765 	case DRM_MODE_CONNECTOR_Composite:
766 	case DRM_MODE_CONNECTOR_SVIDEO:
767 	case DRM_MODE_CONNECTOR_9PinDIN:
768 		/* fix me */
769 		return ATOM_ENCODER_MODE_TV;
770 		/*return ATOM_ENCODER_MODE_CV;*/
771 		break;
772 	}
773 }
774 
775 /*
776  * DIG Encoder/Transmitter Setup
777  *
778  * DCE 3.0/3.1
779  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
780  * Supports up to 3 digital outputs
781  * - 2 DIG encoder blocks.
782  * DIG1 can drive UNIPHY link A or link B
783  * DIG2 can drive UNIPHY link B or LVTMA
784  *
785  * DCE 3.2
786  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
787  * Supports up to 5 digital outputs
788  * - 2 DIG encoder blocks.
789  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
790  *
791  * DCE 4.0/5.0/6.0
792  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
793  * Supports up to 6 digital outputs
794  * - 6 DIG encoder blocks.
795  * - DIG to PHY mapping is hardcoded
796  * DIG1 drives UNIPHY0 link A, A+B
797  * DIG2 drives UNIPHY0 link B
798  * DIG3 drives UNIPHY1 link A, A+B
799  * DIG4 drives UNIPHY1 link B
800  * DIG5 drives UNIPHY2 link A, A+B
801  * DIG6 drives UNIPHY2 link B
802  *
803  * DCE 4.1
804  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
805  * Supports up to 6 digital outputs
806  * - 2 DIG encoder blocks.
807  * llano
808  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
809  * ontario
810  * DIG1 drives UNIPHY0/1/2 link A
811  * DIG2 drives UNIPHY0/1/2 link B
812  *
813  * Routing
814  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
815  * Examples:
816  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
817  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
818  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
819  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
820  */
821 
822 union dig_encoder_control {
823 	DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
824 	DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
825 	DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
826 	DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
827 };
828 
829 void
atombios_dig_encoder_setup2(struct drm_encoder * encoder,int action,int panel_mode,int enc_override)830 atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override)
831 {
832 	struct drm_device *dev = encoder->dev;
833 	struct radeon_device *rdev = dev->dev_private;
834 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
835 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
836 	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
837 	union dig_encoder_control args;
838 	int index = 0;
839 	uint8_t frev, crev;
840 	int dp_clock = 0;
841 	int dp_lane_count = 0;
842 	int hpd_id = RADEON_HPD_NONE;
843 
844 	if (connector) {
845 		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
846 		struct radeon_connector_atom_dig *dig_connector =
847 			radeon_connector->con_priv;
848 
849 		dp_clock = dig_connector->dp_clock;
850 		dp_lane_count = dig_connector->dp_lane_count;
851 		hpd_id = radeon_connector->hpd.hpd;
852 	}
853 
854 	/* no dig encoder assigned */
855 	if (dig->dig_encoder == -1)
856 		return;
857 
858 	memset(&args, 0, sizeof(args));
859 
860 	if (ASIC_IS_DCE4(rdev))
861 		index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
862 	else {
863 		if (dig->dig_encoder)
864 			index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
865 		else
866 			index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
867 	}
868 
869 	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
870 		return;
871 
872 	switch (frev) {
873 	case 1:
874 		switch (crev) {
875 		case 1:
876 			args.v1.ucAction = action;
877 			args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
878 			if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
879 				args.v3.ucPanelMode = panel_mode;
880 			else
881 				args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
882 
883 			if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
884 				args.v1.ucLaneNum = dp_lane_count;
885 			else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
886 				args.v1.ucLaneNum = 8;
887 			else
888 				args.v1.ucLaneNum = 4;
889 
890 			switch (radeon_encoder->encoder_id) {
891 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
892 				args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
893 				break;
894 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
895 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
896 				args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
897 				break;
898 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
899 				args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
900 				break;
901 			}
902 			if (dig->linkb)
903 				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
904 			else
905 				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
906 
907 			if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
908 				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
909 
910 			break;
911 		case 2:
912 		case 3:
913 			args.v3.ucAction = action;
914 			args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
915 			if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
916 				args.v3.ucPanelMode = panel_mode;
917 			else
918 				args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
919 
920 			if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
921 				args.v3.ucLaneNum = dp_lane_count;
922 			else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
923 				args.v3.ucLaneNum = 8;
924 			else
925 				args.v3.ucLaneNum = 4;
926 
927 			if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
928 				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
929 			if (enc_override != -1)
930 				args.v3.acConfig.ucDigSel = enc_override;
931 			else
932 				args.v3.acConfig.ucDigSel = dig->dig_encoder;
933 			args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
934 			break;
935 		case 4:
936 			args.v4.ucAction = action;
937 			args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
938 			if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
939 				args.v4.ucPanelMode = panel_mode;
940 			else
941 				args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
942 
943 			if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
944 				args.v4.ucLaneNum = dp_lane_count;
945 			else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
946 				args.v4.ucLaneNum = 8;
947 			else
948 				args.v4.ucLaneNum = 4;
949 
950 			if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
951 				if (dp_clock == 540000)
952 					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
953 				else if (dp_clock == 324000)
954 					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
955 				else if (dp_clock == 270000)
956 					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
957 				else
958 					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
959 			}
960 
961 			if (enc_override != -1)
962 				args.v4.acConfig.ucDigSel = enc_override;
963 			else
964 				args.v4.acConfig.ucDigSel = dig->dig_encoder;
965 			args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
966 			if (hpd_id == RADEON_HPD_NONE)
967 				args.v4.ucHPD_ID = 0;
968 			else
969 				args.v4.ucHPD_ID = hpd_id + 1;
970 			break;
971 		default:
972 			DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
973 			break;
974 		}
975 		break;
976 	default:
977 		DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
978 		break;
979 	}
980 
981 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
982 
983 }
984 
985 void
atombios_dig_encoder_setup(struct drm_encoder * encoder,int action,int panel_mode)986 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
987 {
988 	atombios_dig_encoder_setup2(encoder, action, panel_mode, -1);
989 }
990 
991 union dig_transmitter_control {
992 	DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
993 	DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
994 	DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
995 	DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
996 	DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
997 };
998 
999 void
atombios_dig_transmitter_setup2(struct drm_encoder * encoder,int action,uint8_t lane_num,uint8_t lane_set,int fe)1000 atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe)
1001 {
1002 	struct drm_device *dev = encoder->dev;
1003 	struct radeon_device *rdev = dev->dev_private;
1004 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1005 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1006 	struct drm_connector *connector;
1007 	union dig_transmitter_control args;
1008 	int index = 0;
1009 	uint8_t frev, crev;
1010 	bool is_dp = false;
1011 	int pll_id = 0;
1012 	int dp_clock = 0;
1013 	int dp_lane_count = 0;
1014 	int connector_object_id = 0;
1015 	int igp_lane_info = 0;
1016 	int dig_encoder = dig->dig_encoder;
1017 	int hpd_id = RADEON_HPD_NONE;
1018 
1019 	if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1020 		connector = radeon_get_connector_for_encoder_init(encoder);
1021 		/* just needed to avoid bailing in the encoder check.  the encoder
1022 		 * isn't used for init
1023 		 */
1024 		dig_encoder = 0;
1025 	} else
1026 		connector = radeon_get_connector_for_encoder(encoder);
1027 
1028 	if (connector) {
1029 		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1030 		struct radeon_connector_atom_dig *dig_connector =
1031 			radeon_connector->con_priv;
1032 
1033 		hpd_id = radeon_connector->hpd.hpd;
1034 		dp_clock = dig_connector->dp_clock;
1035 		dp_lane_count = dig_connector->dp_lane_count;
1036 		connector_object_id =
1037 			(radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1038 		igp_lane_info = dig_connector->igp_lane_info;
1039 	}
1040 
1041 	if (encoder->crtc) {
1042 		struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1043 		pll_id = radeon_crtc->pll_id;
1044 	}
1045 
1046 	/* no dig encoder assigned */
1047 	if (dig_encoder == -1)
1048 		return;
1049 
1050 	if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1051 		is_dp = true;
1052 
1053 	memset(&args, 0, sizeof(args));
1054 
1055 	switch (radeon_encoder->encoder_id) {
1056 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1057 		index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1058 		break;
1059 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1060 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1061 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1062 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1063 		index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1064 		break;
1065 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1066 		index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1067 		break;
1068 	}
1069 
1070 	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1071 		return;
1072 
1073 	switch (frev) {
1074 	case 1:
1075 		switch (crev) {
1076 		case 1:
1077 			args.v1.ucAction = action;
1078 			if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1079 				args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1080 			} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1081 				args.v1.asMode.ucLaneSel = lane_num;
1082 				args.v1.asMode.ucLaneSet = lane_set;
1083 			} else {
1084 				if (is_dp)
1085 					args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1086 				else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1087 					args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1088 				else
1089 					args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1090 			}
1091 
1092 			args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1093 
1094 			if (dig_encoder)
1095 				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1096 			else
1097 				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1098 
1099 			if ((rdev->flags & RADEON_IS_IGP) &&
1100 			    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1101 				if (is_dp ||
1102 				    !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1103 					if (igp_lane_info & 0x1)
1104 						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1105 					else if (igp_lane_info & 0x2)
1106 						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1107 					else if (igp_lane_info & 0x4)
1108 						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1109 					else if (igp_lane_info & 0x8)
1110 						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1111 				} else {
1112 					if (igp_lane_info & 0x3)
1113 						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1114 					else if (igp_lane_info & 0xc)
1115 						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1116 				}
1117 			}
1118 
1119 			if (dig->linkb)
1120 				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1121 			else
1122 				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1123 
1124 			if (is_dp)
1125 				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1126 			else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1127 				if (dig->coherent_mode)
1128 					args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1129 				if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1130 					args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1131 			}
1132 			break;
1133 		case 2:
1134 			args.v2.ucAction = action;
1135 			if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1136 				args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1137 			} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1138 				args.v2.asMode.ucLaneSel = lane_num;
1139 				args.v2.asMode.ucLaneSet = lane_set;
1140 			} else {
1141 				if (is_dp)
1142 					args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1143 				else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1144 					args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1145 				else
1146 					args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1147 			}
1148 
1149 			args.v2.acConfig.ucEncoderSel = dig_encoder;
1150 			if (dig->linkb)
1151 				args.v2.acConfig.ucLinkSel = 1;
1152 
1153 			switch (radeon_encoder->encoder_id) {
1154 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1155 				args.v2.acConfig.ucTransmitterSel = 0;
1156 				break;
1157 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1158 				args.v2.acConfig.ucTransmitterSel = 1;
1159 				break;
1160 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1161 				args.v2.acConfig.ucTransmitterSel = 2;
1162 				break;
1163 			}
1164 
1165 			if (is_dp) {
1166 				args.v2.acConfig.fCoherentMode = 1;
1167 				args.v2.acConfig.fDPConnector = 1;
1168 			} else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1169 				if (dig->coherent_mode)
1170 					args.v2.acConfig.fCoherentMode = 1;
1171 				if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1172 					args.v2.acConfig.fDualLinkConnector = 1;
1173 			}
1174 			break;
1175 		case 3:
1176 			args.v3.ucAction = action;
1177 			if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1178 				args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1179 			} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1180 				args.v3.asMode.ucLaneSel = lane_num;
1181 				args.v3.asMode.ucLaneSet = lane_set;
1182 			} else {
1183 				if (is_dp)
1184 					args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1185 				else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1186 					args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1187 				else
1188 					args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1189 			}
1190 
1191 			if (is_dp)
1192 				args.v3.ucLaneNum = dp_lane_count;
1193 			else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1194 				args.v3.ucLaneNum = 8;
1195 			else
1196 				args.v3.ucLaneNum = 4;
1197 
1198 			if (dig->linkb)
1199 				args.v3.acConfig.ucLinkSel = 1;
1200 			if (dig_encoder & 1)
1201 				args.v3.acConfig.ucEncoderSel = 1;
1202 
1203 			/* Select the PLL for the PHY
1204 			 * DP PHY should be clocked from external src if there is
1205 			 * one.
1206 			 */
1207 			/* On DCE4, if there is an external clock, it generates the DP ref clock */
1208 			if (is_dp && rdev->clock.dp_extclk)
1209 				args.v3.acConfig.ucRefClkSource = 2; /* external src */
1210 			else
1211 				args.v3.acConfig.ucRefClkSource = pll_id;
1212 
1213 			switch (radeon_encoder->encoder_id) {
1214 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1215 				args.v3.acConfig.ucTransmitterSel = 0;
1216 				break;
1217 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1218 				args.v3.acConfig.ucTransmitterSel = 1;
1219 				break;
1220 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1221 				args.v3.acConfig.ucTransmitterSel = 2;
1222 				break;
1223 			}
1224 
1225 			if (is_dp)
1226 				args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1227 			else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1228 				if (dig->coherent_mode)
1229 					args.v3.acConfig.fCoherentMode = 1;
1230 				if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1231 					args.v3.acConfig.fDualLinkConnector = 1;
1232 			}
1233 			break;
1234 		case 4:
1235 			args.v4.ucAction = action;
1236 			if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1237 				args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1238 			} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1239 				args.v4.asMode.ucLaneSel = lane_num;
1240 				args.v4.asMode.ucLaneSet = lane_set;
1241 			} else {
1242 				if (is_dp)
1243 					args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1244 				else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1245 					args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1246 				else
1247 					args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1248 			}
1249 
1250 			if (is_dp)
1251 				args.v4.ucLaneNum = dp_lane_count;
1252 			else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1253 				args.v4.ucLaneNum = 8;
1254 			else
1255 				args.v4.ucLaneNum = 4;
1256 
1257 			if (dig->linkb)
1258 				args.v4.acConfig.ucLinkSel = 1;
1259 			if (dig_encoder & 1)
1260 				args.v4.acConfig.ucEncoderSel = 1;
1261 
1262 			/* Select the PLL for the PHY
1263 			 * DP PHY should be clocked from external src if there is
1264 			 * one.
1265 			 */
1266 			/* On DCE5 DCPLL usually generates the DP ref clock */
1267 			if (is_dp) {
1268 				if (rdev->clock.dp_extclk)
1269 					args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1270 				else
1271 					args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1272 			} else
1273 				args.v4.acConfig.ucRefClkSource = pll_id;
1274 
1275 			switch (radeon_encoder->encoder_id) {
1276 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1277 				args.v4.acConfig.ucTransmitterSel = 0;
1278 				break;
1279 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1280 				args.v4.acConfig.ucTransmitterSel = 1;
1281 				break;
1282 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1283 				args.v4.acConfig.ucTransmitterSel = 2;
1284 				break;
1285 			}
1286 
1287 			if (is_dp)
1288 				args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1289 			else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1290 				if (dig->coherent_mode)
1291 					args.v4.acConfig.fCoherentMode = 1;
1292 				if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1293 					args.v4.acConfig.fDualLinkConnector = 1;
1294 			}
1295 			break;
1296 		case 5:
1297 			args.v5.ucAction = action;
1298 			if (is_dp)
1299 				args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1300 			else
1301 				args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1302 
1303 			switch (radeon_encoder->encoder_id) {
1304 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1305 				if (dig->linkb)
1306 					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1307 				else
1308 					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1309 				break;
1310 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1311 				if (dig->linkb)
1312 					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1313 				else
1314 					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1315 				break;
1316 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1317 				if (dig->linkb)
1318 					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1319 				else
1320 					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1321 				break;
1322 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1323 				args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1324 				break;
1325 			}
1326 			if (is_dp)
1327 				args.v5.ucLaneNum = dp_lane_count;
1328 			else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1329 				args.v5.ucLaneNum = 8;
1330 			else
1331 				args.v5.ucLaneNum = 4;
1332 			args.v5.ucConnObjId = connector_object_id;
1333 			args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1334 
1335 			if (is_dp && rdev->clock.dp_extclk)
1336 				args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1337 			else
1338 				args.v5.asConfig.ucPhyClkSrcId = pll_id;
1339 
1340 			if (is_dp)
1341 				args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1342 			else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1343 				if (dig->coherent_mode)
1344 					args.v5.asConfig.ucCoherentMode = 1;
1345 			}
1346 			if (hpd_id == RADEON_HPD_NONE)
1347 				args.v5.asConfig.ucHPDSel = 0;
1348 			else
1349 				args.v5.asConfig.ucHPDSel = hpd_id + 1;
1350 			args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder);
1351 			args.v5.ucDPLaneSet = lane_set;
1352 			break;
1353 		default:
1354 			DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1355 			break;
1356 		}
1357 		break;
1358 	default:
1359 		DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1360 		break;
1361 	}
1362 
1363 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1364 }
1365 
1366 void
atombios_dig_transmitter_setup(struct drm_encoder * encoder,int action,uint8_t lane_num,uint8_t lane_set)1367 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
1368 {
1369 	atombios_dig_transmitter_setup2(encoder, action, lane_num, lane_set, -1);
1370 }
1371 
1372 bool
atombios_set_edp_panel_power(struct drm_connector * connector,int action)1373 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1374 {
1375 	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1376 	struct drm_device *dev = radeon_connector->base.dev;
1377 	struct radeon_device *rdev = dev->dev_private;
1378 	union dig_transmitter_control args;
1379 	int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1380 	uint8_t frev, crev;
1381 
1382 	if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1383 		goto done;
1384 
1385 	if (!ASIC_IS_DCE4(rdev))
1386 		goto done;
1387 
1388 	if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1389 	    (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1390 		goto done;
1391 
1392 	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1393 		goto done;
1394 
1395 	memset(&args, 0, sizeof(args));
1396 
1397 	args.v1.ucAction = action;
1398 
1399 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1400 
1401 	/* wait for the panel to power up */
1402 	if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1403 		int i;
1404 
1405 		for (i = 0; i < 300; i++) {
1406 			if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1407 				return true;
1408 			mdelay(1);
1409 		}
1410 		return false;
1411 	}
1412 done:
1413 	return true;
1414 }
1415 
1416 union external_encoder_control {
1417 	EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1418 	EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1419 };
1420 
1421 static void
atombios_external_encoder_setup(struct drm_encoder * encoder,struct drm_encoder * ext_encoder,int action)1422 atombios_external_encoder_setup(struct drm_encoder *encoder,
1423 				struct drm_encoder *ext_encoder,
1424 				int action)
1425 {
1426 	struct drm_device *dev = encoder->dev;
1427 	struct radeon_device *rdev = dev->dev_private;
1428 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1429 	struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1430 	union external_encoder_control args;
1431 	struct drm_connector *connector;
1432 	int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1433 	u8 frev, crev;
1434 	int dp_clock = 0;
1435 	int dp_lane_count = 0;
1436 	int connector_object_id = 0;
1437 	u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1438 
1439 	if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1440 		connector = radeon_get_connector_for_encoder_init(encoder);
1441 	else
1442 		connector = radeon_get_connector_for_encoder(encoder);
1443 
1444 	if (connector) {
1445 		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1446 		struct radeon_connector_atom_dig *dig_connector =
1447 			radeon_connector->con_priv;
1448 
1449 		dp_clock = dig_connector->dp_clock;
1450 		dp_lane_count = dig_connector->dp_lane_count;
1451 		connector_object_id =
1452 			(radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1453 	}
1454 
1455 	memset(&args, 0, sizeof(args));
1456 
1457 	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1458 		return;
1459 
1460 	switch (frev) {
1461 	case 1:
1462 		/* no params on frev 1 */
1463 		break;
1464 	case 2:
1465 		switch (crev) {
1466 		case 1:
1467 		case 2:
1468 			args.v1.sDigEncoder.ucAction = action;
1469 			args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1470 			args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1471 
1472 			if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1473 				if (dp_clock == 270000)
1474 					args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1475 				args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1476 			} else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1477 				args.v1.sDigEncoder.ucLaneNum = 8;
1478 			else
1479 				args.v1.sDigEncoder.ucLaneNum = 4;
1480 			break;
1481 		case 3:
1482 			args.v3.sExtEncoder.ucAction = action;
1483 			if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1484 				args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1485 			else
1486 				args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1487 			args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1488 
1489 			if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1490 				if (dp_clock == 270000)
1491 					args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1492 				else if (dp_clock == 540000)
1493 					args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1494 				args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1495 			} else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1496 				args.v3.sExtEncoder.ucLaneNum = 8;
1497 			else
1498 				args.v3.sExtEncoder.ucLaneNum = 4;
1499 			switch (ext_enum) {
1500 			case GRAPH_OBJECT_ENUM_ID1:
1501 				args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1502 				break;
1503 			case GRAPH_OBJECT_ENUM_ID2:
1504 				args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1505 				break;
1506 			case GRAPH_OBJECT_ENUM_ID3:
1507 				args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1508 				break;
1509 			}
1510 			args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1511 			break;
1512 		default:
1513 			DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1514 			return;
1515 		}
1516 		break;
1517 	default:
1518 		DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1519 		return;
1520 	}
1521 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1522 }
1523 
1524 static void
atombios_yuv_setup(struct drm_encoder * encoder,bool enable)1525 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1526 {
1527 	struct drm_device *dev = encoder->dev;
1528 	struct radeon_device *rdev = dev->dev_private;
1529 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1530 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1531 	ENABLE_YUV_PS_ALLOCATION args;
1532 	int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1533 	uint32_t temp, reg;
1534 
1535 	memset(&args, 0, sizeof(args));
1536 
1537 	if (rdev->family >= CHIP_R600)
1538 		reg = R600_BIOS_3_SCRATCH;
1539 	else
1540 		reg = RADEON_BIOS_3_SCRATCH;
1541 
1542 	/* XXX: fix up scratch reg handling */
1543 	temp = RREG32(reg);
1544 	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1545 		WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1546 			     (radeon_crtc->crtc_id << 18)));
1547 	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1548 		WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1549 	else
1550 		WREG32(reg, 0);
1551 
1552 	if (enable)
1553 		args.ucEnable = ATOM_ENABLE;
1554 	args.ucCRTC = radeon_crtc->crtc_id;
1555 
1556 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1557 
1558 	WREG32(reg, temp);
1559 }
1560 
1561 static void
radeon_atom_encoder_dpms_avivo(struct drm_encoder * encoder,int mode)1562 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1563 {
1564 	struct drm_device *dev = encoder->dev;
1565 	struct radeon_device *rdev = dev->dev_private;
1566 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1567 	DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1568 	int index = 0;
1569 
1570 	memset(&args, 0, sizeof(args));
1571 
1572 	switch (radeon_encoder->encoder_id) {
1573 	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1574 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1575 		index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1576 		break;
1577 	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1578 	case ENCODER_OBJECT_ID_INTERNAL_DDI:
1579 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1580 		index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1581 		break;
1582 	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1583 		index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1584 		break;
1585 	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1586 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1587 			index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1588 		else
1589 			index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1590 		break;
1591 	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1592 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1593 		if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1594 			index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1595 		else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1596 			index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1597 		else
1598 			index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1599 		break;
1600 	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1601 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1602 		if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1603 			index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1604 		else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1605 			index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1606 		else
1607 			index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1608 		break;
1609 	default:
1610 		return;
1611 	}
1612 
1613 	switch (mode) {
1614 	case DRM_MODE_DPMS_ON:
1615 		args.ucAction = ATOM_ENABLE;
1616 		/* workaround for DVOOutputControl on some RS690 systems */
1617 		if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1618 			u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1619 			WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1620 			atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1621 			WREG32(RADEON_BIOS_3_SCRATCH, reg);
1622 		} else
1623 			atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1624 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1625 			if (rdev->mode_info.bl_encoder) {
1626 				struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1627 
1628 				atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1629 			} else {
1630 				args.ucAction = ATOM_LCD_BLON;
1631 				atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1632 			}
1633 		}
1634 		break;
1635 	case DRM_MODE_DPMS_STANDBY:
1636 	case DRM_MODE_DPMS_SUSPEND:
1637 	case DRM_MODE_DPMS_OFF:
1638 		args.ucAction = ATOM_DISABLE;
1639 		atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1640 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1641 			args.ucAction = ATOM_LCD_BLOFF;
1642 			atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1643 		}
1644 		break;
1645 	}
1646 }
1647 
1648 static void
radeon_atom_encoder_dpms_dig(struct drm_encoder * encoder,int mode)1649 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1650 {
1651 	struct drm_device *dev = encoder->dev;
1652 	struct radeon_device *rdev = dev->dev_private;
1653 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1654 	struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1655 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1656 	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1657 	struct radeon_connector *radeon_connector = NULL;
1658 	struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1659 	bool travis_quirk = false;
1660 
1661 	if (connector) {
1662 		radeon_connector = to_radeon_connector(connector);
1663 		radeon_dig_connector = radeon_connector->con_priv;
1664 		if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
1665 		     ENCODER_OBJECT_ID_TRAVIS) &&
1666 		    (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
1667 		    !ASIC_IS_DCE5(rdev))
1668 			travis_quirk = true;
1669 	}
1670 
1671 	switch (mode) {
1672 	case DRM_MODE_DPMS_ON:
1673 		if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1674 			if (!connector)
1675 				dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1676 			else
1677 				dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1678 
1679 			/* setup and enable the encoder */
1680 			atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1681 			atombios_dig_encoder_setup(encoder,
1682 						   ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1683 						   dig->panel_mode);
1684 			if (ext_encoder) {
1685 				if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1686 					atombios_external_encoder_setup(encoder, ext_encoder,
1687 									EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1688 			}
1689 		} else if (ASIC_IS_DCE4(rdev)) {
1690 			/* setup and enable the encoder */
1691 			atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1692 		} else {
1693 			/* setup and enable the encoder and transmitter */
1694 			atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1695 			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1696 		}
1697 		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1698 			if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1699 				atombios_set_edp_panel_power(connector,
1700 							     ATOM_TRANSMITTER_ACTION_POWER_ON);
1701 				radeon_dig_connector->edp_on = true;
1702 			}
1703 		}
1704 		/* enable the transmitter */
1705 		atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1706 		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1707 			/* DP_SET_POWER_D0 is set in radeon_dp_link_train */
1708 			radeon_dp_link_train(encoder, connector);
1709 			if (ASIC_IS_DCE4(rdev))
1710 				atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1711 		}
1712 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1713 			if (rdev->mode_info.bl_encoder)
1714 				atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1715 			else
1716 				atombios_dig_transmitter_setup(encoder,
1717 							       ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1718 		}
1719 		if (ext_encoder)
1720 			atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1721 		break;
1722 	case DRM_MODE_DPMS_STANDBY:
1723 	case DRM_MODE_DPMS_SUSPEND:
1724 	case DRM_MODE_DPMS_OFF:
1725 
1726 		if (ASIC_IS_DCE4(rdev)) {
1727 			if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector)
1728 				atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1729 		}
1730 		if (ext_encoder)
1731 			atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1732 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1733 			atombios_dig_transmitter_setup(encoder,
1734 						       ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1735 
1736 		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) &&
1737 		    connector && !travis_quirk)
1738 			radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1739 		if (ASIC_IS_DCE4(rdev)) {
1740 			/* disable the transmitter */
1741 			atombios_dig_transmitter_setup(encoder,
1742 						       ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1743 		} else {
1744 			/* disable the encoder and transmitter */
1745 			atombios_dig_transmitter_setup(encoder,
1746 						       ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1747 			atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1748 		}
1749 		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1750 			if (travis_quirk)
1751 				radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1752 			if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1753 				atombios_set_edp_panel_power(connector,
1754 							     ATOM_TRANSMITTER_ACTION_POWER_OFF);
1755 				radeon_dig_connector->edp_on = false;
1756 			}
1757 		}
1758 		break;
1759 	}
1760 }
1761 
1762 static void
radeon_atom_encoder_dpms(struct drm_encoder * encoder,int mode)1763 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1764 {
1765 	struct drm_device *dev = encoder->dev;
1766 	struct radeon_device *rdev = dev->dev_private;
1767 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1768 	int encoder_mode = atombios_get_encoder_mode(encoder);
1769 
1770 	DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1771 		  radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1772 		  radeon_encoder->active_device);
1773 
1774 	if ((radeon_audio != 0) &&
1775 	    ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
1776 	     ENCODER_MODE_IS_DP(encoder_mode)))
1777 		radeon_audio_dpms(encoder, mode);
1778 
1779 	switch (radeon_encoder->encoder_id) {
1780 	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1781 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1782 	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1783 	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1784 	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1785 	case ENCODER_OBJECT_ID_INTERNAL_DDI:
1786 	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1787 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1788 		radeon_atom_encoder_dpms_avivo(encoder, mode);
1789 		break;
1790 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1791 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1792 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1793 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1794 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1795 		radeon_atom_encoder_dpms_dig(encoder, mode);
1796 		break;
1797 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1798 		if (ASIC_IS_DCE5(rdev)) {
1799 			switch (mode) {
1800 			case DRM_MODE_DPMS_ON:
1801 				atombios_dvo_setup(encoder, ATOM_ENABLE);
1802 				break;
1803 			case DRM_MODE_DPMS_STANDBY:
1804 			case DRM_MODE_DPMS_SUSPEND:
1805 			case DRM_MODE_DPMS_OFF:
1806 				atombios_dvo_setup(encoder, ATOM_DISABLE);
1807 				break;
1808 			}
1809 		} else if (ASIC_IS_DCE3(rdev))
1810 			radeon_atom_encoder_dpms_dig(encoder, mode);
1811 		else
1812 			radeon_atom_encoder_dpms_avivo(encoder, mode);
1813 		break;
1814 	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1815 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1816 		if (ASIC_IS_DCE5(rdev)) {
1817 			switch (mode) {
1818 			case DRM_MODE_DPMS_ON:
1819 				atombios_dac_setup(encoder, ATOM_ENABLE);
1820 				break;
1821 			case DRM_MODE_DPMS_STANDBY:
1822 			case DRM_MODE_DPMS_SUSPEND:
1823 			case DRM_MODE_DPMS_OFF:
1824 				atombios_dac_setup(encoder, ATOM_DISABLE);
1825 				break;
1826 			}
1827 		} else
1828 			radeon_atom_encoder_dpms_avivo(encoder, mode);
1829 		break;
1830 	default:
1831 		return;
1832 	}
1833 
1834 	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1835 
1836 }
1837 
1838 union crtc_source_param {
1839 	SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1840 	SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1841 };
1842 
1843 static void
atombios_set_encoder_crtc_source(struct drm_encoder * encoder)1844 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1845 {
1846 	struct drm_device *dev = encoder->dev;
1847 	struct radeon_device *rdev = dev->dev_private;
1848 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1849 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1850 	union crtc_source_param args;
1851 	int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1852 	uint8_t frev, crev;
1853 	struct radeon_encoder_atom_dig *dig;
1854 
1855 	memset(&args, 0, sizeof(args));
1856 
1857 	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1858 		return;
1859 
1860 	switch (frev) {
1861 	case 1:
1862 		switch (crev) {
1863 		case 1:
1864 		default:
1865 			if (ASIC_IS_AVIVO(rdev))
1866 				args.v1.ucCRTC = radeon_crtc->crtc_id;
1867 			else {
1868 				if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1)
1869 					args.v1.ucCRTC = radeon_crtc->crtc_id;
1870 				else
1871 					args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1872 			}
1873 			switch (radeon_encoder->encoder_id) {
1874 			case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1875 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1876 				args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1877 				break;
1878 			case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1879 			case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1880 				if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1881 					args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1882 				else
1883 					args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1884 				break;
1885 			case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1886 			case ENCODER_OBJECT_ID_INTERNAL_DDI:
1887 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1888 				args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1889 				break;
1890 			case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1891 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1892 				if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1893 					args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1894 				else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1895 					args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1896 				else
1897 					args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1898 				break;
1899 			case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1900 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1901 				if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1902 					args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1903 				else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1904 					args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1905 				else
1906 					args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1907 				break;
1908 			}
1909 			break;
1910 		case 2:
1911 			args.v2.ucCRTC = radeon_crtc->crtc_id;
1912 			if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1913 				struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1914 
1915 				if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1916 					args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1917 				else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1918 					args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1919 				else
1920 					args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1921 			} else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1922 				args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1923 			} else {
1924 				args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1925 			}
1926 			switch (radeon_encoder->encoder_id) {
1927 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1928 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1929 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1930 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1931 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1932 				dig = radeon_encoder->enc_priv;
1933 				switch (dig->dig_encoder) {
1934 				case 0:
1935 					args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1936 					break;
1937 				case 1:
1938 					args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1939 					break;
1940 				case 2:
1941 					args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1942 					break;
1943 				case 3:
1944 					args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1945 					break;
1946 				case 4:
1947 					args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1948 					break;
1949 				case 5:
1950 					args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1951 					break;
1952 				case 6:
1953 					args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1954 					break;
1955 				}
1956 				break;
1957 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1958 				args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1959 				break;
1960 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1961 				if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1962 					args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1963 				else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1964 					args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1965 				else
1966 					args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1967 				break;
1968 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1969 				if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1970 					args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1971 				else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1972 					args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1973 				else
1974 					args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1975 				break;
1976 			}
1977 			break;
1978 		}
1979 		break;
1980 	default:
1981 		DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1982 		return;
1983 	}
1984 
1985 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1986 
1987 	/* update scratch regs with new routing */
1988 	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1989 }
1990 
1991 static void
atombios_apply_encoder_quirks(struct drm_encoder * encoder,struct drm_display_mode * mode)1992 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1993 			      struct drm_display_mode *mode)
1994 {
1995 	struct drm_device *dev = encoder->dev;
1996 	struct radeon_device *rdev = dev->dev_private;
1997 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1998 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1999 
2000 	/* Funky macbooks */
2001 	if ((rdev->pdev->device == 0x71C5) &&
2002 	    (rdev->pdev->subsystem_vendor == 0x106b) &&
2003 	    (rdev->pdev->subsystem_device == 0x0080)) {
2004 		if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2005 			uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
2006 
2007 			lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
2008 			lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
2009 
2010 			WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
2011 		}
2012 	}
2013 
2014 	/* set scaler clears this on some chips */
2015 	if (ASIC_IS_AVIVO(rdev) &&
2016 	    (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
2017 		if (ASIC_IS_DCE8(rdev)) {
2018 			if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2019 				WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
2020 				       CIK_INTERLEAVE_EN);
2021 			else
2022 				WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2023 		} else if (ASIC_IS_DCE4(rdev)) {
2024 			if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2025 				WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
2026 				       EVERGREEN_INTERLEAVE_EN);
2027 			else
2028 				WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2029 		} else {
2030 			if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2031 				WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
2032 				       AVIVO_D1MODE_INTERLEAVE_EN);
2033 			else
2034 				WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2035 		}
2036 	}
2037 }
2038 
radeon_atom_release_dig_encoder(struct radeon_device * rdev,int enc_idx)2039 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx)
2040 {
2041 	if (enc_idx < 0)
2042 		return;
2043 	rdev->mode_info.active_encoders &= ~(1 << enc_idx);
2044 }
2045 
radeon_atom_pick_dig_encoder(struct drm_encoder * encoder,int fe_idx)2046 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx)
2047 {
2048 	struct drm_device *dev = encoder->dev;
2049 	struct radeon_device *rdev = dev->dev_private;
2050 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2051 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2052 	struct drm_encoder *test_encoder;
2053 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2054 	uint32_t dig_enc_in_use = 0;
2055 	int enc_idx = -1;
2056 
2057 	if (fe_idx >= 0) {
2058 		enc_idx = fe_idx;
2059 		goto assigned;
2060 	}
2061 	if (ASIC_IS_DCE6(rdev)) {
2062 		/* DCE6 */
2063 		switch (radeon_encoder->encoder_id) {
2064 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2065 			if (dig->linkb)
2066 				enc_idx = 1;
2067 			else
2068 				enc_idx = 0;
2069 			break;
2070 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2071 			if (dig->linkb)
2072 				enc_idx = 3;
2073 			else
2074 				enc_idx = 2;
2075 			break;
2076 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2077 			if (dig->linkb)
2078 				enc_idx = 5;
2079 			else
2080 				enc_idx = 4;
2081 			break;
2082 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2083 			enc_idx = 6;
2084 			break;
2085 		}
2086 		goto assigned;
2087 	} else if (ASIC_IS_DCE4(rdev)) {
2088 		/* DCE4/5 */
2089 		if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2090 			/* ontario follows DCE4 */
2091 			if (rdev->family == CHIP_PALM) {
2092 				if (dig->linkb)
2093 					enc_idx = 1;
2094 				else
2095 					enc_idx = 0;
2096 			} else
2097 				/* llano follows DCE3.2 */
2098 				enc_idx = radeon_crtc->crtc_id;
2099 		} else {
2100 			switch (radeon_encoder->encoder_id) {
2101 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2102 				if (dig->linkb)
2103 					enc_idx = 1;
2104 				else
2105 					enc_idx = 0;
2106 				break;
2107 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2108 				if (dig->linkb)
2109 					enc_idx = 3;
2110 				else
2111 					enc_idx = 2;
2112 				break;
2113 			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2114 				if (dig->linkb)
2115 					enc_idx = 5;
2116 				else
2117 					enc_idx = 4;
2118 				break;
2119 			}
2120 		}
2121 		goto assigned;
2122 	}
2123 
2124 	/*
2125 	 * On DCE32 any encoder can drive any block so usually just use crtc id,
2126 	 * but Apple thinks different at least on iMac10,1 and iMac11,2, so there use linkb,
2127 	 * otherwise the internal eDP panel will stay dark.
2128 	 */
2129 	if (ASIC_IS_DCE32(rdev)) {
2130 		if (dmi_match(DMI_PRODUCT_NAME, "iMac10,1") ||
2131 		    dmi_match(DMI_PRODUCT_NAME, "iMac11,2"))
2132 			enc_idx = (dig->linkb) ? 1 : 0;
2133 		else
2134 			enc_idx = radeon_crtc->crtc_id;
2135 
2136 		goto assigned;
2137 	}
2138 
2139 	/* on DCE3 - LVTMA can only be driven by DIGB */
2140 	list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2141 		struct radeon_encoder *radeon_test_encoder;
2142 
2143 		if (encoder == test_encoder)
2144 			continue;
2145 
2146 		if (!radeon_encoder_is_digital(test_encoder))
2147 			continue;
2148 
2149 		radeon_test_encoder = to_radeon_encoder(test_encoder);
2150 		dig = radeon_test_encoder->enc_priv;
2151 
2152 		if (dig->dig_encoder >= 0)
2153 			dig_enc_in_use |= (1 << dig->dig_encoder);
2154 	}
2155 
2156 	if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2157 		if (dig_enc_in_use & 0x2)
2158 			DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2159 		return 1;
2160 	}
2161 	if (!(dig_enc_in_use & 1))
2162 		return 0;
2163 	return 1;
2164 
2165 assigned:
2166 	if (enc_idx == -1) {
2167 		DRM_ERROR("Got encoder index incorrect - returning 0\n");
2168 		return 0;
2169 	}
2170 	if (rdev->mode_info.active_encoders & (1 << enc_idx))
2171 		DRM_ERROR("chosen encoder in use %d\n", enc_idx);
2172 
2173 	rdev->mode_info.active_encoders |= (1 << enc_idx);
2174 	return enc_idx;
2175 }
2176 
2177 /* This only needs to be called once at startup */
2178 void
radeon_atom_encoder_init(struct radeon_device * rdev)2179 radeon_atom_encoder_init(struct radeon_device *rdev)
2180 {
2181 	struct drm_device *dev = rdev->ddev;
2182 	struct drm_encoder *encoder;
2183 
2184 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2185 		struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2186 		struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2187 
2188 		switch (radeon_encoder->encoder_id) {
2189 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2190 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2191 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2192 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2193 		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2194 			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2195 			break;
2196 		default:
2197 			break;
2198 		}
2199 
2200 		if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2201 			atombios_external_encoder_setup(encoder, ext_encoder,
2202 							EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2203 	}
2204 }
2205 
2206 static void
radeon_atom_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)2207 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2208 			     struct drm_display_mode *mode,
2209 			     struct drm_display_mode *adjusted_mode)
2210 {
2211 	struct drm_device *dev = encoder->dev;
2212 	struct radeon_device *rdev = dev->dev_private;
2213 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2214 	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2215 	int encoder_mode;
2216 
2217 	radeon_encoder->pixel_clock = adjusted_mode->clock;
2218 
2219 	/* need to call this here rather than in prepare() since we need some crtc info */
2220 	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2221 
2222 	if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2223 		if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2224 			atombios_yuv_setup(encoder, true);
2225 		else
2226 			atombios_yuv_setup(encoder, false);
2227 	}
2228 
2229 	switch (radeon_encoder->encoder_id) {
2230 	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2231 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2232 	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2233 	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2234 		atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2235 		break;
2236 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2237 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2238 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2239 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2240 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2241 		/* handled in dpms */
2242 		break;
2243 	case ENCODER_OBJECT_ID_INTERNAL_DDI:
2244 	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2245 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2246 		atombios_dvo_setup(encoder, ATOM_ENABLE);
2247 		break;
2248 	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2249 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2250 	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2251 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2252 		atombios_dac_setup(encoder, ATOM_ENABLE);
2253 		if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2254 			if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2255 				atombios_tv_setup(encoder, ATOM_ENABLE);
2256 			else
2257 				atombios_tv_setup(encoder, ATOM_DISABLE);
2258 		}
2259 		break;
2260 	}
2261 
2262 	atombios_apply_encoder_quirks(encoder, adjusted_mode);
2263 
2264 	encoder_mode = atombios_get_encoder_mode(encoder);
2265 	if (connector && (radeon_audio != 0) &&
2266 	    ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
2267 	     ENCODER_MODE_IS_DP(encoder_mode)))
2268 		radeon_audio_mode_set(encoder, adjusted_mode);
2269 }
2270 
2271 static bool
atombios_dac_load_detect(struct drm_encoder * encoder,struct drm_connector * connector)2272 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2273 {
2274 	struct drm_device *dev = encoder->dev;
2275 	struct radeon_device *rdev = dev->dev_private;
2276 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2277 	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2278 
2279 	if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2280 				       ATOM_DEVICE_CV_SUPPORT |
2281 				       ATOM_DEVICE_CRT_SUPPORT)) {
2282 		DAC_LOAD_DETECTION_PS_ALLOCATION args;
2283 		int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2284 		uint8_t frev, crev;
2285 
2286 		memset(&args, 0, sizeof(args));
2287 
2288 		if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2289 			return false;
2290 
2291 		args.sDacload.ucMisc = 0;
2292 
2293 		if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2294 		    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2295 			args.sDacload.ucDacType = ATOM_DAC_A;
2296 		else
2297 			args.sDacload.ucDacType = ATOM_DAC_B;
2298 
2299 		if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2300 			args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2301 		else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2302 			args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2303 		else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2304 			args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2305 			if (crev >= 3)
2306 				args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2307 		} else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2308 			args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2309 			if (crev >= 3)
2310 				args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2311 		}
2312 
2313 		atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2314 
2315 		return true;
2316 	} else
2317 		return false;
2318 }
2319 
2320 static enum drm_connector_status
radeon_atom_dac_detect(struct drm_encoder * encoder,struct drm_connector * connector)2321 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2322 {
2323 	struct drm_device *dev = encoder->dev;
2324 	struct radeon_device *rdev = dev->dev_private;
2325 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2326 	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2327 	uint32_t bios_0_scratch;
2328 
2329 	if (!atombios_dac_load_detect(encoder, connector)) {
2330 		DRM_DEBUG_KMS("detect returned false \n");
2331 		return connector_status_unknown;
2332 	}
2333 
2334 	if (rdev->family >= CHIP_R600)
2335 		bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2336 	else
2337 		bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2338 
2339 	DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2340 	if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2341 		if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2342 			return connector_status_connected;
2343 	}
2344 	if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2345 		if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2346 			return connector_status_connected;
2347 	}
2348 	if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2349 		if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2350 			return connector_status_connected;
2351 	}
2352 	if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2353 		if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2354 			return connector_status_connected; /* CTV */
2355 		else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2356 			return connector_status_connected; /* STV */
2357 	}
2358 	return connector_status_disconnected;
2359 }
2360 
2361 static enum drm_connector_status
radeon_atom_dig_detect(struct drm_encoder * encoder,struct drm_connector * connector)2362 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2363 {
2364 	struct drm_device *dev = encoder->dev;
2365 	struct radeon_device *rdev = dev->dev_private;
2366 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2367 	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2368 	struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2369 	u32 bios_0_scratch;
2370 
2371 	if (!ASIC_IS_DCE4(rdev))
2372 		return connector_status_unknown;
2373 
2374 	if (!ext_encoder)
2375 		return connector_status_unknown;
2376 
2377 	if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2378 		return connector_status_unknown;
2379 
2380 	/* load detect on the dp bridge */
2381 	atombios_external_encoder_setup(encoder, ext_encoder,
2382 					EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2383 
2384 	bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2385 
2386 	DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2387 	if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2388 		if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2389 			return connector_status_connected;
2390 	}
2391 	if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2392 		if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2393 			return connector_status_connected;
2394 	}
2395 	if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2396 		if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2397 			return connector_status_connected;
2398 	}
2399 	if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2400 		if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2401 			return connector_status_connected; /* CTV */
2402 		else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2403 			return connector_status_connected; /* STV */
2404 	}
2405 	return connector_status_disconnected;
2406 }
2407 
2408 void
radeon_atom_ext_encoder_setup_ddc(struct drm_encoder * encoder)2409 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2410 {
2411 	struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2412 
2413 	if (ext_encoder)
2414 		/* ddc_setup on the dp bridge */
2415 		atombios_external_encoder_setup(encoder, ext_encoder,
2416 						EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2417 
2418 }
2419 
radeon_atom_encoder_prepare(struct drm_encoder * encoder)2420 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2421 {
2422 	struct radeon_device *rdev = encoder->dev->dev_private;
2423 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2424 	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2425 
2426 	if ((radeon_encoder->active_device &
2427 	     (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2428 	    (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2429 	     ENCODER_OBJECT_ID_NONE)) {
2430 		struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2431 		if (dig) {
2432 			if (dig->dig_encoder >= 0)
2433 				radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2434 			dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder, -1);
2435 			if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2436 				if (rdev->family >= CHIP_R600)
2437 					dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2438 				else
2439 					/* RS600/690/740 have only 1 afmt block */
2440 					dig->afmt = rdev->mode_info.afmt[0];
2441 			}
2442 		}
2443 	}
2444 
2445 	radeon_atom_output_lock(encoder, true);
2446 
2447 	if (connector) {
2448 		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2449 
2450 		/* select the clock/data port if it uses a router */
2451 		if (radeon_connector->router.cd_valid)
2452 			radeon_router_select_cd_port(radeon_connector);
2453 
2454 		/* turn eDP panel on for mode set */
2455 		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2456 			atombios_set_edp_panel_power(connector,
2457 						     ATOM_TRANSMITTER_ACTION_POWER_ON);
2458 	}
2459 
2460 	/* this is needed for the pll/ss setup to work correctly in some cases */
2461 	atombios_set_encoder_crtc_source(encoder);
2462 	/* set up the FMT blocks */
2463 	if (ASIC_IS_DCE8(rdev))
2464 		dce8_program_fmt(encoder);
2465 	else if (ASIC_IS_DCE4(rdev))
2466 		dce4_program_fmt(encoder);
2467 	else if (ASIC_IS_DCE3(rdev))
2468 		dce3_program_fmt(encoder);
2469 	else if (ASIC_IS_AVIVO(rdev))
2470 		avivo_program_fmt(encoder);
2471 }
2472 
radeon_atom_encoder_commit(struct drm_encoder * encoder)2473 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2474 {
2475 	/* need to call this here as we need the crtc set up */
2476 	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2477 	radeon_atom_output_lock(encoder, false);
2478 }
2479 
radeon_atom_encoder_disable(struct drm_encoder * encoder)2480 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2481 {
2482 	struct drm_device *dev = encoder->dev;
2483 	struct radeon_device *rdev = dev->dev_private;
2484 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2485 	struct radeon_encoder_atom_dig *dig;
2486 
2487 	/* check for pre-DCE3 cards with shared encoders;
2488 	 * can't really use the links individually, so don't disable
2489 	 * the encoder if it's in use by another connector
2490 	 */
2491 	if (!ASIC_IS_DCE3(rdev)) {
2492 		struct drm_encoder *other_encoder;
2493 		struct radeon_encoder *other_radeon_encoder;
2494 
2495 		list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2496 			other_radeon_encoder = to_radeon_encoder(other_encoder);
2497 			if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2498 			    drm_helper_encoder_in_use(other_encoder))
2499 				goto disable_done;
2500 		}
2501 	}
2502 
2503 	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2504 
2505 	switch (radeon_encoder->encoder_id) {
2506 	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2507 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2508 	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2509 	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2510 		atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2511 		break;
2512 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2513 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2514 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2515 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2516 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2517 		/* handled in dpms */
2518 		break;
2519 	case ENCODER_OBJECT_ID_INTERNAL_DDI:
2520 	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2521 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2522 		atombios_dvo_setup(encoder, ATOM_DISABLE);
2523 		break;
2524 	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2525 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2526 	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2527 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2528 		atombios_dac_setup(encoder, ATOM_DISABLE);
2529 		if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2530 			atombios_tv_setup(encoder, ATOM_DISABLE);
2531 		break;
2532 	}
2533 
2534 disable_done:
2535 	if (radeon_encoder_is_digital(encoder)) {
2536 		if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2537 			if (rdev->asic->display.hdmi_enable)
2538 				radeon_hdmi_enable(rdev, encoder, false);
2539 		}
2540 		if (atombios_get_encoder_mode(encoder) != ATOM_ENCODER_MODE_DP_MST) {
2541 			dig = radeon_encoder->enc_priv;
2542 			radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2543 			dig->dig_encoder = -1;
2544 			radeon_encoder->active_device = 0;
2545 		}
2546 	} else
2547 		radeon_encoder->active_device = 0;
2548 }
2549 
2550 /* these are handled by the primary encoders */
radeon_atom_ext_prepare(struct drm_encoder * encoder)2551 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2552 {
2553 
2554 }
2555 
radeon_atom_ext_commit(struct drm_encoder * encoder)2556 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2557 {
2558 
2559 }
2560 
2561 static void
radeon_atom_ext_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)2562 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2563 			 struct drm_display_mode *mode,
2564 			 struct drm_display_mode *adjusted_mode)
2565 {
2566 
2567 }
2568 
radeon_atom_ext_disable(struct drm_encoder * encoder)2569 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2570 {
2571 
2572 }
2573 
2574 static void
radeon_atom_ext_dpms(struct drm_encoder * encoder,int mode)2575 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2576 {
2577 
2578 }
2579 
2580 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2581 	.dpms = radeon_atom_ext_dpms,
2582 	.prepare = radeon_atom_ext_prepare,
2583 	.mode_set = radeon_atom_ext_mode_set,
2584 	.commit = radeon_atom_ext_commit,
2585 	.disable = radeon_atom_ext_disable,
2586 	/* no detect for TMDS/LVDS yet */
2587 };
2588 
2589 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2590 	.dpms = radeon_atom_encoder_dpms,
2591 	.mode_fixup = radeon_atom_mode_fixup,
2592 	.prepare = radeon_atom_encoder_prepare,
2593 	.mode_set = radeon_atom_encoder_mode_set,
2594 	.commit = radeon_atom_encoder_commit,
2595 	.disable = radeon_atom_encoder_disable,
2596 	.detect = radeon_atom_dig_detect,
2597 };
2598 
2599 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2600 	.dpms = radeon_atom_encoder_dpms,
2601 	.mode_fixup = radeon_atom_mode_fixup,
2602 	.prepare = radeon_atom_encoder_prepare,
2603 	.mode_set = radeon_atom_encoder_mode_set,
2604 	.commit = radeon_atom_encoder_commit,
2605 	.detect = radeon_atom_dac_detect,
2606 };
2607 
radeon_enc_destroy(struct drm_encoder * encoder)2608 void radeon_enc_destroy(struct drm_encoder *encoder)
2609 {
2610 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2611 	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2612 		radeon_atom_backlight_exit(radeon_encoder);
2613 	kfree(radeon_encoder->enc_priv);
2614 	drm_encoder_cleanup(encoder);
2615 	kfree(radeon_encoder);
2616 }
2617 
2618 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2619 	.destroy = radeon_enc_destroy,
2620 };
2621 
2622 static struct radeon_encoder_atom_dac *
radeon_atombios_set_dac_info(struct radeon_encoder * radeon_encoder)2623 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2624 {
2625 	struct drm_device *dev = radeon_encoder->base.dev;
2626 	struct radeon_device *rdev = dev->dev_private;
2627 	struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2628 
2629 	if (!dac)
2630 		return NULL;
2631 
2632 	dac->tv_std = radeon_atombios_get_tv_info(rdev);
2633 	return dac;
2634 }
2635 
2636 static struct radeon_encoder_atom_dig *
radeon_atombios_set_dig_info(struct radeon_encoder * radeon_encoder)2637 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2638 {
2639 	int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2640 	struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2641 
2642 	if (!dig)
2643 		return NULL;
2644 
2645 	/* coherent mode by default */
2646 	dig->coherent_mode = true;
2647 	dig->dig_encoder = -1;
2648 
2649 	if (encoder_enum == 2)
2650 		dig->linkb = true;
2651 	else
2652 		dig->linkb = false;
2653 
2654 	return dig;
2655 }
2656 
2657 void
radeon_add_atom_encoder(struct drm_device * dev,uint32_t encoder_enum,uint32_t supported_device,u16 caps)2658 radeon_add_atom_encoder(struct drm_device *dev,
2659 			uint32_t encoder_enum,
2660 			uint32_t supported_device,
2661 			u16 caps)
2662 {
2663 	struct radeon_device *rdev = dev->dev_private;
2664 	struct drm_encoder *encoder;
2665 	struct radeon_encoder *radeon_encoder;
2666 
2667 	/* see if we already added it */
2668 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2669 		radeon_encoder = to_radeon_encoder(encoder);
2670 		if (radeon_encoder->encoder_enum == encoder_enum) {
2671 			radeon_encoder->devices |= supported_device;
2672 			return;
2673 		}
2674 
2675 	}
2676 
2677 	/* add a new one */
2678 	radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2679 	if (!radeon_encoder)
2680 		return;
2681 
2682 	encoder = &radeon_encoder->base;
2683 	switch (rdev->num_crtc) {
2684 	case 1:
2685 		encoder->possible_crtcs = 0x1;
2686 		break;
2687 	case 2:
2688 	default:
2689 		encoder->possible_crtcs = 0x3;
2690 		break;
2691 	case 4:
2692 		encoder->possible_crtcs = 0xf;
2693 		break;
2694 	case 6:
2695 		encoder->possible_crtcs = 0x3f;
2696 		break;
2697 	}
2698 
2699 	radeon_encoder->enc_priv = NULL;
2700 
2701 	radeon_encoder->encoder_enum = encoder_enum;
2702 	radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2703 	radeon_encoder->devices = supported_device;
2704 	radeon_encoder->rmx_type = RMX_OFF;
2705 	radeon_encoder->underscan_type = UNDERSCAN_OFF;
2706 	radeon_encoder->is_ext_encoder = false;
2707 	radeon_encoder->caps = caps;
2708 
2709 	switch (radeon_encoder->encoder_id) {
2710 	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2711 	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2712 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2713 	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2714 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2715 			radeon_encoder->rmx_type = RMX_FULL;
2716 			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2717 					 DRM_MODE_ENCODER_LVDS, NULL);
2718 			radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2719 		} else {
2720 			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2721 					 DRM_MODE_ENCODER_TMDS, NULL);
2722 			radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2723 		}
2724 		drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2725 		break;
2726 	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2727 		drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2728 				 DRM_MODE_ENCODER_DAC, NULL);
2729 		radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2730 		drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2731 		break;
2732 	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2733 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2734 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2735 		drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2736 				 DRM_MODE_ENCODER_TVDAC, NULL);
2737 		radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2738 		drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2739 		break;
2740 	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2741 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2742 	case ENCODER_OBJECT_ID_INTERNAL_DDI:
2743 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2744 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2745 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2746 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2747 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2748 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2749 			radeon_encoder->rmx_type = RMX_FULL;
2750 			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2751 					 DRM_MODE_ENCODER_LVDS, NULL);
2752 			radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2753 		} else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2754 			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2755 					 DRM_MODE_ENCODER_DAC, NULL);
2756 			radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2757 		} else {
2758 			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2759 					 DRM_MODE_ENCODER_TMDS, NULL);
2760 			radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2761 		}
2762 		drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2763 		break;
2764 	case ENCODER_OBJECT_ID_SI170B:
2765 	case ENCODER_OBJECT_ID_CH7303:
2766 	case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2767 	case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2768 	case ENCODER_OBJECT_ID_TITFP513:
2769 	case ENCODER_OBJECT_ID_VT1623:
2770 	case ENCODER_OBJECT_ID_HDMI_SI1930:
2771 	case ENCODER_OBJECT_ID_TRAVIS:
2772 	case ENCODER_OBJECT_ID_NUTMEG:
2773 		/* these are handled by the primary encoders */
2774 		radeon_encoder->is_ext_encoder = true;
2775 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2776 			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2777 					 DRM_MODE_ENCODER_LVDS, NULL);
2778 		else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2779 			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2780 					 DRM_MODE_ENCODER_DAC, NULL);
2781 		else
2782 			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2783 					 DRM_MODE_ENCODER_TMDS, NULL);
2784 		drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2785 		break;
2786 	}
2787 }
2788