1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) Overkiz SAS 2012
4 *
5 * Author: Boris BREZILLON <b.brezillon@overkiz.com>
6 */
7
8 #include <linux/module.h>
9 #include <linux/init.h>
10 #include <linux/clocksource.h>
11 #include <linux/clockchips.h>
12 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14
15 #include <linux/clk.h>
16 #include <linux/err.h>
17 #include <linux/ioport.h>
18 #include <linux/io.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/platform_device.h>
21 #include <linux/pwm.h>
22 #include <linux/of.h>
23 #include <linux/regmap.h>
24 #include <linux/slab.h>
25 #include <soc/at91/atmel_tcb.h>
26
27 #define NPWM 2
28
29 #define ATMEL_TC_ACMR_MASK (ATMEL_TC_ACPA | ATMEL_TC_ACPC | \
30 ATMEL_TC_AEEVT | ATMEL_TC_ASWTRG)
31
32 #define ATMEL_TC_BCMR_MASK (ATMEL_TC_BCPB | ATMEL_TC_BCPC | \
33 ATMEL_TC_BEEVT | ATMEL_TC_BSWTRG)
34
35 struct atmel_tcb_pwm_device {
36 unsigned div; /* PWM clock divider */
37 unsigned duty; /* PWM duty expressed in clk cycles */
38 unsigned period; /* PWM period expressed in clk cycles */
39 };
40
41 struct atmel_tcb_channel {
42 u32 enabled;
43 u32 cmr;
44 u32 ra;
45 u32 rb;
46 u32 rc;
47 };
48
49 struct atmel_tcb_pwm_chip {
50 struct pwm_chip chip;
51 spinlock_t lock;
52 u8 channel;
53 u8 width;
54 struct regmap *regmap;
55 struct clk *clk;
56 struct clk *gclk;
57 struct clk *slow_clk;
58 struct atmel_tcb_pwm_device pwms[NPWM];
59 struct atmel_tcb_channel bkup;
60 };
61
62 static const u8 atmel_tcb_divisors[] = { 2, 8, 32, 128, 0, };
63
to_tcb_chip(struct pwm_chip * chip)64 static inline struct atmel_tcb_pwm_chip *to_tcb_chip(struct pwm_chip *chip)
65 {
66 return container_of(chip, struct atmel_tcb_pwm_chip, chip);
67 }
68
atmel_tcb_pwm_request(struct pwm_chip * chip,struct pwm_device * pwm)69 static int atmel_tcb_pwm_request(struct pwm_chip *chip,
70 struct pwm_device *pwm)
71 {
72 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
73 struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
74 unsigned cmr;
75 int ret;
76
77 ret = clk_prepare_enable(tcbpwmc->clk);
78 if (ret)
79 return ret;
80
81 tcbpwm->duty = 0;
82 tcbpwm->period = 0;
83 tcbpwm->div = 0;
84
85 guard(spinlock)(&tcbpwmc->lock);
86
87 regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
88 /*
89 * Get init config from Timer Counter registers if
90 * Timer Counter is already configured as a PWM generator.
91 */
92 if (cmr & ATMEL_TC_WAVE) {
93 if (pwm->hwpwm == 0)
94 regmap_read(tcbpwmc->regmap,
95 ATMEL_TC_REG(tcbpwmc->channel, RA),
96 &tcbpwm->duty);
97 else
98 regmap_read(tcbpwmc->regmap,
99 ATMEL_TC_REG(tcbpwmc->channel, RB),
100 &tcbpwm->duty);
101
102 tcbpwm->div = cmr & ATMEL_TC_TCCLKS;
103 regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
104 &tcbpwm->period);
105 cmr &= (ATMEL_TC_TCCLKS | ATMEL_TC_ACMR_MASK |
106 ATMEL_TC_BCMR_MASK);
107 } else
108 cmr = 0;
109
110 cmr |= ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO | ATMEL_TC_EEVT_XC0;
111 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
112
113 return 0;
114 }
115
atmel_tcb_pwm_free(struct pwm_chip * chip,struct pwm_device * pwm)116 static void atmel_tcb_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
117 {
118 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
119
120 clk_disable_unprepare(tcbpwmc->clk);
121 }
122
atmel_tcb_pwm_disable(struct pwm_chip * chip,struct pwm_device * pwm,enum pwm_polarity polarity)123 static void atmel_tcb_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,
124 enum pwm_polarity polarity)
125 {
126 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
127 struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
128 unsigned cmr;
129
130 /*
131 * If duty is 0 the timer will be stopped and we have to
132 * configure the output correctly on software trigger:
133 * - set output to high if PWM_POLARITY_INVERSED
134 * - set output to low if PWM_POLARITY_NORMAL
135 *
136 * This is why we're reverting polarity in this case.
137 */
138 if (tcbpwm->duty == 0)
139 polarity = !polarity;
140
141 regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
142
143 /* flush old setting and set the new one */
144 if (pwm->hwpwm == 0) {
145 cmr &= ~ATMEL_TC_ACMR_MASK;
146 if (polarity == PWM_POLARITY_INVERSED)
147 cmr |= ATMEL_TC_ASWTRG_CLEAR;
148 else
149 cmr |= ATMEL_TC_ASWTRG_SET;
150 } else {
151 cmr &= ~ATMEL_TC_BCMR_MASK;
152 if (polarity == PWM_POLARITY_INVERSED)
153 cmr |= ATMEL_TC_BSWTRG_CLEAR;
154 else
155 cmr |= ATMEL_TC_BSWTRG_SET;
156 }
157
158 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
159
160 /*
161 * Use software trigger to apply the new setting.
162 * If both PWM devices in this group are disabled we stop the clock.
163 */
164 if (!(cmr & (ATMEL_TC_ACPC | ATMEL_TC_BCPC))) {
165 regmap_write(tcbpwmc->regmap,
166 ATMEL_TC_REG(tcbpwmc->channel, CCR),
167 ATMEL_TC_SWTRG | ATMEL_TC_CLKDIS);
168 tcbpwmc->bkup.enabled = 1;
169 } else {
170 regmap_write(tcbpwmc->regmap,
171 ATMEL_TC_REG(tcbpwmc->channel, CCR),
172 ATMEL_TC_SWTRG);
173 tcbpwmc->bkup.enabled = 0;
174 }
175 }
176
atmel_tcb_pwm_enable(struct pwm_chip * chip,struct pwm_device * pwm,enum pwm_polarity polarity)177 static int atmel_tcb_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm,
178 enum pwm_polarity polarity)
179 {
180 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
181 struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
182 u32 cmr;
183
184 /*
185 * If duty is 0 the timer will be stopped and we have to
186 * configure the output correctly on software trigger:
187 * - set output to high if PWM_POLARITY_INVERSED
188 * - set output to low if PWM_POLARITY_NORMAL
189 *
190 * This is why we're reverting polarity in this case.
191 */
192 if (tcbpwm->duty == 0)
193 polarity = !polarity;
194
195 regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
196
197 /* flush old setting and set the new one */
198 cmr &= ~ATMEL_TC_TCCLKS;
199
200 if (pwm->hwpwm == 0) {
201 cmr &= ~ATMEL_TC_ACMR_MASK;
202
203 /* Set CMR flags according to given polarity */
204 if (polarity == PWM_POLARITY_INVERSED)
205 cmr |= ATMEL_TC_ASWTRG_CLEAR;
206 else
207 cmr |= ATMEL_TC_ASWTRG_SET;
208 } else {
209 cmr &= ~ATMEL_TC_BCMR_MASK;
210 if (polarity == PWM_POLARITY_INVERSED)
211 cmr |= ATMEL_TC_BSWTRG_CLEAR;
212 else
213 cmr |= ATMEL_TC_BSWTRG_SET;
214 }
215
216 /*
217 * If duty is 0 or equal to period there's no need to register
218 * a specific action on RA/RB and RC compare.
219 * The output will be configured on software trigger and keep
220 * this config till next config call.
221 */
222 if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) {
223 if (pwm->hwpwm == 0) {
224 if (polarity == PWM_POLARITY_INVERSED)
225 cmr |= ATMEL_TC_ACPA_SET | ATMEL_TC_ACPC_CLEAR;
226 else
227 cmr |= ATMEL_TC_ACPA_CLEAR | ATMEL_TC_ACPC_SET;
228 } else {
229 if (polarity == PWM_POLARITY_INVERSED)
230 cmr |= ATMEL_TC_BCPB_SET | ATMEL_TC_BCPC_CLEAR;
231 else
232 cmr |= ATMEL_TC_BCPB_CLEAR | ATMEL_TC_BCPC_SET;
233 }
234 }
235
236 cmr |= (tcbpwm->div & ATMEL_TC_TCCLKS);
237
238 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
239
240 if (pwm->hwpwm == 0)
241 regmap_write(tcbpwmc->regmap,
242 ATMEL_TC_REG(tcbpwmc->channel, RA),
243 tcbpwm->duty);
244 else
245 regmap_write(tcbpwmc->regmap,
246 ATMEL_TC_REG(tcbpwmc->channel, RB),
247 tcbpwm->duty);
248
249 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
250 tcbpwm->period);
251
252 /* Use software trigger to apply the new setting */
253 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CCR),
254 ATMEL_TC_SWTRG | ATMEL_TC_CLKEN);
255 tcbpwmc->bkup.enabled = 1;
256 return 0;
257 }
258
atmel_tcb_pwm_config(struct pwm_chip * chip,struct pwm_device * pwm,int duty_ns,int period_ns)259 static int atmel_tcb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
260 int duty_ns, int period_ns)
261 {
262 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
263 struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
264 struct atmel_tcb_pwm_device *atcbpwm = NULL;
265 int i = 0;
266 int slowclk = 0;
267 unsigned period;
268 unsigned duty;
269 unsigned rate = clk_get_rate(tcbpwmc->clk);
270 unsigned long long min;
271 unsigned long long max;
272
273 /*
274 * Find best clk divisor:
275 * the smallest divisor which can fulfill the period_ns requirements.
276 * If there is a gclk, the first divisor is actually the gclk selector
277 */
278 if (tcbpwmc->gclk)
279 i = 1;
280 for (; i < ARRAY_SIZE(atmel_tcb_divisors); ++i) {
281 if (atmel_tcb_divisors[i] == 0) {
282 slowclk = i;
283 continue;
284 }
285 min = div_u64((u64)NSEC_PER_SEC * atmel_tcb_divisors[i], rate);
286 max = min << tcbpwmc->width;
287 if (max >= period_ns)
288 break;
289 }
290
291 /*
292 * If none of the divisor are small enough to represent period_ns
293 * take slow clock (32KHz).
294 */
295 if (i == ARRAY_SIZE(atmel_tcb_divisors)) {
296 i = slowclk;
297 rate = clk_get_rate(tcbpwmc->slow_clk);
298 min = div_u64(NSEC_PER_SEC, rate);
299 max = min << tcbpwmc->width;
300
301 /* If period is too big return ERANGE error */
302 if (max < period_ns)
303 return -ERANGE;
304 }
305
306 duty = div_u64(duty_ns, min);
307 period = div_u64(period_ns, min);
308
309 if (pwm->hwpwm == 0)
310 atcbpwm = &tcbpwmc->pwms[1];
311 else
312 atcbpwm = &tcbpwmc->pwms[0];
313
314 /*
315 * PWM devices provided by the TCB driver are grouped by 2.
316 * PWM devices in a given group must be configured with the
317 * same period_ns.
318 *
319 * We're checking the period value of the second PWM device
320 * in this group before applying the new config.
321 */
322 if ((atcbpwm && atcbpwm->duty > 0 &&
323 atcbpwm->duty != atcbpwm->period) &&
324 (atcbpwm->div != i || atcbpwm->period != period)) {
325 dev_err(chip->dev,
326 "failed to configure period_ns: PWM group already configured with a different value\n");
327 return -EINVAL;
328 }
329
330 tcbpwm->period = period;
331 tcbpwm->div = i;
332 tcbpwm->duty = duty;
333
334 return 0;
335 }
336
atmel_tcb_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)337 static int atmel_tcb_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
338 const struct pwm_state *state)
339 {
340 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
341 int duty_cycle, period;
342 int ret;
343
344 guard(spinlock)(&tcbpwmc->lock);
345
346 if (!state->enabled) {
347 atmel_tcb_pwm_disable(chip, pwm, state->polarity);
348 return 0;
349 }
350
351 period = state->period < INT_MAX ? state->period : INT_MAX;
352 duty_cycle = state->duty_cycle < INT_MAX ? state->duty_cycle : INT_MAX;
353
354 ret = atmel_tcb_pwm_config(chip, pwm, duty_cycle, period);
355 if (ret)
356 return ret;
357
358 return atmel_tcb_pwm_enable(chip, pwm, state->polarity);
359 }
360
361 static const struct pwm_ops atmel_tcb_pwm_ops = {
362 .request = atmel_tcb_pwm_request,
363 .free = atmel_tcb_pwm_free,
364 .apply = atmel_tcb_pwm_apply,
365 .owner = THIS_MODULE,
366 };
367
368 static struct atmel_tcb_config tcb_rm9200_config = {
369 .counter_width = 16,
370 };
371
372 static struct atmel_tcb_config tcb_sam9x5_config = {
373 .counter_width = 32,
374 };
375
376 static struct atmel_tcb_config tcb_sama5d2_config = {
377 .counter_width = 32,
378 .has_gclk = 1,
379 };
380
381 static const struct of_device_id atmel_tcb_of_match[] = {
382 { .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
383 { .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
384 { .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
385 { /* sentinel */ }
386 };
387
atmel_tcb_pwm_probe(struct platform_device * pdev)388 static int atmel_tcb_pwm_probe(struct platform_device *pdev)
389 {
390 const struct of_device_id *match;
391 struct atmel_tcb_pwm_chip *tcbpwm;
392 const struct atmel_tcb_config *config;
393 struct device_node *np = pdev->dev.of_node;
394 char clk_name[] = "t0_clk";
395 int err;
396 int channel;
397
398 tcbpwm = devm_kzalloc(&pdev->dev, sizeof(*tcbpwm), GFP_KERNEL);
399 if (tcbpwm == NULL)
400 return -ENOMEM;
401
402 err = of_property_read_u32(np, "reg", &channel);
403 if (err < 0) {
404 dev_err(&pdev->dev,
405 "failed to get Timer Counter Block channel from device tree (error: %d)\n",
406 err);
407 return err;
408 }
409
410 tcbpwm->regmap = syscon_node_to_regmap(np->parent);
411 if (IS_ERR(tcbpwm->regmap))
412 return PTR_ERR(tcbpwm->regmap);
413
414 tcbpwm->slow_clk = of_clk_get_by_name(np->parent, "slow_clk");
415 if (IS_ERR(tcbpwm->slow_clk))
416 return PTR_ERR(tcbpwm->slow_clk);
417
418 clk_name[1] += channel;
419 tcbpwm->clk = of_clk_get_by_name(np->parent, clk_name);
420 if (IS_ERR(tcbpwm->clk))
421 tcbpwm->clk = of_clk_get_by_name(np->parent, "t0_clk");
422 if (IS_ERR(tcbpwm->clk)) {
423 err = PTR_ERR(tcbpwm->clk);
424 goto err_slow_clk;
425 }
426
427 match = of_match_node(atmel_tcb_of_match, np->parent);
428 config = match->data;
429
430 if (config->has_gclk) {
431 tcbpwm->gclk = of_clk_get_by_name(np->parent, "gclk");
432 if (IS_ERR(tcbpwm->gclk)) {
433 err = PTR_ERR(tcbpwm->gclk);
434 goto err_clk;
435 }
436 }
437
438 tcbpwm->chip.dev = &pdev->dev;
439 tcbpwm->chip.ops = &atmel_tcb_pwm_ops;
440 tcbpwm->chip.npwm = NPWM;
441 tcbpwm->channel = channel;
442 tcbpwm->width = config->counter_width;
443
444 err = clk_prepare_enable(tcbpwm->slow_clk);
445 if (err)
446 goto err_gclk;
447
448 spin_lock_init(&tcbpwm->lock);
449
450 err = pwmchip_add(&tcbpwm->chip);
451 if (err < 0)
452 goto err_disable_clk;
453
454 platform_set_drvdata(pdev, tcbpwm);
455
456 return 0;
457
458 err_disable_clk:
459 clk_disable_unprepare(tcbpwm->slow_clk);
460
461 err_gclk:
462 clk_put(tcbpwm->gclk);
463
464 err_clk:
465 clk_put(tcbpwm->clk);
466
467 err_slow_clk:
468 clk_put(tcbpwm->slow_clk);
469
470 return err;
471 }
472
atmel_tcb_pwm_remove(struct platform_device * pdev)473 static void atmel_tcb_pwm_remove(struct platform_device *pdev)
474 {
475 struct atmel_tcb_pwm_chip *tcbpwm = platform_get_drvdata(pdev);
476
477 pwmchip_remove(&tcbpwm->chip);
478
479 clk_disable_unprepare(tcbpwm->slow_clk);
480 clk_put(tcbpwm->gclk);
481 clk_put(tcbpwm->clk);
482 clk_put(tcbpwm->slow_clk);
483 }
484
485 static const struct of_device_id atmel_tcb_pwm_dt_ids[] = {
486 { .compatible = "atmel,tcb-pwm", },
487 { /* sentinel */ }
488 };
489 MODULE_DEVICE_TABLE(of, atmel_tcb_pwm_dt_ids);
490
491 #ifdef CONFIG_PM_SLEEP
atmel_tcb_pwm_suspend(struct device * dev)492 static int atmel_tcb_pwm_suspend(struct device *dev)
493 {
494 struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev);
495 struct atmel_tcb_channel *chan = &tcbpwm->bkup;
496 unsigned int channel = tcbpwm->channel;
497
498 regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, CMR), &chan->cmr);
499 regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RA), &chan->ra);
500 regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RB), &chan->rb);
501 regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RC), &chan->rc);
502
503 return 0;
504 }
505
atmel_tcb_pwm_resume(struct device * dev)506 static int atmel_tcb_pwm_resume(struct device *dev)
507 {
508 struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev);
509 struct atmel_tcb_channel *chan = &tcbpwm->bkup;
510 unsigned int channel = tcbpwm->channel;
511
512 regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, CMR), chan->cmr);
513 regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RA), chan->ra);
514 regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RB), chan->rb);
515 regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RC), chan->rc);
516
517 if (chan->enabled)
518 regmap_write(tcbpwm->regmap,
519 ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
520 ATMEL_TC_REG(channel, CCR));
521
522 return 0;
523 }
524 #endif
525
526 static SIMPLE_DEV_PM_OPS(atmel_tcb_pwm_pm_ops, atmel_tcb_pwm_suspend,
527 atmel_tcb_pwm_resume);
528
529 static struct platform_driver atmel_tcb_pwm_driver = {
530 .driver = {
531 .name = "atmel-tcb-pwm",
532 .of_match_table = atmel_tcb_pwm_dt_ids,
533 .pm = &atmel_tcb_pwm_pm_ops,
534 },
535 .probe = atmel_tcb_pwm_probe,
536 .remove_new = atmel_tcb_pwm_remove,
537 };
538 module_platform_driver(atmel_tcb_pwm_driver);
539
540 MODULE_AUTHOR("Boris BREZILLON <b.brezillon@overkiz.com>");
541 MODULE_DESCRIPTION("Atmel Timer Counter Pulse Width Modulation Driver");
542 MODULE_LICENSE("GPL v2");
543