1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6 #include <linux/skbuff.h>
7 #include <linux/ctype.h>
8 #include <net/mac80211.h>
9 #include <net/cfg80211.h>
10 #include <linux/completion.h>
11 #include <linux/if_ether.h>
12 #include <linux/types.h>
13 #include <linux/pci.h>
14 #include <linux/uuid.h>
15 #include <linux/time.h>
16 #include <linux/of.h>
17 #include "core.h"
18 #include "debug.h"
19 #include "mac.h"
20 #include "hw.h"
21 #include "peer.h"
22
23 struct ath12k_wmi_svc_ready_parse {
24 bool wmi_svc_bitmap_done;
25 };
26
27 struct ath12k_wmi_dma_ring_caps_parse {
28 struct ath12k_wmi_dma_ring_caps_params *dma_ring_caps;
29 u32 n_dma_ring_caps;
30 };
31
32 struct ath12k_wmi_service_ext_arg {
33 u32 default_conc_scan_config_bits;
34 u32 default_fw_config_bits;
35 struct ath12k_wmi_ppe_threshold_arg ppet;
36 u32 he_cap_info;
37 u32 mpdu_density;
38 u32 max_bssid_rx_filters;
39 u32 num_hw_modes;
40 u32 num_phy;
41 };
42
43 struct ath12k_wmi_svc_rdy_ext_parse {
44 struct ath12k_wmi_service_ext_arg arg;
45 const struct ath12k_wmi_soc_mac_phy_hw_mode_caps_params *hw_caps;
46 const struct ath12k_wmi_hw_mode_cap_params *hw_mode_caps;
47 u32 n_hw_mode_caps;
48 u32 tot_phy_id;
49 struct ath12k_wmi_hw_mode_cap_params pref_hw_mode_caps;
50 struct ath12k_wmi_mac_phy_caps_params *mac_phy_caps;
51 u32 n_mac_phy_caps;
52 const struct ath12k_wmi_soc_hal_reg_caps_params *soc_hal_reg_caps;
53 const struct ath12k_wmi_hal_reg_caps_ext_params *ext_hal_reg_caps;
54 u32 n_ext_hal_reg_caps;
55 struct ath12k_wmi_dma_ring_caps_parse dma_caps_parse;
56 bool hw_mode_done;
57 bool mac_phy_done;
58 bool ext_hal_reg_done;
59 bool mac_phy_chainmask_combo_done;
60 bool mac_phy_chainmask_cap_done;
61 bool oem_dma_ring_cap_done;
62 bool dma_ring_cap_done;
63 };
64
65 struct ath12k_wmi_svc_rdy_ext2_arg {
66 u32 reg_db_version;
67 u32 hw_min_max_tx_power_2ghz;
68 u32 hw_min_max_tx_power_5ghz;
69 u32 chwidth_num_peer_caps;
70 u32 preamble_puncture_bw;
71 u32 max_user_per_ppdu_ofdma;
72 u32 max_user_per_ppdu_mumimo;
73 u32 target_cap_flags;
74 u32 eht_cap_mac_info[WMI_MAX_EHTCAP_MAC_SIZE];
75 u32 max_num_linkview_peers;
76 u32 max_num_msduq_supported_per_tid;
77 u32 default_num_msduq_supported_per_tid;
78 };
79
80 struct ath12k_wmi_svc_rdy_ext2_parse {
81 struct ath12k_wmi_svc_rdy_ext2_arg arg;
82 struct ath12k_wmi_dma_ring_caps_parse dma_caps_parse;
83 bool dma_ring_cap_done;
84 bool spectral_bin_scaling_done;
85 bool mac_phy_caps_ext_done;
86 };
87
88 struct ath12k_wmi_rdy_parse {
89 u32 num_extra_mac_addr;
90 };
91
92 struct ath12k_wmi_dma_buf_release_arg {
93 struct ath12k_wmi_dma_buf_release_fixed_params fixed;
94 const struct ath12k_wmi_dma_buf_release_entry_params *buf_entry;
95 const struct ath12k_wmi_dma_buf_release_meta_data_params *meta_data;
96 u32 num_buf_entry;
97 u32 num_meta;
98 bool buf_entry_done;
99 bool meta_data_done;
100 };
101
102 struct ath12k_wmi_tlv_policy {
103 size_t min_len;
104 };
105
106 struct wmi_tlv_mgmt_rx_parse {
107 const struct ath12k_wmi_mgmt_rx_params *fixed;
108 const u8 *frame_buf;
109 bool frame_buf_done;
110 };
111
112 static const struct ath12k_wmi_tlv_policy ath12k_wmi_tlv_policies[] = {
113 [WMI_TAG_ARRAY_BYTE] = { .min_len = 0 },
114 [WMI_TAG_ARRAY_UINT32] = { .min_len = 0 },
115 [WMI_TAG_SERVICE_READY_EVENT] = {
116 .min_len = sizeof(struct wmi_service_ready_event) },
117 [WMI_TAG_SERVICE_READY_EXT_EVENT] = {
118 .min_len = sizeof(struct wmi_service_ready_ext_event) },
119 [WMI_TAG_SOC_MAC_PHY_HW_MODE_CAPS] = {
120 .min_len = sizeof(struct ath12k_wmi_soc_mac_phy_hw_mode_caps_params) },
121 [WMI_TAG_SOC_HAL_REG_CAPABILITIES] = {
122 .min_len = sizeof(struct ath12k_wmi_soc_hal_reg_caps_params) },
123 [WMI_TAG_VDEV_START_RESPONSE_EVENT] = {
124 .min_len = sizeof(struct wmi_vdev_start_resp_event) },
125 [WMI_TAG_PEER_DELETE_RESP_EVENT] = {
126 .min_len = sizeof(struct wmi_peer_delete_resp_event) },
127 [WMI_TAG_OFFLOAD_BCN_TX_STATUS_EVENT] = {
128 .min_len = sizeof(struct wmi_bcn_tx_status_event) },
129 [WMI_TAG_VDEV_STOPPED_EVENT] = {
130 .min_len = sizeof(struct wmi_vdev_stopped_event) },
131 [WMI_TAG_REG_CHAN_LIST_CC_EXT_EVENT] = {
132 .min_len = sizeof(struct wmi_reg_chan_list_cc_ext_event) },
133 [WMI_TAG_MGMT_RX_HDR] = {
134 .min_len = sizeof(struct ath12k_wmi_mgmt_rx_params) },
135 [WMI_TAG_MGMT_TX_COMPL_EVENT] = {
136 .min_len = sizeof(struct wmi_mgmt_tx_compl_event) },
137 [WMI_TAG_SCAN_EVENT] = {
138 .min_len = sizeof(struct wmi_scan_event) },
139 [WMI_TAG_PEER_STA_KICKOUT_EVENT] = {
140 .min_len = sizeof(struct wmi_peer_sta_kickout_event) },
141 [WMI_TAG_ROAM_EVENT] = {
142 .min_len = sizeof(struct wmi_roam_event) },
143 [WMI_TAG_CHAN_INFO_EVENT] = {
144 .min_len = sizeof(struct wmi_chan_info_event) },
145 [WMI_TAG_PDEV_BSS_CHAN_INFO_EVENT] = {
146 .min_len = sizeof(struct wmi_pdev_bss_chan_info_event) },
147 [WMI_TAG_VDEV_INSTALL_KEY_COMPLETE_EVENT] = {
148 .min_len = sizeof(struct wmi_vdev_install_key_compl_event) },
149 [WMI_TAG_READY_EVENT] = {
150 .min_len = sizeof(struct ath12k_wmi_ready_event_min_params) },
151 [WMI_TAG_SERVICE_AVAILABLE_EVENT] = {
152 .min_len = sizeof(struct wmi_service_available_event) },
153 [WMI_TAG_PEER_ASSOC_CONF_EVENT] = {
154 .min_len = sizeof(struct wmi_peer_assoc_conf_event) },
155 [WMI_TAG_PDEV_CTL_FAILSAFE_CHECK_EVENT] = {
156 .min_len = sizeof(struct wmi_pdev_ctl_failsafe_chk_event) },
157 [WMI_TAG_HOST_SWFDA_EVENT] = {
158 .min_len = sizeof(struct wmi_fils_discovery_event) },
159 [WMI_TAG_OFFLOAD_PRB_RSP_TX_STATUS_EVENT] = {
160 .min_len = sizeof(struct wmi_probe_resp_tx_status_event) },
161 [WMI_TAG_VDEV_DELETE_RESP_EVENT] = {
162 .min_len = sizeof(struct wmi_vdev_delete_resp_event) },
163 };
164
ath12k_wmi_tlv_hdr(u32 cmd,u32 len)165 static __le32 ath12k_wmi_tlv_hdr(u32 cmd, u32 len)
166 {
167 return le32_encode_bits(cmd, WMI_TLV_TAG) |
168 le32_encode_bits(len, WMI_TLV_LEN);
169 }
170
ath12k_wmi_tlv_cmd_hdr(u32 cmd,u32 len)171 static __le32 ath12k_wmi_tlv_cmd_hdr(u32 cmd, u32 len)
172 {
173 return ath12k_wmi_tlv_hdr(cmd, len - TLV_HDR_SIZE);
174 }
175
ath12k_wmi_init_qcn9274(struct ath12k_base * ab,struct ath12k_wmi_resource_config_arg * config)176 void ath12k_wmi_init_qcn9274(struct ath12k_base *ab,
177 struct ath12k_wmi_resource_config_arg *config)
178 {
179 config->num_vdevs = ab->num_radios * TARGET_NUM_VDEVS;
180
181 if (ab->num_radios == 2) {
182 config->num_peers = TARGET_NUM_PEERS(DBS);
183 config->num_tids = TARGET_NUM_TIDS(DBS);
184 } else if (ab->num_radios == 3) {
185 config->num_peers = TARGET_NUM_PEERS(DBS_SBS);
186 config->num_tids = TARGET_NUM_TIDS(DBS_SBS);
187 } else {
188 /* Control should not reach here */
189 config->num_peers = TARGET_NUM_PEERS(SINGLE);
190 config->num_tids = TARGET_NUM_TIDS(SINGLE);
191 }
192 config->num_offload_peers = TARGET_NUM_OFFLD_PEERS;
193 config->num_offload_reorder_buffs = TARGET_NUM_OFFLD_REORDER_BUFFS;
194 config->num_peer_keys = TARGET_NUM_PEER_KEYS;
195 config->ast_skid_limit = TARGET_AST_SKID_LIMIT;
196 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
197 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
198 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI;
199 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI;
200 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI;
201 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI;
202
203 if (test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags))
204 config->rx_decap_mode = TARGET_DECAP_MODE_RAW;
205 else
206 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI;
207
208 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS;
209 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV;
210 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV;
211 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES;
212 config->num_mcast_groups = TARGET_NUM_MCAST_GROUPS;
213 config->num_mcast_table_elems = TARGET_NUM_MCAST_TABLE_ELEMS;
214 config->mcast2ucast_mode = TARGET_MCAST2UCAST_MODE;
215 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE;
216 config->num_wds_entries = TARGET_NUM_WDS_ENTRIES;
217 config->dma_burst_size = TARGET_DMA_BURST_SIZE;
218 config->rx_skip_defrag_timeout_dup_detection_check =
219 TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK;
220 config->vow_config = TARGET_VOW_CONFIG;
221 config->gtk_offload_max_vdev = TARGET_GTK_OFFLOAD_MAX_VDEV;
222 config->num_msdu_desc = TARGET_NUM_MSDU_DESC;
223 config->beacon_tx_offload_max_vdev = ab->num_radios * TARGET_MAX_BCN_OFFLD;
224 config->rx_batchmode = TARGET_RX_BATCHMODE;
225 /* Indicates host supports peer map v3 and unmap v2 support */
226 config->peer_map_unmap_version = 0x32;
227 config->twt_ap_pdev_count = ab->num_radios;
228 config->twt_ap_sta_count = 1000;
229 }
230
ath12k_wmi_init_wcn7850(struct ath12k_base * ab,struct ath12k_wmi_resource_config_arg * config)231 void ath12k_wmi_init_wcn7850(struct ath12k_base *ab,
232 struct ath12k_wmi_resource_config_arg *config)
233 {
234 config->num_vdevs = 4;
235 config->num_peers = 16;
236 config->num_tids = 32;
237
238 config->num_offload_peers = 3;
239 config->num_offload_reorder_buffs = 3;
240 config->num_peer_keys = TARGET_NUM_PEER_KEYS;
241 config->ast_skid_limit = TARGET_AST_SKID_LIMIT;
242 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
243 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
244 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI;
245 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI;
246 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI;
247 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI;
248 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI;
249 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS;
250 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV;
251 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV;
252 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES;
253 config->num_mcast_groups = 0;
254 config->num_mcast_table_elems = 0;
255 config->mcast2ucast_mode = 0;
256 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE;
257 config->num_wds_entries = 0;
258 config->dma_burst_size = 0;
259 config->rx_skip_defrag_timeout_dup_detection_check = 0;
260 config->vow_config = TARGET_VOW_CONFIG;
261 config->gtk_offload_max_vdev = 2;
262 config->num_msdu_desc = 0x400;
263 config->beacon_tx_offload_max_vdev = 2;
264 config->rx_batchmode = TARGET_RX_BATCHMODE;
265
266 config->peer_map_unmap_version = 0x1;
267 config->use_pdev_id = 1;
268 config->max_frag_entries = 0xa;
269 config->num_tdls_vdevs = 0x1;
270 config->num_tdls_conn_table_entries = 8;
271 config->beacon_tx_offload_max_vdev = 0x2;
272 config->num_multicast_filter_entries = 0x20;
273 config->num_wow_filters = 0x16;
274 config->num_keep_alive_pattern = 0;
275 }
276
277 #define PRIMAP(_hw_mode_) \
278 [_hw_mode_] = _hw_mode_##_PRI
279
280 static const int ath12k_hw_mode_pri_map[] = {
281 PRIMAP(WMI_HOST_HW_MODE_SINGLE),
282 PRIMAP(WMI_HOST_HW_MODE_DBS),
283 PRIMAP(WMI_HOST_HW_MODE_SBS_PASSIVE),
284 PRIMAP(WMI_HOST_HW_MODE_SBS),
285 PRIMAP(WMI_HOST_HW_MODE_DBS_SBS),
286 PRIMAP(WMI_HOST_HW_MODE_DBS_OR_SBS),
287 /* keep last */
288 PRIMAP(WMI_HOST_HW_MODE_MAX),
289 };
290
291 static int
ath12k_wmi_tlv_iter(struct ath12k_base * ab,const void * ptr,size_t len,int (* iter)(struct ath12k_base * ab,u16 tag,u16 len,const void * ptr,void * data),void * data)292 ath12k_wmi_tlv_iter(struct ath12k_base *ab, const void *ptr, size_t len,
293 int (*iter)(struct ath12k_base *ab, u16 tag, u16 len,
294 const void *ptr, void *data),
295 void *data)
296 {
297 const void *begin = ptr;
298 const struct wmi_tlv *tlv;
299 u16 tlv_tag, tlv_len;
300 int ret;
301
302 while (len > 0) {
303 if (len < sizeof(*tlv)) {
304 ath12k_err(ab, "wmi tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n",
305 ptr - begin, len, sizeof(*tlv));
306 return -EINVAL;
307 }
308
309 tlv = ptr;
310 tlv_tag = le32_get_bits(tlv->header, WMI_TLV_TAG);
311 tlv_len = le32_get_bits(tlv->header, WMI_TLV_LEN);
312 ptr += sizeof(*tlv);
313 len -= sizeof(*tlv);
314
315 if (tlv_len > len) {
316 ath12k_err(ab, "wmi tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n",
317 tlv_tag, ptr - begin, len, tlv_len);
318 return -EINVAL;
319 }
320
321 if (tlv_tag < ARRAY_SIZE(ath12k_wmi_tlv_policies) &&
322 ath12k_wmi_tlv_policies[tlv_tag].min_len &&
323 ath12k_wmi_tlv_policies[tlv_tag].min_len > tlv_len) {
324 ath12k_err(ab, "wmi tlv parse failure of tag %u at byte %zd (%u bytes is less than min length %zu)\n",
325 tlv_tag, ptr - begin, tlv_len,
326 ath12k_wmi_tlv_policies[tlv_tag].min_len);
327 return -EINVAL;
328 }
329
330 ret = iter(ab, tlv_tag, tlv_len, ptr, data);
331 if (ret)
332 return ret;
333
334 ptr += tlv_len;
335 len -= tlv_len;
336 }
337
338 return 0;
339 }
340
ath12k_wmi_tlv_iter_parse(struct ath12k_base * ab,u16 tag,u16 len,const void * ptr,void * data)341 static int ath12k_wmi_tlv_iter_parse(struct ath12k_base *ab, u16 tag, u16 len,
342 const void *ptr, void *data)
343 {
344 const void **tb = data;
345
346 if (tag < WMI_TAG_MAX)
347 tb[tag] = ptr;
348
349 return 0;
350 }
351
ath12k_wmi_tlv_parse(struct ath12k_base * ar,const void ** tb,const void * ptr,size_t len)352 static int ath12k_wmi_tlv_parse(struct ath12k_base *ar, const void **tb,
353 const void *ptr, size_t len)
354 {
355 return ath12k_wmi_tlv_iter(ar, ptr, len, ath12k_wmi_tlv_iter_parse,
356 (void *)tb);
357 }
358
359 static const void **
ath12k_wmi_tlv_parse_alloc(struct ath12k_base * ab,const void * ptr,size_t len,gfp_t gfp)360 ath12k_wmi_tlv_parse_alloc(struct ath12k_base *ab, const void *ptr,
361 size_t len, gfp_t gfp)
362 {
363 const void **tb;
364 int ret;
365
366 tb = kcalloc(WMI_TAG_MAX, sizeof(*tb), gfp);
367 if (!tb)
368 return ERR_PTR(-ENOMEM);
369
370 ret = ath12k_wmi_tlv_parse(ab, tb, ptr, len);
371 if (ret) {
372 kfree(tb);
373 return ERR_PTR(ret);
374 }
375
376 return tb;
377 }
378
ath12k_wmi_cmd_send_nowait(struct ath12k_wmi_pdev * wmi,struct sk_buff * skb,u32 cmd_id)379 static int ath12k_wmi_cmd_send_nowait(struct ath12k_wmi_pdev *wmi, struct sk_buff *skb,
380 u32 cmd_id)
381 {
382 struct ath12k_skb_cb *skb_cb = ATH12K_SKB_CB(skb);
383 struct ath12k_base *ab = wmi->wmi_ab->ab;
384 struct wmi_cmd_hdr *cmd_hdr;
385 int ret;
386
387 if (!skb_push(skb, sizeof(struct wmi_cmd_hdr)))
388 return -ENOMEM;
389
390 cmd_hdr = (struct wmi_cmd_hdr *)skb->data;
391 cmd_hdr->cmd_id = le32_encode_bits(cmd_id, WMI_CMD_HDR_CMD_ID);
392
393 memset(skb_cb, 0, sizeof(*skb_cb));
394 ret = ath12k_htc_send(&ab->htc, wmi->eid, skb);
395
396 if (ret)
397 goto err_pull;
398
399 return 0;
400
401 err_pull:
402 skb_pull(skb, sizeof(struct wmi_cmd_hdr));
403 return ret;
404 }
405
ath12k_wmi_cmd_send(struct ath12k_wmi_pdev * wmi,struct sk_buff * skb,u32 cmd_id)406 int ath12k_wmi_cmd_send(struct ath12k_wmi_pdev *wmi, struct sk_buff *skb,
407 u32 cmd_id)
408 {
409 struct ath12k_wmi_base *wmi_sc = wmi->wmi_ab;
410 int ret = -EOPNOTSUPP;
411
412 might_sleep();
413
414 wait_event_timeout(wmi_sc->tx_credits_wq, ({
415 ret = ath12k_wmi_cmd_send_nowait(wmi, skb, cmd_id);
416
417 if (ret && test_bit(ATH12K_FLAG_CRASH_FLUSH, &wmi_sc->ab->dev_flags))
418 ret = -ESHUTDOWN;
419
420 (ret != -EAGAIN);
421 }), WMI_SEND_TIMEOUT_HZ);
422
423 if (ret == -EAGAIN)
424 ath12k_warn(wmi_sc->ab, "wmi command %d timeout\n", cmd_id);
425
426 return ret;
427 }
428
ath12k_pull_svc_ready_ext(struct ath12k_wmi_pdev * wmi_handle,const void * ptr,struct ath12k_wmi_service_ext_arg * arg)429 static int ath12k_pull_svc_ready_ext(struct ath12k_wmi_pdev *wmi_handle,
430 const void *ptr,
431 struct ath12k_wmi_service_ext_arg *arg)
432 {
433 const struct wmi_service_ready_ext_event *ev = ptr;
434 int i;
435
436 if (!ev)
437 return -EINVAL;
438
439 /* Move this to host based bitmap */
440 arg->default_conc_scan_config_bits =
441 le32_to_cpu(ev->default_conc_scan_config_bits);
442 arg->default_fw_config_bits = le32_to_cpu(ev->default_fw_config_bits);
443 arg->he_cap_info = le32_to_cpu(ev->he_cap_info);
444 arg->mpdu_density = le32_to_cpu(ev->mpdu_density);
445 arg->max_bssid_rx_filters = le32_to_cpu(ev->max_bssid_rx_filters);
446 arg->ppet.numss_m1 = le32_to_cpu(ev->ppet.numss_m1);
447 arg->ppet.ru_bit_mask = le32_to_cpu(ev->ppet.ru_info);
448
449 for (i = 0; i < WMI_MAX_NUM_SS; i++)
450 arg->ppet.ppet16_ppet8_ru3_ru0[i] =
451 le32_to_cpu(ev->ppet.ppet16_ppet8_ru3_ru0[i]);
452
453 return 0;
454 }
455
456 static int
ath12k_pull_mac_phy_cap_svc_ready_ext(struct ath12k_wmi_pdev * wmi_handle,struct ath12k_wmi_svc_rdy_ext_parse * svc,u8 hw_mode_id,u8 phy_id,struct ath12k_pdev * pdev)457 ath12k_pull_mac_phy_cap_svc_ready_ext(struct ath12k_wmi_pdev *wmi_handle,
458 struct ath12k_wmi_svc_rdy_ext_parse *svc,
459 u8 hw_mode_id, u8 phy_id,
460 struct ath12k_pdev *pdev)
461 {
462 const struct ath12k_wmi_mac_phy_caps_params *mac_caps;
463 const struct ath12k_wmi_soc_mac_phy_hw_mode_caps_params *hw_caps = svc->hw_caps;
464 const struct ath12k_wmi_hw_mode_cap_params *wmi_hw_mode_caps = svc->hw_mode_caps;
465 const struct ath12k_wmi_mac_phy_caps_params *wmi_mac_phy_caps = svc->mac_phy_caps;
466 struct ath12k_base *ab = wmi_handle->wmi_ab->ab;
467 struct ath12k_band_cap *cap_band;
468 struct ath12k_pdev_cap *pdev_cap = &pdev->cap;
469 struct ath12k_fw_pdev *fw_pdev;
470 u32 phy_map;
471 u32 hw_idx, phy_idx = 0;
472 int i;
473
474 if (!hw_caps || !wmi_hw_mode_caps || !svc->soc_hal_reg_caps)
475 return -EINVAL;
476
477 for (hw_idx = 0; hw_idx < le32_to_cpu(hw_caps->num_hw_modes); hw_idx++) {
478 if (hw_mode_id == le32_to_cpu(wmi_hw_mode_caps[hw_idx].hw_mode_id))
479 break;
480
481 phy_map = le32_to_cpu(wmi_hw_mode_caps[hw_idx].phy_id_map);
482 phy_idx = fls(phy_map);
483 }
484
485 if (hw_idx == le32_to_cpu(hw_caps->num_hw_modes))
486 return -EINVAL;
487
488 phy_idx += phy_id;
489 if (phy_id >= le32_to_cpu(svc->soc_hal_reg_caps->num_phy))
490 return -EINVAL;
491
492 mac_caps = wmi_mac_phy_caps + phy_idx;
493
494 pdev->pdev_id = le32_to_cpu(mac_caps->pdev_id);
495 pdev_cap->supported_bands |= le32_to_cpu(mac_caps->supported_bands);
496 pdev_cap->ampdu_density = le32_to_cpu(mac_caps->ampdu_density);
497
498 fw_pdev = &ab->fw_pdev[ab->fw_pdev_count];
499 fw_pdev->supported_bands = le32_to_cpu(mac_caps->supported_bands);
500 fw_pdev->pdev_id = le32_to_cpu(mac_caps->pdev_id);
501 fw_pdev->phy_id = le32_to_cpu(mac_caps->phy_id);
502 ab->fw_pdev_count++;
503
504 /* Take non-zero tx/rx chainmask. If tx/rx chainmask differs from
505 * band to band for a single radio, need to see how this should be
506 * handled.
507 */
508 if (le32_to_cpu(mac_caps->supported_bands) & WMI_HOST_WLAN_2G_CAP) {
509 pdev_cap->tx_chain_mask = le32_to_cpu(mac_caps->tx_chain_mask_2g);
510 pdev_cap->rx_chain_mask = le32_to_cpu(mac_caps->rx_chain_mask_2g);
511 } else if (le32_to_cpu(mac_caps->supported_bands) & WMI_HOST_WLAN_5G_CAP) {
512 pdev_cap->vht_cap = le32_to_cpu(mac_caps->vht_cap_info_5g);
513 pdev_cap->vht_mcs = le32_to_cpu(mac_caps->vht_supp_mcs_5g);
514 pdev_cap->he_mcs = le32_to_cpu(mac_caps->he_supp_mcs_5g);
515 pdev_cap->tx_chain_mask = le32_to_cpu(mac_caps->tx_chain_mask_5g);
516 pdev_cap->rx_chain_mask = le32_to_cpu(mac_caps->rx_chain_mask_5g);
517 } else {
518 return -EINVAL;
519 }
520
521 /* tx/rx chainmask reported from fw depends on the actual hw chains used,
522 * For example, for 4x4 capable macphys, first 4 chains can be used for first
523 * mac and the remaining 4 chains can be used for the second mac or vice-versa.
524 * In this case, tx/rx chainmask 0xf will be advertised for first mac and 0xf0
525 * will be advertised for second mac or vice-versa. Compute the shift value
526 * for tx/rx chainmask which will be used to advertise supported ht/vht rates to
527 * mac80211.
528 */
529 pdev_cap->tx_chain_mask_shift =
530 find_first_bit((unsigned long *)&pdev_cap->tx_chain_mask, 32);
531 pdev_cap->rx_chain_mask_shift =
532 find_first_bit((unsigned long *)&pdev_cap->rx_chain_mask, 32);
533
534 if (le32_to_cpu(mac_caps->supported_bands) & WMI_HOST_WLAN_2G_CAP) {
535 cap_band = &pdev_cap->band[NL80211_BAND_2GHZ];
536 cap_band->phy_id = le32_to_cpu(mac_caps->phy_id);
537 cap_band->max_bw_supported = le32_to_cpu(mac_caps->max_bw_supported_2g);
538 cap_band->ht_cap_info = le32_to_cpu(mac_caps->ht_cap_info_2g);
539 cap_band->he_cap_info[0] = le32_to_cpu(mac_caps->he_cap_info_2g);
540 cap_band->he_cap_info[1] = le32_to_cpu(mac_caps->he_cap_info_2g_ext);
541 cap_band->he_mcs = le32_to_cpu(mac_caps->he_supp_mcs_2g);
542 for (i = 0; i < WMI_MAX_HECAP_PHY_SIZE; i++)
543 cap_band->he_cap_phy_info[i] =
544 le32_to_cpu(mac_caps->he_cap_phy_info_2g[i]);
545
546 cap_band->he_ppet.numss_m1 = le32_to_cpu(mac_caps->he_ppet2g.numss_m1);
547 cap_band->he_ppet.ru_bit_mask = le32_to_cpu(mac_caps->he_ppet2g.ru_info);
548
549 for (i = 0; i < WMI_MAX_NUM_SS; i++)
550 cap_band->he_ppet.ppet16_ppet8_ru3_ru0[i] =
551 le32_to_cpu(mac_caps->he_ppet2g.ppet16_ppet8_ru3_ru0[i]);
552 }
553
554 if (le32_to_cpu(mac_caps->supported_bands) & WMI_HOST_WLAN_5G_CAP) {
555 cap_band = &pdev_cap->band[NL80211_BAND_5GHZ];
556 cap_band->phy_id = le32_to_cpu(mac_caps->phy_id);
557 cap_band->max_bw_supported =
558 le32_to_cpu(mac_caps->max_bw_supported_5g);
559 cap_band->ht_cap_info = le32_to_cpu(mac_caps->ht_cap_info_5g);
560 cap_band->he_cap_info[0] = le32_to_cpu(mac_caps->he_cap_info_5g);
561 cap_band->he_cap_info[1] = le32_to_cpu(mac_caps->he_cap_info_5g_ext);
562 cap_band->he_mcs = le32_to_cpu(mac_caps->he_supp_mcs_5g);
563 for (i = 0; i < WMI_MAX_HECAP_PHY_SIZE; i++)
564 cap_band->he_cap_phy_info[i] =
565 le32_to_cpu(mac_caps->he_cap_phy_info_5g[i]);
566
567 cap_band->he_ppet.numss_m1 = le32_to_cpu(mac_caps->he_ppet5g.numss_m1);
568 cap_band->he_ppet.ru_bit_mask = le32_to_cpu(mac_caps->he_ppet5g.ru_info);
569
570 for (i = 0; i < WMI_MAX_NUM_SS; i++)
571 cap_band->he_ppet.ppet16_ppet8_ru3_ru0[i] =
572 le32_to_cpu(mac_caps->he_ppet5g.ppet16_ppet8_ru3_ru0[i]);
573
574 cap_band = &pdev_cap->band[NL80211_BAND_6GHZ];
575 cap_band->max_bw_supported =
576 le32_to_cpu(mac_caps->max_bw_supported_5g);
577 cap_band->ht_cap_info = le32_to_cpu(mac_caps->ht_cap_info_5g);
578 cap_band->he_cap_info[0] = le32_to_cpu(mac_caps->he_cap_info_5g);
579 cap_band->he_cap_info[1] = le32_to_cpu(mac_caps->he_cap_info_5g_ext);
580 cap_band->he_mcs = le32_to_cpu(mac_caps->he_supp_mcs_5g);
581 for (i = 0; i < WMI_MAX_HECAP_PHY_SIZE; i++)
582 cap_band->he_cap_phy_info[i] =
583 le32_to_cpu(mac_caps->he_cap_phy_info_5g[i]);
584
585 cap_band->he_ppet.numss_m1 = le32_to_cpu(mac_caps->he_ppet5g.numss_m1);
586 cap_band->he_ppet.ru_bit_mask = le32_to_cpu(mac_caps->he_ppet5g.ru_info);
587
588 for (i = 0; i < WMI_MAX_NUM_SS; i++)
589 cap_band->he_ppet.ppet16_ppet8_ru3_ru0[i] =
590 le32_to_cpu(mac_caps->he_ppet5g.ppet16_ppet8_ru3_ru0[i]);
591 }
592
593 return 0;
594 }
595
596 static int
ath12k_pull_reg_cap_svc_rdy_ext(struct ath12k_wmi_pdev * wmi_handle,const struct ath12k_wmi_soc_hal_reg_caps_params * reg_caps,const struct ath12k_wmi_hal_reg_caps_ext_params * ext_caps,u8 phy_idx,struct ath12k_wmi_hal_reg_capabilities_ext_arg * param)597 ath12k_pull_reg_cap_svc_rdy_ext(struct ath12k_wmi_pdev *wmi_handle,
598 const struct ath12k_wmi_soc_hal_reg_caps_params *reg_caps,
599 const struct ath12k_wmi_hal_reg_caps_ext_params *ext_caps,
600 u8 phy_idx,
601 struct ath12k_wmi_hal_reg_capabilities_ext_arg *param)
602 {
603 const struct ath12k_wmi_hal_reg_caps_ext_params *ext_reg_cap;
604
605 if (!reg_caps || !ext_caps)
606 return -EINVAL;
607
608 if (phy_idx >= le32_to_cpu(reg_caps->num_phy))
609 return -EINVAL;
610
611 ext_reg_cap = &ext_caps[phy_idx];
612
613 param->phy_id = le32_to_cpu(ext_reg_cap->phy_id);
614 param->eeprom_reg_domain = le32_to_cpu(ext_reg_cap->eeprom_reg_domain);
615 param->eeprom_reg_domain_ext =
616 le32_to_cpu(ext_reg_cap->eeprom_reg_domain_ext);
617 param->regcap1 = le32_to_cpu(ext_reg_cap->regcap1);
618 param->regcap2 = le32_to_cpu(ext_reg_cap->regcap2);
619 /* check if param->wireless_mode is needed */
620 param->low_2ghz_chan = le32_to_cpu(ext_reg_cap->low_2ghz_chan);
621 param->high_2ghz_chan = le32_to_cpu(ext_reg_cap->high_2ghz_chan);
622 param->low_5ghz_chan = le32_to_cpu(ext_reg_cap->low_5ghz_chan);
623 param->high_5ghz_chan = le32_to_cpu(ext_reg_cap->high_5ghz_chan);
624
625 return 0;
626 }
627
ath12k_pull_service_ready_tlv(struct ath12k_base * ab,const void * evt_buf,struct ath12k_wmi_target_cap_arg * cap)628 static int ath12k_pull_service_ready_tlv(struct ath12k_base *ab,
629 const void *evt_buf,
630 struct ath12k_wmi_target_cap_arg *cap)
631 {
632 const struct wmi_service_ready_event *ev = evt_buf;
633
634 if (!ev) {
635 ath12k_err(ab, "%s: failed by NULL param\n",
636 __func__);
637 return -EINVAL;
638 }
639
640 cap->phy_capability = le32_to_cpu(ev->phy_capability);
641 cap->max_frag_entry = le32_to_cpu(ev->max_frag_entry);
642 cap->num_rf_chains = le32_to_cpu(ev->num_rf_chains);
643 cap->ht_cap_info = le32_to_cpu(ev->ht_cap_info);
644 cap->vht_cap_info = le32_to_cpu(ev->vht_cap_info);
645 cap->vht_supp_mcs = le32_to_cpu(ev->vht_supp_mcs);
646 cap->hw_min_tx_power = le32_to_cpu(ev->hw_min_tx_power);
647 cap->hw_max_tx_power = le32_to_cpu(ev->hw_max_tx_power);
648 cap->sys_cap_info = le32_to_cpu(ev->sys_cap_info);
649 cap->min_pkt_size_enable = le32_to_cpu(ev->min_pkt_size_enable);
650 cap->max_bcn_ie_size = le32_to_cpu(ev->max_bcn_ie_size);
651 cap->max_num_scan_channels = le32_to_cpu(ev->max_num_scan_channels);
652 cap->max_supported_macs = le32_to_cpu(ev->max_supported_macs);
653 cap->wmi_fw_sub_feat_caps = le32_to_cpu(ev->wmi_fw_sub_feat_caps);
654 cap->txrx_chainmask = le32_to_cpu(ev->txrx_chainmask);
655 cap->default_dbs_hw_mode_index = le32_to_cpu(ev->default_dbs_hw_mode_index);
656 cap->num_msdu_desc = le32_to_cpu(ev->num_msdu_desc);
657
658 return 0;
659 }
660
661 /* Save the wmi_service_bitmap into a linear bitmap. The wmi_services in
662 * wmi_service ready event are advertised in b0-b3 (LSB 4-bits) of each
663 * 4-byte word.
664 */
ath12k_wmi_service_bitmap_copy(struct ath12k_wmi_pdev * wmi,const u32 * wmi_svc_bm)665 static void ath12k_wmi_service_bitmap_copy(struct ath12k_wmi_pdev *wmi,
666 const u32 *wmi_svc_bm)
667 {
668 int i, j;
669
670 for (i = 0, j = 0; i < WMI_SERVICE_BM_SIZE && j < WMI_MAX_SERVICE; i++) {
671 do {
672 if (wmi_svc_bm[i] & BIT(j % WMI_SERVICE_BITS_IN_SIZE32))
673 set_bit(j, wmi->wmi_ab->svc_map);
674 } while (++j % WMI_SERVICE_BITS_IN_SIZE32);
675 }
676 }
677
ath12k_wmi_svc_rdy_parse(struct ath12k_base * ab,u16 tag,u16 len,const void * ptr,void * data)678 static int ath12k_wmi_svc_rdy_parse(struct ath12k_base *ab, u16 tag, u16 len,
679 const void *ptr, void *data)
680 {
681 struct ath12k_wmi_svc_ready_parse *svc_ready = data;
682 struct ath12k_wmi_pdev *wmi_handle = &ab->wmi_ab.wmi[0];
683 u16 expect_len;
684
685 switch (tag) {
686 case WMI_TAG_SERVICE_READY_EVENT:
687 if (ath12k_pull_service_ready_tlv(ab, ptr, &ab->target_caps))
688 return -EINVAL;
689 break;
690
691 case WMI_TAG_ARRAY_UINT32:
692 if (!svc_ready->wmi_svc_bitmap_done) {
693 expect_len = WMI_SERVICE_BM_SIZE * sizeof(u32);
694 if (len < expect_len) {
695 ath12k_warn(ab, "invalid len %d for the tag 0x%x\n",
696 len, tag);
697 return -EINVAL;
698 }
699
700 ath12k_wmi_service_bitmap_copy(wmi_handle, ptr);
701
702 svc_ready->wmi_svc_bitmap_done = true;
703 }
704 break;
705 default:
706 break;
707 }
708
709 return 0;
710 }
711
ath12k_service_ready_event(struct ath12k_base * ab,struct sk_buff * skb)712 static int ath12k_service_ready_event(struct ath12k_base *ab, struct sk_buff *skb)
713 {
714 struct ath12k_wmi_svc_ready_parse svc_ready = { };
715 int ret;
716
717 ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len,
718 ath12k_wmi_svc_rdy_parse,
719 &svc_ready);
720 if (ret) {
721 ath12k_warn(ab, "failed to parse tlv %d\n", ret);
722 return ret;
723 }
724
725 return 0;
726 }
727
ath12k_wmi_alloc_skb(struct ath12k_wmi_base * wmi_sc,u32 len)728 struct sk_buff *ath12k_wmi_alloc_skb(struct ath12k_wmi_base *wmi_sc, u32 len)
729 {
730 struct sk_buff *skb;
731 struct ath12k_base *ab = wmi_sc->ab;
732 u32 round_len = roundup(len, 4);
733
734 skb = ath12k_htc_alloc_skb(ab, WMI_SKB_HEADROOM + round_len);
735 if (!skb)
736 return NULL;
737
738 skb_reserve(skb, WMI_SKB_HEADROOM);
739 if (!IS_ALIGNED((unsigned long)skb->data, 4))
740 ath12k_warn(ab, "unaligned WMI skb data\n");
741
742 skb_put(skb, round_len);
743 memset(skb->data, 0, round_len);
744
745 return skb;
746 }
747
ath12k_wmi_mgmt_send(struct ath12k * ar,u32 vdev_id,u32 buf_id,struct sk_buff * frame)748 int ath12k_wmi_mgmt_send(struct ath12k *ar, u32 vdev_id, u32 buf_id,
749 struct sk_buff *frame)
750 {
751 struct ath12k_wmi_pdev *wmi = ar->wmi;
752 struct wmi_mgmt_send_cmd *cmd;
753 struct wmi_tlv *frame_tlv;
754 struct sk_buff *skb;
755 u32 buf_len;
756 int ret, len;
757
758 buf_len = min_t(int, frame->len, WMI_MGMT_SEND_DOWNLD_LEN);
759
760 len = sizeof(*cmd) + sizeof(*frame_tlv) + roundup(buf_len, 4);
761
762 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len);
763 if (!skb)
764 return -ENOMEM;
765
766 cmd = (struct wmi_mgmt_send_cmd *)skb->data;
767 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_MGMT_TX_SEND_CMD,
768 sizeof(*cmd));
769 cmd->vdev_id = cpu_to_le32(vdev_id);
770 cmd->desc_id = cpu_to_le32(buf_id);
771 cmd->chanfreq = 0;
772 cmd->paddr_lo = cpu_to_le32(lower_32_bits(ATH12K_SKB_CB(frame)->paddr));
773 cmd->paddr_hi = cpu_to_le32(upper_32_bits(ATH12K_SKB_CB(frame)->paddr));
774 cmd->frame_len = cpu_to_le32(frame->len);
775 cmd->buf_len = cpu_to_le32(buf_len);
776 cmd->tx_params_valid = 0;
777
778 frame_tlv = (struct wmi_tlv *)(skb->data + sizeof(*cmd));
779 frame_tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_BYTE, buf_len);
780
781 memcpy(frame_tlv->value, frame->data, buf_len);
782
783 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_MGMT_TX_SEND_CMDID);
784 if (ret) {
785 ath12k_warn(ar->ab,
786 "failed to submit WMI_MGMT_TX_SEND_CMDID cmd\n");
787 dev_kfree_skb(skb);
788 }
789
790 return ret;
791 }
792
ath12k_wmi_vdev_create(struct ath12k * ar,u8 * macaddr,struct ath12k_wmi_vdev_create_arg * args)793 int ath12k_wmi_vdev_create(struct ath12k *ar, u8 *macaddr,
794 struct ath12k_wmi_vdev_create_arg *args)
795 {
796 struct ath12k_wmi_pdev *wmi = ar->wmi;
797 struct wmi_vdev_create_cmd *cmd;
798 struct sk_buff *skb;
799 struct ath12k_wmi_vdev_txrx_streams_params *txrx_streams;
800 struct wmi_tlv *tlv;
801 int ret, len;
802 void *ptr;
803
804 /* It can be optimized my sending tx/rx chain configuration
805 * only for supported bands instead of always sending it for
806 * both the bands.
807 */
808 len = sizeof(*cmd) + TLV_HDR_SIZE +
809 (WMI_NUM_SUPPORTED_BAND_MAX * sizeof(*txrx_streams));
810
811 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len);
812 if (!skb)
813 return -ENOMEM;
814
815 cmd = (struct wmi_vdev_create_cmd *)skb->data;
816 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_CREATE_CMD,
817 sizeof(*cmd));
818
819 cmd->vdev_id = cpu_to_le32(args->if_id);
820 cmd->vdev_type = cpu_to_le32(args->type);
821 cmd->vdev_subtype = cpu_to_le32(args->subtype);
822 cmd->num_cfg_txrx_streams = cpu_to_le32(WMI_NUM_SUPPORTED_BAND_MAX);
823 cmd->pdev_id = cpu_to_le32(args->pdev_id);
824 cmd->vdev_stats_id = cpu_to_le32(args->if_stats_id);
825 ether_addr_copy(cmd->vdev_macaddr.addr, macaddr);
826
827 ptr = skb->data + sizeof(*cmd);
828 len = WMI_NUM_SUPPORTED_BAND_MAX * sizeof(*txrx_streams);
829
830 tlv = ptr;
831 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, len);
832
833 ptr += TLV_HDR_SIZE;
834 txrx_streams = ptr;
835 len = sizeof(*txrx_streams);
836 txrx_streams->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_TXRX_STREAMS,
837 len);
838 txrx_streams->band = WMI_TPC_CHAINMASK_CONFIG_BAND_2G;
839 txrx_streams->supported_tx_streams =
840 args->chains[NL80211_BAND_2GHZ].tx;
841 txrx_streams->supported_rx_streams =
842 args->chains[NL80211_BAND_2GHZ].rx;
843
844 txrx_streams++;
845 txrx_streams->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_TXRX_STREAMS,
846 len);
847 txrx_streams->band = WMI_TPC_CHAINMASK_CONFIG_BAND_5G;
848 txrx_streams->supported_tx_streams =
849 args->chains[NL80211_BAND_5GHZ].tx;
850 txrx_streams->supported_rx_streams =
851 args->chains[NL80211_BAND_5GHZ].rx;
852
853 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
854 "WMI vdev create: id %d type %d subtype %d macaddr %pM pdevid %d\n",
855 args->if_id, args->type, args->subtype,
856 macaddr, args->pdev_id);
857
858 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_VDEV_CREATE_CMDID);
859 if (ret) {
860 ath12k_warn(ar->ab,
861 "failed to submit WMI_VDEV_CREATE_CMDID\n");
862 dev_kfree_skb(skb);
863 }
864
865 return ret;
866 }
867
ath12k_wmi_vdev_delete(struct ath12k * ar,u8 vdev_id)868 int ath12k_wmi_vdev_delete(struct ath12k *ar, u8 vdev_id)
869 {
870 struct ath12k_wmi_pdev *wmi = ar->wmi;
871 struct wmi_vdev_delete_cmd *cmd;
872 struct sk_buff *skb;
873 int ret;
874
875 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
876 if (!skb)
877 return -ENOMEM;
878
879 cmd = (struct wmi_vdev_delete_cmd *)skb->data;
880 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_DELETE_CMD,
881 sizeof(*cmd));
882 cmd->vdev_id = cpu_to_le32(vdev_id);
883
884 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "WMI vdev delete id %d\n", vdev_id);
885
886 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_VDEV_DELETE_CMDID);
887 if (ret) {
888 ath12k_warn(ar->ab, "failed to submit WMI_VDEV_DELETE_CMDID\n");
889 dev_kfree_skb(skb);
890 }
891
892 return ret;
893 }
894
ath12k_wmi_vdev_stop(struct ath12k * ar,u8 vdev_id)895 int ath12k_wmi_vdev_stop(struct ath12k *ar, u8 vdev_id)
896 {
897 struct ath12k_wmi_pdev *wmi = ar->wmi;
898 struct wmi_vdev_stop_cmd *cmd;
899 struct sk_buff *skb;
900 int ret;
901
902 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
903 if (!skb)
904 return -ENOMEM;
905
906 cmd = (struct wmi_vdev_stop_cmd *)skb->data;
907
908 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_STOP_CMD,
909 sizeof(*cmd));
910 cmd->vdev_id = cpu_to_le32(vdev_id);
911
912 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "WMI vdev stop id 0x%x\n", vdev_id);
913
914 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_VDEV_STOP_CMDID);
915 if (ret) {
916 ath12k_warn(ar->ab, "failed to submit WMI_VDEV_STOP cmd\n");
917 dev_kfree_skb(skb);
918 }
919
920 return ret;
921 }
922
ath12k_wmi_vdev_down(struct ath12k * ar,u8 vdev_id)923 int ath12k_wmi_vdev_down(struct ath12k *ar, u8 vdev_id)
924 {
925 struct ath12k_wmi_pdev *wmi = ar->wmi;
926 struct wmi_vdev_down_cmd *cmd;
927 struct sk_buff *skb;
928 int ret;
929
930 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
931 if (!skb)
932 return -ENOMEM;
933
934 cmd = (struct wmi_vdev_down_cmd *)skb->data;
935
936 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_DOWN_CMD,
937 sizeof(*cmd));
938 cmd->vdev_id = cpu_to_le32(vdev_id);
939
940 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "WMI vdev down id 0x%x\n", vdev_id);
941
942 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_VDEV_DOWN_CMDID);
943 if (ret) {
944 ath12k_warn(ar->ab, "failed to submit WMI_VDEV_DOWN cmd\n");
945 dev_kfree_skb(skb);
946 }
947
948 return ret;
949 }
950
ath12k_wmi_put_wmi_channel(struct ath12k_wmi_channel_params * chan,struct wmi_vdev_start_req_arg * arg)951 static void ath12k_wmi_put_wmi_channel(struct ath12k_wmi_channel_params *chan,
952 struct wmi_vdev_start_req_arg *arg)
953 {
954 u32 center_freq1 = arg->band_center_freq1;
955
956 memset(chan, 0, sizeof(*chan));
957
958 chan->mhz = cpu_to_le32(arg->freq);
959 chan->band_center_freq1 = cpu_to_le32(center_freq1);
960 if (arg->mode == MODE_11BE_EHT160) {
961 if (arg->freq > center_freq1)
962 chan->band_center_freq1 = cpu_to_le32(center_freq1 + 40);
963 else
964 chan->band_center_freq1 = cpu_to_le32(center_freq1 - 40);
965
966 chan->band_center_freq2 = cpu_to_le32(center_freq1);
967 } else if (arg->mode == MODE_11BE_EHT80_80) {
968 chan->band_center_freq2 = cpu_to_le32(arg->band_center_freq2);
969 } else {
970 chan->band_center_freq2 = 0;
971 }
972
973 chan->info |= le32_encode_bits(arg->mode, WMI_CHAN_INFO_MODE);
974 if (arg->passive)
975 chan->info |= cpu_to_le32(WMI_CHAN_INFO_PASSIVE);
976 if (arg->allow_ibss)
977 chan->info |= cpu_to_le32(WMI_CHAN_INFO_ADHOC_ALLOWED);
978 if (arg->allow_ht)
979 chan->info |= cpu_to_le32(WMI_CHAN_INFO_ALLOW_HT);
980 if (arg->allow_vht)
981 chan->info |= cpu_to_le32(WMI_CHAN_INFO_ALLOW_VHT);
982 if (arg->allow_he)
983 chan->info |= cpu_to_le32(WMI_CHAN_INFO_ALLOW_HE);
984 if (arg->ht40plus)
985 chan->info |= cpu_to_le32(WMI_CHAN_INFO_HT40_PLUS);
986 if (arg->chan_radar)
987 chan->info |= cpu_to_le32(WMI_CHAN_INFO_DFS);
988 if (arg->freq2_radar)
989 chan->info |= cpu_to_le32(WMI_CHAN_INFO_DFS_FREQ2);
990
991 chan->reg_info_1 = le32_encode_bits(arg->max_power,
992 WMI_CHAN_REG_INFO1_MAX_PWR) |
993 le32_encode_bits(arg->max_reg_power,
994 WMI_CHAN_REG_INFO1_MAX_REG_PWR);
995
996 chan->reg_info_2 = le32_encode_bits(arg->max_antenna_gain,
997 WMI_CHAN_REG_INFO2_ANT_MAX) |
998 le32_encode_bits(arg->max_power, WMI_CHAN_REG_INFO2_MAX_TX_PWR);
999 }
1000
ath12k_wmi_vdev_start(struct ath12k * ar,struct wmi_vdev_start_req_arg * arg,bool restart)1001 int ath12k_wmi_vdev_start(struct ath12k *ar, struct wmi_vdev_start_req_arg *arg,
1002 bool restart)
1003 {
1004 struct ath12k_wmi_pdev *wmi = ar->wmi;
1005 struct wmi_vdev_start_request_cmd *cmd;
1006 struct sk_buff *skb;
1007 struct ath12k_wmi_channel_params *chan;
1008 struct wmi_tlv *tlv;
1009 void *ptr;
1010 int ret, len;
1011
1012 if (WARN_ON(arg->ssid_len > sizeof(cmd->ssid.ssid)))
1013 return -EINVAL;
1014
1015 len = sizeof(*cmd) + sizeof(*chan) + TLV_HDR_SIZE;
1016
1017 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len);
1018 if (!skb)
1019 return -ENOMEM;
1020
1021 cmd = (struct wmi_vdev_start_request_cmd *)skb->data;
1022 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_START_REQUEST_CMD,
1023 sizeof(*cmd));
1024 cmd->vdev_id = cpu_to_le32(arg->vdev_id);
1025 cmd->beacon_interval = cpu_to_le32(arg->bcn_intval);
1026 cmd->bcn_tx_rate = cpu_to_le32(arg->bcn_tx_rate);
1027 cmd->dtim_period = cpu_to_le32(arg->dtim_period);
1028 cmd->num_noa_descriptors = cpu_to_le32(arg->num_noa_descriptors);
1029 cmd->preferred_rx_streams = cpu_to_le32(arg->pref_rx_streams);
1030 cmd->preferred_tx_streams = cpu_to_le32(arg->pref_tx_streams);
1031 cmd->cac_duration_ms = cpu_to_le32(arg->cac_duration_ms);
1032 cmd->regdomain = cpu_to_le32(arg->regdomain);
1033 cmd->he_ops = cpu_to_le32(arg->he_ops);
1034 cmd->punct_bitmap = cpu_to_le32(arg->punct_bitmap);
1035
1036 if (!restart) {
1037 if (arg->ssid) {
1038 cmd->ssid.ssid_len = cpu_to_le32(arg->ssid_len);
1039 memcpy(cmd->ssid.ssid, arg->ssid, arg->ssid_len);
1040 }
1041 if (arg->hidden_ssid)
1042 cmd->flags |= cpu_to_le32(WMI_VDEV_START_HIDDEN_SSID);
1043 if (arg->pmf_enabled)
1044 cmd->flags |= cpu_to_le32(WMI_VDEV_START_PMF_ENABLED);
1045 }
1046
1047 cmd->flags |= cpu_to_le32(WMI_VDEV_START_LDPC_RX_ENABLED);
1048
1049 ptr = skb->data + sizeof(*cmd);
1050 chan = ptr;
1051
1052 ath12k_wmi_put_wmi_channel(chan, arg);
1053
1054 chan->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_CHANNEL,
1055 sizeof(*chan));
1056 ptr += sizeof(*chan);
1057
1058 tlv = ptr;
1059 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, 0);
1060
1061 /* Note: This is a nested TLV containing:
1062 * [wmi_tlv][wmi_p2p_noa_descriptor][wmi_tlv]..
1063 */
1064
1065 ptr += sizeof(*tlv);
1066
1067 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "vdev %s id 0x%x freq 0x%x mode 0x%x\n",
1068 restart ? "restart" : "start", arg->vdev_id,
1069 arg->freq, arg->mode);
1070
1071 if (restart)
1072 ret = ath12k_wmi_cmd_send(wmi, skb,
1073 WMI_VDEV_RESTART_REQUEST_CMDID);
1074 else
1075 ret = ath12k_wmi_cmd_send(wmi, skb,
1076 WMI_VDEV_START_REQUEST_CMDID);
1077 if (ret) {
1078 ath12k_warn(ar->ab, "failed to submit vdev_%s cmd\n",
1079 restart ? "restart" : "start");
1080 dev_kfree_skb(skb);
1081 }
1082
1083 return ret;
1084 }
1085
ath12k_wmi_vdev_up(struct ath12k * ar,u32 vdev_id,u32 aid,const u8 * bssid)1086 int ath12k_wmi_vdev_up(struct ath12k *ar, u32 vdev_id, u32 aid, const u8 *bssid)
1087 {
1088 struct ath12k_wmi_pdev *wmi = ar->wmi;
1089 struct wmi_vdev_up_cmd *cmd;
1090 struct sk_buff *skb;
1091 int ret;
1092
1093 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
1094 if (!skb)
1095 return -ENOMEM;
1096
1097 cmd = (struct wmi_vdev_up_cmd *)skb->data;
1098
1099 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_UP_CMD,
1100 sizeof(*cmd));
1101 cmd->vdev_id = cpu_to_le32(vdev_id);
1102 cmd->vdev_assoc_id = cpu_to_le32(aid);
1103
1104 ether_addr_copy(cmd->vdev_bssid.addr, bssid);
1105
1106 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
1107 "WMI mgmt vdev up id 0x%x assoc id %d bssid %pM\n",
1108 vdev_id, aid, bssid);
1109
1110 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_VDEV_UP_CMDID);
1111 if (ret) {
1112 ath12k_warn(ar->ab, "failed to submit WMI_VDEV_UP cmd\n");
1113 dev_kfree_skb(skb);
1114 }
1115
1116 return ret;
1117 }
1118
ath12k_wmi_send_peer_create_cmd(struct ath12k * ar,struct ath12k_wmi_peer_create_arg * arg)1119 int ath12k_wmi_send_peer_create_cmd(struct ath12k *ar,
1120 struct ath12k_wmi_peer_create_arg *arg)
1121 {
1122 struct ath12k_wmi_pdev *wmi = ar->wmi;
1123 struct wmi_peer_create_cmd *cmd;
1124 struct sk_buff *skb;
1125 int ret;
1126
1127 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
1128 if (!skb)
1129 return -ENOMEM;
1130
1131 cmd = (struct wmi_peer_create_cmd *)skb->data;
1132 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PEER_CREATE_CMD,
1133 sizeof(*cmd));
1134
1135 ether_addr_copy(cmd->peer_macaddr.addr, arg->peer_addr);
1136 cmd->peer_type = cpu_to_le32(arg->peer_type);
1137 cmd->vdev_id = cpu_to_le32(arg->vdev_id);
1138
1139 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
1140 "WMI peer create vdev_id %d peer_addr %pM\n",
1141 arg->vdev_id, arg->peer_addr);
1142
1143 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PEER_CREATE_CMDID);
1144 if (ret) {
1145 ath12k_warn(ar->ab, "failed to submit WMI_PEER_CREATE cmd\n");
1146 dev_kfree_skb(skb);
1147 }
1148
1149 return ret;
1150 }
1151
ath12k_wmi_send_peer_delete_cmd(struct ath12k * ar,const u8 * peer_addr,u8 vdev_id)1152 int ath12k_wmi_send_peer_delete_cmd(struct ath12k *ar,
1153 const u8 *peer_addr, u8 vdev_id)
1154 {
1155 struct ath12k_wmi_pdev *wmi = ar->wmi;
1156 struct wmi_peer_delete_cmd *cmd;
1157 struct sk_buff *skb;
1158 int ret;
1159
1160 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
1161 if (!skb)
1162 return -ENOMEM;
1163
1164 cmd = (struct wmi_peer_delete_cmd *)skb->data;
1165 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PEER_DELETE_CMD,
1166 sizeof(*cmd));
1167
1168 ether_addr_copy(cmd->peer_macaddr.addr, peer_addr);
1169 cmd->vdev_id = cpu_to_le32(vdev_id);
1170
1171 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
1172 "WMI peer delete vdev_id %d peer_addr %pM\n",
1173 vdev_id, peer_addr);
1174
1175 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PEER_DELETE_CMDID);
1176 if (ret) {
1177 ath12k_warn(ar->ab, "failed to send WMI_PEER_DELETE cmd\n");
1178 dev_kfree_skb(skb);
1179 }
1180
1181 return ret;
1182 }
1183
ath12k_wmi_send_pdev_set_regdomain(struct ath12k * ar,struct ath12k_wmi_pdev_set_regdomain_arg * arg)1184 int ath12k_wmi_send_pdev_set_regdomain(struct ath12k *ar,
1185 struct ath12k_wmi_pdev_set_regdomain_arg *arg)
1186 {
1187 struct ath12k_wmi_pdev *wmi = ar->wmi;
1188 struct wmi_pdev_set_regdomain_cmd *cmd;
1189 struct sk_buff *skb;
1190 int ret;
1191
1192 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
1193 if (!skb)
1194 return -ENOMEM;
1195
1196 cmd = (struct wmi_pdev_set_regdomain_cmd *)skb->data;
1197 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_SET_REGDOMAIN_CMD,
1198 sizeof(*cmd));
1199
1200 cmd->reg_domain = cpu_to_le32(arg->current_rd_in_use);
1201 cmd->reg_domain_2g = cpu_to_le32(arg->current_rd_2g);
1202 cmd->reg_domain_5g = cpu_to_le32(arg->current_rd_5g);
1203 cmd->conformance_test_limit_2g = cpu_to_le32(arg->ctl_2g);
1204 cmd->conformance_test_limit_5g = cpu_to_le32(arg->ctl_5g);
1205 cmd->dfs_domain = cpu_to_le32(arg->dfs_domain);
1206 cmd->pdev_id = cpu_to_le32(arg->pdev_id);
1207
1208 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
1209 "WMI pdev regd rd %d rd2g %d rd5g %d domain %d pdev id %d\n",
1210 arg->current_rd_in_use, arg->current_rd_2g,
1211 arg->current_rd_5g, arg->dfs_domain, arg->pdev_id);
1212
1213 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PDEV_SET_REGDOMAIN_CMDID);
1214 if (ret) {
1215 ath12k_warn(ar->ab,
1216 "failed to send WMI_PDEV_SET_REGDOMAIN cmd\n");
1217 dev_kfree_skb(skb);
1218 }
1219
1220 return ret;
1221 }
1222
ath12k_wmi_set_peer_param(struct ath12k * ar,const u8 * peer_addr,u32 vdev_id,u32 param_id,u32 param_val)1223 int ath12k_wmi_set_peer_param(struct ath12k *ar, const u8 *peer_addr,
1224 u32 vdev_id, u32 param_id, u32 param_val)
1225 {
1226 struct ath12k_wmi_pdev *wmi = ar->wmi;
1227 struct wmi_peer_set_param_cmd *cmd;
1228 struct sk_buff *skb;
1229 int ret;
1230
1231 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
1232 if (!skb)
1233 return -ENOMEM;
1234
1235 cmd = (struct wmi_peer_set_param_cmd *)skb->data;
1236 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PEER_SET_PARAM_CMD,
1237 sizeof(*cmd));
1238 ether_addr_copy(cmd->peer_macaddr.addr, peer_addr);
1239 cmd->vdev_id = cpu_to_le32(vdev_id);
1240 cmd->param_id = cpu_to_le32(param_id);
1241 cmd->param_value = cpu_to_le32(param_val);
1242
1243 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
1244 "WMI vdev %d peer 0x%pM set param %d value %d\n",
1245 vdev_id, peer_addr, param_id, param_val);
1246
1247 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PEER_SET_PARAM_CMDID);
1248 if (ret) {
1249 ath12k_warn(ar->ab, "failed to send WMI_PEER_SET_PARAM cmd\n");
1250 dev_kfree_skb(skb);
1251 }
1252
1253 return ret;
1254 }
1255
ath12k_wmi_send_peer_flush_tids_cmd(struct ath12k * ar,u8 peer_addr[ETH_ALEN],u32 peer_tid_bitmap,u8 vdev_id)1256 int ath12k_wmi_send_peer_flush_tids_cmd(struct ath12k *ar,
1257 u8 peer_addr[ETH_ALEN],
1258 u32 peer_tid_bitmap,
1259 u8 vdev_id)
1260 {
1261 struct ath12k_wmi_pdev *wmi = ar->wmi;
1262 struct wmi_peer_flush_tids_cmd *cmd;
1263 struct sk_buff *skb;
1264 int ret;
1265
1266 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
1267 if (!skb)
1268 return -ENOMEM;
1269
1270 cmd = (struct wmi_peer_flush_tids_cmd *)skb->data;
1271 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PEER_FLUSH_TIDS_CMD,
1272 sizeof(*cmd));
1273
1274 ether_addr_copy(cmd->peer_macaddr.addr, peer_addr);
1275 cmd->peer_tid_bitmap = cpu_to_le32(peer_tid_bitmap);
1276 cmd->vdev_id = cpu_to_le32(vdev_id);
1277
1278 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
1279 "WMI peer flush vdev_id %d peer_addr %pM tids %08x\n",
1280 vdev_id, peer_addr, peer_tid_bitmap);
1281
1282 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PEER_FLUSH_TIDS_CMDID);
1283 if (ret) {
1284 ath12k_warn(ar->ab,
1285 "failed to send WMI_PEER_FLUSH_TIDS cmd\n");
1286 dev_kfree_skb(skb);
1287 }
1288
1289 return ret;
1290 }
1291
ath12k_wmi_peer_rx_reorder_queue_setup(struct ath12k * ar,int vdev_id,const u8 * addr,dma_addr_t paddr,u8 tid,u8 ba_window_size_valid,u32 ba_window_size)1292 int ath12k_wmi_peer_rx_reorder_queue_setup(struct ath12k *ar,
1293 int vdev_id, const u8 *addr,
1294 dma_addr_t paddr, u8 tid,
1295 u8 ba_window_size_valid,
1296 u32 ba_window_size)
1297 {
1298 struct wmi_peer_reorder_queue_setup_cmd *cmd;
1299 struct sk_buff *skb;
1300 int ret;
1301
1302 skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, sizeof(*cmd));
1303 if (!skb)
1304 return -ENOMEM;
1305
1306 cmd = (struct wmi_peer_reorder_queue_setup_cmd *)skb->data;
1307 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_REORDER_QUEUE_SETUP_CMD,
1308 sizeof(*cmd));
1309
1310 ether_addr_copy(cmd->peer_macaddr.addr, addr);
1311 cmd->vdev_id = cpu_to_le32(vdev_id);
1312 cmd->tid = cpu_to_le32(tid);
1313 cmd->queue_ptr_lo = cpu_to_le32(lower_32_bits(paddr));
1314 cmd->queue_ptr_hi = cpu_to_le32(upper_32_bits(paddr));
1315 cmd->queue_no = cpu_to_le32(tid);
1316 cmd->ba_window_size_valid = cpu_to_le32(ba_window_size_valid);
1317 cmd->ba_window_size = cpu_to_le32(ba_window_size);
1318
1319 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
1320 "wmi rx reorder queue setup addr %pM vdev_id %d tid %d\n",
1321 addr, vdev_id, tid);
1322
1323 ret = ath12k_wmi_cmd_send(ar->wmi, skb,
1324 WMI_PEER_REORDER_QUEUE_SETUP_CMDID);
1325 if (ret) {
1326 ath12k_warn(ar->ab,
1327 "failed to send WMI_PEER_REORDER_QUEUE_SETUP\n");
1328 dev_kfree_skb(skb);
1329 }
1330
1331 return ret;
1332 }
1333
1334 int
ath12k_wmi_rx_reord_queue_remove(struct ath12k * ar,struct ath12k_wmi_rx_reorder_queue_remove_arg * arg)1335 ath12k_wmi_rx_reord_queue_remove(struct ath12k *ar,
1336 struct ath12k_wmi_rx_reorder_queue_remove_arg *arg)
1337 {
1338 struct ath12k_wmi_pdev *wmi = ar->wmi;
1339 struct wmi_peer_reorder_queue_remove_cmd *cmd;
1340 struct sk_buff *skb;
1341 int ret;
1342
1343 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
1344 if (!skb)
1345 return -ENOMEM;
1346
1347 cmd = (struct wmi_peer_reorder_queue_remove_cmd *)skb->data;
1348 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_REORDER_QUEUE_REMOVE_CMD,
1349 sizeof(*cmd));
1350
1351 ether_addr_copy(cmd->peer_macaddr.addr, arg->peer_macaddr);
1352 cmd->vdev_id = cpu_to_le32(arg->vdev_id);
1353 cmd->tid_mask = cpu_to_le32(arg->peer_tid_bitmap);
1354
1355 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
1356 "%s: peer_macaddr %pM vdev_id %d, tid_map %d", __func__,
1357 arg->peer_macaddr, arg->vdev_id, arg->peer_tid_bitmap);
1358
1359 ret = ath12k_wmi_cmd_send(wmi, skb,
1360 WMI_PEER_REORDER_QUEUE_REMOVE_CMDID);
1361 if (ret) {
1362 ath12k_warn(ar->ab,
1363 "failed to send WMI_PEER_REORDER_QUEUE_REMOVE_CMDID");
1364 dev_kfree_skb(skb);
1365 }
1366
1367 return ret;
1368 }
1369
ath12k_wmi_pdev_set_param(struct ath12k * ar,u32 param_id,u32 param_value,u8 pdev_id)1370 int ath12k_wmi_pdev_set_param(struct ath12k *ar, u32 param_id,
1371 u32 param_value, u8 pdev_id)
1372 {
1373 struct ath12k_wmi_pdev *wmi = ar->wmi;
1374 struct wmi_pdev_set_param_cmd *cmd;
1375 struct sk_buff *skb;
1376 int ret;
1377
1378 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
1379 if (!skb)
1380 return -ENOMEM;
1381
1382 cmd = (struct wmi_pdev_set_param_cmd *)skb->data;
1383 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_SET_PARAM_CMD,
1384 sizeof(*cmd));
1385 cmd->pdev_id = cpu_to_le32(pdev_id);
1386 cmd->param_id = cpu_to_le32(param_id);
1387 cmd->param_value = cpu_to_le32(param_value);
1388
1389 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
1390 "WMI pdev set param %d pdev id %d value %d\n",
1391 param_id, pdev_id, param_value);
1392
1393 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PDEV_SET_PARAM_CMDID);
1394 if (ret) {
1395 ath12k_warn(ar->ab, "failed to send WMI_PDEV_SET_PARAM cmd\n");
1396 dev_kfree_skb(skb);
1397 }
1398
1399 return ret;
1400 }
1401
ath12k_wmi_pdev_set_ps_mode(struct ath12k * ar,int vdev_id,u32 enable)1402 int ath12k_wmi_pdev_set_ps_mode(struct ath12k *ar, int vdev_id, u32 enable)
1403 {
1404 struct ath12k_wmi_pdev *wmi = ar->wmi;
1405 struct wmi_pdev_set_ps_mode_cmd *cmd;
1406 struct sk_buff *skb;
1407 int ret;
1408
1409 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
1410 if (!skb)
1411 return -ENOMEM;
1412
1413 cmd = (struct wmi_pdev_set_ps_mode_cmd *)skb->data;
1414 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_STA_POWERSAVE_MODE_CMD,
1415 sizeof(*cmd));
1416 cmd->vdev_id = cpu_to_le32(vdev_id);
1417 cmd->sta_ps_mode = cpu_to_le32(enable);
1418
1419 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
1420 "WMI vdev set psmode %d vdev id %d\n",
1421 enable, vdev_id);
1422
1423 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_STA_POWERSAVE_MODE_CMDID);
1424 if (ret) {
1425 ath12k_warn(ar->ab, "failed to send WMI_PDEV_SET_PARAM cmd\n");
1426 dev_kfree_skb(skb);
1427 }
1428
1429 return ret;
1430 }
1431
ath12k_wmi_pdev_suspend(struct ath12k * ar,u32 suspend_opt,u32 pdev_id)1432 int ath12k_wmi_pdev_suspend(struct ath12k *ar, u32 suspend_opt,
1433 u32 pdev_id)
1434 {
1435 struct ath12k_wmi_pdev *wmi = ar->wmi;
1436 struct wmi_pdev_suspend_cmd *cmd;
1437 struct sk_buff *skb;
1438 int ret;
1439
1440 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
1441 if (!skb)
1442 return -ENOMEM;
1443
1444 cmd = (struct wmi_pdev_suspend_cmd *)skb->data;
1445
1446 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_SUSPEND_CMD,
1447 sizeof(*cmd));
1448
1449 cmd->suspend_opt = cpu_to_le32(suspend_opt);
1450 cmd->pdev_id = cpu_to_le32(pdev_id);
1451
1452 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
1453 "WMI pdev suspend pdev_id %d\n", pdev_id);
1454
1455 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PDEV_SUSPEND_CMDID);
1456 if (ret) {
1457 ath12k_warn(ar->ab, "failed to send WMI_PDEV_SUSPEND cmd\n");
1458 dev_kfree_skb(skb);
1459 }
1460
1461 return ret;
1462 }
1463
ath12k_wmi_pdev_resume(struct ath12k * ar,u32 pdev_id)1464 int ath12k_wmi_pdev_resume(struct ath12k *ar, u32 pdev_id)
1465 {
1466 struct ath12k_wmi_pdev *wmi = ar->wmi;
1467 struct wmi_pdev_resume_cmd *cmd;
1468 struct sk_buff *skb;
1469 int ret;
1470
1471 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
1472 if (!skb)
1473 return -ENOMEM;
1474
1475 cmd = (struct wmi_pdev_resume_cmd *)skb->data;
1476
1477 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_RESUME_CMD,
1478 sizeof(*cmd));
1479 cmd->pdev_id = cpu_to_le32(pdev_id);
1480
1481 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
1482 "WMI pdev resume pdev id %d\n", pdev_id);
1483
1484 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PDEV_RESUME_CMDID);
1485 if (ret) {
1486 ath12k_warn(ar->ab, "failed to send WMI_PDEV_RESUME cmd\n");
1487 dev_kfree_skb(skb);
1488 }
1489
1490 return ret;
1491 }
1492
1493 /* TODO FW Support for the cmd is not available yet.
1494 * Can be tested once the command and corresponding
1495 * event is implemented in FW
1496 */
ath12k_wmi_pdev_bss_chan_info_request(struct ath12k * ar,enum wmi_bss_chan_info_req_type type)1497 int ath12k_wmi_pdev_bss_chan_info_request(struct ath12k *ar,
1498 enum wmi_bss_chan_info_req_type type)
1499 {
1500 struct ath12k_wmi_pdev *wmi = ar->wmi;
1501 struct wmi_pdev_bss_chan_info_req_cmd *cmd;
1502 struct sk_buff *skb;
1503 int ret;
1504
1505 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
1506 if (!skb)
1507 return -ENOMEM;
1508
1509 cmd = (struct wmi_pdev_bss_chan_info_req_cmd *)skb->data;
1510
1511 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_BSS_CHAN_INFO_REQUEST,
1512 sizeof(*cmd));
1513 cmd->req_type = cpu_to_le32(type);
1514 cmd->pdev_id = cpu_to_le32(ar->pdev->pdev_id);
1515
1516 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
1517 "WMI bss chan info req type %d\n", type);
1518
1519 ret = ath12k_wmi_cmd_send(wmi, skb,
1520 WMI_PDEV_BSS_CHAN_INFO_REQUEST_CMDID);
1521 if (ret) {
1522 ath12k_warn(ar->ab,
1523 "failed to send WMI_PDEV_BSS_CHAN_INFO_REQUEST cmd\n");
1524 dev_kfree_skb(skb);
1525 }
1526
1527 return ret;
1528 }
1529
ath12k_wmi_send_set_ap_ps_param_cmd(struct ath12k * ar,u8 * peer_addr,struct ath12k_wmi_ap_ps_arg * arg)1530 int ath12k_wmi_send_set_ap_ps_param_cmd(struct ath12k *ar, u8 *peer_addr,
1531 struct ath12k_wmi_ap_ps_arg *arg)
1532 {
1533 struct ath12k_wmi_pdev *wmi = ar->wmi;
1534 struct wmi_ap_ps_peer_cmd *cmd;
1535 struct sk_buff *skb;
1536 int ret;
1537
1538 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
1539 if (!skb)
1540 return -ENOMEM;
1541
1542 cmd = (struct wmi_ap_ps_peer_cmd *)skb->data;
1543 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_AP_PS_PEER_CMD,
1544 sizeof(*cmd));
1545
1546 cmd->vdev_id = cpu_to_le32(arg->vdev_id);
1547 ether_addr_copy(cmd->peer_macaddr.addr, peer_addr);
1548 cmd->param = cpu_to_le32(arg->param);
1549 cmd->value = cpu_to_le32(arg->value);
1550
1551 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
1552 "WMI set ap ps vdev id %d peer %pM param %d value %d\n",
1553 arg->vdev_id, peer_addr, arg->param, arg->value);
1554
1555 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_AP_PS_PEER_PARAM_CMDID);
1556 if (ret) {
1557 ath12k_warn(ar->ab,
1558 "failed to send WMI_AP_PS_PEER_PARAM_CMDID\n");
1559 dev_kfree_skb(skb);
1560 }
1561
1562 return ret;
1563 }
1564
ath12k_wmi_set_sta_ps_param(struct ath12k * ar,u32 vdev_id,u32 param,u32 param_value)1565 int ath12k_wmi_set_sta_ps_param(struct ath12k *ar, u32 vdev_id,
1566 u32 param, u32 param_value)
1567 {
1568 struct ath12k_wmi_pdev *wmi = ar->wmi;
1569 struct wmi_sta_powersave_param_cmd *cmd;
1570 struct sk_buff *skb;
1571 int ret;
1572
1573 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
1574 if (!skb)
1575 return -ENOMEM;
1576
1577 cmd = (struct wmi_sta_powersave_param_cmd *)skb->data;
1578 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_STA_POWERSAVE_PARAM_CMD,
1579 sizeof(*cmd));
1580
1581 cmd->vdev_id = cpu_to_le32(vdev_id);
1582 cmd->param = cpu_to_le32(param);
1583 cmd->value = cpu_to_le32(param_value);
1584
1585 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
1586 "WMI set sta ps vdev_id %d param %d value %d\n",
1587 vdev_id, param, param_value);
1588
1589 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_STA_POWERSAVE_PARAM_CMDID);
1590 if (ret) {
1591 ath12k_warn(ar->ab, "failed to send WMI_STA_POWERSAVE_PARAM_CMDID");
1592 dev_kfree_skb(skb);
1593 }
1594
1595 return ret;
1596 }
1597
ath12k_wmi_force_fw_hang_cmd(struct ath12k * ar,u32 type,u32 delay_time_ms)1598 int ath12k_wmi_force_fw_hang_cmd(struct ath12k *ar, u32 type, u32 delay_time_ms)
1599 {
1600 struct ath12k_wmi_pdev *wmi = ar->wmi;
1601 struct wmi_force_fw_hang_cmd *cmd;
1602 struct sk_buff *skb;
1603 int ret, len;
1604
1605 len = sizeof(*cmd);
1606
1607 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len);
1608 if (!skb)
1609 return -ENOMEM;
1610
1611 cmd = (struct wmi_force_fw_hang_cmd *)skb->data;
1612 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_FORCE_FW_HANG_CMD,
1613 len);
1614
1615 cmd->type = cpu_to_le32(type);
1616 cmd->delay_time_ms = cpu_to_le32(delay_time_ms);
1617
1618 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_FORCE_FW_HANG_CMDID);
1619
1620 if (ret) {
1621 ath12k_warn(ar->ab, "Failed to send WMI_FORCE_FW_HANG_CMDID");
1622 dev_kfree_skb(skb);
1623 }
1624 return ret;
1625 }
1626
ath12k_wmi_vdev_set_param_cmd(struct ath12k * ar,u32 vdev_id,u32 param_id,u32 param_value)1627 int ath12k_wmi_vdev_set_param_cmd(struct ath12k *ar, u32 vdev_id,
1628 u32 param_id, u32 param_value)
1629 {
1630 struct ath12k_wmi_pdev *wmi = ar->wmi;
1631 struct wmi_vdev_set_param_cmd *cmd;
1632 struct sk_buff *skb;
1633 int ret;
1634
1635 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
1636 if (!skb)
1637 return -ENOMEM;
1638
1639 cmd = (struct wmi_vdev_set_param_cmd *)skb->data;
1640 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_SET_PARAM_CMD,
1641 sizeof(*cmd));
1642
1643 cmd->vdev_id = cpu_to_le32(vdev_id);
1644 cmd->param_id = cpu_to_le32(param_id);
1645 cmd->param_value = cpu_to_le32(param_value);
1646
1647 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
1648 "WMI vdev id 0x%x set param %d value %d\n",
1649 vdev_id, param_id, param_value);
1650
1651 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_VDEV_SET_PARAM_CMDID);
1652 if (ret) {
1653 ath12k_warn(ar->ab,
1654 "failed to send WMI_VDEV_SET_PARAM_CMDID\n");
1655 dev_kfree_skb(skb);
1656 }
1657
1658 return ret;
1659 }
1660
ath12k_wmi_send_pdev_temperature_cmd(struct ath12k * ar)1661 int ath12k_wmi_send_pdev_temperature_cmd(struct ath12k *ar)
1662 {
1663 struct ath12k_wmi_pdev *wmi = ar->wmi;
1664 struct wmi_get_pdev_temperature_cmd *cmd;
1665 struct sk_buff *skb;
1666 int ret;
1667
1668 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
1669 if (!skb)
1670 return -ENOMEM;
1671
1672 cmd = (struct wmi_get_pdev_temperature_cmd *)skb->data;
1673 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_GET_TEMPERATURE_CMD,
1674 sizeof(*cmd));
1675 cmd->pdev_id = cpu_to_le32(ar->pdev->pdev_id);
1676
1677 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
1678 "WMI pdev get temperature for pdev_id %d\n", ar->pdev->pdev_id);
1679
1680 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PDEV_GET_TEMPERATURE_CMDID);
1681 if (ret) {
1682 ath12k_warn(ar->ab, "failed to send WMI_PDEV_GET_TEMPERATURE cmd\n");
1683 dev_kfree_skb(skb);
1684 }
1685
1686 return ret;
1687 }
1688
ath12k_wmi_send_bcn_offload_control_cmd(struct ath12k * ar,u32 vdev_id,u32 bcn_ctrl_op)1689 int ath12k_wmi_send_bcn_offload_control_cmd(struct ath12k *ar,
1690 u32 vdev_id, u32 bcn_ctrl_op)
1691 {
1692 struct ath12k_wmi_pdev *wmi = ar->wmi;
1693 struct wmi_bcn_offload_ctrl_cmd *cmd;
1694 struct sk_buff *skb;
1695 int ret;
1696
1697 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
1698 if (!skb)
1699 return -ENOMEM;
1700
1701 cmd = (struct wmi_bcn_offload_ctrl_cmd *)skb->data;
1702 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_BCN_OFFLOAD_CTRL_CMD,
1703 sizeof(*cmd));
1704
1705 cmd->vdev_id = cpu_to_le32(vdev_id);
1706 cmd->bcn_ctrl_op = cpu_to_le32(bcn_ctrl_op);
1707
1708 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
1709 "WMI bcn ctrl offload vdev id %d ctrl_op %d\n",
1710 vdev_id, bcn_ctrl_op);
1711
1712 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_BCN_OFFLOAD_CTRL_CMDID);
1713 if (ret) {
1714 ath12k_warn(ar->ab,
1715 "failed to send WMI_BCN_OFFLOAD_CTRL_CMDID\n");
1716 dev_kfree_skb(skb);
1717 }
1718
1719 return ret;
1720 }
1721
ath12k_wmi_bcn_tmpl(struct ath12k * ar,u32 vdev_id,struct ieee80211_mutable_offsets * offs,struct sk_buff * bcn)1722 int ath12k_wmi_bcn_tmpl(struct ath12k *ar, u32 vdev_id,
1723 struct ieee80211_mutable_offsets *offs,
1724 struct sk_buff *bcn)
1725 {
1726 struct ath12k_wmi_pdev *wmi = ar->wmi;
1727 struct wmi_bcn_tmpl_cmd *cmd;
1728 struct ath12k_wmi_bcn_prb_info_params *bcn_prb_info;
1729 struct wmi_tlv *tlv;
1730 struct sk_buff *skb;
1731 void *ptr;
1732 int ret, len;
1733 size_t aligned_len = roundup(bcn->len, 4);
1734
1735 len = sizeof(*cmd) + sizeof(*bcn_prb_info) + TLV_HDR_SIZE + aligned_len;
1736
1737 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len);
1738 if (!skb)
1739 return -ENOMEM;
1740
1741 cmd = (struct wmi_bcn_tmpl_cmd *)skb->data;
1742 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_BCN_TMPL_CMD,
1743 sizeof(*cmd));
1744 cmd->vdev_id = cpu_to_le32(vdev_id);
1745 cmd->tim_ie_offset = cpu_to_le32(offs->tim_offset);
1746 cmd->csa_switch_count_offset = cpu_to_le32(offs->cntdwn_counter_offs[0]);
1747 cmd->ext_csa_switch_count_offset = cpu_to_le32(offs->cntdwn_counter_offs[1]);
1748 cmd->buf_len = cpu_to_le32(bcn->len);
1749
1750 ptr = skb->data + sizeof(*cmd);
1751
1752 bcn_prb_info = ptr;
1753 len = sizeof(*bcn_prb_info);
1754 bcn_prb_info->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_BCN_PRB_INFO,
1755 len);
1756 bcn_prb_info->caps = 0;
1757 bcn_prb_info->erp = 0;
1758
1759 ptr += sizeof(*bcn_prb_info);
1760
1761 tlv = ptr;
1762 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_BYTE, aligned_len);
1763 memcpy(tlv->value, bcn->data, bcn->len);
1764
1765 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_BCN_TMPL_CMDID);
1766 if (ret) {
1767 ath12k_warn(ar->ab, "failed to send WMI_BCN_TMPL_CMDID\n");
1768 dev_kfree_skb(skb);
1769 }
1770
1771 return ret;
1772 }
1773
ath12k_wmi_vdev_install_key(struct ath12k * ar,struct wmi_vdev_install_key_arg * arg)1774 int ath12k_wmi_vdev_install_key(struct ath12k *ar,
1775 struct wmi_vdev_install_key_arg *arg)
1776 {
1777 struct ath12k_wmi_pdev *wmi = ar->wmi;
1778 struct wmi_vdev_install_key_cmd *cmd;
1779 struct wmi_tlv *tlv;
1780 struct sk_buff *skb;
1781 int ret, len, key_len_aligned;
1782
1783 /* WMI_TAG_ARRAY_BYTE needs to be aligned with 4, the actual key
1784 * length is specified in cmd->key_len.
1785 */
1786 key_len_aligned = roundup(arg->key_len, 4);
1787
1788 len = sizeof(*cmd) + TLV_HDR_SIZE + key_len_aligned;
1789
1790 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len);
1791 if (!skb)
1792 return -ENOMEM;
1793
1794 cmd = (struct wmi_vdev_install_key_cmd *)skb->data;
1795 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_INSTALL_KEY_CMD,
1796 sizeof(*cmd));
1797 cmd->vdev_id = cpu_to_le32(arg->vdev_id);
1798 ether_addr_copy(cmd->peer_macaddr.addr, arg->macaddr);
1799 cmd->key_idx = cpu_to_le32(arg->key_idx);
1800 cmd->key_flags = cpu_to_le32(arg->key_flags);
1801 cmd->key_cipher = cpu_to_le32(arg->key_cipher);
1802 cmd->key_len = cpu_to_le32(arg->key_len);
1803 cmd->key_txmic_len = cpu_to_le32(arg->key_txmic_len);
1804 cmd->key_rxmic_len = cpu_to_le32(arg->key_rxmic_len);
1805
1806 if (arg->key_rsc_counter)
1807 cmd->key_rsc_counter = cpu_to_le64(arg->key_rsc_counter);
1808
1809 tlv = (struct wmi_tlv *)(skb->data + sizeof(*cmd));
1810 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_BYTE, key_len_aligned);
1811 memcpy(tlv->value, arg->key_data, arg->key_len);
1812
1813 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
1814 "WMI vdev install key idx %d cipher %d len %d\n",
1815 arg->key_idx, arg->key_cipher, arg->key_len);
1816
1817 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_VDEV_INSTALL_KEY_CMDID);
1818 if (ret) {
1819 ath12k_warn(ar->ab,
1820 "failed to send WMI_VDEV_INSTALL_KEY cmd\n");
1821 dev_kfree_skb(skb);
1822 }
1823
1824 return ret;
1825 }
1826
ath12k_wmi_copy_peer_flags(struct wmi_peer_assoc_complete_cmd * cmd,struct ath12k_wmi_peer_assoc_arg * arg,bool hw_crypto_disabled)1827 static void ath12k_wmi_copy_peer_flags(struct wmi_peer_assoc_complete_cmd *cmd,
1828 struct ath12k_wmi_peer_assoc_arg *arg,
1829 bool hw_crypto_disabled)
1830 {
1831 cmd->peer_flags = 0;
1832 cmd->peer_flags_ext = 0;
1833
1834 if (arg->is_wme_set) {
1835 if (arg->qos_flag)
1836 cmd->peer_flags |= cpu_to_le32(WMI_PEER_QOS);
1837 if (arg->apsd_flag)
1838 cmd->peer_flags |= cpu_to_le32(WMI_PEER_APSD);
1839 if (arg->ht_flag)
1840 cmd->peer_flags |= cpu_to_le32(WMI_PEER_HT);
1841 if (arg->bw_40)
1842 cmd->peer_flags |= cpu_to_le32(WMI_PEER_40MHZ);
1843 if (arg->bw_80)
1844 cmd->peer_flags |= cpu_to_le32(WMI_PEER_80MHZ);
1845 if (arg->bw_160)
1846 cmd->peer_flags |= cpu_to_le32(WMI_PEER_160MHZ);
1847 if (arg->bw_320)
1848 cmd->peer_flags_ext |= cpu_to_le32(WMI_PEER_EXT_320MHZ);
1849
1850 /* Typically if STBC is enabled for VHT it should be enabled
1851 * for HT as well
1852 **/
1853 if (arg->stbc_flag)
1854 cmd->peer_flags |= cpu_to_le32(WMI_PEER_STBC);
1855
1856 /* Typically if LDPC is enabled for VHT it should be enabled
1857 * for HT as well
1858 **/
1859 if (arg->ldpc_flag)
1860 cmd->peer_flags |= cpu_to_le32(WMI_PEER_LDPC);
1861
1862 if (arg->static_mimops_flag)
1863 cmd->peer_flags |= cpu_to_le32(WMI_PEER_STATIC_MIMOPS);
1864 if (arg->dynamic_mimops_flag)
1865 cmd->peer_flags |= cpu_to_le32(WMI_PEER_DYN_MIMOPS);
1866 if (arg->spatial_mux_flag)
1867 cmd->peer_flags |= cpu_to_le32(WMI_PEER_SPATIAL_MUX);
1868 if (arg->vht_flag)
1869 cmd->peer_flags |= cpu_to_le32(WMI_PEER_VHT);
1870 if (arg->he_flag)
1871 cmd->peer_flags |= cpu_to_le32(WMI_PEER_HE);
1872 if (arg->twt_requester)
1873 cmd->peer_flags |= cpu_to_le32(WMI_PEER_TWT_REQ);
1874 if (arg->twt_responder)
1875 cmd->peer_flags |= cpu_to_le32(WMI_PEER_TWT_RESP);
1876 if (arg->eht_flag)
1877 cmd->peer_flags_ext |= cpu_to_le32(WMI_PEER_EXT_EHT);
1878 }
1879
1880 /* Suppress authorization for all AUTH modes that need 4-way handshake
1881 * (during re-association).
1882 * Authorization will be done for these modes on key installation.
1883 */
1884 if (arg->auth_flag)
1885 cmd->peer_flags |= cpu_to_le32(WMI_PEER_AUTH);
1886 if (arg->need_ptk_4_way) {
1887 cmd->peer_flags |= cpu_to_le32(WMI_PEER_NEED_PTK_4_WAY);
1888 if (!hw_crypto_disabled)
1889 cmd->peer_flags &= cpu_to_le32(~WMI_PEER_AUTH);
1890 }
1891 if (arg->need_gtk_2_way)
1892 cmd->peer_flags |= cpu_to_le32(WMI_PEER_NEED_GTK_2_WAY);
1893 /* safe mode bypass the 4-way handshake */
1894 if (arg->safe_mode_enabled)
1895 cmd->peer_flags &= cpu_to_le32(~(WMI_PEER_NEED_PTK_4_WAY |
1896 WMI_PEER_NEED_GTK_2_WAY));
1897
1898 if (arg->is_pmf_enabled)
1899 cmd->peer_flags |= cpu_to_le32(WMI_PEER_PMF);
1900
1901 /* Disable AMSDU for station transmit, if user configures it */
1902 /* Disable AMSDU for AP transmit to 11n Stations, if user configures
1903 * it
1904 * if (arg->amsdu_disable) Add after FW support
1905 **/
1906
1907 /* Target asserts if node is marked HT and all MCS is set to 0.
1908 * Mark the node as non-HT if all the mcs rates are disabled through
1909 * iwpriv
1910 **/
1911 if (arg->peer_ht_rates.num_rates == 0)
1912 cmd->peer_flags &= cpu_to_le32(~WMI_PEER_HT);
1913 }
1914
ath12k_wmi_send_peer_assoc_cmd(struct ath12k * ar,struct ath12k_wmi_peer_assoc_arg * arg)1915 int ath12k_wmi_send_peer_assoc_cmd(struct ath12k *ar,
1916 struct ath12k_wmi_peer_assoc_arg *arg)
1917 {
1918 struct ath12k_wmi_pdev *wmi = ar->wmi;
1919 struct wmi_peer_assoc_complete_cmd *cmd;
1920 struct ath12k_wmi_vht_rate_set_params *mcs;
1921 struct ath12k_wmi_he_rate_set_params *he_mcs;
1922 struct ath12k_wmi_eht_rate_set_params *eht_mcs;
1923 struct sk_buff *skb;
1924 struct wmi_tlv *tlv;
1925 void *ptr;
1926 u32 peer_legacy_rates_align;
1927 u32 peer_ht_rates_align;
1928 int i, ret, len;
1929
1930 peer_legacy_rates_align = roundup(arg->peer_legacy_rates.num_rates,
1931 sizeof(u32));
1932 peer_ht_rates_align = roundup(arg->peer_ht_rates.num_rates,
1933 sizeof(u32));
1934
1935 len = sizeof(*cmd) +
1936 TLV_HDR_SIZE + (peer_legacy_rates_align * sizeof(u8)) +
1937 TLV_HDR_SIZE + (peer_ht_rates_align * sizeof(u8)) +
1938 sizeof(*mcs) + TLV_HDR_SIZE +
1939 (sizeof(*he_mcs) * arg->peer_he_mcs_count) +
1940 TLV_HDR_SIZE + (sizeof(*eht_mcs) * arg->peer_eht_mcs_count) +
1941 TLV_HDR_SIZE + TLV_HDR_SIZE;
1942
1943 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len);
1944 if (!skb)
1945 return -ENOMEM;
1946
1947 ptr = skb->data;
1948
1949 cmd = ptr;
1950 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PEER_ASSOC_COMPLETE_CMD,
1951 sizeof(*cmd));
1952
1953 cmd->vdev_id = cpu_to_le32(arg->vdev_id);
1954
1955 cmd->peer_new_assoc = cpu_to_le32(arg->peer_new_assoc);
1956 cmd->peer_associd = cpu_to_le32(arg->peer_associd);
1957 cmd->punct_bitmap = cpu_to_le32(arg->punct_bitmap);
1958
1959 ath12k_wmi_copy_peer_flags(cmd, arg,
1960 test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED,
1961 &ar->ab->dev_flags));
1962
1963 ether_addr_copy(cmd->peer_macaddr.addr, arg->peer_mac);
1964
1965 cmd->peer_rate_caps = cpu_to_le32(arg->peer_rate_caps);
1966 cmd->peer_caps = cpu_to_le32(arg->peer_caps);
1967 cmd->peer_listen_intval = cpu_to_le32(arg->peer_listen_intval);
1968 cmd->peer_ht_caps = cpu_to_le32(arg->peer_ht_caps);
1969 cmd->peer_max_mpdu = cpu_to_le32(arg->peer_max_mpdu);
1970 cmd->peer_mpdu_density = cpu_to_le32(arg->peer_mpdu_density);
1971 cmd->peer_vht_caps = cpu_to_le32(arg->peer_vht_caps);
1972 cmd->peer_phymode = cpu_to_le32(arg->peer_phymode);
1973
1974 /* Update 11ax capabilities */
1975 cmd->peer_he_cap_info = cpu_to_le32(arg->peer_he_cap_macinfo[0]);
1976 cmd->peer_he_cap_info_ext = cpu_to_le32(arg->peer_he_cap_macinfo[1]);
1977 cmd->peer_he_cap_info_internal = cpu_to_le32(arg->peer_he_cap_macinfo_internal);
1978 cmd->peer_he_caps_6ghz = cpu_to_le32(arg->peer_he_caps_6ghz);
1979 cmd->peer_he_ops = cpu_to_le32(arg->peer_he_ops);
1980 for (i = 0; i < WMI_MAX_HECAP_PHY_SIZE; i++)
1981 cmd->peer_he_cap_phy[i] =
1982 cpu_to_le32(arg->peer_he_cap_phyinfo[i]);
1983 cmd->peer_ppet.numss_m1 = cpu_to_le32(arg->peer_ppet.numss_m1);
1984 cmd->peer_ppet.ru_info = cpu_to_le32(arg->peer_ppet.ru_bit_mask);
1985 for (i = 0; i < WMI_MAX_NUM_SS; i++)
1986 cmd->peer_ppet.ppet16_ppet8_ru3_ru0[i] =
1987 cpu_to_le32(arg->peer_ppet.ppet16_ppet8_ru3_ru0[i]);
1988
1989 /* Update 11be capabilities */
1990 memcpy_and_pad(cmd->peer_eht_cap_mac, sizeof(cmd->peer_eht_cap_mac),
1991 arg->peer_eht_cap_mac, sizeof(arg->peer_eht_cap_mac),
1992 0);
1993 memcpy_and_pad(cmd->peer_eht_cap_phy, sizeof(cmd->peer_eht_cap_phy),
1994 arg->peer_eht_cap_phy, sizeof(arg->peer_eht_cap_phy),
1995 0);
1996 memcpy_and_pad(&cmd->peer_eht_ppet, sizeof(cmd->peer_eht_ppet),
1997 &arg->peer_eht_ppet, sizeof(arg->peer_eht_ppet), 0);
1998
1999 /* Update peer legacy rate information */
2000 ptr += sizeof(*cmd);
2001
2002 tlv = ptr;
2003 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_BYTE, peer_legacy_rates_align);
2004
2005 ptr += TLV_HDR_SIZE;
2006
2007 cmd->num_peer_legacy_rates = cpu_to_le32(arg->peer_legacy_rates.num_rates);
2008 memcpy(ptr, arg->peer_legacy_rates.rates,
2009 arg->peer_legacy_rates.num_rates);
2010
2011 /* Update peer HT rate information */
2012 ptr += peer_legacy_rates_align;
2013
2014 tlv = ptr;
2015 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_BYTE, peer_ht_rates_align);
2016 ptr += TLV_HDR_SIZE;
2017 cmd->num_peer_ht_rates = cpu_to_le32(arg->peer_ht_rates.num_rates);
2018 memcpy(ptr, arg->peer_ht_rates.rates,
2019 arg->peer_ht_rates.num_rates);
2020
2021 /* VHT Rates */
2022 ptr += peer_ht_rates_align;
2023
2024 mcs = ptr;
2025
2026 mcs->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VHT_RATE_SET,
2027 sizeof(*mcs));
2028
2029 cmd->peer_nss = cpu_to_le32(arg->peer_nss);
2030
2031 /* Update bandwidth-NSS mapping */
2032 cmd->peer_bw_rxnss_override = 0;
2033 cmd->peer_bw_rxnss_override |= cpu_to_le32(arg->peer_bw_rxnss_override);
2034
2035 if (arg->vht_capable) {
2036 mcs->rx_max_rate = cpu_to_le32(arg->rx_max_rate);
2037 mcs->rx_mcs_set = cpu_to_le32(arg->rx_mcs_set);
2038 mcs->tx_max_rate = cpu_to_le32(arg->tx_max_rate);
2039 mcs->tx_mcs_set = cpu_to_le32(arg->tx_mcs_set);
2040 }
2041
2042 /* HE Rates */
2043 cmd->peer_he_mcs = cpu_to_le32(arg->peer_he_mcs_count);
2044 cmd->min_data_rate = cpu_to_le32(arg->min_data_rate);
2045
2046 ptr += sizeof(*mcs);
2047
2048 len = arg->peer_he_mcs_count * sizeof(*he_mcs);
2049
2050 tlv = ptr;
2051 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, len);
2052 ptr += TLV_HDR_SIZE;
2053
2054 /* Loop through the HE rate set */
2055 for (i = 0; i < arg->peer_he_mcs_count; i++) {
2056 he_mcs = ptr;
2057 he_mcs->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_HE_RATE_SET,
2058 sizeof(*he_mcs));
2059
2060 he_mcs->rx_mcs_set = cpu_to_le32(arg->peer_he_rx_mcs_set[i]);
2061 he_mcs->tx_mcs_set = cpu_to_le32(arg->peer_he_tx_mcs_set[i]);
2062 ptr += sizeof(*he_mcs);
2063 }
2064
2065 /* MLO header tag with 0 length */
2066 len = 0;
2067 tlv = ptr;
2068 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, len);
2069 ptr += TLV_HDR_SIZE;
2070
2071 /* Loop through the EHT rate set */
2072 len = arg->peer_eht_mcs_count * sizeof(*eht_mcs);
2073 tlv = ptr;
2074 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, len);
2075 ptr += TLV_HDR_SIZE;
2076
2077 for (i = 0; i < arg->peer_eht_mcs_count; i++) {
2078 eht_mcs = ptr;
2079 eht_mcs->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_EHT_RATE_SET,
2080 sizeof(*eht_mcs));
2081
2082 eht_mcs->rx_mcs_set = cpu_to_le32(arg->peer_eht_rx_mcs_set[i]);
2083 eht_mcs->tx_mcs_set = cpu_to_le32(arg->peer_eht_tx_mcs_set[i]);
2084 ptr += sizeof(*eht_mcs);
2085 }
2086
2087 /* ML partner links tag with 0 length */
2088 len = 0;
2089 tlv = ptr;
2090 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, len);
2091 ptr += TLV_HDR_SIZE;
2092
2093 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
2094 "wmi peer assoc vdev id %d assoc id %d peer mac %pM peer_flags %x rate_caps %x peer_caps %x listen_intval %d ht_caps %x max_mpdu %d nss %d phymode %d peer_mpdu_density %d vht_caps %x he cap_info %x he ops %x he cap_info_ext %x he phy %x %x %x peer_bw_rxnss_override %x peer_flags_ext %x eht mac_cap %x %x eht phy_cap %x %x %x\n",
2095 cmd->vdev_id, cmd->peer_associd, arg->peer_mac,
2096 cmd->peer_flags, cmd->peer_rate_caps, cmd->peer_caps,
2097 cmd->peer_listen_intval, cmd->peer_ht_caps,
2098 cmd->peer_max_mpdu, cmd->peer_nss, cmd->peer_phymode,
2099 cmd->peer_mpdu_density,
2100 cmd->peer_vht_caps, cmd->peer_he_cap_info,
2101 cmd->peer_he_ops, cmd->peer_he_cap_info_ext,
2102 cmd->peer_he_cap_phy[0], cmd->peer_he_cap_phy[1],
2103 cmd->peer_he_cap_phy[2],
2104 cmd->peer_bw_rxnss_override, cmd->peer_flags_ext,
2105 cmd->peer_eht_cap_mac[0], cmd->peer_eht_cap_mac[1],
2106 cmd->peer_eht_cap_phy[0], cmd->peer_eht_cap_phy[1],
2107 cmd->peer_eht_cap_phy[2]);
2108
2109 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PEER_ASSOC_CMDID);
2110 if (ret) {
2111 ath12k_warn(ar->ab,
2112 "failed to send WMI_PEER_ASSOC_CMDID\n");
2113 dev_kfree_skb(skb);
2114 }
2115
2116 return ret;
2117 }
2118
ath12k_wmi_start_scan_init(struct ath12k * ar,struct ath12k_wmi_scan_req_arg * arg)2119 void ath12k_wmi_start_scan_init(struct ath12k *ar,
2120 struct ath12k_wmi_scan_req_arg *arg)
2121 {
2122 /* setup commonly used values */
2123 arg->scan_req_id = 1;
2124 arg->scan_priority = WMI_SCAN_PRIORITY_LOW;
2125 arg->dwell_time_active = 50;
2126 arg->dwell_time_active_2g = 0;
2127 arg->dwell_time_passive = 150;
2128 arg->dwell_time_active_6g = 70;
2129 arg->dwell_time_passive_6g = 70;
2130 arg->min_rest_time = 50;
2131 arg->max_rest_time = 500;
2132 arg->repeat_probe_time = 0;
2133 arg->probe_spacing_time = 0;
2134 arg->idle_time = 0;
2135 arg->max_scan_time = 20000;
2136 arg->probe_delay = 5;
2137 arg->notify_scan_events = WMI_SCAN_EVENT_STARTED |
2138 WMI_SCAN_EVENT_COMPLETED |
2139 WMI_SCAN_EVENT_BSS_CHANNEL |
2140 WMI_SCAN_EVENT_FOREIGN_CHAN |
2141 WMI_SCAN_EVENT_DEQUEUED;
2142 arg->scan_flags |= WMI_SCAN_CHAN_STAT_EVENT;
2143 arg->num_bssid = 1;
2144
2145 /* fill bssid_list[0] with 0xff, otherwise bssid and RA will be
2146 * ZEROs in probe request
2147 */
2148 eth_broadcast_addr(arg->bssid_list[0].addr);
2149 }
2150
ath12k_wmi_copy_scan_event_cntrl_flags(struct wmi_start_scan_cmd * cmd,struct ath12k_wmi_scan_req_arg * arg)2151 static void ath12k_wmi_copy_scan_event_cntrl_flags(struct wmi_start_scan_cmd *cmd,
2152 struct ath12k_wmi_scan_req_arg *arg)
2153 {
2154 /* Scan events subscription */
2155 if (arg->scan_ev_started)
2156 cmd->notify_scan_events |= cpu_to_le32(WMI_SCAN_EVENT_STARTED);
2157 if (arg->scan_ev_completed)
2158 cmd->notify_scan_events |= cpu_to_le32(WMI_SCAN_EVENT_COMPLETED);
2159 if (arg->scan_ev_bss_chan)
2160 cmd->notify_scan_events |= cpu_to_le32(WMI_SCAN_EVENT_BSS_CHANNEL);
2161 if (arg->scan_ev_foreign_chan)
2162 cmd->notify_scan_events |= cpu_to_le32(WMI_SCAN_EVENT_FOREIGN_CHAN);
2163 if (arg->scan_ev_dequeued)
2164 cmd->notify_scan_events |= cpu_to_le32(WMI_SCAN_EVENT_DEQUEUED);
2165 if (arg->scan_ev_preempted)
2166 cmd->notify_scan_events |= cpu_to_le32(WMI_SCAN_EVENT_PREEMPTED);
2167 if (arg->scan_ev_start_failed)
2168 cmd->notify_scan_events |= cpu_to_le32(WMI_SCAN_EVENT_START_FAILED);
2169 if (arg->scan_ev_restarted)
2170 cmd->notify_scan_events |= cpu_to_le32(WMI_SCAN_EVENT_RESTARTED);
2171 if (arg->scan_ev_foreign_chn_exit)
2172 cmd->notify_scan_events |= cpu_to_le32(WMI_SCAN_EVENT_FOREIGN_CHAN_EXIT);
2173 if (arg->scan_ev_suspended)
2174 cmd->notify_scan_events |= cpu_to_le32(WMI_SCAN_EVENT_SUSPENDED);
2175 if (arg->scan_ev_resumed)
2176 cmd->notify_scan_events |= cpu_to_le32(WMI_SCAN_EVENT_RESUMED);
2177
2178 /** Set scan control flags */
2179 cmd->scan_ctrl_flags = 0;
2180 if (arg->scan_f_passive)
2181 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_FLAG_PASSIVE);
2182 if (arg->scan_f_strict_passive_pch)
2183 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_FLAG_STRICT_PASSIVE_ON_PCHN);
2184 if (arg->scan_f_promisc_mode)
2185 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_FILTER_PROMISCUOS);
2186 if (arg->scan_f_capture_phy_err)
2187 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_CAPTURE_PHY_ERROR);
2188 if (arg->scan_f_half_rate)
2189 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_FLAG_HALF_RATE_SUPPORT);
2190 if (arg->scan_f_quarter_rate)
2191 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_FLAG_QUARTER_RATE_SUPPORT);
2192 if (arg->scan_f_cck_rates)
2193 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_ADD_CCK_RATES);
2194 if (arg->scan_f_ofdm_rates)
2195 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_ADD_OFDM_RATES);
2196 if (arg->scan_f_chan_stat_evnt)
2197 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_CHAN_STAT_EVENT);
2198 if (arg->scan_f_filter_prb_req)
2199 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_FILTER_PROBE_REQ);
2200 if (arg->scan_f_bcast_probe)
2201 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_ADD_BCAST_PROBE_REQ);
2202 if (arg->scan_f_offchan_mgmt_tx)
2203 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_OFFCHAN_MGMT_TX);
2204 if (arg->scan_f_offchan_data_tx)
2205 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_OFFCHAN_DATA_TX);
2206 if (arg->scan_f_force_active_dfs_chn)
2207 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_FLAG_FORCE_ACTIVE_ON_DFS);
2208 if (arg->scan_f_add_tpc_ie_in_probe)
2209 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_ADD_TPC_IE_IN_PROBE_REQ);
2210 if (arg->scan_f_add_ds_ie_in_probe)
2211 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_ADD_DS_IE_IN_PROBE_REQ);
2212 if (arg->scan_f_add_spoofed_mac_in_probe)
2213 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_ADD_SPOOF_MAC_IN_PROBE_REQ);
2214 if (arg->scan_f_add_rand_seq_in_probe)
2215 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_RANDOM_SEQ_NO_IN_PROBE_REQ);
2216 if (arg->scan_f_en_ie_whitelist_in_probe)
2217 cmd->scan_ctrl_flags |=
2218 cpu_to_le32(WMI_SCAN_ENABLE_IE_WHTELIST_IN_PROBE_REQ);
2219
2220 cmd->scan_ctrl_flags |= le32_encode_bits(arg->adaptive_dwell_time_mode,
2221 WMI_SCAN_DWELL_MODE_MASK);
2222 }
2223
ath12k_wmi_send_scan_start_cmd(struct ath12k * ar,struct ath12k_wmi_scan_req_arg * arg)2224 int ath12k_wmi_send_scan_start_cmd(struct ath12k *ar,
2225 struct ath12k_wmi_scan_req_arg *arg)
2226 {
2227 struct ath12k_wmi_pdev *wmi = ar->wmi;
2228 struct wmi_start_scan_cmd *cmd;
2229 struct ath12k_wmi_ssid_params *ssid = NULL;
2230 struct ath12k_wmi_mac_addr_params *bssid;
2231 struct sk_buff *skb;
2232 struct wmi_tlv *tlv;
2233 void *ptr;
2234 int i, ret, len;
2235 u32 *tmp_ptr, extraie_len_with_pad = 0;
2236 struct ath12k_wmi_hint_short_ssid_arg *s_ssid = NULL;
2237 struct ath12k_wmi_hint_bssid_arg *hint_bssid = NULL;
2238
2239 len = sizeof(*cmd);
2240
2241 len += TLV_HDR_SIZE;
2242 if (arg->num_chan)
2243 len += arg->num_chan * sizeof(u32);
2244
2245 len += TLV_HDR_SIZE;
2246 if (arg->num_ssids)
2247 len += arg->num_ssids * sizeof(*ssid);
2248
2249 len += TLV_HDR_SIZE;
2250 if (arg->num_bssid)
2251 len += sizeof(*bssid) * arg->num_bssid;
2252
2253 if (arg->num_hint_bssid)
2254 len += TLV_HDR_SIZE +
2255 arg->num_hint_bssid * sizeof(*hint_bssid);
2256
2257 if (arg->num_hint_s_ssid)
2258 len += TLV_HDR_SIZE +
2259 arg->num_hint_s_ssid * sizeof(*s_ssid);
2260
2261 len += TLV_HDR_SIZE;
2262 if (arg->extraie.len)
2263 extraie_len_with_pad =
2264 roundup(arg->extraie.len, sizeof(u32));
2265 if (extraie_len_with_pad <= (wmi->wmi_ab->max_msg_len[ar->pdev_idx] - len)) {
2266 len += extraie_len_with_pad;
2267 } else {
2268 ath12k_warn(ar->ab, "discard large size %d bytes extraie for scan start\n",
2269 arg->extraie.len);
2270 extraie_len_with_pad = 0;
2271 }
2272
2273 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len);
2274 if (!skb)
2275 return -ENOMEM;
2276
2277 ptr = skb->data;
2278
2279 cmd = ptr;
2280 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_START_SCAN_CMD,
2281 sizeof(*cmd));
2282
2283 cmd->scan_id = cpu_to_le32(arg->scan_id);
2284 cmd->scan_req_id = cpu_to_le32(arg->scan_req_id);
2285 cmd->vdev_id = cpu_to_le32(arg->vdev_id);
2286 cmd->scan_priority = cpu_to_le32(arg->scan_priority);
2287 cmd->notify_scan_events = cpu_to_le32(arg->notify_scan_events);
2288
2289 ath12k_wmi_copy_scan_event_cntrl_flags(cmd, arg);
2290
2291 cmd->dwell_time_active = cpu_to_le32(arg->dwell_time_active);
2292 cmd->dwell_time_active_2g = cpu_to_le32(arg->dwell_time_active_2g);
2293 cmd->dwell_time_passive = cpu_to_le32(arg->dwell_time_passive);
2294 cmd->dwell_time_active_6g = cpu_to_le32(arg->dwell_time_active_6g);
2295 cmd->dwell_time_passive_6g = cpu_to_le32(arg->dwell_time_passive_6g);
2296 cmd->min_rest_time = cpu_to_le32(arg->min_rest_time);
2297 cmd->max_rest_time = cpu_to_le32(arg->max_rest_time);
2298 cmd->repeat_probe_time = cpu_to_le32(arg->repeat_probe_time);
2299 cmd->probe_spacing_time = cpu_to_le32(arg->probe_spacing_time);
2300 cmd->idle_time = cpu_to_le32(arg->idle_time);
2301 cmd->max_scan_time = cpu_to_le32(arg->max_scan_time);
2302 cmd->probe_delay = cpu_to_le32(arg->probe_delay);
2303 cmd->burst_duration = cpu_to_le32(arg->burst_duration);
2304 cmd->num_chan = cpu_to_le32(arg->num_chan);
2305 cmd->num_bssid = cpu_to_le32(arg->num_bssid);
2306 cmd->num_ssids = cpu_to_le32(arg->num_ssids);
2307 cmd->ie_len = cpu_to_le32(arg->extraie.len);
2308 cmd->n_probes = cpu_to_le32(arg->n_probes);
2309
2310 ptr += sizeof(*cmd);
2311
2312 len = arg->num_chan * sizeof(u32);
2313
2314 tlv = ptr;
2315 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_UINT32, len);
2316 ptr += TLV_HDR_SIZE;
2317 tmp_ptr = (u32 *)ptr;
2318
2319 memcpy(tmp_ptr, arg->chan_list, arg->num_chan * 4);
2320
2321 ptr += len;
2322
2323 len = arg->num_ssids * sizeof(*ssid);
2324 tlv = ptr;
2325 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_FIXED_STRUCT, len);
2326
2327 ptr += TLV_HDR_SIZE;
2328
2329 if (arg->num_ssids) {
2330 ssid = ptr;
2331 for (i = 0; i < arg->num_ssids; ++i) {
2332 ssid->ssid_len = cpu_to_le32(arg->ssid[i].ssid_len);
2333 memcpy(ssid->ssid, arg->ssid[i].ssid,
2334 arg->ssid[i].ssid_len);
2335 ssid++;
2336 }
2337 }
2338
2339 ptr += (arg->num_ssids * sizeof(*ssid));
2340 len = arg->num_bssid * sizeof(*bssid);
2341 tlv = ptr;
2342 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_FIXED_STRUCT, len);
2343
2344 ptr += TLV_HDR_SIZE;
2345 bssid = ptr;
2346
2347 if (arg->num_bssid) {
2348 for (i = 0; i < arg->num_bssid; ++i) {
2349 ether_addr_copy(bssid->addr,
2350 arg->bssid_list[i].addr);
2351 bssid++;
2352 }
2353 }
2354
2355 ptr += arg->num_bssid * sizeof(*bssid);
2356
2357 len = extraie_len_with_pad;
2358 tlv = ptr;
2359 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_BYTE, len);
2360 ptr += TLV_HDR_SIZE;
2361
2362 if (extraie_len_with_pad)
2363 memcpy(ptr, arg->extraie.ptr,
2364 arg->extraie.len);
2365
2366 ptr += extraie_len_with_pad;
2367
2368 if (arg->num_hint_s_ssid) {
2369 len = arg->num_hint_s_ssid * sizeof(*s_ssid);
2370 tlv = ptr;
2371 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_FIXED_STRUCT, len);
2372 ptr += TLV_HDR_SIZE;
2373 s_ssid = ptr;
2374 for (i = 0; i < arg->num_hint_s_ssid; ++i) {
2375 s_ssid->freq_flags = arg->hint_s_ssid[i].freq_flags;
2376 s_ssid->short_ssid = arg->hint_s_ssid[i].short_ssid;
2377 s_ssid++;
2378 }
2379 ptr += len;
2380 }
2381
2382 if (arg->num_hint_bssid) {
2383 len = arg->num_hint_bssid * sizeof(struct ath12k_wmi_hint_bssid_arg);
2384 tlv = ptr;
2385 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_FIXED_STRUCT, len);
2386 ptr += TLV_HDR_SIZE;
2387 hint_bssid = ptr;
2388 for (i = 0; i < arg->num_hint_bssid; ++i) {
2389 hint_bssid->freq_flags =
2390 arg->hint_bssid[i].freq_flags;
2391 ether_addr_copy(&arg->hint_bssid[i].bssid.addr[0],
2392 &hint_bssid->bssid.addr[0]);
2393 hint_bssid++;
2394 }
2395 }
2396
2397 ret = ath12k_wmi_cmd_send(wmi, skb,
2398 WMI_START_SCAN_CMDID);
2399 if (ret) {
2400 ath12k_warn(ar->ab, "failed to send WMI_START_SCAN_CMDID\n");
2401 dev_kfree_skb(skb);
2402 }
2403
2404 return ret;
2405 }
2406
ath12k_wmi_send_scan_stop_cmd(struct ath12k * ar,struct ath12k_wmi_scan_cancel_arg * arg)2407 int ath12k_wmi_send_scan_stop_cmd(struct ath12k *ar,
2408 struct ath12k_wmi_scan_cancel_arg *arg)
2409 {
2410 struct ath12k_wmi_pdev *wmi = ar->wmi;
2411 struct wmi_stop_scan_cmd *cmd;
2412 struct sk_buff *skb;
2413 int ret;
2414
2415 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
2416 if (!skb)
2417 return -ENOMEM;
2418
2419 cmd = (struct wmi_stop_scan_cmd *)skb->data;
2420
2421 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_STOP_SCAN_CMD,
2422 sizeof(*cmd));
2423
2424 cmd->vdev_id = cpu_to_le32(arg->vdev_id);
2425 cmd->requestor = cpu_to_le32(arg->requester);
2426 cmd->scan_id = cpu_to_le32(arg->scan_id);
2427 cmd->pdev_id = cpu_to_le32(arg->pdev_id);
2428 /* stop the scan with the corresponding scan_id */
2429 if (arg->req_type == WLAN_SCAN_CANCEL_PDEV_ALL) {
2430 /* Cancelling all scans */
2431 cmd->req_type = cpu_to_le32(WMI_SCAN_STOP_ALL);
2432 } else if (arg->req_type == WLAN_SCAN_CANCEL_VDEV_ALL) {
2433 /* Cancelling VAP scans */
2434 cmd->req_type = cpu_to_le32(WMI_SCAN_STOP_VAP_ALL);
2435 } else if (arg->req_type == WLAN_SCAN_CANCEL_SINGLE) {
2436 /* Cancelling specific scan */
2437 cmd->req_type = WMI_SCAN_STOP_ONE;
2438 } else {
2439 ath12k_warn(ar->ab, "invalid scan cancel req_type %d",
2440 arg->req_type);
2441 dev_kfree_skb(skb);
2442 return -EINVAL;
2443 }
2444
2445 ret = ath12k_wmi_cmd_send(wmi, skb,
2446 WMI_STOP_SCAN_CMDID);
2447 if (ret) {
2448 ath12k_warn(ar->ab, "failed to send WMI_STOP_SCAN_CMDID\n");
2449 dev_kfree_skb(skb);
2450 }
2451
2452 return ret;
2453 }
2454
ath12k_wmi_send_scan_chan_list_cmd(struct ath12k * ar,struct ath12k_wmi_scan_chan_list_arg * arg)2455 int ath12k_wmi_send_scan_chan_list_cmd(struct ath12k *ar,
2456 struct ath12k_wmi_scan_chan_list_arg *arg)
2457 {
2458 struct ath12k_wmi_pdev *wmi = ar->wmi;
2459 struct wmi_scan_chan_list_cmd *cmd;
2460 struct sk_buff *skb;
2461 struct ath12k_wmi_channel_params *chan_info;
2462 struct ath12k_wmi_channel_arg *channel_arg;
2463 struct wmi_tlv *tlv;
2464 void *ptr;
2465 int i, ret, len;
2466 u16 num_send_chans, num_sends = 0, max_chan_limit = 0;
2467 __le32 *reg1, *reg2;
2468
2469 channel_arg = &arg->channel[0];
2470 while (arg->nallchans) {
2471 len = sizeof(*cmd) + TLV_HDR_SIZE;
2472 max_chan_limit = (wmi->wmi_ab->max_msg_len[ar->pdev_idx] - len) /
2473 sizeof(*chan_info);
2474
2475 num_send_chans = min(arg->nallchans, max_chan_limit);
2476
2477 arg->nallchans -= num_send_chans;
2478 len += sizeof(*chan_info) * num_send_chans;
2479
2480 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len);
2481 if (!skb)
2482 return -ENOMEM;
2483
2484 cmd = (struct wmi_scan_chan_list_cmd *)skb->data;
2485 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_SCAN_CHAN_LIST_CMD,
2486 sizeof(*cmd));
2487 cmd->pdev_id = cpu_to_le32(arg->pdev_id);
2488 cmd->num_scan_chans = cpu_to_le32(num_send_chans);
2489 if (num_sends)
2490 cmd->flags |= cpu_to_le32(WMI_APPEND_TO_EXISTING_CHAN_LIST_FLAG);
2491
2492 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
2493 "WMI no.of chan = %d len = %d pdev_id = %d num_sends = %d\n",
2494 num_send_chans, len, cmd->pdev_id, num_sends);
2495
2496 ptr = skb->data + sizeof(*cmd);
2497
2498 len = sizeof(*chan_info) * num_send_chans;
2499 tlv = ptr;
2500 tlv->header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_ARRAY_STRUCT,
2501 len);
2502 ptr += TLV_HDR_SIZE;
2503
2504 for (i = 0; i < num_send_chans; ++i) {
2505 chan_info = ptr;
2506 memset(chan_info, 0, sizeof(*chan_info));
2507 len = sizeof(*chan_info);
2508 chan_info->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_CHANNEL,
2509 len);
2510
2511 reg1 = &chan_info->reg_info_1;
2512 reg2 = &chan_info->reg_info_2;
2513 chan_info->mhz = cpu_to_le32(channel_arg->mhz);
2514 chan_info->band_center_freq1 = cpu_to_le32(channel_arg->cfreq1);
2515 chan_info->band_center_freq2 = cpu_to_le32(channel_arg->cfreq2);
2516
2517 if (channel_arg->is_chan_passive)
2518 chan_info->info |= cpu_to_le32(WMI_CHAN_INFO_PASSIVE);
2519 if (channel_arg->allow_he)
2520 chan_info->info |= cpu_to_le32(WMI_CHAN_INFO_ALLOW_HE);
2521 else if (channel_arg->allow_vht)
2522 chan_info->info |= cpu_to_le32(WMI_CHAN_INFO_ALLOW_VHT);
2523 else if (channel_arg->allow_ht)
2524 chan_info->info |= cpu_to_le32(WMI_CHAN_INFO_ALLOW_HT);
2525 if (channel_arg->half_rate)
2526 chan_info->info |= cpu_to_le32(WMI_CHAN_INFO_HALF_RATE);
2527 if (channel_arg->quarter_rate)
2528 chan_info->info |=
2529 cpu_to_le32(WMI_CHAN_INFO_QUARTER_RATE);
2530
2531 if (channel_arg->psc_channel)
2532 chan_info->info |= cpu_to_le32(WMI_CHAN_INFO_PSC);
2533
2534 if (channel_arg->dfs_set)
2535 chan_info->info |= cpu_to_le32(WMI_CHAN_INFO_DFS);
2536
2537 chan_info->info |= le32_encode_bits(channel_arg->phy_mode,
2538 WMI_CHAN_INFO_MODE);
2539 *reg1 |= le32_encode_bits(channel_arg->minpower,
2540 WMI_CHAN_REG_INFO1_MIN_PWR);
2541 *reg1 |= le32_encode_bits(channel_arg->maxpower,
2542 WMI_CHAN_REG_INFO1_MAX_PWR);
2543 *reg1 |= le32_encode_bits(channel_arg->maxregpower,
2544 WMI_CHAN_REG_INFO1_MAX_REG_PWR);
2545 *reg1 |= le32_encode_bits(channel_arg->reg_class_id,
2546 WMI_CHAN_REG_INFO1_REG_CLS);
2547 *reg2 |= le32_encode_bits(channel_arg->antennamax,
2548 WMI_CHAN_REG_INFO2_ANT_MAX);
2549
2550 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
2551 "WMI chan scan list chan[%d] = %u, chan_info->info %8x\n",
2552 i, chan_info->mhz, chan_info->info);
2553
2554 ptr += sizeof(*chan_info);
2555
2556 channel_arg++;
2557 }
2558
2559 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_SCAN_CHAN_LIST_CMDID);
2560 if (ret) {
2561 ath12k_warn(ar->ab, "failed to send WMI_SCAN_CHAN_LIST cmd\n");
2562 dev_kfree_skb(skb);
2563 return ret;
2564 }
2565
2566 num_sends++;
2567 }
2568
2569 return 0;
2570 }
2571
ath12k_wmi_send_wmm_update_cmd(struct ath12k * ar,u32 vdev_id,struct wmi_wmm_params_all_arg * param)2572 int ath12k_wmi_send_wmm_update_cmd(struct ath12k *ar, u32 vdev_id,
2573 struct wmi_wmm_params_all_arg *param)
2574 {
2575 struct ath12k_wmi_pdev *wmi = ar->wmi;
2576 struct wmi_vdev_set_wmm_params_cmd *cmd;
2577 struct wmi_wmm_params *wmm_param;
2578 struct wmi_wmm_params_arg *wmi_wmm_arg;
2579 struct sk_buff *skb;
2580 int ret, ac;
2581
2582 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
2583 if (!skb)
2584 return -ENOMEM;
2585
2586 cmd = (struct wmi_vdev_set_wmm_params_cmd *)skb->data;
2587 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_SET_WMM_PARAMS_CMD,
2588 sizeof(*cmd));
2589
2590 cmd->vdev_id = cpu_to_le32(vdev_id);
2591 cmd->wmm_param_type = 0;
2592
2593 for (ac = 0; ac < WME_NUM_AC; ac++) {
2594 switch (ac) {
2595 case WME_AC_BE:
2596 wmi_wmm_arg = ¶m->ac_be;
2597 break;
2598 case WME_AC_BK:
2599 wmi_wmm_arg = ¶m->ac_bk;
2600 break;
2601 case WME_AC_VI:
2602 wmi_wmm_arg = ¶m->ac_vi;
2603 break;
2604 case WME_AC_VO:
2605 wmi_wmm_arg = ¶m->ac_vo;
2606 break;
2607 }
2608
2609 wmm_param = (struct wmi_wmm_params *)&cmd->wmm_params[ac];
2610 wmm_param->tlv_header =
2611 ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_SET_WMM_PARAMS_CMD,
2612 sizeof(*wmm_param));
2613
2614 wmm_param->aifs = cpu_to_le32(wmi_wmm_arg->aifs);
2615 wmm_param->cwmin = cpu_to_le32(wmi_wmm_arg->cwmin);
2616 wmm_param->cwmax = cpu_to_le32(wmi_wmm_arg->cwmax);
2617 wmm_param->txoplimit = cpu_to_le32(wmi_wmm_arg->txop);
2618 wmm_param->acm = cpu_to_le32(wmi_wmm_arg->acm);
2619 wmm_param->no_ack = cpu_to_le32(wmi_wmm_arg->no_ack);
2620
2621 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
2622 "wmi wmm set ac %d aifs %d cwmin %d cwmax %d txop %d acm %d no_ack %d\n",
2623 ac, wmm_param->aifs, wmm_param->cwmin,
2624 wmm_param->cwmax, wmm_param->txoplimit,
2625 wmm_param->acm, wmm_param->no_ack);
2626 }
2627 ret = ath12k_wmi_cmd_send(wmi, skb,
2628 WMI_VDEV_SET_WMM_PARAMS_CMDID);
2629 if (ret) {
2630 ath12k_warn(ar->ab,
2631 "failed to send WMI_VDEV_SET_WMM_PARAMS_CMDID");
2632 dev_kfree_skb(skb);
2633 }
2634
2635 return ret;
2636 }
2637
ath12k_wmi_send_dfs_phyerr_offload_enable_cmd(struct ath12k * ar,u32 pdev_id)2638 int ath12k_wmi_send_dfs_phyerr_offload_enable_cmd(struct ath12k *ar,
2639 u32 pdev_id)
2640 {
2641 struct ath12k_wmi_pdev *wmi = ar->wmi;
2642 struct wmi_dfs_phyerr_offload_cmd *cmd;
2643 struct sk_buff *skb;
2644 int ret;
2645
2646 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
2647 if (!skb)
2648 return -ENOMEM;
2649
2650 cmd = (struct wmi_dfs_phyerr_offload_cmd *)skb->data;
2651 cmd->tlv_header =
2652 ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMD,
2653 sizeof(*cmd));
2654
2655 cmd->pdev_id = cpu_to_le32(pdev_id);
2656
2657 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
2658 "WMI dfs phy err offload enable pdev id %d\n", pdev_id);
2659
2660 ret = ath12k_wmi_cmd_send(wmi, skb,
2661 WMI_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMDID);
2662 if (ret) {
2663 ath12k_warn(ar->ab,
2664 "failed to send WMI_PDEV_DFS_PHYERR_OFFLOAD_ENABLE cmd\n");
2665 dev_kfree_skb(skb);
2666 }
2667
2668 return ret;
2669 }
2670
ath12k_wmi_delba_send(struct ath12k * ar,u32 vdev_id,const u8 * mac,u32 tid,u32 initiator,u32 reason)2671 int ath12k_wmi_delba_send(struct ath12k *ar, u32 vdev_id, const u8 *mac,
2672 u32 tid, u32 initiator, u32 reason)
2673 {
2674 struct ath12k_wmi_pdev *wmi = ar->wmi;
2675 struct wmi_delba_send_cmd *cmd;
2676 struct sk_buff *skb;
2677 int ret;
2678
2679 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
2680 if (!skb)
2681 return -ENOMEM;
2682
2683 cmd = (struct wmi_delba_send_cmd *)skb->data;
2684 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_DELBA_SEND_CMD,
2685 sizeof(*cmd));
2686 cmd->vdev_id = cpu_to_le32(vdev_id);
2687 ether_addr_copy(cmd->peer_macaddr.addr, mac);
2688 cmd->tid = cpu_to_le32(tid);
2689 cmd->initiator = cpu_to_le32(initiator);
2690 cmd->reasoncode = cpu_to_le32(reason);
2691
2692 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
2693 "wmi delba send vdev_id 0x%X mac_addr %pM tid %u initiator %u reason %u\n",
2694 vdev_id, mac, tid, initiator, reason);
2695
2696 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_DELBA_SEND_CMDID);
2697
2698 if (ret) {
2699 ath12k_warn(ar->ab,
2700 "failed to send WMI_DELBA_SEND_CMDID cmd\n");
2701 dev_kfree_skb(skb);
2702 }
2703
2704 return ret;
2705 }
2706
ath12k_wmi_addba_set_resp(struct ath12k * ar,u32 vdev_id,const u8 * mac,u32 tid,u32 status)2707 int ath12k_wmi_addba_set_resp(struct ath12k *ar, u32 vdev_id, const u8 *mac,
2708 u32 tid, u32 status)
2709 {
2710 struct ath12k_wmi_pdev *wmi = ar->wmi;
2711 struct wmi_addba_setresponse_cmd *cmd;
2712 struct sk_buff *skb;
2713 int ret;
2714
2715 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
2716 if (!skb)
2717 return -ENOMEM;
2718
2719 cmd = (struct wmi_addba_setresponse_cmd *)skb->data;
2720 cmd->tlv_header =
2721 ath12k_wmi_tlv_cmd_hdr(WMI_TAG_ADDBA_SETRESPONSE_CMD,
2722 sizeof(*cmd));
2723 cmd->vdev_id = cpu_to_le32(vdev_id);
2724 ether_addr_copy(cmd->peer_macaddr.addr, mac);
2725 cmd->tid = cpu_to_le32(tid);
2726 cmd->statuscode = cpu_to_le32(status);
2727
2728 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
2729 "wmi addba set resp vdev_id 0x%X mac_addr %pM tid %u status %u\n",
2730 vdev_id, mac, tid, status);
2731
2732 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_ADDBA_SET_RESP_CMDID);
2733
2734 if (ret) {
2735 ath12k_warn(ar->ab,
2736 "failed to send WMI_ADDBA_SET_RESP_CMDID cmd\n");
2737 dev_kfree_skb(skb);
2738 }
2739
2740 return ret;
2741 }
2742
ath12k_wmi_addba_send(struct ath12k * ar,u32 vdev_id,const u8 * mac,u32 tid,u32 buf_size)2743 int ath12k_wmi_addba_send(struct ath12k *ar, u32 vdev_id, const u8 *mac,
2744 u32 tid, u32 buf_size)
2745 {
2746 struct ath12k_wmi_pdev *wmi = ar->wmi;
2747 struct wmi_addba_send_cmd *cmd;
2748 struct sk_buff *skb;
2749 int ret;
2750
2751 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
2752 if (!skb)
2753 return -ENOMEM;
2754
2755 cmd = (struct wmi_addba_send_cmd *)skb->data;
2756 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_ADDBA_SEND_CMD,
2757 sizeof(*cmd));
2758 cmd->vdev_id = cpu_to_le32(vdev_id);
2759 ether_addr_copy(cmd->peer_macaddr.addr, mac);
2760 cmd->tid = cpu_to_le32(tid);
2761 cmd->buffersize = cpu_to_le32(buf_size);
2762
2763 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
2764 "wmi addba send vdev_id 0x%X mac_addr %pM tid %u bufsize %u\n",
2765 vdev_id, mac, tid, buf_size);
2766
2767 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_ADDBA_SEND_CMDID);
2768
2769 if (ret) {
2770 ath12k_warn(ar->ab,
2771 "failed to send WMI_ADDBA_SEND_CMDID cmd\n");
2772 dev_kfree_skb(skb);
2773 }
2774
2775 return ret;
2776 }
2777
ath12k_wmi_addba_clear_resp(struct ath12k * ar,u32 vdev_id,const u8 * mac)2778 int ath12k_wmi_addba_clear_resp(struct ath12k *ar, u32 vdev_id, const u8 *mac)
2779 {
2780 struct ath12k_wmi_pdev *wmi = ar->wmi;
2781 struct wmi_addba_clear_resp_cmd *cmd;
2782 struct sk_buff *skb;
2783 int ret;
2784
2785 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
2786 if (!skb)
2787 return -ENOMEM;
2788
2789 cmd = (struct wmi_addba_clear_resp_cmd *)skb->data;
2790 cmd->tlv_header =
2791 ath12k_wmi_tlv_cmd_hdr(WMI_TAG_ADDBA_CLEAR_RESP_CMD,
2792 sizeof(*cmd));
2793 cmd->vdev_id = cpu_to_le32(vdev_id);
2794 ether_addr_copy(cmd->peer_macaddr.addr, mac);
2795
2796 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
2797 "wmi addba clear resp vdev_id 0x%X mac_addr %pM\n",
2798 vdev_id, mac);
2799
2800 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_ADDBA_CLEAR_RESP_CMDID);
2801
2802 if (ret) {
2803 ath12k_warn(ar->ab,
2804 "failed to send WMI_ADDBA_CLEAR_RESP_CMDID cmd\n");
2805 dev_kfree_skb(skb);
2806 }
2807
2808 return ret;
2809 }
2810
ath12k_wmi_send_init_country_cmd(struct ath12k * ar,struct ath12k_wmi_init_country_arg * arg)2811 int ath12k_wmi_send_init_country_cmd(struct ath12k *ar,
2812 struct ath12k_wmi_init_country_arg *arg)
2813 {
2814 struct ath12k_wmi_pdev *wmi = ar->wmi;
2815 struct wmi_init_country_cmd *cmd;
2816 struct sk_buff *skb;
2817 int ret;
2818
2819 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd));
2820 if (!skb)
2821 return -ENOMEM;
2822
2823 cmd = (struct wmi_init_country_cmd *)skb->data;
2824 cmd->tlv_header =
2825 ath12k_wmi_tlv_cmd_hdr(WMI_TAG_SET_INIT_COUNTRY_CMD,
2826 sizeof(*cmd));
2827
2828 cmd->pdev_id = cpu_to_le32(ar->pdev->pdev_id);
2829
2830 switch (arg->flags) {
2831 case ALPHA_IS_SET:
2832 cmd->init_cc_type = WMI_COUNTRY_INFO_TYPE_ALPHA;
2833 memcpy(&cmd->cc_info.alpha2, arg->cc_info.alpha2, 3);
2834 break;
2835 case CC_IS_SET:
2836 cmd->init_cc_type = cpu_to_le32(WMI_COUNTRY_INFO_TYPE_COUNTRY_CODE);
2837 cmd->cc_info.country_code =
2838 cpu_to_le32(arg->cc_info.country_code);
2839 break;
2840 case REGDMN_IS_SET:
2841 cmd->init_cc_type = cpu_to_le32(WMI_COUNTRY_INFO_TYPE_REGDOMAIN);
2842 cmd->cc_info.regdom_id = cpu_to_le32(arg->cc_info.regdom_id);
2843 break;
2844 default:
2845 ret = -EINVAL;
2846 goto out;
2847 }
2848
2849 ret = ath12k_wmi_cmd_send(wmi, skb,
2850 WMI_SET_INIT_COUNTRY_CMDID);
2851
2852 out:
2853 if (ret) {
2854 ath12k_warn(ar->ab,
2855 "failed to send WMI_SET_INIT_COUNTRY CMD :%d\n",
2856 ret);
2857 dev_kfree_skb(skb);
2858 }
2859
2860 return ret;
2861 }
2862
2863 int
ath12k_wmi_send_twt_enable_cmd(struct ath12k * ar,u32 pdev_id)2864 ath12k_wmi_send_twt_enable_cmd(struct ath12k *ar, u32 pdev_id)
2865 {
2866 struct ath12k_wmi_pdev *wmi = ar->wmi;
2867 struct ath12k_base *ab = wmi->wmi_ab->ab;
2868 struct wmi_twt_enable_params_cmd *cmd;
2869 struct sk_buff *skb;
2870 int ret, len;
2871
2872 len = sizeof(*cmd);
2873
2874 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len);
2875 if (!skb)
2876 return -ENOMEM;
2877
2878 cmd = (struct wmi_twt_enable_params_cmd *)skb->data;
2879 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_TWT_ENABLE_CMD,
2880 len);
2881 cmd->pdev_id = cpu_to_le32(pdev_id);
2882 cmd->sta_cong_timer_ms = cpu_to_le32(ATH12K_TWT_DEF_STA_CONG_TIMER_MS);
2883 cmd->default_slot_size = cpu_to_le32(ATH12K_TWT_DEF_DEFAULT_SLOT_SIZE);
2884 cmd->congestion_thresh_setup =
2885 cpu_to_le32(ATH12K_TWT_DEF_CONGESTION_THRESH_SETUP);
2886 cmd->congestion_thresh_teardown =
2887 cpu_to_le32(ATH12K_TWT_DEF_CONGESTION_THRESH_TEARDOWN);
2888 cmd->congestion_thresh_critical =
2889 cpu_to_le32(ATH12K_TWT_DEF_CONGESTION_THRESH_CRITICAL);
2890 cmd->interference_thresh_teardown =
2891 cpu_to_le32(ATH12K_TWT_DEF_INTERFERENCE_THRESH_TEARDOWN);
2892 cmd->interference_thresh_setup =
2893 cpu_to_le32(ATH12K_TWT_DEF_INTERFERENCE_THRESH_SETUP);
2894 cmd->min_no_sta_setup = cpu_to_le32(ATH12K_TWT_DEF_MIN_NO_STA_SETUP);
2895 cmd->min_no_sta_teardown = cpu_to_le32(ATH12K_TWT_DEF_MIN_NO_STA_TEARDOWN);
2896 cmd->no_of_bcast_mcast_slots =
2897 cpu_to_le32(ATH12K_TWT_DEF_NO_OF_BCAST_MCAST_SLOTS);
2898 cmd->min_no_twt_slots = cpu_to_le32(ATH12K_TWT_DEF_MIN_NO_TWT_SLOTS);
2899 cmd->max_no_sta_twt = cpu_to_le32(ATH12K_TWT_DEF_MAX_NO_STA_TWT);
2900 cmd->mode_check_interval = cpu_to_le32(ATH12K_TWT_DEF_MODE_CHECK_INTERVAL);
2901 cmd->add_sta_slot_interval = cpu_to_le32(ATH12K_TWT_DEF_ADD_STA_SLOT_INTERVAL);
2902 cmd->remove_sta_slot_interval =
2903 cpu_to_le32(ATH12K_TWT_DEF_REMOVE_STA_SLOT_INTERVAL);
2904 /* TODO add MBSSID support */
2905 cmd->mbss_support = 0;
2906
2907 ret = ath12k_wmi_cmd_send(wmi, skb,
2908 WMI_TWT_ENABLE_CMDID);
2909 if (ret) {
2910 ath12k_warn(ab, "Failed to send WMI_TWT_ENABLE_CMDID");
2911 dev_kfree_skb(skb);
2912 }
2913 return ret;
2914 }
2915
2916 int
ath12k_wmi_send_twt_disable_cmd(struct ath12k * ar,u32 pdev_id)2917 ath12k_wmi_send_twt_disable_cmd(struct ath12k *ar, u32 pdev_id)
2918 {
2919 struct ath12k_wmi_pdev *wmi = ar->wmi;
2920 struct ath12k_base *ab = wmi->wmi_ab->ab;
2921 struct wmi_twt_disable_params_cmd *cmd;
2922 struct sk_buff *skb;
2923 int ret, len;
2924
2925 len = sizeof(*cmd);
2926
2927 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len);
2928 if (!skb)
2929 return -ENOMEM;
2930
2931 cmd = (struct wmi_twt_disable_params_cmd *)skb->data;
2932 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_TWT_DISABLE_CMD,
2933 len);
2934 cmd->pdev_id = cpu_to_le32(pdev_id);
2935
2936 ret = ath12k_wmi_cmd_send(wmi, skb,
2937 WMI_TWT_DISABLE_CMDID);
2938 if (ret) {
2939 ath12k_warn(ab, "Failed to send WMI_TWT_DISABLE_CMDID");
2940 dev_kfree_skb(skb);
2941 }
2942 return ret;
2943 }
2944
2945 int
ath12k_wmi_send_obss_spr_cmd(struct ath12k * ar,u32 vdev_id,struct ieee80211_he_obss_pd * he_obss_pd)2946 ath12k_wmi_send_obss_spr_cmd(struct ath12k *ar, u32 vdev_id,
2947 struct ieee80211_he_obss_pd *he_obss_pd)
2948 {
2949 struct ath12k_wmi_pdev *wmi = ar->wmi;
2950 struct ath12k_base *ab = wmi->wmi_ab->ab;
2951 struct wmi_obss_spatial_reuse_params_cmd *cmd;
2952 struct sk_buff *skb;
2953 int ret, len;
2954
2955 len = sizeof(*cmd);
2956
2957 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len);
2958 if (!skb)
2959 return -ENOMEM;
2960
2961 cmd = (struct wmi_obss_spatial_reuse_params_cmd *)skb->data;
2962 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_OBSS_SPATIAL_REUSE_SET_CMD,
2963 len);
2964 cmd->vdev_id = cpu_to_le32(vdev_id);
2965 cmd->enable = cpu_to_le32(he_obss_pd->enable);
2966 cmd->obss_min = a_cpu_to_sle32(he_obss_pd->min_offset);
2967 cmd->obss_max = a_cpu_to_sle32(he_obss_pd->max_offset);
2968
2969 ret = ath12k_wmi_cmd_send(wmi, skb,
2970 WMI_PDEV_OBSS_PD_SPATIAL_REUSE_CMDID);
2971 if (ret) {
2972 ath12k_warn(ab,
2973 "Failed to send WMI_PDEV_OBSS_PD_SPATIAL_REUSE_CMDID");
2974 dev_kfree_skb(skb);
2975 }
2976 return ret;
2977 }
2978
ath12k_wmi_obss_color_cfg_cmd(struct ath12k * ar,u32 vdev_id,u8 bss_color,u32 period,bool enable)2979 int ath12k_wmi_obss_color_cfg_cmd(struct ath12k *ar, u32 vdev_id,
2980 u8 bss_color, u32 period,
2981 bool enable)
2982 {
2983 struct ath12k_wmi_pdev *wmi = ar->wmi;
2984 struct ath12k_base *ab = wmi->wmi_ab->ab;
2985 struct wmi_obss_color_collision_cfg_params_cmd *cmd;
2986 struct sk_buff *skb;
2987 int ret, len;
2988
2989 len = sizeof(*cmd);
2990
2991 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len);
2992 if (!skb)
2993 return -ENOMEM;
2994
2995 cmd = (struct wmi_obss_color_collision_cfg_params_cmd *)skb->data;
2996 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_OBSS_COLOR_COLLISION_DET_CONFIG,
2997 len);
2998 cmd->vdev_id = cpu_to_le32(vdev_id);
2999 cmd->evt_type = enable ? cpu_to_le32(ATH12K_OBSS_COLOR_COLLISION_DETECTION) :
3000 cpu_to_le32(ATH12K_OBSS_COLOR_COLLISION_DETECTION_DISABLE);
3001 cmd->current_bss_color = cpu_to_le32(bss_color);
3002 cmd->detection_period_ms = cpu_to_le32(period);
3003 cmd->scan_period_ms = cpu_to_le32(ATH12K_BSS_COLOR_COLLISION_SCAN_PERIOD_MS);
3004 cmd->free_slot_expiry_time_ms = 0;
3005 cmd->flags = 0;
3006
3007 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
3008 "wmi_send_obss_color_collision_cfg id %d type %d bss_color %d detect_period %d scan_period %d\n",
3009 cmd->vdev_id, cmd->evt_type, cmd->current_bss_color,
3010 cmd->detection_period_ms, cmd->scan_period_ms);
3011
3012 ret = ath12k_wmi_cmd_send(wmi, skb,
3013 WMI_OBSS_COLOR_COLLISION_DET_CONFIG_CMDID);
3014 if (ret) {
3015 ath12k_warn(ab, "Failed to send WMI_OBSS_COLOR_COLLISION_DET_CONFIG_CMDID");
3016 dev_kfree_skb(skb);
3017 }
3018 return ret;
3019 }
3020
ath12k_wmi_send_bss_color_change_enable_cmd(struct ath12k * ar,u32 vdev_id,bool enable)3021 int ath12k_wmi_send_bss_color_change_enable_cmd(struct ath12k *ar, u32 vdev_id,
3022 bool enable)
3023 {
3024 struct ath12k_wmi_pdev *wmi = ar->wmi;
3025 struct ath12k_base *ab = wmi->wmi_ab->ab;
3026 struct wmi_bss_color_change_enable_params_cmd *cmd;
3027 struct sk_buff *skb;
3028 int ret, len;
3029
3030 len = sizeof(*cmd);
3031
3032 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len);
3033 if (!skb)
3034 return -ENOMEM;
3035
3036 cmd = (struct wmi_bss_color_change_enable_params_cmd *)skb->data;
3037 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_BSS_COLOR_CHANGE_ENABLE,
3038 len);
3039 cmd->vdev_id = cpu_to_le32(vdev_id);
3040 cmd->enable = enable ? cpu_to_le32(1) : 0;
3041
3042 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
3043 "wmi_send_bss_color_change_enable id %d enable %d\n",
3044 cmd->vdev_id, cmd->enable);
3045
3046 ret = ath12k_wmi_cmd_send(wmi, skb,
3047 WMI_BSS_COLOR_CHANGE_ENABLE_CMDID);
3048 if (ret) {
3049 ath12k_warn(ab, "Failed to send WMI_BSS_COLOR_CHANGE_ENABLE_CMDID");
3050 dev_kfree_skb(skb);
3051 }
3052 return ret;
3053 }
3054
ath12k_wmi_fils_discovery_tmpl(struct ath12k * ar,u32 vdev_id,struct sk_buff * tmpl)3055 int ath12k_wmi_fils_discovery_tmpl(struct ath12k *ar, u32 vdev_id,
3056 struct sk_buff *tmpl)
3057 {
3058 struct wmi_tlv *tlv;
3059 struct sk_buff *skb;
3060 void *ptr;
3061 int ret, len;
3062 size_t aligned_len;
3063 struct wmi_fils_discovery_tmpl_cmd *cmd;
3064
3065 aligned_len = roundup(tmpl->len, 4);
3066 len = sizeof(*cmd) + TLV_HDR_SIZE + aligned_len;
3067
3068 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
3069 "WMI vdev %i set FILS discovery template\n", vdev_id);
3070
3071 skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, len);
3072 if (!skb)
3073 return -ENOMEM;
3074
3075 cmd = (struct wmi_fils_discovery_tmpl_cmd *)skb->data;
3076 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_FILS_DISCOVERY_TMPL_CMD,
3077 sizeof(*cmd));
3078 cmd->vdev_id = cpu_to_le32(vdev_id);
3079 cmd->buf_len = cpu_to_le32(tmpl->len);
3080 ptr = skb->data + sizeof(*cmd);
3081
3082 tlv = ptr;
3083 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_BYTE, aligned_len);
3084 memcpy(tlv->value, tmpl->data, tmpl->len);
3085
3086 ret = ath12k_wmi_cmd_send(ar->wmi, skb, WMI_FILS_DISCOVERY_TMPL_CMDID);
3087 if (ret) {
3088 ath12k_warn(ar->ab,
3089 "WMI vdev %i failed to send FILS discovery template command\n",
3090 vdev_id);
3091 dev_kfree_skb(skb);
3092 }
3093 return ret;
3094 }
3095
ath12k_wmi_probe_resp_tmpl(struct ath12k * ar,u32 vdev_id,struct sk_buff * tmpl)3096 int ath12k_wmi_probe_resp_tmpl(struct ath12k *ar, u32 vdev_id,
3097 struct sk_buff *tmpl)
3098 {
3099 struct wmi_probe_tmpl_cmd *cmd;
3100 struct ath12k_wmi_bcn_prb_info_params *probe_info;
3101 struct wmi_tlv *tlv;
3102 struct sk_buff *skb;
3103 void *ptr;
3104 int ret, len;
3105 size_t aligned_len = roundup(tmpl->len, 4);
3106
3107 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
3108 "WMI vdev %i set probe response template\n", vdev_id);
3109
3110 len = sizeof(*cmd) + sizeof(*probe_info) + TLV_HDR_SIZE + aligned_len;
3111
3112 skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, len);
3113 if (!skb)
3114 return -ENOMEM;
3115
3116 cmd = (struct wmi_probe_tmpl_cmd *)skb->data;
3117 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PRB_TMPL_CMD,
3118 sizeof(*cmd));
3119 cmd->vdev_id = cpu_to_le32(vdev_id);
3120 cmd->buf_len = cpu_to_le32(tmpl->len);
3121
3122 ptr = skb->data + sizeof(*cmd);
3123
3124 probe_info = ptr;
3125 len = sizeof(*probe_info);
3126 probe_info->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_BCN_PRB_INFO,
3127 len);
3128 probe_info->caps = 0;
3129 probe_info->erp = 0;
3130
3131 ptr += sizeof(*probe_info);
3132
3133 tlv = ptr;
3134 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_BYTE, aligned_len);
3135 memcpy(tlv->value, tmpl->data, tmpl->len);
3136
3137 ret = ath12k_wmi_cmd_send(ar->wmi, skb, WMI_PRB_TMPL_CMDID);
3138 if (ret) {
3139 ath12k_warn(ar->ab,
3140 "WMI vdev %i failed to send probe response template command\n",
3141 vdev_id);
3142 dev_kfree_skb(skb);
3143 }
3144 return ret;
3145 }
3146
ath12k_wmi_fils_discovery(struct ath12k * ar,u32 vdev_id,u32 interval,bool unsol_bcast_probe_resp_enabled)3147 int ath12k_wmi_fils_discovery(struct ath12k *ar, u32 vdev_id, u32 interval,
3148 bool unsol_bcast_probe_resp_enabled)
3149 {
3150 struct sk_buff *skb;
3151 int ret, len;
3152 struct wmi_fils_discovery_cmd *cmd;
3153
3154 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
3155 "WMI vdev %i set %s interval to %u TU\n",
3156 vdev_id, unsol_bcast_probe_resp_enabled ?
3157 "unsolicited broadcast probe response" : "FILS discovery",
3158 interval);
3159
3160 len = sizeof(*cmd);
3161 skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, len);
3162 if (!skb)
3163 return -ENOMEM;
3164
3165 cmd = (struct wmi_fils_discovery_cmd *)skb->data;
3166 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_ENABLE_FILS_CMD,
3167 len);
3168 cmd->vdev_id = cpu_to_le32(vdev_id);
3169 cmd->interval = cpu_to_le32(interval);
3170 cmd->config = cpu_to_le32(unsol_bcast_probe_resp_enabled);
3171
3172 ret = ath12k_wmi_cmd_send(ar->wmi, skb, WMI_ENABLE_FILS_CMDID);
3173 if (ret) {
3174 ath12k_warn(ar->ab,
3175 "WMI vdev %i failed to send FILS discovery enable/disable command\n",
3176 vdev_id);
3177 dev_kfree_skb(skb);
3178 }
3179 return ret;
3180 }
3181
3182 static void
ath12k_fill_band_to_mac_param(struct ath12k_base * soc,struct ath12k_wmi_pdev_band_arg * arg)3183 ath12k_fill_band_to_mac_param(struct ath12k_base *soc,
3184 struct ath12k_wmi_pdev_band_arg *arg)
3185 {
3186 u8 i;
3187 struct ath12k_wmi_hal_reg_capabilities_ext_arg *hal_reg_cap;
3188 struct ath12k_pdev *pdev;
3189
3190 for (i = 0; i < soc->num_radios; i++) {
3191 pdev = &soc->pdevs[i];
3192 hal_reg_cap = &soc->hal_reg_cap[i];
3193 arg[i].pdev_id = pdev->pdev_id;
3194
3195 switch (pdev->cap.supported_bands) {
3196 case WMI_HOST_WLAN_2G_5G_CAP:
3197 arg[i].start_freq = hal_reg_cap->low_2ghz_chan;
3198 arg[i].end_freq = hal_reg_cap->high_5ghz_chan;
3199 break;
3200 case WMI_HOST_WLAN_2G_CAP:
3201 arg[i].start_freq = hal_reg_cap->low_2ghz_chan;
3202 arg[i].end_freq = hal_reg_cap->high_2ghz_chan;
3203 break;
3204 case WMI_HOST_WLAN_5G_CAP:
3205 arg[i].start_freq = hal_reg_cap->low_5ghz_chan;
3206 arg[i].end_freq = hal_reg_cap->high_5ghz_chan;
3207 break;
3208 default:
3209 break;
3210 }
3211 }
3212 }
3213
3214 static void
ath12k_wmi_copy_resource_config(struct ath12k_wmi_resource_config_params * wmi_cfg,struct ath12k_wmi_resource_config_arg * tg_cfg)3215 ath12k_wmi_copy_resource_config(struct ath12k_wmi_resource_config_params *wmi_cfg,
3216 struct ath12k_wmi_resource_config_arg *tg_cfg)
3217 {
3218 wmi_cfg->num_vdevs = cpu_to_le32(tg_cfg->num_vdevs);
3219 wmi_cfg->num_peers = cpu_to_le32(tg_cfg->num_peers);
3220 wmi_cfg->num_offload_peers = cpu_to_le32(tg_cfg->num_offload_peers);
3221 wmi_cfg->num_offload_reorder_buffs =
3222 cpu_to_le32(tg_cfg->num_offload_reorder_buffs);
3223 wmi_cfg->num_peer_keys = cpu_to_le32(tg_cfg->num_peer_keys);
3224 wmi_cfg->num_tids = cpu_to_le32(tg_cfg->num_tids);
3225 wmi_cfg->ast_skid_limit = cpu_to_le32(tg_cfg->ast_skid_limit);
3226 wmi_cfg->tx_chain_mask = cpu_to_le32(tg_cfg->tx_chain_mask);
3227 wmi_cfg->rx_chain_mask = cpu_to_le32(tg_cfg->rx_chain_mask);
3228 wmi_cfg->rx_timeout_pri[0] = cpu_to_le32(tg_cfg->rx_timeout_pri[0]);
3229 wmi_cfg->rx_timeout_pri[1] = cpu_to_le32(tg_cfg->rx_timeout_pri[1]);
3230 wmi_cfg->rx_timeout_pri[2] = cpu_to_le32(tg_cfg->rx_timeout_pri[2]);
3231 wmi_cfg->rx_timeout_pri[3] = cpu_to_le32(tg_cfg->rx_timeout_pri[3]);
3232 wmi_cfg->rx_decap_mode = cpu_to_le32(tg_cfg->rx_decap_mode);
3233 wmi_cfg->scan_max_pending_req = cpu_to_le32(tg_cfg->scan_max_pending_req);
3234 wmi_cfg->bmiss_offload_max_vdev = cpu_to_le32(tg_cfg->bmiss_offload_max_vdev);
3235 wmi_cfg->roam_offload_max_vdev = cpu_to_le32(tg_cfg->roam_offload_max_vdev);
3236 wmi_cfg->roam_offload_max_ap_profiles =
3237 cpu_to_le32(tg_cfg->roam_offload_max_ap_profiles);
3238 wmi_cfg->num_mcast_groups = cpu_to_le32(tg_cfg->num_mcast_groups);
3239 wmi_cfg->num_mcast_table_elems = cpu_to_le32(tg_cfg->num_mcast_table_elems);
3240 wmi_cfg->mcast2ucast_mode = cpu_to_le32(tg_cfg->mcast2ucast_mode);
3241 wmi_cfg->tx_dbg_log_size = cpu_to_le32(tg_cfg->tx_dbg_log_size);
3242 wmi_cfg->num_wds_entries = cpu_to_le32(tg_cfg->num_wds_entries);
3243 wmi_cfg->dma_burst_size = cpu_to_le32(tg_cfg->dma_burst_size);
3244 wmi_cfg->mac_aggr_delim = cpu_to_le32(tg_cfg->mac_aggr_delim);
3245 wmi_cfg->rx_skip_defrag_timeout_dup_detection_check =
3246 cpu_to_le32(tg_cfg->rx_skip_defrag_timeout_dup_detection_check);
3247 wmi_cfg->vow_config = cpu_to_le32(tg_cfg->vow_config);
3248 wmi_cfg->gtk_offload_max_vdev = cpu_to_le32(tg_cfg->gtk_offload_max_vdev);
3249 wmi_cfg->num_msdu_desc = cpu_to_le32(tg_cfg->num_msdu_desc);
3250 wmi_cfg->max_frag_entries = cpu_to_le32(tg_cfg->max_frag_entries);
3251 wmi_cfg->num_tdls_vdevs = cpu_to_le32(tg_cfg->num_tdls_vdevs);
3252 wmi_cfg->num_tdls_conn_table_entries =
3253 cpu_to_le32(tg_cfg->num_tdls_conn_table_entries);
3254 wmi_cfg->beacon_tx_offload_max_vdev =
3255 cpu_to_le32(tg_cfg->beacon_tx_offload_max_vdev);
3256 wmi_cfg->num_multicast_filter_entries =
3257 cpu_to_le32(tg_cfg->num_multicast_filter_entries);
3258 wmi_cfg->num_wow_filters = cpu_to_le32(tg_cfg->num_wow_filters);
3259 wmi_cfg->num_keep_alive_pattern = cpu_to_le32(tg_cfg->num_keep_alive_pattern);
3260 wmi_cfg->keep_alive_pattern_size = cpu_to_le32(tg_cfg->keep_alive_pattern_size);
3261 wmi_cfg->max_tdls_concurrent_sleep_sta =
3262 cpu_to_le32(tg_cfg->max_tdls_concurrent_sleep_sta);
3263 wmi_cfg->max_tdls_concurrent_buffer_sta =
3264 cpu_to_le32(tg_cfg->max_tdls_concurrent_buffer_sta);
3265 wmi_cfg->wmi_send_separate = cpu_to_le32(tg_cfg->wmi_send_separate);
3266 wmi_cfg->num_ocb_vdevs = cpu_to_le32(tg_cfg->num_ocb_vdevs);
3267 wmi_cfg->num_ocb_channels = cpu_to_le32(tg_cfg->num_ocb_channels);
3268 wmi_cfg->num_ocb_schedules = cpu_to_le32(tg_cfg->num_ocb_schedules);
3269 wmi_cfg->bpf_instruction_size = cpu_to_le32(tg_cfg->bpf_instruction_size);
3270 wmi_cfg->max_bssid_rx_filters = cpu_to_le32(tg_cfg->max_bssid_rx_filters);
3271 wmi_cfg->use_pdev_id = cpu_to_le32(tg_cfg->use_pdev_id);
3272 wmi_cfg->flag1 = cpu_to_le32(tg_cfg->atf_config);
3273 wmi_cfg->peer_map_unmap_version = cpu_to_le32(tg_cfg->peer_map_unmap_version);
3274 wmi_cfg->sched_params = cpu_to_le32(tg_cfg->sched_params);
3275 wmi_cfg->twt_ap_pdev_count = cpu_to_le32(tg_cfg->twt_ap_pdev_count);
3276 wmi_cfg->twt_ap_sta_count = cpu_to_le32(tg_cfg->twt_ap_sta_count);
3277 wmi_cfg->host_service_flags = cpu_to_le32(tg_cfg->is_reg_cc_ext_event_supported <<
3278 WMI_RSRC_CFG_HOST_SVC_FLAG_REG_CC_EXT_SUPPORT_BIT);
3279 }
3280
ath12k_init_cmd_send(struct ath12k_wmi_pdev * wmi,struct ath12k_wmi_init_cmd_arg * arg)3281 static int ath12k_init_cmd_send(struct ath12k_wmi_pdev *wmi,
3282 struct ath12k_wmi_init_cmd_arg *arg)
3283 {
3284 struct ath12k_base *ab = wmi->wmi_ab->ab;
3285 struct sk_buff *skb;
3286 struct wmi_init_cmd *cmd;
3287 struct ath12k_wmi_resource_config_params *cfg;
3288 struct ath12k_wmi_pdev_set_hw_mode_cmd *hw_mode;
3289 struct ath12k_wmi_pdev_band_to_mac_params *band_to_mac;
3290 struct ath12k_wmi_host_mem_chunk_params *host_mem_chunks;
3291 struct wmi_tlv *tlv;
3292 size_t ret, len;
3293 void *ptr;
3294 u32 hw_mode_len = 0;
3295 u16 idx;
3296
3297 if (arg->hw_mode_id != WMI_HOST_HW_MODE_MAX)
3298 hw_mode_len = sizeof(*hw_mode) + TLV_HDR_SIZE +
3299 (arg->num_band_to_mac * sizeof(*band_to_mac));
3300
3301 len = sizeof(*cmd) + TLV_HDR_SIZE + sizeof(*cfg) + hw_mode_len +
3302 (arg->num_mem_chunks ? (sizeof(*host_mem_chunks) * WMI_MAX_MEM_REQS) : 0);
3303
3304 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len);
3305 if (!skb)
3306 return -ENOMEM;
3307
3308 cmd = (struct wmi_init_cmd *)skb->data;
3309
3310 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_INIT_CMD,
3311 sizeof(*cmd));
3312
3313 ptr = skb->data + sizeof(*cmd);
3314 cfg = ptr;
3315
3316 ath12k_wmi_copy_resource_config(cfg, &arg->res_cfg);
3317
3318 cfg->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_RESOURCE_CONFIG,
3319 sizeof(*cfg));
3320
3321 ptr += sizeof(*cfg);
3322 host_mem_chunks = ptr + TLV_HDR_SIZE;
3323 len = sizeof(struct ath12k_wmi_host_mem_chunk_params);
3324
3325 for (idx = 0; idx < arg->num_mem_chunks; ++idx) {
3326 host_mem_chunks[idx].tlv_header =
3327 ath12k_wmi_tlv_hdr(WMI_TAG_WLAN_HOST_MEMORY_CHUNK,
3328 len);
3329
3330 host_mem_chunks[idx].ptr = cpu_to_le32(arg->mem_chunks[idx].paddr);
3331 host_mem_chunks[idx].size = cpu_to_le32(arg->mem_chunks[idx].len);
3332 host_mem_chunks[idx].req_id = cpu_to_le32(arg->mem_chunks[idx].req_id);
3333
3334 ath12k_dbg(ab, ATH12K_DBG_WMI,
3335 "WMI host mem chunk req_id %d paddr 0x%llx len %d\n",
3336 arg->mem_chunks[idx].req_id,
3337 (u64)arg->mem_chunks[idx].paddr,
3338 arg->mem_chunks[idx].len);
3339 }
3340 cmd->num_host_mem_chunks = cpu_to_le32(arg->num_mem_chunks);
3341 len = sizeof(struct ath12k_wmi_host_mem_chunk_params) * arg->num_mem_chunks;
3342
3343 /* num_mem_chunks is zero */
3344 tlv = ptr;
3345 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, len);
3346 ptr += TLV_HDR_SIZE + len;
3347
3348 if (arg->hw_mode_id != WMI_HOST_HW_MODE_MAX) {
3349 hw_mode = (struct ath12k_wmi_pdev_set_hw_mode_cmd *)ptr;
3350 hw_mode->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_SET_HW_MODE_CMD,
3351 sizeof(*hw_mode));
3352
3353 hw_mode->hw_mode_index = cpu_to_le32(arg->hw_mode_id);
3354 hw_mode->num_band_to_mac = cpu_to_le32(arg->num_band_to_mac);
3355
3356 ptr += sizeof(*hw_mode);
3357
3358 len = arg->num_band_to_mac * sizeof(*band_to_mac);
3359 tlv = ptr;
3360 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, len);
3361
3362 ptr += TLV_HDR_SIZE;
3363 len = sizeof(*band_to_mac);
3364
3365 for (idx = 0; idx < arg->num_band_to_mac; idx++) {
3366 band_to_mac = (void *)ptr;
3367
3368 band_to_mac->tlv_header =
3369 ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_BAND_TO_MAC,
3370 len);
3371 band_to_mac->pdev_id = cpu_to_le32(arg->band_to_mac[idx].pdev_id);
3372 band_to_mac->start_freq =
3373 cpu_to_le32(arg->band_to_mac[idx].start_freq);
3374 band_to_mac->end_freq =
3375 cpu_to_le32(arg->band_to_mac[idx].end_freq);
3376 ptr += sizeof(*band_to_mac);
3377 }
3378 }
3379
3380 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_INIT_CMDID);
3381 if (ret) {
3382 ath12k_warn(ab, "failed to send WMI_INIT_CMDID\n");
3383 dev_kfree_skb(skb);
3384 }
3385
3386 return ret;
3387 }
3388
ath12k_wmi_pdev_lro_cfg(struct ath12k * ar,int pdev_id)3389 int ath12k_wmi_pdev_lro_cfg(struct ath12k *ar,
3390 int pdev_id)
3391 {
3392 struct ath12k_wmi_pdev_lro_config_cmd *cmd;
3393 struct sk_buff *skb;
3394 int ret;
3395
3396 skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, sizeof(*cmd));
3397 if (!skb)
3398 return -ENOMEM;
3399
3400 cmd = (struct ath12k_wmi_pdev_lro_config_cmd *)skb->data;
3401 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_LRO_INFO_CMD,
3402 sizeof(*cmd));
3403
3404 get_random_bytes(cmd->th_4, sizeof(cmd->th_4));
3405 get_random_bytes(cmd->th_6, sizeof(cmd->th_6));
3406
3407 cmd->pdev_id = cpu_to_le32(pdev_id);
3408
3409 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
3410 "WMI lro cfg cmd pdev_id 0x%x\n", pdev_id);
3411
3412 ret = ath12k_wmi_cmd_send(ar->wmi, skb, WMI_LRO_CONFIG_CMDID);
3413 if (ret) {
3414 ath12k_warn(ar->ab,
3415 "failed to send lro cfg req wmi cmd\n");
3416 goto err;
3417 }
3418
3419 return 0;
3420 err:
3421 dev_kfree_skb(skb);
3422 return ret;
3423 }
3424
ath12k_wmi_wait_for_service_ready(struct ath12k_base * ab)3425 int ath12k_wmi_wait_for_service_ready(struct ath12k_base *ab)
3426 {
3427 unsigned long time_left;
3428
3429 time_left = wait_for_completion_timeout(&ab->wmi_ab.service_ready,
3430 WMI_SERVICE_READY_TIMEOUT_HZ);
3431 if (!time_left)
3432 return -ETIMEDOUT;
3433
3434 return 0;
3435 }
3436
ath12k_wmi_wait_for_unified_ready(struct ath12k_base * ab)3437 int ath12k_wmi_wait_for_unified_ready(struct ath12k_base *ab)
3438 {
3439 unsigned long time_left;
3440
3441 time_left = wait_for_completion_timeout(&ab->wmi_ab.unified_ready,
3442 WMI_SERVICE_READY_TIMEOUT_HZ);
3443 if (!time_left)
3444 return -ETIMEDOUT;
3445
3446 return 0;
3447 }
3448
ath12k_wmi_set_hw_mode(struct ath12k_base * ab,enum wmi_host_hw_mode_config_type mode)3449 int ath12k_wmi_set_hw_mode(struct ath12k_base *ab,
3450 enum wmi_host_hw_mode_config_type mode)
3451 {
3452 struct ath12k_wmi_pdev_set_hw_mode_cmd *cmd;
3453 struct sk_buff *skb;
3454 struct ath12k_wmi_base *wmi_ab = &ab->wmi_ab;
3455 int len;
3456 int ret;
3457
3458 len = sizeof(*cmd);
3459
3460 skb = ath12k_wmi_alloc_skb(wmi_ab, len);
3461 if (!skb)
3462 return -ENOMEM;
3463
3464 cmd = (struct ath12k_wmi_pdev_set_hw_mode_cmd *)skb->data;
3465
3466 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_SET_HW_MODE_CMD,
3467 sizeof(*cmd));
3468
3469 cmd->pdev_id = WMI_PDEV_ID_SOC;
3470 cmd->hw_mode_index = cpu_to_le32(mode);
3471
3472 ret = ath12k_wmi_cmd_send(&wmi_ab->wmi[0], skb, WMI_PDEV_SET_HW_MODE_CMDID);
3473 if (ret) {
3474 ath12k_warn(ab, "failed to send WMI_PDEV_SET_HW_MODE_CMDID\n");
3475 dev_kfree_skb(skb);
3476 }
3477
3478 return ret;
3479 }
3480
ath12k_wmi_cmd_init(struct ath12k_base * ab)3481 int ath12k_wmi_cmd_init(struct ath12k_base *ab)
3482 {
3483 struct ath12k_wmi_base *wmi_sc = &ab->wmi_ab;
3484 struct ath12k_wmi_init_cmd_arg arg = {};
3485
3486 if (test_bit(WMI_TLV_SERVICE_REG_CC_EXT_EVENT_SUPPORT,
3487 ab->wmi_ab.svc_map))
3488 arg.res_cfg.is_reg_cc_ext_event_supported = true;
3489
3490 ab->hw_params->wmi_init(ab, &arg.res_cfg);
3491
3492 arg.num_mem_chunks = wmi_sc->num_mem_chunks;
3493 arg.hw_mode_id = wmi_sc->preferred_hw_mode;
3494 arg.mem_chunks = wmi_sc->mem_chunks;
3495
3496 if (ab->hw_params->single_pdev_only)
3497 arg.hw_mode_id = WMI_HOST_HW_MODE_MAX;
3498
3499 arg.num_band_to_mac = ab->num_radios;
3500 ath12k_fill_band_to_mac_param(ab, arg.band_to_mac);
3501
3502 return ath12k_init_cmd_send(&wmi_sc->wmi[0], &arg);
3503 }
3504
ath12k_wmi_vdev_spectral_conf(struct ath12k * ar,struct ath12k_wmi_vdev_spectral_conf_arg * arg)3505 int ath12k_wmi_vdev_spectral_conf(struct ath12k *ar,
3506 struct ath12k_wmi_vdev_spectral_conf_arg *arg)
3507 {
3508 struct ath12k_wmi_vdev_spectral_conf_cmd *cmd;
3509 struct sk_buff *skb;
3510 int ret;
3511
3512 skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, sizeof(*cmd));
3513 if (!skb)
3514 return -ENOMEM;
3515
3516 cmd = (struct ath12k_wmi_vdev_spectral_conf_cmd *)skb->data;
3517 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_SPECTRAL_CONFIGURE_CMD,
3518 sizeof(*cmd));
3519 cmd->vdev_id = cpu_to_le32(arg->vdev_id);
3520 cmd->scan_count = cpu_to_le32(arg->scan_count);
3521 cmd->scan_period = cpu_to_le32(arg->scan_period);
3522 cmd->scan_priority = cpu_to_le32(arg->scan_priority);
3523 cmd->scan_fft_size = cpu_to_le32(arg->scan_fft_size);
3524 cmd->scan_gc_ena = cpu_to_le32(arg->scan_gc_ena);
3525 cmd->scan_restart_ena = cpu_to_le32(arg->scan_restart_ena);
3526 cmd->scan_noise_floor_ref = cpu_to_le32(arg->scan_noise_floor_ref);
3527 cmd->scan_init_delay = cpu_to_le32(arg->scan_init_delay);
3528 cmd->scan_nb_tone_thr = cpu_to_le32(arg->scan_nb_tone_thr);
3529 cmd->scan_str_bin_thr = cpu_to_le32(arg->scan_str_bin_thr);
3530 cmd->scan_wb_rpt_mode = cpu_to_le32(arg->scan_wb_rpt_mode);
3531 cmd->scan_rssi_rpt_mode = cpu_to_le32(arg->scan_rssi_rpt_mode);
3532 cmd->scan_rssi_thr = cpu_to_le32(arg->scan_rssi_thr);
3533 cmd->scan_pwr_format = cpu_to_le32(arg->scan_pwr_format);
3534 cmd->scan_rpt_mode = cpu_to_le32(arg->scan_rpt_mode);
3535 cmd->scan_bin_scale = cpu_to_le32(arg->scan_bin_scale);
3536 cmd->scan_dbm_adj = cpu_to_le32(arg->scan_dbm_adj);
3537 cmd->scan_chn_mask = cpu_to_le32(arg->scan_chn_mask);
3538
3539 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
3540 "WMI spectral scan config cmd vdev_id 0x%x\n",
3541 arg->vdev_id);
3542
3543 ret = ath12k_wmi_cmd_send(ar->wmi, skb,
3544 WMI_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID);
3545 if (ret) {
3546 ath12k_warn(ar->ab,
3547 "failed to send spectral scan config wmi cmd\n");
3548 goto err;
3549 }
3550
3551 return 0;
3552 err:
3553 dev_kfree_skb(skb);
3554 return ret;
3555 }
3556
ath12k_wmi_vdev_spectral_enable(struct ath12k * ar,u32 vdev_id,u32 trigger,u32 enable)3557 int ath12k_wmi_vdev_spectral_enable(struct ath12k *ar, u32 vdev_id,
3558 u32 trigger, u32 enable)
3559 {
3560 struct ath12k_wmi_vdev_spectral_enable_cmd *cmd;
3561 struct sk_buff *skb;
3562 int ret;
3563
3564 skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, sizeof(*cmd));
3565 if (!skb)
3566 return -ENOMEM;
3567
3568 cmd = (struct ath12k_wmi_vdev_spectral_enable_cmd *)skb->data;
3569 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_SPECTRAL_ENABLE_CMD,
3570 sizeof(*cmd));
3571
3572 cmd->vdev_id = cpu_to_le32(vdev_id);
3573 cmd->trigger_cmd = cpu_to_le32(trigger);
3574 cmd->enable_cmd = cpu_to_le32(enable);
3575
3576 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
3577 "WMI spectral enable cmd vdev id 0x%x\n",
3578 vdev_id);
3579
3580 ret = ath12k_wmi_cmd_send(ar->wmi, skb,
3581 WMI_VDEV_SPECTRAL_SCAN_ENABLE_CMDID);
3582 if (ret) {
3583 ath12k_warn(ar->ab,
3584 "failed to send spectral enable wmi cmd\n");
3585 goto err;
3586 }
3587
3588 return 0;
3589 err:
3590 dev_kfree_skb(skb);
3591 return ret;
3592 }
3593
ath12k_wmi_pdev_dma_ring_cfg(struct ath12k * ar,struct ath12k_wmi_pdev_dma_ring_cfg_arg * arg)3594 int ath12k_wmi_pdev_dma_ring_cfg(struct ath12k *ar,
3595 struct ath12k_wmi_pdev_dma_ring_cfg_arg *arg)
3596 {
3597 struct ath12k_wmi_pdev_dma_ring_cfg_req_cmd *cmd;
3598 struct sk_buff *skb;
3599 int ret;
3600
3601 skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, sizeof(*cmd));
3602 if (!skb)
3603 return -ENOMEM;
3604
3605 cmd = (struct ath12k_wmi_pdev_dma_ring_cfg_req_cmd *)skb->data;
3606 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_DMA_RING_CFG_REQ,
3607 sizeof(*cmd));
3608
3609 cmd->pdev_id = cpu_to_le32(DP_SW2HW_MACID(arg->pdev_id));
3610 cmd->module_id = cpu_to_le32(arg->module_id);
3611 cmd->base_paddr_lo = cpu_to_le32(arg->base_paddr_lo);
3612 cmd->base_paddr_hi = cpu_to_le32(arg->base_paddr_hi);
3613 cmd->head_idx_paddr_lo = cpu_to_le32(arg->head_idx_paddr_lo);
3614 cmd->head_idx_paddr_hi = cpu_to_le32(arg->head_idx_paddr_hi);
3615 cmd->tail_idx_paddr_lo = cpu_to_le32(arg->tail_idx_paddr_lo);
3616 cmd->tail_idx_paddr_hi = cpu_to_le32(arg->tail_idx_paddr_hi);
3617 cmd->num_elems = cpu_to_le32(arg->num_elems);
3618 cmd->buf_size = cpu_to_le32(arg->buf_size);
3619 cmd->num_resp_per_event = cpu_to_le32(arg->num_resp_per_event);
3620 cmd->event_timeout_ms = cpu_to_le32(arg->event_timeout_ms);
3621
3622 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
3623 "WMI DMA ring cfg req cmd pdev_id 0x%x\n",
3624 arg->pdev_id);
3625
3626 ret = ath12k_wmi_cmd_send(ar->wmi, skb,
3627 WMI_PDEV_DMA_RING_CFG_REQ_CMDID);
3628 if (ret) {
3629 ath12k_warn(ar->ab,
3630 "failed to send dma ring cfg req wmi cmd\n");
3631 goto err;
3632 }
3633
3634 return 0;
3635 err:
3636 dev_kfree_skb(skb);
3637 return ret;
3638 }
3639
ath12k_wmi_dma_buf_entry_parse(struct ath12k_base * soc,u16 tag,u16 len,const void * ptr,void * data)3640 static int ath12k_wmi_dma_buf_entry_parse(struct ath12k_base *soc,
3641 u16 tag, u16 len,
3642 const void *ptr, void *data)
3643 {
3644 struct ath12k_wmi_dma_buf_release_arg *arg = data;
3645
3646 if (tag != WMI_TAG_DMA_BUF_RELEASE_ENTRY)
3647 return -EPROTO;
3648
3649 if (arg->num_buf_entry >= le32_to_cpu(arg->fixed.num_buf_release_entry))
3650 return -ENOBUFS;
3651
3652 arg->num_buf_entry++;
3653 return 0;
3654 }
3655
ath12k_wmi_dma_buf_meta_parse(struct ath12k_base * soc,u16 tag,u16 len,const void * ptr,void * data)3656 static int ath12k_wmi_dma_buf_meta_parse(struct ath12k_base *soc,
3657 u16 tag, u16 len,
3658 const void *ptr, void *data)
3659 {
3660 struct ath12k_wmi_dma_buf_release_arg *arg = data;
3661
3662 if (tag != WMI_TAG_DMA_BUF_RELEASE_SPECTRAL_META_DATA)
3663 return -EPROTO;
3664
3665 if (arg->num_meta >= le32_to_cpu(arg->fixed.num_meta_data_entry))
3666 return -ENOBUFS;
3667
3668 arg->num_meta++;
3669
3670 return 0;
3671 }
3672
ath12k_wmi_dma_buf_parse(struct ath12k_base * ab,u16 tag,u16 len,const void * ptr,void * data)3673 static int ath12k_wmi_dma_buf_parse(struct ath12k_base *ab,
3674 u16 tag, u16 len,
3675 const void *ptr, void *data)
3676 {
3677 struct ath12k_wmi_dma_buf_release_arg *arg = data;
3678 const struct ath12k_wmi_dma_buf_release_fixed_params *fixed;
3679 u32 pdev_id;
3680 int ret;
3681
3682 switch (tag) {
3683 case WMI_TAG_DMA_BUF_RELEASE:
3684 fixed = ptr;
3685 arg->fixed = *fixed;
3686 pdev_id = DP_HW2SW_MACID(le32_to_cpu(fixed->pdev_id));
3687 arg->fixed.pdev_id = cpu_to_le32(pdev_id);
3688 break;
3689 case WMI_TAG_ARRAY_STRUCT:
3690 if (!arg->buf_entry_done) {
3691 arg->num_buf_entry = 0;
3692 arg->buf_entry = ptr;
3693
3694 ret = ath12k_wmi_tlv_iter(ab, ptr, len,
3695 ath12k_wmi_dma_buf_entry_parse,
3696 arg);
3697 if (ret) {
3698 ath12k_warn(ab, "failed to parse dma buf entry tlv %d\n",
3699 ret);
3700 return ret;
3701 }
3702
3703 arg->buf_entry_done = true;
3704 } else if (!arg->meta_data_done) {
3705 arg->num_meta = 0;
3706 arg->meta_data = ptr;
3707
3708 ret = ath12k_wmi_tlv_iter(ab, ptr, len,
3709 ath12k_wmi_dma_buf_meta_parse,
3710 arg);
3711 if (ret) {
3712 ath12k_warn(ab, "failed to parse dma buf meta tlv %d\n",
3713 ret);
3714 return ret;
3715 }
3716
3717 arg->meta_data_done = true;
3718 }
3719 break;
3720 default:
3721 break;
3722 }
3723 return 0;
3724 }
3725
ath12k_wmi_pdev_dma_ring_buf_release_event(struct ath12k_base * ab,struct sk_buff * skb)3726 static void ath12k_wmi_pdev_dma_ring_buf_release_event(struct ath12k_base *ab,
3727 struct sk_buff *skb)
3728 {
3729 struct ath12k_wmi_dma_buf_release_arg arg = {};
3730 struct ath12k_dbring_buf_release_event param;
3731 int ret;
3732
3733 ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len,
3734 ath12k_wmi_dma_buf_parse,
3735 &arg);
3736 if (ret) {
3737 ath12k_warn(ab, "failed to parse dma buf release tlv %d\n", ret);
3738 return;
3739 }
3740
3741 param.fixed = arg.fixed;
3742 param.buf_entry = arg.buf_entry;
3743 param.num_buf_entry = arg.num_buf_entry;
3744 param.meta_data = arg.meta_data;
3745 param.num_meta = arg.num_meta;
3746
3747 ret = ath12k_dbring_buffer_release_event(ab, ¶m);
3748 if (ret) {
3749 ath12k_warn(ab, "failed to handle dma buf release event %d\n", ret);
3750 return;
3751 }
3752 }
3753
ath12k_wmi_hw_mode_caps_parse(struct ath12k_base * soc,u16 tag,u16 len,const void * ptr,void * data)3754 static int ath12k_wmi_hw_mode_caps_parse(struct ath12k_base *soc,
3755 u16 tag, u16 len,
3756 const void *ptr, void *data)
3757 {
3758 struct ath12k_wmi_svc_rdy_ext_parse *svc_rdy_ext = data;
3759 struct ath12k_wmi_hw_mode_cap_params *hw_mode_cap;
3760 u32 phy_map = 0;
3761
3762 if (tag != WMI_TAG_HW_MODE_CAPABILITIES)
3763 return -EPROTO;
3764
3765 if (svc_rdy_ext->n_hw_mode_caps >= svc_rdy_ext->arg.num_hw_modes)
3766 return -ENOBUFS;
3767
3768 hw_mode_cap = container_of(ptr, struct ath12k_wmi_hw_mode_cap_params,
3769 hw_mode_id);
3770 svc_rdy_ext->n_hw_mode_caps++;
3771
3772 phy_map = le32_to_cpu(hw_mode_cap->phy_id_map);
3773 svc_rdy_ext->tot_phy_id += fls(phy_map);
3774
3775 return 0;
3776 }
3777
ath12k_wmi_hw_mode_caps(struct ath12k_base * soc,u16 len,const void * ptr,void * data)3778 static int ath12k_wmi_hw_mode_caps(struct ath12k_base *soc,
3779 u16 len, const void *ptr, void *data)
3780 {
3781 struct ath12k_wmi_svc_rdy_ext_parse *svc_rdy_ext = data;
3782 const struct ath12k_wmi_hw_mode_cap_params *hw_mode_caps;
3783 enum wmi_host_hw_mode_config_type mode, pref;
3784 u32 i;
3785 int ret;
3786
3787 svc_rdy_ext->n_hw_mode_caps = 0;
3788 svc_rdy_ext->hw_mode_caps = ptr;
3789
3790 ret = ath12k_wmi_tlv_iter(soc, ptr, len,
3791 ath12k_wmi_hw_mode_caps_parse,
3792 svc_rdy_ext);
3793 if (ret) {
3794 ath12k_warn(soc, "failed to parse tlv %d\n", ret);
3795 return ret;
3796 }
3797
3798 for (i = 0 ; i < svc_rdy_ext->n_hw_mode_caps; i++) {
3799 hw_mode_caps = &svc_rdy_ext->hw_mode_caps[i];
3800 mode = le32_to_cpu(hw_mode_caps->hw_mode_id);
3801
3802 if (mode >= WMI_HOST_HW_MODE_MAX)
3803 continue;
3804
3805 pref = soc->wmi_ab.preferred_hw_mode;
3806
3807 if (ath12k_hw_mode_pri_map[mode] < ath12k_hw_mode_pri_map[pref]) {
3808 svc_rdy_ext->pref_hw_mode_caps = *hw_mode_caps;
3809 soc->wmi_ab.preferred_hw_mode = mode;
3810 }
3811 }
3812
3813 ath12k_dbg(soc, ATH12K_DBG_WMI, "preferred_hw_mode:%d\n",
3814 soc->wmi_ab.preferred_hw_mode);
3815 if (soc->wmi_ab.preferred_hw_mode == WMI_HOST_HW_MODE_MAX)
3816 return -EINVAL;
3817
3818 return 0;
3819 }
3820
ath12k_wmi_mac_phy_caps_parse(struct ath12k_base * soc,u16 tag,u16 len,const void * ptr,void * data)3821 static int ath12k_wmi_mac_phy_caps_parse(struct ath12k_base *soc,
3822 u16 tag, u16 len,
3823 const void *ptr, void *data)
3824 {
3825 struct ath12k_wmi_svc_rdy_ext_parse *svc_rdy_ext = data;
3826
3827 if (tag != WMI_TAG_MAC_PHY_CAPABILITIES)
3828 return -EPROTO;
3829
3830 if (svc_rdy_ext->n_mac_phy_caps >= svc_rdy_ext->tot_phy_id)
3831 return -ENOBUFS;
3832
3833 len = min_t(u16, len, sizeof(struct ath12k_wmi_mac_phy_caps_params));
3834 if (!svc_rdy_ext->n_mac_phy_caps) {
3835 svc_rdy_ext->mac_phy_caps = kzalloc((svc_rdy_ext->tot_phy_id) * len,
3836 GFP_ATOMIC);
3837 if (!svc_rdy_ext->mac_phy_caps)
3838 return -ENOMEM;
3839 }
3840
3841 memcpy(svc_rdy_ext->mac_phy_caps + svc_rdy_ext->n_mac_phy_caps, ptr, len);
3842 svc_rdy_ext->n_mac_phy_caps++;
3843 return 0;
3844 }
3845
ath12k_wmi_ext_hal_reg_caps_parse(struct ath12k_base * soc,u16 tag,u16 len,const void * ptr,void * data)3846 static int ath12k_wmi_ext_hal_reg_caps_parse(struct ath12k_base *soc,
3847 u16 tag, u16 len,
3848 const void *ptr, void *data)
3849 {
3850 struct ath12k_wmi_svc_rdy_ext_parse *svc_rdy_ext = data;
3851
3852 if (tag != WMI_TAG_HAL_REG_CAPABILITIES_EXT)
3853 return -EPROTO;
3854
3855 if (svc_rdy_ext->n_ext_hal_reg_caps >= svc_rdy_ext->arg.num_phy)
3856 return -ENOBUFS;
3857
3858 svc_rdy_ext->n_ext_hal_reg_caps++;
3859 return 0;
3860 }
3861
ath12k_wmi_ext_hal_reg_caps(struct ath12k_base * soc,u16 len,const void * ptr,void * data)3862 static int ath12k_wmi_ext_hal_reg_caps(struct ath12k_base *soc,
3863 u16 len, const void *ptr, void *data)
3864 {
3865 struct ath12k_wmi_pdev *wmi_handle = &soc->wmi_ab.wmi[0];
3866 struct ath12k_wmi_svc_rdy_ext_parse *svc_rdy_ext = data;
3867 struct ath12k_wmi_hal_reg_capabilities_ext_arg reg_cap;
3868 int ret;
3869 u32 i;
3870
3871 svc_rdy_ext->n_ext_hal_reg_caps = 0;
3872 svc_rdy_ext->ext_hal_reg_caps = ptr;
3873 ret = ath12k_wmi_tlv_iter(soc, ptr, len,
3874 ath12k_wmi_ext_hal_reg_caps_parse,
3875 svc_rdy_ext);
3876 if (ret) {
3877 ath12k_warn(soc, "failed to parse tlv %d\n", ret);
3878 return ret;
3879 }
3880
3881 for (i = 0; i < svc_rdy_ext->arg.num_phy; i++) {
3882 ret = ath12k_pull_reg_cap_svc_rdy_ext(wmi_handle,
3883 svc_rdy_ext->soc_hal_reg_caps,
3884 svc_rdy_ext->ext_hal_reg_caps, i,
3885 ®_cap);
3886 if (ret) {
3887 ath12k_warn(soc, "failed to extract reg cap %d\n", i);
3888 return ret;
3889 }
3890
3891 if (reg_cap.phy_id >= MAX_RADIOS) {
3892 ath12k_warn(soc, "unexpected phy id %u\n", reg_cap.phy_id);
3893 return -EINVAL;
3894 }
3895
3896 soc->hal_reg_cap[reg_cap.phy_id] = reg_cap;
3897 }
3898 return 0;
3899 }
3900
ath12k_wmi_ext_soc_hal_reg_caps_parse(struct ath12k_base * soc,u16 len,const void * ptr,void * data)3901 static int ath12k_wmi_ext_soc_hal_reg_caps_parse(struct ath12k_base *soc,
3902 u16 len, const void *ptr,
3903 void *data)
3904 {
3905 struct ath12k_wmi_pdev *wmi_handle = &soc->wmi_ab.wmi[0];
3906 struct ath12k_wmi_svc_rdy_ext_parse *svc_rdy_ext = data;
3907 u8 hw_mode_id = le32_to_cpu(svc_rdy_ext->pref_hw_mode_caps.hw_mode_id);
3908 u32 phy_id_map;
3909 int pdev_index = 0;
3910 int ret;
3911
3912 svc_rdy_ext->soc_hal_reg_caps = ptr;
3913 svc_rdy_ext->arg.num_phy = le32_to_cpu(svc_rdy_ext->soc_hal_reg_caps->num_phy);
3914
3915 soc->num_radios = 0;
3916 phy_id_map = le32_to_cpu(svc_rdy_ext->pref_hw_mode_caps.phy_id_map);
3917 soc->fw_pdev_count = 0;
3918
3919 while (phy_id_map && soc->num_radios < MAX_RADIOS) {
3920 ret = ath12k_pull_mac_phy_cap_svc_ready_ext(wmi_handle,
3921 svc_rdy_ext,
3922 hw_mode_id, soc->num_radios,
3923 &soc->pdevs[pdev_index]);
3924 if (ret) {
3925 ath12k_warn(soc, "failed to extract mac caps, idx :%d\n",
3926 soc->num_radios);
3927 return ret;
3928 }
3929
3930 soc->num_radios++;
3931
3932 /* For single_pdev_only targets,
3933 * save mac_phy capability in the same pdev
3934 */
3935 if (soc->hw_params->single_pdev_only)
3936 pdev_index = 0;
3937 else
3938 pdev_index = soc->num_radios;
3939
3940 /* TODO: mac_phy_cap prints */
3941 phy_id_map >>= 1;
3942 }
3943
3944 if (soc->hw_params->single_pdev_only) {
3945 soc->num_radios = 1;
3946 soc->pdevs[0].pdev_id = 0;
3947 }
3948
3949 return 0;
3950 }
3951
ath12k_wmi_dma_ring_caps_parse(struct ath12k_base * soc,u16 tag,u16 len,const void * ptr,void * data)3952 static int ath12k_wmi_dma_ring_caps_parse(struct ath12k_base *soc,
3953 u16 tag, u16 len,
3954 const void *ptr, void *data)
3955 {
3956 struct ath12k_wmi_dma_ring_caps_parse *parse = data;
3957
3958 if (tag != WMI_TAG_DMA_RING_CAPABILITIES)
3959 return -EPROTO;
3960
3961 parse->n_dma_ring_caps++;
3962 return 0;
3963 }
3964
ath12k_wmi_alloc_dbring_caps(struct ath12k_base * ab,u32 num_cap)3965 static int ath12k_wmi_alloc_dbring_caps(struct ath12k_base *ab,
3966 u32 num_cap)
3967 {
3968 size_t sz;
3969 void *ptr;
3970
3971 sz = num_cap * sizeof(struct ath12k_dbring_cap);
3972 ptr = kzalloc(sz, GFP_ATOMIC);
3973 if (!ptr)
3974 return -ENOMEM;
3975
3976 ab->db_caps = ptr;
3977 ab->num_db_cap = num_cap;
3978
3979 return 0;
3980 }
3981
ath12k_wmi_free_dbring_caps(struct ath12k_base * ab)3982 static void ath12k_wmi_free_dbring_caps(struct ath12k_base *ab)
3983 {
3984 kfree(ab->db_caps);
3985 ab->db_caps = NULL;
3986 }
3987
ath12k_wmi_dma_ring_caps(struct ath12k_base * ab,u16 len,const void * ptr,void * data)3988 static int ath12k_wmi_dma_ring_caps(struct ath12k_base *ab,
3989 u16 len, const void *ptr, void *data)
3990 {
3991 struct ath12k_wmi_dma_ring_caps_parse *dma_caps_parse = data;
3992 struct ath12k_wmi_dma_ring_caps_params *dma_caps;
3993 struct ath12k_dbring_cap *dir_buff_caps;
3994 int ret;
3995 u32 i;
3996
3997 dma_caps_parse->n_dma_ring_caps = 0;
3998 dma_caps = (struct ath12k_wmi_dma_ring_caps_params *)ptr;
3999 ret = ath12k_wmi_tlv_iter(ab, ptr, len,
4000 ath12k_wmi_dma_ring_caps_parse,
4001 dma_caps_parse);
4002 if (ret) {
4003 ath12k_warn(ab, "failed to parse dma ring caps tlv %d\n", ret);
4004 return ret;
4005 }
4006
4007 if (!dma_caps_parse->n_dma_ring_caps)
4008 return 0;
4009
4010 if (ab->num_db_cap) {
4011 ath12k_warn(ab, "Already processed, so ignoring dma ring caps\n");
4012 return 0;
4013 }
4014
4015 ret = ath12k_wmi_alloc_dbring_caps(ab, dma_caps_parse->n_dma_ring_caps);
4016 if (ret)
4017 return ret;
4018
4019 dir_buff_caps = ab->db_caps;
4020 for (i = 0; i < dma_caps_parse->n_dma_ring_caps; i++) {
4021 if (le32_to_cpu(dma_caps[i].module_id) >= WMI_DIRECT_BUF_MAX) {
4022 ath12k_warn(ab, "Invalid module id %d\n",
4023 le32_to_cpu(dma_caps[i].module_id));
4024 ret = -EINVAL;
4025 goto free_dir_buff;
4026 }
4027
4028 dir_buff_caps[i].id = le32_to_cpu(dma_caps[i].module_id);
4029 dir_buff_caps[i].pdev_id =
4030 DP_HW2SW_MACID(le32_to_cpu(dma_caps[i].pdev_id));
4031 dir_buff_caps[i].min_elem = le32_to_cpu(dma_caps[i].min_elem);
4032 dir_buff_caps[i].min_buf_sz = le32_to_cpu(dma_caps[i].min_buf_sz);
4033 dir_buff_caps[i].min_buf_align = le32_to_cpu(dma_caps[i].min_buf_align);
4034 }
4035
4036 return 0;
4037
4038 free_dir_buff:
4039 ath12k_wmi_free_dbring_caps(ab);
4040 return ret;
4041 }
4042
ath12k_wmi_svc_rdy_ext_parse(struct ath12k_base * ab,u16 tag,u16 len,const void * ptr,void * data)4043 static int ath12k_wmi_svc_rdy_ext_parse(struct ath12k_base *ab,
4044 u16 tag, u16 len,
4045 const void *ptr, void *data)
4046 {
4047 struct ath12k_wmi_pdev *wmi_handle = &ab->wmi_ab.wmi[0];
4048 struct ath12k_wmi_svc_rdy_ext_parse *svc_rdy_ext = data;
4049 int ret;
4050
4051 switch (tag) {
4052 case WMI_TAG_SERVICE_READY_EXT_EVENT:
4053 ret = ath12k_pull_svc_ready_ext(wmi_handle, ptr,
4054 &svc_rdy_ext->arg);
4055 if (ret) {
4056 ath12k_warn(ab, "unable to extract ext params\n");
4057 return ret;
4058 }
4059 break;
4060
4061 case WMI_TAG_SOC_MAC_PHY_HW_MODE_CAPS:
4062 svc_rdy_ext->hw_caps = ptr;
4063 svc_rdy_ext->arg.num_hw_modes =
4064 le32_to_cpu(svc_rdy_ext->hw_caps->num_hw_modes);
4065 break;
4066
4067 case WMI_TAG_SOC_HAL_REG_CAPABILITIES:
4068 ret = ath12k_wmi_ext_soc_hal_reg_caps_parse(ab, len, ptr,
4069 svc_rdy_ext);
4070 if (ret)
4071 return ret;
4072 break;
4073
4074 case WMI_TAG_ARRAY_STRUCT:
4075 if (!svc_rdy_ext->hw_mode_done) {
4076 ret = ath12k_wmi_hw_mode_caps(ab, len, ptr, svc_rdy_ext);
4077 if (ret)
4078 return ret;
4079
4080 svc_rdy_ext->hw_mode_done = true;
4081 } else if (!svc_rdy_ext->mac_phy_done) {
4082 svc_rdy_ext->n_mac_phy_caps = 0;
4083 ret = ath12k_wmi_tlv_iter(ab, ptr, len,
4084 ath12k_wmi_mac_phy_caps_parse,
4085 svc_rdy_ext);
4086 if (ret) {
4087 ath12k_warn(ab, "failed to parse tlv %d\n", ret);
4088 return ret;
4089 }
4090
4091 svc_rdy_ext->mac_phy_done = true;
4092 } else if (!svc_rdy_ext->ext_hal_reg_done) {
4093 ret = ath12k_wmi_ext_hal_reg_caps(ab, len, ptr, svc_rdy_ext);
4094 if (ret)
4095 return ret;
4096
4097 svc_rdy_ext->ext_hal_reg_done = true;
4098 } else if (!svc_rdy_ext->mac_phy_chainmask_combo_done) {
4099 svc_rdy_ext->mac_phy_chainmask_combo_done = true;
4100 } else if (!svc_rdy_ext->mac_phy_chainmask_cap_done) {
4101 svc_rdy_ext->mac_phy_chainmask_cap_done = true;
4102 } else if (!svc_rdy_ext->oem_dma_ring_cap_done) {
4103 svc_rdy_ext->oem_dma_ring_cap_done = true;
4104 } else if (!svc_rdy_ext->dma_ring_cap_done) {
4105 ret = ath12k_wmi_dma_ring_caps(ab, len, ptr,
4106 &svc_rdy_ext->dma_caps_parse);
4107 if (ret)
4108 return ret;
4109
4110 svc_rdy_ext->dma_ring_cap_done = true;
4111 }
4112 break;
4113
4114 default:
4115 break;
4116 }
4117 return 0;
4118 }
4119
ath12k_service_ready_ext_event(struct ath12k_base * ab,struct sk_buff * skb)4120 static int ath12k_service_ready_ext_event(struct ath12k_base *ab,
4121 struct sk_buff *skb)
4122 {
4123 struct ath12k_wmi_svc_rdy_ext_parse svc_rdy_ext = { };
4124 int ret;
4125
4126 ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len,
4127 ath12k_wmi_svc_rdy_ext_parse,
4128 &svc_rdy_ext);
4129 if (ret) {
4130 ath12k_warn(ab, "failed to parse tlv %d\n", ret);
4131 goto err;
4132 }
4133
4134 if (!test_bit(WMI_TLV_SERVICE_EXT2_MSG, ab->wmi_ab.svc_map))
4135 complete(&ab->wmi_ab.service_ready);
4136
4137 kfree(svc_rdy_ext.mac_phy_caps);
4138 return 0;
4139
4140 err:
4141 kfree(svc_rdy_ext.mac_phy_caps);
4142 ath12k_wmi_free_dbring_caps(ab);
4143 return ret;
4144 }
4145
ath12k_pull_svc_ready_ext2(struct ath12k_wmi_pdev * wmi_handle,const void * ptr,struct ath12k_wmi_svc_rdy_ext2_arg * arg)4146 static int ath12k_pull_svc_ready_ext2(struct ath12k_wmi_pdev *wmi_handle,
4147 const void *ptr,
4148 struct ath12k_wmi_svc_rdy_ext2_arg *arg)
4149 {
4150 const struct wmi_service_ready_ext2_event *ev = ptr;
4151
4152 if (!ev)
4153 return -EINVAL;
4154
4155 arg->reg_db_version = le32_to_cpu(ev->reg_db_version);
4156 arg->hw_min_max_tx_power_2ghz = le32_to_cpu(ev->hw_min_max_tx_power_2ghz);
4157 arg->hw_min_max_tx_power_5ghz = le32_to_cpu(ev->hw_min_max_tx_power_5ghz);
4158 arg->chwidth_num_peer_caps = le32_to_cpu(ev->chwidth_num_peer_caps);
4159 arg->preamble_puncture_bw = le32_to_cpu(ev->preamble_puncture_bw);
4160 arg->max_user_per_ppdu_ofdma = le32_to_cpu(ev->max_user_per_ppdu_ofdma);
4161 arg->max_user_per_ppdu_mumimo = le32_to_cpu(ev->max_user_per_ppdu_mumimo);
4162 arg->target_cap_flags = le32_to_cpu(ev->target_cap_flags);
4163 return 0;
4164 }
4165
ath12k_wmi_eht_caps_parse(struct ath12k_pdev * pdev,u32 band,const __le32 cap_mac_info[],const __le32 cap_phy_info[],const __le32 supp_mcs[],const struct ath12k_wmi_ppe_threshold_params * ppet,__le32 cap_info_internal)4166 static void ath12k_wmi_eht_caps_parse(struct ath12k_pdev *pdev, u32 band,
4167 const __le32 cap_mac_info[],
4168 const __le32 cap_phy_info[],
4169 const __le32 supp_mcs[],
4170 const struct ath12k_wmi_ppe_threshold_params *ppet,
4171 __le32 cap_info_internal)
4172 {
4173 struct ath12k_band_cap *cap_band = &pdev->cap.band[band];
4174 u8 i;
4175
4176 for (i = 0; i < WMI_MAX_EHTCAP_MAC_SIZE; i++)
4177 cap_band->eht_cap_mac_info[i] = le32_to_cpu(cap_mac_info[i]);
4178
4179 for (i = 0; i < WMI_MAX_EHTCAP_PHY_SIZE; i++)
4180 cap_band->eht_cap_phy_info[i] = le32_to_cpu(cap_phy_info[i]);
4181
4182 cap_band->eht_mcs_20_only = le32_to_cpu(supp_mcs[0]);
4183 cap_band->eht_mcs_80 = le32_to_cpu(supp_mcs[1]);
4184 if (band != NL80211_BAND_2GHZ) {
4185 cap_band->eht_mcs_160 = le32_to_cpu(supp_mcs[2]);
4186 cap_band->eht_mcs_320 = le32_to_cpu(supp_mcs[3]);
4187 }
4188
4189 cap_band->eht_ppet.numss_m1 = le32_to_cpu(ppet->numss_m1);
4190 cap_band->eht_ppet.ru_bit_mask = le32_to_cpu(ppet->ru_info);
4191 for (i = 0; i < WMI_MAX_NUM_SS; i++)
4192 cap_band->eht_ppet.ppet16_ppet8_ru3_ru0[i] =
4193 le32_to_cpu(ppet->ppet16_ppet8_ru3_ru0[i]);
4194
4195 cap_band->eht_cap_info_internal = le32_to_cpu(cap_info_internal);
4196 }
4197
4198 static int
ath12k_wmi_tlv_mac_phy_caps_ext_parse(struct ath12k_base * ab,const struct ath12k_wmi_caps_ext_params * caps,struct ath12k_pdev * pdev)4199 ath12k_wmi_tlv_mac_phy_caps_ext_parse(struct ath12k_base *ab,
4200 const struct ath12k_wmi_caps_ext_params *caps,
4201 struct ath12k_pdev *pdev)
4202 {
4203 u32 bands;
4204 int i;
4205
4206 if (ab->hw_params->single_pdev_only) {
4207 for (i = 0; i < ab->fw_pdev_count; i++) {
4208 struct ath12k_fw_pdev *fw_pdev = &ab->fw_pdev[i];
4209
4210 if (fw_pdev->pdev_id == le32_to_cpu(caps->pdev_id) &&
4211 fw_pdev->phy_id == le32_to_cpu(caps->phy_id)) {
4212 bands = fw_pdev->supported_bands;
4213 break;
4214 }
4215 }
4216
4217 if (i == ab->fw_pdev_count)
4218 return -EINVAL;
4219 } else {
4220 bands = pdev->cap.supported_bands;
4221 }
4222
4223 if (bands & WMI_HOST_WLAN_2G_CAP) {
4224 ath12k_wmi_eht_caps_parse(pdev, NL80211_BAND_2GHZ,
4225 caps->eht_cap_mac_info_2ghz,
4226 caps->eht_cap_phy_info_2ghz,
4227 caps->eht_supp_mcs_ext_2ghz,
4228 &caps->eht_ppet_2ghz,
4229 caps->eht_cap_info_internal);
4230 }
4231
4232 if (bands & WMI_HOST_WLAN_5G_CAP) {
4233 ath12k_wmi_eht_caps_parse(pdev, NL80211_BAND_5GHZ,
4234 caps->eht_cap_mac_info_5ghz,
4235 caps->eht_cap_phy_info_5ghz,
4236 caps->eht_supp_mcs_ext_5ghz,
4237 &caps->eht_ppet_5ghz,
4238 caps->eht_cap_info_internal);
4239
4240 ath12k_wmi_eht_caps_parse(pdev, NL80211_BAND_6GHZ,
4241 caps->eht_cap_mac_info_5ghz,
4242 caps->eht_cap_phy_info_5ghz,
4243 caps->eht_supp_mcs_ext_5ghz,
4244 &caps->eht_ppet_5ghz,
4245 caps->eht_cap_info_internal);
4246 }
4247
4248 return 0;
4249 }
4250
ath12k_wmi_tlv_mac_phy_caps_ext(struct ath12k_base * ab,u16 tag,u16 len,const void * ptr,void * data)4251 static int ath12k_wmi_tlv_mac_phy_caps_ext(struct ath12k_base *ab, u16 tag,
4252 u16 len, const void *ptr,
4253 void *data)
4254 {
4255 const struct ath12k_wmi_caps_ext_params *caps = ptr;
4256 int i = 0, ret;
4257
4258 if (tag != WMI_TAG_MAC_PHY_CAPABILITIES_EXT)
4259 return -EPROTO;
4260
4261 if (ab->hw_params->single_pdev_only) {
4262 if (ab->wmi_ab.preferred_hw_mode != le32_to_cpu(caps->hw_mode_id))
4263 return 0;
4264 } else {
4265 for (i = 0; i < ab->num_radios; i++) {
4266 if (ab->pdevs[i].pdev_id == le32_to_cpu(caps->pdev_id))
4267 break;
4268 }
4269
4270 if (i == ab->num_radios)
4271 return -EINVAL;
4272 }
4273
4274 ret = ath12k_wmi_tlv_mac_phy_caps_ext_parse(ab, caps, &ab->pdevs[i]);
4275 if (ret) {
4276 ath12k_warn(ab,
4277 "failed to parse extended MAC PHY capabilities for pdev %d: %d\n",
4278 ret, ab->pdevs[i].pdev_id);
4279 return ret;
4280 }
4281
4282 return 0;
4283 }
4284
ath12k_wmi_svc_rdy_ext2_parse(struct ath12k_base * ab,u16 tag,u16 len,const void * ptr,void * data)4285 static int ath12k_wmi_svc_rdy_ext2_parse(struct ath12k_base *ab,
4286 u16 tag, u16 len,
4287 const void *ptr, void *data)
4288 {
4289 struct ath12k_wmi_pdev *wmi_handle = &ab->wmi_ab.wmi[0];
4290 struct ath12k_wmi_svc_rdy_ext2_parse *parse = data;
4291 int ret;
4292
4293 switch (tag) {
4294 case WMI_TAG_SERVICE_READY_EXT2_EVENT:
4295 ret = ath12k_pull_svc_ready_ext2(wmi_handle, ptr,
4296 &parse->arg);
4297 if (ret) {
4298 ath12k_warn(ab,
4299 "failed to extract wmi service ready ext2 parameters: %d\n",
4300 ret);
4301 return ret;
4302 }
4303 break;
4304
4305 case WMI_TAG_ARRAY_STRUCT:
4306 if (!parse->dma_ring_cap_done) {
4307 ret = ath12k_wmi_dma_ring_caps(ab, len, ptr,
4308 &parse->dma_caps_parse);
4309 if (ret)
4310 return ret;
4311
4312 parse->dma_ring_cap_done = true;
4313 } else if (!parse->spectral_bin_scaling_done) {
4314 /* TODO: This is a place-holder as WMI tag for
4315 * spectral scaling is before
4316 * WMI_TAG_MAC_PHY_CAPABILITIES_EXT
4317 */
4318 parse->spectral_bin_scaling_done = true;
4319 } else if (!parse->mac_phy_caps_ext_done) {
4320 ret = ath12k_wmi_tlv_iter(ab, ptr, len,
4321 ath12k_wmi_tlv_mac_phy_caps_ext,
4322 parse);
4323 if (ret) {
4324 ath12k_warn(ab, "failed to parse extended MAC PHY capabilities WMI TLV: %d\n",
4325 ret);
4326 return ret;
4327 }
4328
4329 parse->mac_phy_caps_ext_done = true;
4330 }
4331 break;
4332 default:
4333 break;
4334 }
4335
4336 return 0;
4337 }
4338
ath12k_service_ready_ext2_event(struct ath12k_base * ab,struct sk_buff * skb)4339 static int ath12k_service_ready_ext2_event(struct ath12k_base *ab,
4340 struct sk_buff *skb)
4341 {
4342 struct ath12k_wmi_svc_rdy_ext2_parse svc_rdy_ext2 = { };
4343 int ret;
4344
4345 ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len,
4346 ath12k_wmi_svc_rdy_ext2_parse,
4347 &svc_rdy_ext2);
4348 if (ret) {
4349 ath12k_warn(ab, "failed to parse ext2 event tlv %d\n", ret);
4350 goto err;
4351 }
4352
4353 complete(&ab->wmi_ab.service_ready);
4354
4355 return 0;
4356
4357 err:
4358 ath12k_wmi_free_dbring_caps(ab);
4359 return ret;
4360 }
4361
ath12k_pull_vdev_start_resp_tlv(struct ath12k_base * ab,struct sk_buff * skb,struct wmi_vdev_start_resp_event * vdev_rsp)4362 static int ath12k_pull_vdev_start_resp_tlv(struct ath12k_base *ab, struct sk_buff *skb,
4363 struct wmi_vdev_start_resp_event *vdev_rsp)
4364 {
4365 const void **tb;
4366 const struct wmi_vdev_start_resp_event *ev;
4367 int ret;
4368
4369 tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC);
4370 if (IS_ERR(tb)) {
4371 ret = PTR_ERR(tb);
4372 ath12k_warn(ab, "failed to parse tlv: %d\n", ret);
4373 return ret;
4374 }
4375
4376 ev = tb[WMI_TAG_VDEV_START_RESPONSE_EVENT];
4377 if (!ev) {
4378 ath12k_warn(ab, "failed to fetch vdev start resp ev");
4379 kfree(tb);
4380 return -EPROTO;
4381 }
4382
4383 *vdev_rsp = *ev;
4384
4385 kfree(tb);
4386 return 0;
4387 }
4388
4389 static struct ath12k_reg_rule
create_ext_reg_rules_from_wmi(u32 num_reg_rules,struct ath12k_wmi_reg_rule_ext_params * wmi_reg_rule)4390 *create_ext_reg_rules_from_wmi(u32 num_reg_rules,
4391 struct ath12k_wmi_reg_rule_ext_params *wmi_reg_rule)
4392 {
4393 struct ath12k_reg_rule *reg_rule_ptr;
4394 u32 count;
4395
4396 reg_rule_ptr = kzalloc((num_reg_rules * sizeof(*reg_rule_ptr)),
4397 GFP_ATOMIC);
4398
4399 if (!reg_rule_ptr)
4400 return NULL;
4401
4402 for (count = 0; count < num_reg_rules; count++) {
4403 reg_rule_ptr[count].start_freq =
4404 le32_get_bits(wmi_reg_rule[count].freq_info,
4405 REG_RULE_START_FREQ);
4406 reg_rule_ptr[count].end_freq =
4407 le32_get_bits(wmi_reg_rule[count].freq_info,
4408 REG_RULE_END_FREQ);
4409 reg_rule_ptr[count].max_bw =
4410 le32_get_bits(wmi_reg_rule[count].bw_pwr_info,
4411 REG_RULE_MAX_BW);
4412 reg_rule_ptr[count].reg_power =
4413 le32_get_bits(wmi_reg_rule[count].bw_pwr_info,
4414 REG_RULE_REG_PWR);
4415 reg_rule_ptr[count].ant_gain =
4416 le32_get_bits(wmi_reg_rule[count].bw_pwr_info,
4417 REG_RULE_ANT_GAIN);
4418 reg_rule_ptr[count].flags =
4419 le32_get_bits(wmi_reg_rule[count].flag_info,
4420 REG_RULE_FLAGS);
4421 reg_rule_ptr[count].psd_flag =
4422 le32_get_bits(wmi_reg_rule[count].psd_power_info,
4423 REG_RULE_PSD_INFO);
4424 reg_rule_ptr[count].psd_eirp =
4425 le32_get_bits(wmi_reg_rule[count].psd_power_info,
4426 REG_RULE_PSD_EIRP);
4427 }
4428
4429 return reg_rule_ptr;
4430 }
4431
ath12k_wmi_ignore_num_extra_rules(struct ath12k_wmi_reg_rule_ext_params * rule,u32 num_reg_rules)4432 static u8 ath12k_wmi_ignore_num_extra_rules(struct ath12k_wmi_reg_rule_ext_params *rule,
4433 u32 num_reg_rules)
4434 {
4435 u8 num_invalid_5ghz_rules = 0;
4436 u32 count, start_freq;
4437
4438 for (count = 0; count < num_reg_rules; count++) {
4439 start_freq = le32_get_bits(rule[count].freq_info, REG_RULE_START_FREQ);
4440
4441 if (start_freq >= ATH12K_MIN_6G_FREQ)
4442 num_invalid_5ghz_rules++;
4443 }
4444
4445 return num_invalid_5ghz_rules;
4446 }
4447
ath12k_pull_reg_chan_list_ext_update_ev(struct ath12k_base * ab,struct sk_buff * skb,struct ath12k_reg_info * reg_info)4448 static int ath12k_pull_reg_chan_list_ext_update_ev(struct ath12k_base *ab,
4449 struct sk_buff *skb,
4450 struct ath12k_reg_info *reg_info)
4451 {
4452 const void **tb;
4453 const struct wmi_reg_chan_list_cc_ext_event *ev;
4454 struct ath12k_wmi_reg_rule_ext_params *ext_wmi_reg_rule;
4455 u32 num_2g_reg_rules, num_5g_reg_rules;
4456 u32 num_6g_reg_rules_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
4457 u32 num_6g_reg_rules_cl[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
4458 u8 num_invalid_5ghz_ext_rules;
4459 u32 total_reg_rules = 0;
4460 int ret, i, j;
4461
4462 ath12k_dbg(ab, ATH12K_DBG_WMI, "processing regulatory ext channel list\n");
4463
4464 tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC);
4465 if (IS_ERR(tb)) {
4466 ret = PTR_ERR(tb);
4467 ath12k_warn(ab, "failed to parse tlv: %d\n", ret);
4468 return ret;
4469 }
4470
4471 ev = tb[WMI_TAG_REG_CHAN_LIST_CC_EXT_EVENT];
4472 if (!ev) {
4473 ath12k_warn(ab, "failed to fetch reg chan list ext update ev\n");
4474 kfree(tb);
4475 return -EPROTO;
4476 }
4477
4478 reg_info->num_2g_reg_rules = le32_to_cpu(ev->num_2g_reg_rules);
4479 reg_info->num_5g_reg_rules = le32_to_cpu(ev->num_5g_reg_rules);
4480 reg_info->num_6g_reg_rules_ap[WMI_REG_INDOOR_AP] =
4481 le32_to_cpu(ev->num_6g_reg_rules_ap_lpi);
4482 reg_info->num_6g_reg_rules_ap[WMI_REG_STD_POWER_AP] =
4483 le32_to_cpu(ev->num_6g_reg_rules_ap_sp);
4484 reg_info->num_6g_reg_rules_ap[WMI_REG_VLP_AP] =
4485 le32_to_cpu(ev->num_6g_reg_rules_ap_vlp);
4486
4487 for (i = 0; i < WMI_REG_MAX_CLIENT_TYPE; i++) {
4488 reg_info->num_6g_reg_rules_cl[WMI_REG_INDOOR_AP][i] =
4489 le32_to_cpu(ev->num_6g_reg_rules_cl_lpi[i]);
4490 reg_info->num_6g_reg_rules_cl[WMI_REG_STD_POWER_AP][i] =
4491 le32_to_cpu(ev->num_6g_reg_rules_cl_sp[i]);
4492 reg_info->num_6g_reg_rules_cl[WMI_REG_VLP_AP][i] =
4493 le32_to_cpu(ev->num_6g_reg_rules_cl_vlp[i]);
4494 }
4495
4496 num_2g_reg_rules = reg_info->num_2g_reg_rules;
4497 total_reg_rules += num_2g_reg_rules;
4498 num_5g_reg_rules = reg_info->num_5g_reg_rules;
4499 total_reg_rules += num_5g_reg_rules;
4500
4501 if (num_2g_reg_rules > MAX_REG_RULES || num_5g_reg_rules > MAX_REG_RULES) {
4502 ath12k_warn(ab, "Num reg rules for 2G/5G exceeds max limit (num_2g_reg_rules: %d num_5g_reg_rules: %d max_rules: %d)\n",
4503 num_2g_reg_rules, num_5g_reg_rules, MAX_REG_RULES);
4504 kfree(tb);
4505 return -EINVAL;
4506 }
4507
4508 for (i = 0; i < WMI_REG_CURRENT_MAX_AP_TYPE; i++) {
4509 num_6g_reg_rules_ap[i] = reg_info->num_6g_reg_rules_ap[i];
4510
4511 if (num_6g_reg_rules_ap[i] > MAX_6G_REG_RULES) {
4512 ath12k_warn(ab, "Num 6G reg rules for AP mode(%d) exceeds max limit (num_6g_reg_rules_ap: %d, max_rules: %d)\n",
4513 i, num_6g_reg_rules_ap[i], MAX_6G_REG_RULES);
4514 kfree(tb);
4515 return -EINVAL;
4516 }
4517
4518 total_reg_rules += num_6g_reg_rules_ap[i];
4519 }
4520
4521 for (i = 0; i < WMI_REG_MAX_CLIENT_TYPE; i++) {
4522 num_6g_reg_rules_cl[WMI_REG_INDOOR_AP][i] =
4523 reg_info->num_6g_reg_rules_cl[WMI_REG_INDOOR_AP][i];
4524 total_reg_rules += num_6g_reg_rules_cl[WMI_REG_INDOOR_AP][i];
4525
4526 num_6g_reg_rules_cl[WMI_REG_STD_POWER_AP][i] =
4527 reg_info->num_6g_reg_rules_cl[WMI_REG_STD_POWER_AP][i];
4528 total_reg_rules += num_6g_reg_rules_cl[WMI_REG_STD_POWER_AP][i];
4529
4530 num_6g_reg_rules_cl[WMI_REG_VLP_AP][i] =
4531 reg_info->num_6g_reg_rules_cl[WMI_REG_VLP_AP][i];
4532 total_reg_rules += num_6g_reg_rules_cl[WMI_REG_VLP_AP][i];
4533
4534 if (num_6g_reg_rules_cl[WMI_REG_INDOOR_AP][i] > MAX_6G_REG_RULES ||
4535 num_6g_reg_rules_cl[WMI_REG_STD_POWER_AP][i] > MAX_6G_REG_RULES ||
4536 num_6g_reg_rules_cl[WMI_REG_VLP_AP][i] > MAX_6G_REG_RULES) {
4537 ath12k_warn(ab, "Num 6g client reg rules exceeds max limit, for client(type: %d)\n",
4538 i);
4539 kfree(tb);
4540 return -EINVAL;
4541 }
4542 }
4543
4544 if (!total_reg_rules) {
4545 ath12k_warn(ab, "No reg rules available\n");
4546 kfree(tb);
4547 return -EINVAL;
4548 }
4549
4550 memcpy(reg_info->alpha2, &ev->alpha2, REG_ALPHA2_LEN);
4551
4552 reg_info->dfs_region = le32_to_cpu(ev->dfs_region);
4553 reg_info->phybitmap = le32_to_cpu(ev->phybitmap);
4554 reg_info->num_phy = le32_to_cpu(ev->num_phy);
4555 reg_info->phy_id = le32_to_cpu(ev->phy_id);
4556 reg_info->ctry_code = le32_to_cpu(ev->country_id);
4557 reg_info->reg_dmn_pair = le32_to_cpu(ev->domain_code);
4558
4559 switch (le32_to_cpu(ev->status_code)) {
4560 case WMI_REG_SET_CC_STATUS_PASS:
4561 reg_info->status_code = REG_SET_CC_STATUS_PASS;
4562 break;
4563 case WMI_REG_CURRENT_ALPHA2_NOT_FOUND:
4564 reg_info->status_code = REG_CURRENT_ALPHA2_NOT_FOUND;
4565 break;
4566 case WMI_REG_INIT_ALPHA2_NOT_FOUND:
4567 reg_info->status_code = REG_INIT_ALPHA2_NOT_FOUND;
4568 break;
4569 case WMI_REG_SET_CC_CHANGE_NOT_ALLOWED:
4570 reg_info->status_code = REG_SET_CC_CHANGE_NOT_ALLOWED;
4571 break;
4572 case WMI_REG_SET_CC_STATUS_NO_MEMORY:
4573 reg_info->status_code = REG_SET_CC_STATUS_NO_MEMORY;
4574 break;
4575 case WMI_REG_SET_CC_STATUS_FAIL:
4576 reg_info->status_code = REG_SET_CC_STATUS_FAIL;
4577 break;
4578 }
4579
4580 reg_info->is_ext_reg_event = true;
4581
4582 reg_info->min_bw_2g = le32_to_cpu(ev->min_bw_2g);
4583 reg_info->max_bw_2g = le32_to_cpu(ev->max_bw_2g);
4584 reg_info->min_bw_5g = le32_to_cpu(ev->min_bw_5g);
4585 reg_info->max_bw_5g = le32_to_cpu(ev->max_bw_5g);
4586 reg_info->min_bw_6g_ap[WMI_REG_INDOOR_AP] = le32_to_cpu(ev->min_bw_6g_ap_lpi);
4587 reg_info->max_bw_6g_ap[WMI_REG_INDOOR_AP] = le32_to_cpu(ev->max_bw_6g_ap_lpi);
4588 reg_info->min_bw_6g_ap[WMI_REG_STD_POWER_AP] = le32_to_cpu(ev->min_bw_6g_ap_sp);
4589 reg_info->max_bw_6g_ap[WMI_REG_STD_POWER_AP] = le32_to_cpu(ev->max_bw_6g_ap_sp);
4590 reg_info->min_bw_6g_ap[WMI_REG_VLP_AP] = le32_to_cpu(ev->min_bw_6g_ap_vlp);
4591 reg_info->max_bw_6g_ap[WMI_REG_VLP_AP] = le32_to_cpu(ev->max_bw_6g_ap_vlp);
4592
4593 for (i = 0; i < WMI_REG_MAX_CLIENT_TYPE; i++) {
4594 reg_info->min_bw_6g_client[WMI_REG_INDOOR_AP][i] =
4595 le32_to_cpu(ev->min_bw_6g_client_lpi[i]);
4596 reg_info->max_bw_6g_client[WMI_REG_INDOOR_AP][i] =
4597 le32_to_cpu(ev->max_bw_6g_client_lpi[i]);
4598 reg_info->min_bw_6g_client[WMI_REG_STD_POWER_AP][i] =
4599 le32_to_cpu(ev->min_bw_6g_client_sp[i]);
4600 reg_info->max_bw_6g_client[WMI_REG_STD_POWER_AP][i] =
4601 le32_to_cpu(ev->max_bw_6g_client_sp[i]);
4602 reg_info->min_bw_6g_client[WMI_REG_VLP_AP][i] =
4603 le32_to_cpu(ev->min_bw_6g_client_vlp[i]);
4604 reg_info->max_bw_6g_client[WMI_REG_VLP_AP][i] =
4605 le32_to_cpu(ev->max_bw_6g_client_vlp[i]);
4606 }
4607
4608 ath12k_dbg(ab, ATH12K_DBG_WMI,
4609 "%s:cc_ext %s dsf %d BW: min_2g %d max_2g %d min_5g %d max_5g %d",
4610 __func__, reg_info->alpha2, reg_info->dfs_region,
4611 reg_info->min_bw_2g, reg_info->max_bw_2g,
4612 reg_info->min_bw_5g, reg_info->max_bw_5g);
4613
4614 ath12k_dbg(ab, ATH12K_DBG_WMI,
4615 "num_2g_reg_rules %d num_5g_reg_rules %d",
4616 num_2g_reg_rules, num_5g_reg_rules);
4617
4618 ath12k_dbg(ab, ATH12K_DBG_WMI,
4619 "num_6g_reg_rules_ap_lpi: %d num_6g_reg_rules_ap_sp: %d num_6g_reg_rules_ap_vlp: %d",
4620 num_6g_reg_rules_ap[WMI_REG_INDOOR_AP],
4621 num_6g_reg_rules_ap[WMI_REG_STD_POWER_AP],
4622 num_6g_reg_rules_ap[WMI_REG_VLP_AP]);
4623
4624 ath12k_dbg(ab, ATH12K_DBG_WMI,
4625 "6g Regular client: num_6g_reg_rules_lpi: %d num_6g_reg_rules_sp: %d num_6g_reg_rules_vlp: %d",
4626 num_6g_reg_rules_cl[WMI_REG_INDOOR_AP][WMI_REG_DEFAULT_CLIENT],
4627 num_6g_reg_rules_cl[WMI_REG_STD_POWER_AP][WMI_REG_DEFAULT_CLIENT],
4628 num_6g_reg_rules_cl[WMI_REG_VLP_AP][WMI_REG_DEFAULT_CLIENT]);
4629
4630 ath12k_dbg(ab, ATH12K_DBG_WMI,
4631 "6g Subordinate client: num_6g_reg_rules_lpi: %d num_6g_reg_rules_sp: %d num_6g_reg_rules_vlp: %d",
4632 num_6g_reg_rules_cl[WMI_REG_INDOOR_AP][WMI_REG_SUBORDINATE_CLIENT],
4633 num_6g_reg_rules_cl[WMI_REG_STD_POWER_AP][WMI_REG_SUBORDINATE_CLIENT],
4634 num_6g_reg_rules_cl[WMI_REG_VLP_AP][WMI_REG_SUBORDINATE_CLIENT]);
4635
4636 ext_wmi_reg_rule =
4637 (struct ath12k_wmi_reg_rule_ext_params *)((u8 *)ev
4638 + sizeof(*ev)
4639 + sizeof(struct wmi_tlv));
4640
4641 if (num_2g_reg_rules) {
4642 reg_info->reg_rules_2g_ptr =
4643 create_ext_reg_rules_from_wmi(num_2g_reg_rules,
4644 ext_wmi_reg_rule);
4645
4646 if (!reg_info->reg_rules_2g_ptr) {
4647 kfree(tb);
4648 ath12k_warn(ab, "Unable to Allocate memory for 2g rules\n");
4649 return -ENOMEM;
4650 }
4651 }
4652
4653 ext_wmi_reg_rule += num_2g_reg_rules;
4654
4655 /* Firmware might include 6 GHz reg rule in 5 GHz rule list
4656 * for few countries along with separate 6 GHz rule.
4657 * Having same 6 GHz reg rule in 5 GHz and 6 GHz rules list
4658 * causes intersect check to be true, and same rules will be
4659 * shown multiple times in iw cmd.
4660 * Hence, avoid parsing 6 GHz rule from 5 GHz reg rule list
4661 */
4662 num_invalid_5ghz_ext_rules = ath12k_wmi_ignore_num_extra_rules(ext_wmi_reg_rule,
4663 num_5g_reg_rules);
4664
4665 if (num_invalid_5ghz_ext_rules) {
4666 ath12k_dbg(ab, ATH12K_DBG_WMI,
4667 "CC: %s 5 GHz reg rules number %d from fw, %d number of invalid 5 GHz rules",
4668 reg_info->alpha2, reg_info->num_5g_reg_rules,
4669 num_invalid_5ghz_ext_rules);
4670
4671 num_5g_reg_rules = num_5g_reg_rules - num_invalid_5ghz_ext_rules;
4672 reg_info->num_5g_reg_rules = num_5g_reg_rules;
4673 }
4674
4675 if (num_5g_reg_rules) {
4676 reg_info->reg_rules_5g_ptr =
4677 create_ext_reg_rules_from_wmi(num_5g_reg_rules,
4678 ext_wmi_reg_rule);
4679
4680 if (!reg_info->reg_rules_5g_ptr) {
4681 kfree(tb);
4682 ath12k_warn(ab, "Unable to Allocate memory for 5g rules\n");
4683 return -ENOMEM;
4684 }
4685 }
4686
4687 /* We have adjusted the number of 5 GHz reg rules above. But still those
4688 * many rules needs to be adjusted in ext_wmi_reg_rule.
4689 *
4690 * NOTE: num_invalid_5ghz_ext_rules will be 0 for rest other cases.
4691 */
4692 ext_wmi_reg_rule += (num_5g_reg_rules + num_invalid_5ghz_ext_rules);
4693
4694 for (i = 0; i < WMI_REG_CURRENT_MAX_AP_TYPE; i++) {
4695 reg_info->reg_rules_6g_ap_ptr[i] =
4696 create_ext_reg_rules_from_wmi(num_6g_reg_rules_ap[i],
4697 ext_wmi_reg_rule);
4698
4699 if (!reg_info->reg_rules_6g_ap_ptr[i]) {
4700 kfree(tb);
4701 ath12k_warn(ab, "Unable to Allocate memory for 6g ap rules\n");
4702 return -ENOMEM;
4703 }
4704
4705 ext_wmi_reg_rule += num_6g_reg_rules_ap[i];
4706 }
4707
4708 for (j = 0; j < WMI_REG_CURRENT_MAX_AP_TYPE; j++) {
4709 for (i = 0; i < WMI_REG_MAX_CLIENT_TYPE; i++) {
4710 reg_info->reg_rules_6g_client_ptr[j][i] =
4711 create_ext_reg_rules_from_wmi(num_6g_reg_rules_cl[j][i],
4712 ext_wmi_reg_rule);
4713
4714 if (!reg_info->reg_rules_6g_client_ptr[j][i]) {
4715 kfree(tb);
4716 ath12k_warn(ab, "Unable to Allocate memory for 6g client rules\n");
4717 return -ENOMEM;
4718 }
4719
4720 ext_wmi_reg_rule += num_6g_reg_rules_cl[j][i];
4721 }
4722 }
4723
4724 reg_info->client_type = le32_to_cpu(ev->client_type);
4725 reg_info->rnr_tpe_usable = ev->rnr_tpe_usable;
4726 reg_info->unspecified_ap_usable = ev->unspecified_ap_usable;
4727 reg_info->domain_code_6g_ap[WMI_REG_INDOOR_AP] =
4728 le32_to_cpu(ev->domain_code_6g_ap_lpi);
4729 reg_info->domain_code_6g_ap[WMI_REG_STD_POWER_AP] =
4730 le32_to_cpu(ev->domain_code_6g_ap_sp);
4731 reg_info->domain_code_6g_ap[WMI_REG_VLP_AP] =
4732 le32_to_cpu(ev->domain_code_6g_ap_vlp);
4733
4734 for (i = 0; i < WMI_REG_MAX_CLIENT_TYPE; i++) {
4735 reg_info->domain_code_6g_client[WMI_REG_INDOOR_AP][i] =
4736 le32_to_cpu(ev->domain_code_6g_client_lpi[i]);
4737 reg_info->domain_code_6g_client[WMI_REG_STD_POWER_AP][i] =
4738 le32_to_cpu(ev->domain_code_6g_client_sp[i]);
4739 reg_info->domain_code_6g_client[WMI_REG_VLP_AP][i] =
4740 le32_to_cpu(ev->domain_code_6g_client_vlp[i]);
4741 }
4742
4743 reg_info->domain_code_6g_super_id = le32_to_cpu(ev->domain_code_6g_super_id);
4744
4745 ath12k_dbg(ab, ATH12K_DBG_WMI, "6g client_type: %d domain_code_6g_super_id: %d",
4746 reg_info->client_type, reg_info->domain_code_6g_super_id);
4747
4748 ath12k_dbg(ab, ATH12K_DBG_WMI, "processed regulatory ext channel list\n");
4749
4750 kfree(tb);
4751 return 0;
4752 }
4753
ath12k_pull_peer_del_resp_ev(struct ath12k_base * ab,struct sk_buff * skb,struct wmi_peer_delete_resp_event * peer_del_resp)4754 static int ath12k_pull_peer_del_resp_ev(struct ath12k_base *ab, struct sk_buff *skb,
4755 struct wmi_peer_delete_resp_event *peer_del_resp)
4756 {
4757 const void **tb;
4758 const struct wmi_peer_delete_resp_event *ev;
4759 int ret;
4760
4761 tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC);
4762 if (IS_ERR(tb)) {
4763 ret = PTR_ERR(tb);
4764 ath12k_warn(ab, "failed to parse tlv: %d\n", ret);
4765 return ret;
4766 }
4767
4768 ev = tb[WMI_TAG_PEER_DELETE_RESP_EVENT];
4769 if (!ev) {
4770 ath12k_warn(ab, "failed to fetch peer delete resp ev");
4771 kfree(tb);
4772 return -EPROTO;
4773 }
4774
4775 memset(peer_del_resp, 0, sizeof(*peer_del_resp));
4776
4777 peer_del_resp->vdev_id = ev->vdev_id;
4778 ether_addr_copy(peer_del_resp->peer_macaddr.addr,
4779 ev->peer_macaddr.addr);
4780
4781 kfree(tb);
4782 return 0;
4783 }
4784
ath12k_pull_vdev_del_resp_ev(struct ath12k_base * ab,struct sk_buff * skb,u32 * vdev_id)4785 static int ath12k_pull_vdev_del_resp_ev(struct ath12k_base *ab,
4786 struct sk_buff *skb,
4787 u32 *vdev_id)
4788 {
4789 const void **tb;
4790 const struct wmi_vdev_delete_resp_event *ev;
4791 int ret;
4792
4793 tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC);
4794 if (IS_ERR(tb)) {
4795 ret = PTR_ERR(tb);
4796 ath12k_warn(ab, "failed to parse tlv: %d\n", ret);
4797 return ret;
4798 }
4799
4800 ev = tb[WMI_TAG_VDEV_DELETE_RESP_EVENT];
4801 if (!ev) {
4802 ath12k_warn(ab, "failed to fetch vdev delete resp ev");
4803 kfree(tb);
4804 return -EPROTO;
4805 }
4806
4807 *vdev_id = le32_to_cpu(ev->vdev_id);
4808
4809 kfree(tb);
4810 return 0;
4811 }
4812
ath12k_pull_bcn_tx_status_ev(struct ath12k_base * ab,void * evt_buf,u32 len,u32 * vdev_id,u32 * tx_status)4813 static int ath12k_pull_bcn_tx_status_ev(struct ath12k_base *ab, void *evt_buf,
4814 u32 len, u32 *vdev_id,
4815 u32 *tx_status)
4816 {
4817 const void **tb;
4818 const struct wmi_bcn_tx_status_event *ev;
4819 int ret;
4820
4821 tb = ath12k_wmi_tlv_parse_alloc(ab, evt_buf, len, GFP_ATOMIC);
4822 if (IS_ERR(tb)) {
4823 ret = PTR_ERR(tb);
4824 ath12k_warn(ab, "failed to parse tlv: %d\n", ret);
4825 return ret;
4826 }
4827
4828 ev = tb[WMI_TAG_OFFLOAD_BCN_TX_STATUS_EVENT];
4829 if (!ev) {
4830 ath12k_warn(ab, "failed to fetch bcn tx status ev");
4831 kfree(tb);
4832 return -EPROTO;
4833 }
4834
4835 *vdev_id = le32_to_cpu(ev->vdev_id);
4836 *tx_status = le32_to_cpu(ev->tx_status);
4837
4838 kfree(tb);
4839 return 0;
4840 }
4841
ath12k_pull_vdev_stopped_param_tlv(struct ath12k_base * ab,struct sk_buff * skb,u32 * vdev_id)4842 static int ath12k_pull_vdev_stopped_param_tlv(struct ath12k_base *ab, struct sk_buff *skb,
4843 u32 *vdev_id)
4844 {
4845 const void **tb;
4846 const struct wmi_vdev_stopped_event *ev;
4847 int ret;
4848
4849 tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC);
4850 if (IS_ERR(tb)) {
4851 ret = PTR_ERR(tb);
4852 ath12k_warn(ab, "failed to parse tlv: %d\n", ret);
4853 return ret;
4854 }
4855
4856 ev = tb[WMI_TAG_VDEV_STOPPED_EVENT];
4857 if (!ev) {
4858 ath12k_warn(ab, "failed to fetch vdev stop ev");
4859 kfree(tb);
4860 return -EPROTO;
4861 }
4862
4863 *vdev_id = le32_to_cpu(ev->vdev_id);
4864
4865 kfree(tb);
4866 return 0;
4867 }
4868
ath12k_wmi_tlv_mgmt_rx_parse(struct ath12k_base * ab,u16 tag,u16 len,const void * ptr,void * data)4869 static int ath12k_wmi_tlv_mgmt_rx_parse(struct ath12k_base *ab,
4870 u16 tag, u16 len,
4871 const void *ptr, void *data)
4872 {
4873 struct wmi_tlv_mgmt_rx_parse *parse = data;
4874
4875 switch (tag) {
4876 case WMI_TAG_MGMT_RX_HDR:
4877 parse->fixed = ptr;
4878 break;
4879 case WMI_TAG_ARRAY_BYTE:
4880 if (!parse->frame_buf_done) {
4881 parse->frame_buf = ptr;
4882 parse->frame_buf_done = true;
4883 }
4884 break;
4885 }
4886 return 0;
4887 }
4888
ath12k_pull_mgmt_rx_params_tlv(struct ath12k_base * ab,struct sk_buff * skb,struct ath12k_wmi_mgmt_rx_arg * hdr)4889 static int ath12k_pull_mgmt_rx_params_tlv(struct ath12k_base *ab,
4890 struct sk_buff *skb,
4891 struct ath12k_wmi_mgmt_rx_arg *hdr)
4892 {
4893 struct wmi_tlv_mgmt_rx_parse parse = { };
4894 const struct ath12k_wmi_mgmt_rx_params *ev;
4895 const u8 *frame;
4896 int i, ret;
4897
4898 ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len,
4899 ath12k_wmi_tlv_mgmt_rx_parse,
4900 &parse);
4901 if (ret) {
4902 ath12k_warn(ab, "failed to parse mgmt rx tlv %d\n", ret);
4903 return ret;
4904 }
4905
4906 ev = parse.fixed;
4907 frame = parse.frame_buf;
4908
4909 if (!ev || !frame) {
4910 ath12k_warn(ab, "failed to fetch mgmt rx hdr");
4911 return -EPROTO;
4912 }
4913
4914 hdr->pdev_id = le32_to_cpu(ev->pdev_id);
4915 hdr->chan_freq = le32_to_cpu(ev->chan_freq);
4916 hdr->channel = le32_to_cpu(ev->channel);
4917 hdr->snr = le32_to_cpu(ev->snr);
4918 hdr->rate = le32_to_cpu(ev->rate);
4919 hdr->phy_mode = le32_to_cpu(ev->phy_mode);
4920 hdr->buf_len = le32_to_cpu(ev->buf_len);
4921 hdr->status = le32_to_cpu(ev->status);
4922 hdr->flags = le32_to_cpu(ev->flags);
4923 hdr->rssi = a_sle32_to_cpu(ev->rssi);
4924 hdr->tsf_delta = le32_to_cpu(ev->tsf_delta);
4925
4926 for (i = 0; i < ATH_MAX_ANTENNA; i++)
4927 hdr->rssi_ctl[i] = le32_to_cpu(ev->rssi_ctl[i]);
4928
4929 if (skb->len < (frame - skb->data) + hdr->buf_len) {
4930 ath12k_warn(ab, "invalid length in mgmt rx hdr ev");
4931 return -EPROTO;
4932 }
4933
4934 /* shift the sk_buff to point to `frame` */
4935 skb_trim(skb, 0);
4936 skb_put(skb, frame - skb->data);
4937 skb_pull(skb, frame - skb->data);
4938 skb_put(skb, hdr->buf_len);
4939
4940 return 0;
4941 }
4942
wmi_process_mgmt_tx_comp(struct ath12k * ar,u32 desc_id,u32 status)4943 static int wmi_process_mgmt_tx_comp(struct ath12k *ar, u32 desc_id,
4944 u32 status)
4945 {
4946 struct sk_buff *msdu;
4947 struct ieee80211_tx_info *info;
4948 struct ath12k_skb_cb *skb_cb;
4949 int num_mgmt;
4950
4951 spin_lock_bh(&ar->txmgmt_idr_lock);
4952 msdu = idr_find(&ar->txmgmt_idr, desc_id);
4953
4954 if (!msdu) {
4955 ath12k_warn(ar->ab, "received mgmt tx compl for invalid msdu_id: %d\n",
4956 desc_id);
4957 spin_unlock_bh(&ar->txmgmt_idr_lock);
4958 return -ENOENT;
4959 }
4960
4961 idr_remove(&ar->txmgmt_idr, desc_id);
4962 spin_unlock_bh(&ar->txmgmt_idr_lock);
4963
4964 skb_cb = ATH12K_SKB_CB(msdu);
4965 dma_unmap_single(ar->ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
4966
4967 info = IEEE80211_SKB_CB(msdu);
4968 if ((!(info->flags & IEEE80211_TX_CTL_NO_ACK)) && !status)
4969 info->flags |= IEEE80211_TX_STAT_ACK;
4970
4971 ieee80211_tx_status_irqsafe(ar->hw, msdu);
4972
4973 num_mgmt = atomic_dec_if_positive(&ar->num_pending_mgmt_tx);
4974
4975 /* WARN when we received this event without doing any mgmt tx */
4976 if (num_mgmt < 0)
4977 WARN_ON_ONCE(1);
4978
4979 if (!num_mgmt)
4980 wake_up(&ar->txmgmt_empty_waitq);
4981
4982 return 0;
4983 }
4984
ath12k_pull_mgmt_tx_compl_param_tlv(struct ath12k_base * ab,struct sk_buff * skb,struct wmi_mgmt_tx_compl_event * param)4985 static int ath12k_pull_mgmt_tx_compl_param_tlv(struct ath12k_base *ab,
4986 struct sk_buff *skb,
4987 struct wmi_mgmt_tx_compl_event *param)
4988 {
4989 const void **tb;
4990 const struct wmi_mgmt_tx_compl_event *ev;
4991 int ret;
4992
4993 tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC);
4994 if (IS_ERR(tb)) {
4995 ret = PTR_ERR(tb);
4996 ath12k_warn(ab, "failed to parse tlv: %d\n", ret);
4997 return ret;
4998 }
4999
5000 ev = tb[WMI_TAG_MGMT_TX_COMPL_EVENT];
5001 if (!ev) {
5002 ath12k_warn(ab, "failed to fetch mgmt tx compl ev");
5003 kfree(tb);
5004 return -EPROTO;
5005 }
5006
5007 param->pdev_id = ev->pdev_id;
5008 param->desc_id = ev->desc_id;
5009 param->status = ev->status;
5010
5011 kfree(tb);
5012 return 0;
5013 }
5014
ath12k_wmi_event_scan_started(struct ath12k * ar)5015 static void ath12k_wmi_event_scan_started(struct ath12k *ar)
5016 {
5017 lockdep_assert_held(&ar->data_lock);
5018
5019 switch (ar->scan.state) {
5020 case ATH12K_SCAN_IDLE:
5021 case ATH12K_SCAN_RUNNING:
5022 case ATH12K_SCAN_ABORTING:
5023 ath12k_warn(ar->ab, "received scan started event in an invalid scan state: %s (%d)\n",
5024 ath12k_scan_state_str(ar->scan.state),
5025 ar->scan.state);
5026 break;
5027 case ATH12K_SCAN_STARTING:
5028 ar->scan.state = ATH12K_SCAN_RUNNING;
5029 complete(&ar->scan.started);
5030 break;
5031 }
5032 }
5033
ath12k_wmi_event_scan_start_failed(struct ath12k * ar)5034 static void ath12k_wmi_event_scan_start_failed(struct ath12k *ar)
5035 {
5036 lockdep_assert_held(&ar->data_lock);
5037
5038 switch (ar->scan.state) {
5039 case ATH12K_SCAN_IDLE:
5040 case ATH12K_SCAN_RUNNING:
5041 case ATH12K_SCAN_ABORTING:
5042 ath12k_warn(ar->ab, "received scan start failed event in an invalid scan state: %s (%d)\n",
5043 ath12k_scan_state_str(ar->scan.state),
5044 ar->scan.state);
5045 break;
5046 case ATH12K_SCAN_STARTING:
5047 complete(&ar->scan.started);
5048 __ath12k_mac_scan_finish(ar);
5049 break;
5050 }
5051 }
5052
ath12k_wmi_event_scan_completed(struct ath12k * ar)5053 static void ath12k_wmi_event_scan_completed(struct ath12k *ar)
5054 {
5055 lockdep_assert_held(&ar->data_lock);
5056
5057 switch (ar->scan.state) {
5058 case ATH12K_SCAN_IDLE:
5059 case ATH12K_SCAN_STARTING:
5060 /* One suspected reason scan can be completed while starting is
5061 * if firmware fails to deliver all scan events to the host,
5062 * e.g. when transport pipe is full. This has been observed
5063 * with spectral scan phyerr events starving wmi transport
5064 * pipe. In such case the "scan completed" event should be (and
5065 * is) ignored by the host as it may be just firmware's scan
5066 * state machine recovering.
5067 */
5068 ath12k_warn(ar->ab, "received scan completed event in an invalid scan state: %s (%d)\n",
5069 ath12k_scan_state_str(ar->scan.state),
5070 ar->scan.state);
5071 break;
5072 case ATH12K_SCAN_RUNNING:
5073 case ATH12K_SCAN_ABORTING:
5074 __ath12k_mac_scan_finish(ar);
5075 break;
5076 }
5077 }
5078
ath12k_wmi_event_scan_bss_chan(struct ath12k * ar)5079 static void ath12k_wmi_event_scan_bss_chan(struct ath12k *ar)
5080 {
5081 lockdep_assert_held(&ar->data_lock);
5082
5083 switch (ar->scan.state) {
5084 case ATH12K_SCAN_IDLE:
5085 case ATH12K_SCAN_STARTING:
5086 ath12k_warn(ar->ab, "received scan bss chan event in an invalid scan state: %s (%d)\n",
5087 ath12k_scan_state_str(ar->scan.state),
5088 ar->scan.state);
5089 break;
5090 case ATH12K_SCAN_RUNNING:
5091 case ATH12K_SCAN_ABORTING:
5092 ar->scan_channel = NULL;
5093 break;
5094 }
5095 }
5096
ath12k_wmi_event_scan_foreign_chan(struct ath12k * ar,u32 freq)5097 static void ath12k_wmi_event_scan_foreign_chan(struct ath12k *ar, u32 freq)
5098 {
5099 lockdep_assert_held(&ar->data_lock);
5100
5101 switch (ar->scan.state) {
5102 case ATH12K_SCAN_IDLE:
5103 case ATH12K_SCAN_STARTING:
5104 ath12k_warn(ar->ab, "received scan foreign chan event in an invalid scan state: %s (%d)\n",
5105 ath12k_scan_state_str(ar->scan.state),
5106 ar->scan.state);
5107 break;
5108 case ATH12K_SCAN_RUNNING:
5109 case ATH12K_SCAN_ABORTING:
5110 ar->scan_channel = ieee80211_get_channel(ar->hw->wiphy, freq);
5111 break;
5112 }
5113 }
5114
5115 static const char *
ath12k_wmi_event_scan_type_str(enum wmi_scan_event_type type,enum wmi_scan_completion_reason reason)5116 ath12k_wmi_event_scan_type_str(enum wmi_scan_event_type type,
5117 enum wmi_scan_completion_reason reason)
5118 {
5119 switch (type) {
5120 case WMI_SCAN_EVENT_STARTED:
5121 return "started";
5122 case WMI_SCAN_EVENT_COMPLETED:
5123 switch (reason) {
5124 case WMI_SCAN_REASON_COMPLETED:
5125 return "completed";
5126 case WMI_SCAN_REASON_CANCELLED:
5127 return "completed [cancelled]";
5128 case WMI_SCAN_REASON_PREEMPTED:
5129 return "completed [preempted]";
5130 case WMI_SCAN_REASON_TIMEDOUT:
5131 return "completed [timedout]";
5132 case WMI_SCAN_REASON_INTERNAL_FAILURE:
5133 return "completed [internal err]";
5134 case WMI_SCAN_REASON_MAX:
5135 break;
5136 }
5137 return "completed [unknown]";
5138 case WMI_SCAN_EVENT_BSS_CHANNEL:
5139 return "bss channel";
5140 case WMI_SCAN_EVENT_FOREIGN_CHAN:
5141 return "foreign channel";
5142 case WMI_SCAN_EVENT_DEQUEUED:
5143 return "dequeued";
5144 case WMI_SCAN_EVENT_PREEMPTED:
5145 return "preempted";
5146 case WMI_SCAN_EVENT_START_FAILED:
5147 return "start failed";
5148 case WMI_SCAN_EVENT_RESTARTED:
5149 return "restarted";
5150 case WMI_SCAN_EVENT_FOREIGN_CHAN_EXIT:
5151 return "foreign channel exit";
5152 default:
5153 return "unknown";
5154 }
5155 }
5156
ath12k_pull_scan_ev(struct ath12k_base * ab,struct sk_buff * skb,struct wmi_scan_event * scan_evt_param)5157 static int ath12k_pull_scan_ev(struct ath12k_base *ab, struct sk_buff *skb,
5158 struct wmi_scan_event *scan_evt_param)
5159 {
5160 const void **tb;
5161 const struct wmi_scan_event *ev;
5162 int ret;
5163
5164 tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC);
5165 if (IS_ERR(tb)) {
5166 ret = PTR_ERR(tb);
5167 ath12k_warn(ab, "failed to parse tlv: %d\n", ret);
5168 return ret;
5169 }
5170
5171 ev = tb[WMI_TAG_SCAN_EVENT];
5172 if (!ev) {
5173 ath12k_warn(ab, "failed to fetch scan ev");
5174 kfree(tb);
5175 return -EPROTO;
5176 }
5177
5178 scan_evt_param->event_type = ev->event_type;
5179 scan_evt_param->reason = ev->reason;
5180 scan_evt_param->channel_freq = ev->channel_freq;
5181 scan_evt_param->scan_req_id = ev->scan_req_id;
5182 scan_evt_param->scan_id = ev->scan_id;
5183 scan_evt_param->vdev_id = ev->vdev_id;
5184 scan_evt_param->tsf_timestamp = ev->tsf_timestamp;
5185
5186 kfree(tb);
5187 return 0;
5188 }
5189
ath12k_pull_peer_sta_kickout_ev(struct ath12k_base * ab,struct sk_buff * skb,struct wmi_peer_sta_kickout_arg * arg)5190 static int ath12k_pull_peer_sta_kickout_ev(struct ath12k_base *ab, struct sk_buff *skb,
5191 struct wmi_peer_sta_kickout_arg *arg)
5192 {
5193 const void **tb;
5194 const struct wmi_peer_sta_kickout_event *ev;
5195 int ret;
5196
5197 tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC);
5198 if (IS_ERR(tb)) {
5199 ret = PTR_ERR(tb);
5200 ath12k_warn(ab, "failed to parse tlv: %d\n", ret);
5201 return ret;
5202 }
5203
5204 ev = tb[WMI_TAG_PEER_STA_KICKOUT_EVENT];
5205 if (!ev) {
5206 ath12k_warn(ab, "failed to fetch peer sta kickout ev");
5207 kfree(tb);
5208 return -EPROTO;
5209 }
5210
5211 arg->mac_addr = ev->peer_macaddr.addr;
5212
5213 kfree(tb);
5214 return 0;
5215 }
5216
ath12k_pull_roam_ev(struct ath12k_base * ab,struct sk_buff * skb,struct wmi_roam_event * roam_ev)5217 static int ath12k_pull_roam_ev(struct ath12k_base *ab, struct sk_buff *skb,
5218 struct wmi_roam_event *roam_ev)
5219 {
5220 const void **tb;
5221 const struct wmi_roam_event *ev;
5222 int ret;
5223
5224 tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC);
5225 if (IS_ERR(tb)) {
5226 ret = PTR_ERR(tb);
5227 ath12k_warn(ab, "failed to parse tlv: %d\n", ret);
5228 return ret;
5229 }
5230
5231 ev = tb[WMI_TAG_ROAM_EVENT];
5232 if (!ev) {
5233 ath12k_warn(ab, "failed to fetch roam ev");
5234 kfree(tb);
5235 return -EPROTO;
5236 }
5237
5238 roam_ev->vdev_id = ev->vdev_id;
5239 roam_ev->reason = ev->reason;
5240 roam_ev->rssi = ev->rssi;
5241
5242 kfree(tb);
5243 return 0;
5244 }
5245
freq_to_idx(struct ath12k * ar,int freq)5246 static int freq_to_idx(struct ath12k *ar, int freq)
5247 {
5248 struct ieee80211_supported_band *sband;
5249 int band, ch, idx = 0;
5250
5251 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) {
5252 if (!ar->mac.sbands[band].channels)
5253 continue;
5254
5255 sband = ar->hw->wiphy->bands[band];
5256 if (!sband)
5257 continue;
5258
5259 for (ch = 0; ch < sband->n_channels; ch++, idx++)
5260 if (sband->channels[ch].center_freq == freq)
5261 goto exit;
5262 }
5263
5264 exit:
5265 return idx;
5266 }
5267
ath12k_pull_chan_info_ev(struct ath12k_base * ab,u8 * evt_buf,u32 len,struct wmi_chan_info_event * ch_info_ev)5268 static int ath12k_pull_chan_info_ev(struct ath12k_base *ab, u8 *evt_buf,
5269 u32 len, struct wmi_chan_info_event *ch_info_ev)
5270 {
5271 const void **tb;
5272 const struct wmi_chan_info_event *ev;
5273 int ret;
5274
5275 tb = ath12k_wmi_tlv_parse_alloc(ab, evt_buf, len, GFP_ATOMIC);
5276 if (IS_ERR(tb)) {
5277 ret = PTR_ERR(tb);
5278 ath12k_warn(ab, "failed to parse tlv: %d\n", ret);
5279 return ret;
5280 }
5281
5282 ev = tb[WMI_TAG_CHAN_INFO_EVENT];
5283 if (!ev) {
5284 ath12k_warn(ab, "failed to fetch chan info ev");
5285 kfree(tb);
5286 return -EPROTO;
5287 }
5288
5289 ch_info_ev->err_code = ev->err_code;
5290 ch_info_ev->freq = ev->freq;
5291 ch_info_ev->cmd_flags = ev->cmd_flags;
5292 ch_info_ev->noise_floor = ev->noise_floor;
5293 ch_info_ev->rx_clear_count = ev->rx_clear_count;
5294 ch_info_ev->cycle_count = ev->cycle_count;
5295 ch_info_ev->chan_tx_pwr_range = ev->chan_tx_pwr_range;
5296 ch_info_ev->chan_tx_pwr_tp = ev->chan_tx_pwr_tp;
5297 ch_info_ev->rx_frame_count = ev->rx_frame_count;
5298 ch_info_ev->tx_frame_cnt = ev->tx_frame_cnt;
5299 ch_info_ev->mac_clk_mhz = ev->mac_clk_mhz;
5300 ch_info_ev->vdev_id = ev->vdev_id;
5301
5302 kfree(tb);
5303 return 0;
5304 }
5305
5306 static int
ath12k_pull_pdev_bss_chan_info_ev(struct ath12k_base * ab,struct sk_buff * skb,struct wmi_pdev_bss_chan_info_event * bss_ch_info_ev)5307 ath12k_pull_pdev_bss_chan_info_ev(struct ath12k_base *ab, struct sk_buff *skb,
5308 struct wmi_pdev_bss_chan_info_event *bss_ch_info_ev)
5309 {
5310 const void **tb;
5311 const struct wmi_pdev_bss_chan_info_event *ev;
5312 int ret;
5313
5314 tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC);
5315 if (IS_ERR(tb)) {
5316 ret = PTR_ERR(tb);
5317 ath12k_warn(ab, "failed to parse tlv: %d\n", ret);
5318 return ret;
5319 }
5320
5321 ev = tb[WMI_TAG_PDEV_BSS_CHAN_INFO_EVENT];
5322 if (!ev) {
5323 ath12k_warn(ab, "failed to fetch pdev bss chan info ev");
5324 kfree(tb);
5325 return -EPROTO;
5326 }
5327
5328 bss_ch_info_ev->pdev_id = ev->pdev_id;
5329 bss_ch_info_ev->freq = ev->freq;
5330 bss_ch_info_ev->noise_floor = ev->noise_floor;
5331 bss_ch_info_ev->rx_clear_count_low = ev->rx_clear_count_low;
5332 bss_ch_info_ev->rx_clear_count_high = ev->rx_clear_count_high;
5333 bss_ch_info_ev->cycle_count_low = ev->cycle_count_low;
5334 bss_ch_info_ev->cycle_count_high = ev->cycle_count_high;
5335 bss_ch_info_ev->tx_cycle_count_low = ev->tx_cycle_count_low;
5336 bss_ch_info_ev->tx_cycle_count_high = ev->tx_cycle_count_high;
5337 bss_ch_info_ev->rx_cycle_count_low = ev->rx_cycle_count_low;
5338 bss_ch_info_ev->rx_cycle_count_high = ev->rx_cycle_count_high;
5339 bss_ch_info_ev->rx_bss_cycle_count_low = ev->rx_bss_cycle_count_low;
5340 bss_ch_info_ev->rx_bss_cycle_count_high = ev->rx_bss_cycle_count_high;
5341
5342 kfree(tb);
5343 return 0;
5344 }
5345
5346 static int
ath12k_pull_vdev_install_key_compl_ev(struct ath12k_base * ab,struct sk_buff * skb,struct wmi_vdev_install_key_complete_arg * arg)5347 ath12k_pull_vdev_install_key_compl_ev(struct ath12k_base *ab, struct sk_buff *skb,
5348 struct wmi_vdev_install_key_complete_arg *arg)
5349 {
5350 const void **tb;
5351 const struct wmi_vdev_install_key_compl_event *ev;
5352 int ret;
5353
5354 tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC);
5355 if (IS_ERR(tb)) {
5356 ret = PTR_ERR(tb);
5357 ath12k_warn(ab, "failed to parse tlv: %d\n", ret);
5358 return ret;
5359 }
5360
5361 ev = tb[WMI_TAG_VDEV_INSTALL_KEY_COMPLETE_EVENT];
5362 if (!ev) {
5363 ath12k_warn(ab, "failed to fetch vdev install key compl ev");
5364 kfree(tb);
5365 return -EPROTO;
5366 }
5367
5368 arg->vdev_id = le32_to_cpu(ev->vdev_id);
5369 arg->macaddr = ev->peer_macaddr.addr;
5370 arg->key_idx = le32_to_cpu(ev->key_idx);
5371 arg->key_flags = le32_to_cpu(ev->key_flags);
5372 arg->status = le32_to_cpu(ev->status);
5373
5374 kfree(tb);
5375 return 0;
5376 }
5377
ath12k_pull_peer_assoc_conf_ev(struct ath12k_base * ab,struct sk_buff * skb,struct wmi_peer_assoc_conf_arg * peer_assoc_conf)5378 static int ath12k_pull_peer_assoc_conf_ev(struct ath12k_base *ab, struct sk_buff *skb,
5379 struct wmi_peer_assoc_conf_arg *peer_assoc_conf)
5380 {
5381 const void **tb;
5382 const struct wmi_peer_assoc_conf_event *ev;
5383 int ret;
5384
5385 tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC);
5386 if (IS_ERR(tb)) {
5387 ret = PTR_ERR(tb);
5388 ath12k_warn(ab, "failed to parse tlv: %d\n", ret);
5389 return ret;
5390 }
5391
5392 ev = tb[WMI_TAG_PEER_ASSOC_CONF_EVENT];
5393 if (!ev) {
5394 ath12k_warn(ab, "failed to fetch peer assoc conf ev");
5395 kfree(tb);
5396 return -EPROTO;
5397 }
5398
5399 peer_assoc_conf->vdev_id = le32_to_cpu(ev->vdev_id);
5400 peer_assoc_conf->macaddr = ev->peer_macaddr.addr;
5401
5402 kfree(tb);
5403 return 0;
5404 }
5405
5406 static int
ath12k_pull_pdev_temp_ev(struct ath12k_base * ab,u8 * evt_buf,u32 len,const struct wmi_pdev_temperature_event * ev)5407 ath12k_pull_pdev_temp_ev(struct ath12k_base *ab, u8 *evt_buf,
5408 u32 len, const struct wmi_pdev_temperature_event *ev)
5409 {
5410 const void **tb;
5411 int ret;
5412
5413 tb = ath12k_wmi_tlv_parse_alloc(ab, evt_buf, len, GFP_ATOMIC);
5414 if (IS_ERR(tb)) {
5415 ret = PTR_ERR(tb);
5416 ath12k_warn(ab, "failed to parse tlv: %d\n", ret);
5417 return ret;
5418 }
5419
5420 ev = tb[WMI_TAG_PDEV_TEMPERATURE_EVENT];
5421 if (!ev) {
5422 ath12k_warn(ab, "failed to fetch pdev temp ev");
5423 kfree(tb);
5424 return -EPROTO;
5425 }
5426
5427 kfree(tb);
5428 return 0;
5429 }
5430
ath12k_wmi_op_ep_tx_credits(struct ath12k_base * ab)5431 static void ath12k_wmi_op_ep_tx_credits(struct ath12k_base *ab)
5432 {
5433 /* try to send pending beacons first. they take priority */
5434 wake_up(&ab->wmi_ab.tx_credits_wq);
5435 }
5436
ath12k_wmi_htc_tx_complete(struct ath12k_base * ab,struct sk_buff * skb)5437 static void ath12k_wmi_htc_tx_complete(struct ath12k_base *ab,
5438 struct sk_buff *skb)
5439 {
5440 dev_kfree_skb(skb);
5441 }
5442
ath12k_reg_is_world_alpha(char * alpha)5443 static bool ath12k_reg_is_world_alpha(char *alpha)
5444 {
5445 return alpha[0] == '0' && alpha[1] == '0';
5446 }
5447
ath12k_reg_chan_list_event(struct ath12k_base * ab,struct sk_buff * skb)5448 static int ath12k_reg_chan_list_event(struct ath12k_base *ab, struct sk_buff *skb)
5449 {
5450 struct ath12k_reg_info *reg_info = NULL;
5451 struct ieee80211_regdomain *regd = NULL;
5452 bool intersect = false;
5453 int ret = 0, pdev_idx, i, j;
5454 struct ath12k *ar;
5455
5456 reg_info = kzalloc(sizeof(*reg_info), GFP_ATOMIC);
5457 if (!reg_info) {
5458 ret = -ENOMEM;
5459 goto fallback;
5460 }
5461
5462 ret = ath12k_pull_reg_chan_list_ext_update_ev(ab, skb, reg_info);
5463
5464 if (ret) {
5465 ath12k_warn(ab, "failed to extract regulatory info from received event\n");
5466 goto fallback;
5467 }
5468
5469 if (reg_info->status_code != REG_SET_CC_STATUS_PASS) {
5470 /* In case of failure to set the requested ctry,
5471 * fw retains the current regd. We print a failure info
5472 * and return from here.
5473 */
5474 ath12k_warn(ab, "Failed to set the requested Country regulatory setting\n");
5475 goto mem_free;
5476 }
5477
5478 pdev_idx = reg_info->phy_id;
5479
5480 if (pdev_idx >= ab->num_radios) {
5481 /* Process the event for phy0 only if single_pdev_only
5482 * is true. If pdev_idx is valid but not 0, discard the
5483 * event. Otherwise, it goes to fallback.
5484 */
5485 if (ab->hw_params->single_pdev_only &&
5486 pdev_idx < ab->hw_params->num_rxmda_per_pdev)
5487 goto mem_free;
5488 else
5489 goto fallback;
5490 }
5491
5492 /* Avoid multiple overwrites to default regd, during core
5493 * stop-start after mac registration.
5494 */
5495 if (ab->default_regd[pdev_idx] && !ab->new_regd[pdev_idx] &&
5496 !memcmp(ab->default_regd[pdev_idx]->alpha2,
5497 reg_info->alpha2, 2))
5498 goto mem_free;
5499
5500 /* Intersect new rules with default regd if a new country setting was
5501 * requested, i.e a default regd was already set during initialization
5502 * and the regd coming from this event has a valid country info.
5503 */
5504 if (ab->default_regd[pdev_idx] &&
5505 !ath12k_reg_is_world_alpha((char *)
5506 ab->default_regd[pdev_idx]->alpha2) &&
5507 !ath12k_reg_is_world_alpha((char *)reg_info->alpha2))
5508 intersect = true;
5509
5510 regd = ath12k_reg_build_regd(ab, reg_info, intersect);
5511 if (!regd) {
5512 ath12k_warn(ab, "failed to build regd from reg_info\n");
5513 goto fallback;
5514 }
5515
5516 spin_lock_bh(&ab->base_lock);
5517 if (test_bit(ATH12K_FLAG_REGISTERED, &ab->dev_flags)) {
5518 /* Once mac is registered, ar is valid and all CC events from
5519 * fw is considered to be received due to user requests
5520 * currently.
5521 * Free previously built regd before assigning the newly
5522 * generated regd to ar. NULL pointer handling will be
5523 * taken care by kfree itself.
5524 */
5525 ar = ab->pdevs[pdev_idx].ar;
5526 kfree(ab->new_regd[pdev_idx]);
5527 ab->new_regd[pdev_idx] = regd;
5528 queue_work(ab->workqueue, &ar->regd_update_work);
5529 } else {
5530 /* Multiple events for the same *ar is not expected. But we
5531 * can still clear any previously stored default_regd if we
5532 * are receiving this event for the same radio by mistake.
5533 * NULL pointer handling will be taken care by kfree itself.
5534 */
5535 kfree(ab->default_regd[pdev_idx]);
5536 /* This regd would be applied during mac registration */
5537 ab->default_regd[pdev_idx] = regd;
5538 }
5539 ab->dfs_region = reg_info->dfs_region;
5540 spin_unlock_bh(&ab->base_lock);
5541
5542 goto mem_free;
5543
5544 fallback:
5545 /* Fallback to older reg (by sending previous country setting
5546 * again if fw has succeeded and we failed to process here.
5547 * The Regdomain should be uniform across driver and fw. Since the
5548 * FW has processed the command and sent a success status, we expect
5549 * this function to succeed as well. If it doesn't, CTRY needs to be
5550 * reverted at the fw and the old SCAN_CHAN_LIST cmd needs to be sent.
5551 */
5552 /* TODO: This is rare, but still should also be handled */
5553 WARN_ON(1);
5554 mem_free:
5555 if (reg_info) {
5556 kfree(reg_info->reg_rules_2g_ptr);
5557 kfree(reg_info->reg_rules_5g_ptr);
5558 if (reg_info->is_ext_reg_event) {
5559 for (i = 0; i < WMI_REG_CURRENT_MAX_AP_TYPE; i++)
5560 kfree(reg_info->reg_rules_6g_ap_ptr[i]);
5561
5562 for (j = 0; j < WMI_REG_CURRENT_MAX_AP_TYPE; j++)
5563 for (i = 0; i < WMI_REG_MAX_CLIENT_TYPE; i++)
5564 kfree(reg_info->reg_rules_6g_client_ptr[j][i]);
5565 }
5566 kfree(reg_info);
5567 }
5568 return ret;
5569 }
5570
ath12k_wmi_rdy_parse(struct ath12k_base * ab,u16 tag,u16 len,const void * ptr,void * data)5571 static int ath12k_wmi_rdy_parse(struct ath12k_base *ab, u16 tag, u16 len,
5572 const void *ptr, void *data)
5573 {
5574 struct ath12k_wmi_rdy_parse *rdy_parse = data;
5575 struct wmi_ready_event fixed_param;
5576 struct ath12k_wmi_mac_addr_params *addr_list;
5577 struct ath12k_pdev *pdev;
5578 u32 num_mac_addr;
5579 int i;
5580
5581 switch (tag) {
5582 case WMI_TAG_READY_EVENT:
5583 memset(&fixed_param, 0, sizeof(fixed_param));
5584 memcpy(&fixed_param, (struct wmi_ready_event *)ptr,
5585 min_t(u16, sizeof(fixed_param), len));
5586 ab->wlan_init_status = le32_to_cpu(fixed_param.ready_event_min.status);
5587 rdy_parse->num_extra_mac_addr =
5588 le32_to_cpu(fixed_param.ready_event_min.num_extra_mac_addr);
5589
5590 ether_addr_copy(ab->mac_addr,
5591 fixed_param.ready_event_min.mac_addr.addr);
5592 ab->pktlog_defs_checksum = le32_to_cpu(fixed_param.pktlog_defs_checksum);
5593 ab->wmi_ready = true;
5594 break;
5595 case WMI_TAG_ARRAY_FIXED_STRUCT:
5596 addr_list = (struct ath12k_wmi_mac_addr_params *)ptr;
5597 num_mac_addr = rdy_parse->num_extra_mac_addr;
5598
5599 if (!(ab->num_radios > 1 && num_mac_addr >= ab->num_radios))
5600 break;
5601
5602 for (i = 0; i < ab->num_radios; i++) {
5603 pdev = &ab->pdevs[i];
5604 ether_addr_copy(pdev->mac_addr, addr_list[i].addr);
5605 }
5606 ab->pdevs_macaddr_valid = true;
5607 break;
5608 default:
5609 break;
5610 }
5611
5612 return 0;
5613 }
5614
ath12k_ready_event(struct ath12k_base * ab,struct sk_buff * skb)5615 static int ath12k_ready_event(struct ath12k_base *ab, struct sk_buff *skb)
5616 {
5617 struct ath12k_wmi_rdy_parse rdy_parse = { };
5618 int ret;
5619
5620 ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len,
5621 ath12k_wmi_rdy_parse, &rdy_parse);
5622 if (ret) {
5623 ath12k_warn(ab, "failed to parse tlv %d\n", ret);
5624 return ret;
5625 }
5626
5627 complete(&ab->wmi_ab.unified_ready);
5628 return 0;
5629 }
5630
ath12k_peer_delete_resp_event(struct ath12k_base * ab,struct sk_buff * skb)5631 static void ath12k_peer_delete_resp_event(struct ath12k_base *ab, struct sk_buff *skb)
5632 {
5633 struct wmi_peer_delete_resp_event peer_del_resp;
5634 struct ath12k *ar;
5635
5636 if (ath12k_pull_peer_del_resp_ev(ab, skb, &peer_del_resp) != 0) {
5637 ath12k_warn(ab, "failed to extract peer delete resp");
5638 return;
5639 }
5640
5641 rcu_read_lock();
5642 ar = ath12k_mac_get_ar_by_vdev_id(ab, le32_to_cpu(peer_del_resp.vdev_id));
5643 if (!ar) {
5644 ath12k_warn(ab, "invalid vdev id in peer delete resp ev %d",
5645 peer_del_resp.vdev_id);
5646 rcu_read_unlock();
5647 return;
5648 }
5649
5650 complete(&ar->peer_delete_done);
5651 rcu_read_unlock();
5652 ath12k_dbg(ab, ATH12K_DBG_WMI, "peer delete resp for vdev id %d addr %pM\n",
5653 peer_del_resp.vdev_id, peer_del_resp.peer_macaddr.addr);
5654 }
5655
ath12k_vdev_delete_resp_event(struct ath12k_base * ab,struct sk_buff * skb)5656 static void ath12k_vdev_delete_resp_event(struct ath12k_base *ab,
5657 struct sk_buff *skb)
5658 {
5659 struct ath12k *ar;
5660 u32 vdev_id = 0;
5661
5662 if (ath12k_pull_vdev_del_resp_ev(ab, skb, &vdev_id) != 0) {
5663 ath12k_warn(ab, "failed to extract vdev delete resp");
5664 return;
5665 }
5666
5667 rcu_read_lock();
5668 ar = ath12k_mac_get_ar_by_vdev_id(ab, vdev_id);
5669 if (!ar) {
5670 ath12k_warn(ab, "invalid vdev id in vdev delete resp ev %d",
5671 vdev_id);
5672 rcu_read_unlock();
5673 return;
5674 }
5675
5676 complete(&ar->vdev_delete_done);
5677
5678 rcu_read_unlock();
5679
5680 ath12k_dbg(ab, ATH12K_DBG_WMI, "vdev delete resp for vdev id %d\n",
5681 vdev_id);
5682 }
5683
ath12k_wmi_vdev_resp_print(u32 vdev_resp_status)5684 static const char *ath12k_wmi_vdev_resp_print(u32 vdev_resp_status)
5685 {
5686 switch (vdev_resp_status) {
5687 case WMI_VDEV_START_RESPONSE_INVALID_VDEVID:
5688 return "invalid vdev id";
5689 case WMI_VDEV_START_RESPONSE_NOT_SUPPORTED:
5690 return "not supported";
5691 case WMI_VDEV_START_RESPONSE_DFS_VIOLATION:
5692 return "dfs violation";
5693 case WMI_VDEV_START_RESPONSE_INVALID_REGDOMAIN:
5694 return "invalid regdomain";
5695 default:
5696 return "unknown";
5697 }
5698 }
5699
ath12k_vdev_start_resp_event(struct ath12k_base * ab,struct sk_buff * skb)5700 static void ath12k_vdev_start_resp_event(struct ath12k_base *ab, struct sk_buff *skb)
5701 {
5702 struct wmi_vdev_start_resp_event vdev_start_resp;
5703 struct ath12k *ar;
5704 u32 status;
5705
5706 if (ath12k_pull_vdev_start_resp_tlv(ab, skb, &vdev_start_resp) != 0) {
5707 ath12k_warn(ab, "failed to extract vdev start resp");
5708 return;
5709 }
5710
5711 rcu_read_lock();
5712 ar = ath12k_mac_get_ar_by_vdev_id(ab, le32_to_cpu(vdev_start_resp.vdev_id));
5713 if (!ar) {
5714 ath12k_warn(ab, "invalid vdev id in vdev start resp ev %d",
5715 vdev_start_resp.vdev_id);
5716 rcu_read_unlock();
5717 return;
5718 }
5719
5720 ar->last_wmi_vdev_start_status = 0;
5721
5722 status = le32_to_cpu(vdev_start_resp.status);
5723
5724 if (WARN_ON_ONCE(status)) {
5725 ath12k_warn(ab, "vdev start resp error status %d (%s)\n",
5726 status, ath12k_wmi_vdev_resp_print(status));
5727 ar->last_wmi_vdev_start_status = status;
5728 }
5729
5730 complete(&ar->vdev_setup_done);
5731
5732 rcu_read_unlock();
5733
5734 ath12k_dbg(ab, ATH12K_DBG_WMI, "vdev start resp for vdev id %d",
5735 vdev_start_resp.vdev_id);
5736 }
5737
ath12k_bcn_tx_status_event(struct ath12k_base * ab,struct sk_buff * skb)5738 static void ath12k_bcn_tx_status_event(struct ath12k_base *ab, struct sk_buff *skb)
5739 {
5740 u32 vdev_id, tx_status;
5741
5742 if (ath12k_pull_bcn_tx_status_ev(ab, skb->data, skb->len,
5743 &vdev_id, &tx_status) != 0) {
5744 ath12k_warn(ab, "failed to extract bcn tx status");
5745 return;
5746 }
5747 }
5748
ath12k_vdev_stopped_event(struct ath12k_base * ab,struct sk_buff * skb)5749 static void ath12k_vdev_stopped_event(struct ath12k_base *ab, struct sk_buff *skb)
5750 {
5751 struct ath12k *ar;
5752 u32 vdev_id = 0;
5753
5754 if (ath12k_pull_vdev_stopped_param_tlv(ab, skb, &vdev_id) != 0) {
5755 ath12k_warn(ab, "failed to extract vdev stopped event");
5756 return;
5757 }
5758
5759 rcu_read_lock();
5760 ar = ath12k_mac_get_ar_by_vdev_id(ab, vdev_id);
5761 if (!ar) {
5762 ath12k_warn(ab, "invalid vdev id in vdev stopped ev %d",
5763 vdev_id);
5764 rcu_read_unlock();
5765 return;
5766 }
5767
5768 complete(&ar->vdev_setup_done);
5769
5770 rcu_read_unlock();
5771
5772 ath12k_dbg(ab, ATH12K_DBG_WMI, "vdev stopped for vdev id %d", vdev_id);
5773 }
5774
ath12k_mgmt_rx_event(struct ath12k_base * ab,struct sk_buff * skb)5775 static void ath12k_mgmt_rx_event(struct ath12k_base *ab, struct sk_buff *skb)
5776 {
5777 struct ath12k_wmi_mgmt_rx_arg rx_ev = {0};
5778 struct ath12k *ar;
5779 struct ieee80211_rx_status *status = IEEE80211_SKB_RXCB(skb);
5780 struct ieee80211_hdr *hdr;
5781 u16 fc;
5782 struct ieee80211_supported_band *sband;
5783
5784 if (ath12k_pull_mgmt_rx_params_tlv(ab, skb, &rx_ev) != 0) {
5785 ath12k_warn(ab, "failed to extract mgmt rx event");
5786 dev_kfree_skb(skb);
5787 return;
5788 }
5789
5790 memset(status, 0, sizeof(*status));
5791
5792 ath12k_dbg(ab, ATH12K_DBG_MGMT, "mgmt rx event status %08x\n",
5793 rx_ev.status);
5794
5795 rcu_read_lock();
5796 ar = ath12k_mac_get_ar_by_pdev_id(ab, rx_ev.pdev_id);
5797
5798 if (!ar) {
5799 ath12k_warn(ab, "invalid pdev_id %d in mgmt_rx_event\n",
5800 rx_ev.pdev_id);
5801 dev_kfree_skb(skb);
5802 goto exit;
5803 }
5804
5805 if ((test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) ||
5806 (rx_ev.status & (WMI_RX_STATUS_ERR_DECRYPT |
5807 WMI_RX_STATUS_ERR_KEY_CACHE_MISS |
5808 WMI_RX_STATUS_ERR_CRC))) {
5809 dev_kfree_skb(skb);
5810 goto exit;
5811 }
5812
5813 if (rx_ev.status & WMI_RX_STATUS_ERR_MIC)
5814 status->flag |= RX_FLAG_MMIC_ERROR;
5815
5816 if (rx_ev.chan_freq >= ATH12K_MIN_6G_FREQ &&
5817 rx_ev.chan_freq <= ATH12K_MAX_6G_FREQ) {
5818 status->band = NL80211_BAND_6GHZ;
5819 status->freq = rx_ev.chan_freq;
5820 } else if (rx_ev.channel >= 1 && rx_ev.channel <= 14) {
5821 status->band = NL80211_BAND_2GHZ;
5822 } else if (rx_ev.channel >= 36 && rx_ev.channel <= ATH12K_MAX_5G_CHAN) {
5823 status->band = NL80211_BAND_5GHZ;
5824 } else {
5825 /* Shouldn't happen unless list of advertised channels to
5826 * mac80211 has been changed.
5827 */
5828 WARN_ON_ONCE(1);
5829 dev_kfree_skb(skb);
5830 goto exit;
5831 }
5832
5833 if (rx_ev.phy_mode == MODE_11B &&
5834 (status->band == NL80211_BAND_5GHZ || status->band == NL80211_BAND_6GHZ))
5835 ath12k_dbg(ab, ATH12K_DBG_WMI,
5836 "wmi mgmt rx 11b (CCK) on 5/6GHz, band = %d\n", status->band);
5837
5838 sband = &ar->mac.sbands[status->band];
5839
5840 if (status->band != NL80211_BAND_6GHZ)
5841 status->freq = ieee80211_channel_to_frequency(rx_ev.channel,
5842 status->band);
5843
5844 status->signal = rx_ev.snr + ATH12K_DEFAULT_NOISE_FLOOR;
5845 status->rate_idx = ath12k_mac_bitrate_to_idx(sband, rx_ev.rate / 100);
5846
5847 hdr = (struct ieee80211_hdr *)skb->data;
5848 fc = le16_to_cpu(hdr->frame_control);
5849
5850 /* Firmware is guaranteed to report all essential management frames via
5851 * WMI while it can deliver some extra via HTT. Since there can be
5852 * duplicates split the reporting wrt monitor/sniffing.
5853 */
5854 status->flag |= RX_FLAG_SKIP_MONITOR;
5855
5856 /* In case of PMF, FW delivers decrypted frames with Protected Bit set
5857 * including group privacy action frames.
5858 */
5859 if (ieee80211_has_protected(hdr->frame_control)) {
5860 status->flag |= RX_FLAG_DECRYPTED;
5861
5862 if (!ieee80211_is_robust_mgmt_frame(skb)) {
5863 status->flag |= RX_FLAG_IV_STRIPPED |
5864 RX_FLAG_MMIC_STRIPPED;
5865 hdr->frame_control = __cpu_to_le16(fc &
5866 ~IEEE80211_FCTL_PROTECTED);
5867 }
5868 }
5869
5870 /* TODO: Pending handle beacon implementation
5871 *if (ieee80211_is_beacon(hdr->frame_control))
5872 * ath12k_mac_handle_beacon(ar, skb);
5873 */
5874
5875 ath12k_dbg(ab, ATH12K_DBG_MGMT,
5876 "event mgmt rx skb %pK len %d ftype %02x stype %02x\n",
5877 skb, skb->len,
5878 fc & IEEE80211_FCTL_FTYPE, fc & IEEE80211_FCTL_STYPE);
5879
5880 ath12k_dbg(ab, ATH12K_DBG_MGMT,
5881 "event mgmt rx freq %d band %d snr %d, rate_idx %d\n",
5882 status->freq, status->band, status->signal,
5883 status->rate_idx);
5884
5885 ieee80211_rx_ni(ar->hw, skb);
5886
5887 exit:
5888 rcu_read_unlock();
5889 }
5890
ath12k_mgmt_tx_compl_event(struct ath12k_base * ab,struct sk_buff * skb)5891 static void ath12k_mgmt_tx_compl_event(struct ath12k_base *ab, struct sk_buff *skb)
5892 {
5893 struct wmi_mgmt_tx_compl_event tx_compl_param = {0};
5894 struct ath12k *ar;
5895
5896 if (ath12k_pull_mgmt_tx_compl_param_tlv(ab, skb, &tx_compl_param) != 0) {
5897 ath12k_warn(ab, "failed to extract mgmt tx compl event");
5898 return;
5899 }
5900
5901 rcu_read_lock();
5902 ar = ath12k_mac_get_ar_by_pdev_id(ab, le32_to_cpu(tx_compl_param.pdev_id));
5903 if (!ar) {
5904 ath12k_warn(ab, "invalid pdev id %d in mgmt_tx_compl_event\n",
5905 tx_compl_param.pdev_id);
5906 goto exit;
5907 }
5908
5909 wmi_process_mgmt_tx_comp(ar, le32_to_cpu(tx_compl_param.desc_id),
5910 le32_to_cpu(tx_compl_param.status));
5911
5912 ath12k_dbg(ab, ATH12K_DBG_MGMT,
5913 "mgmt tx compl ev pdev_id %d, desc_id %d, status %d",
5914 tx_compl_param.pdev_id, tx_compl_param.desc_id,
5915 tx_compl_param.status);
5916
5917 exit:
5918 rcu_read_unlock();
5919 }
5920
ath12k_get_ar_on_scan_abort(struct ath12k_base * ab,u32 vdev_id)5921 static struct ath12k *ath12k_get_ar_on_scan_abort(struct ath12k_base *ab,
5922 u32 vdev_id)
5923 {
5924 int i;
5925 struct ath12k_pdev *pdev;
5926 struct ath12k *ar;
5927
5928 for (i = 0; i < ab->num_radios; i++) {
5929 pdev = rcu_dereference(ab->pdevs_active[i]);
5930 if (pdev && pdev->ar) {
5931 ar = pdev->ar;
5932
5933 spin_lock_bh(&ar->data_lock);
5934 if (ar->scan.state == ATH12K_SCAN_ABORTING &&
5935 ar->scan.vdev_id == vdev_id) {
5936 spin_unlock_bh(&ar->data_lock);
5937 return ar;
5938 }
5939 spin_unlock_bh(&ar->data_lock);
5940 }
5941 }
5942 return NULL;
5943 }
5944
ath12k_scan_event(struct ath12k_base * ab,struct sk_buff * skb)5945 static void ath12k_scan_event(struct ath12k_base *ab, struct sk_buff *skb)
5946 {
5947 struct ath12k *ar;
5948 struct wmi_scan_event scan_ev = {0};
5949
5950 if (ath12k_pull_scan_ev(ab, skb, &scan_ev) != 0) {
5951 ath12k_warn(ab, "failed to extract scan event");
5952 return;
5953 }
5954
5955 rcu_read_lock();
5956
5957 /* In case the scan was cancelled, ex. during interface teardown,
5958 * the interface will not be found in active interfaces.
5959 * Rather, in such scenarios, iterate over the active pdev's to
5960 * search 'ar' if the corresponding 'ar' scan is ABORTING and the
5961 * aborting scan's vdev id matches this event info.
5962 */
5963 if (le32_to_cpu(scan_ev.event_type) == WMI_SCAN_EVENT_COMPLETED &&
5964 le32_to_cpu(scan_ev.reason) == WMI_SCAN_REASON_CANCELLED)
5965 ar = ath12k_get_ar_on_scan_abort(ab, le32_to_cpu(scan_ev.vdev_id));
5966 else
5967 ar = ath12k_mac_get_ar_by_vdev_id(ab, le32_to_cpu(scan_ev.vdev_id));
5968
5969 if (!ar) {
5970 ath12k_warn(ab, "Received scan event for unknown vdev");
5971 rcu_read_unlock();
5972 return;
5973 }
5974
5975 spin_lock_bh(&ar->data_lock);
5976
5977 ath12k_dbg(ab, ATH12K_DBG_WMI,
5978 "scan event %s type %d reason %d freq %d req_id %d scan_id %d vdev_id %d state %s (%d)\n",
5979 ath12k_wmi_event_scan_type_str(le32_to_cpu(scan_ev.event_type),
5980 le32_to_cpu(scan_ev.reason)),
5981 le32_to_cpu(scan_ev.event_type),
5982 le32_to_cpu(scan_ev.reason),
5983 le32_to_cpu(scan_ev.channel_freq),
5984 le32_to_cpu(scan_ev.scan_req_id),
5985 le32_to_cpu(scan_ev.scan_id),
5986 le32_to_cpu(scan_ev.vdev_id),
5987 ath12k_scan_state_str(ar->scan.state), ar->scan.state);
5988
5989 switch (le32_to_cpu(scan_ev.event_type)) {
5990 case WMI_SCAN_EVENT_STARTED:
5991 ath12k_wmi_event_scan_started(ar);
5992 break;
5993 case WMI_SCAN_EVENT_COMPLETED:
5994 ath12k_wmi_event_scan_completed(ar);
5995 break;
5996 case WMI_SCAN_EVENT_BSS_CHANNEL:
5997 ath12k_wmi_event_scan_bss_chan(ar);
5998 break;
5999 case WMI_SCAN_EVENT_FOREIGN_CHAN:
6000 ath12k_wmi_event_scan_foreign_chan(ar, le32_to_cpu(scan_ev.channel_freq));
6001 break;
6002 case WMI_SCAN_EVENT_START_FAILED:
6003 ath12k_warn(ab, "received scan start failure event\n");
6004 ath12k_wmi_event_scan_start_failed(ar);
6005 break;
6006 case WMI_SCAN_EVENT_DEQUEUED:
6007 __ath12k_mac_scan_finish(ar);
6008 break;
6009 case WMI_SCAN_EVENT_PREEMPTED:
6010 case WMI_SCAN_EVENT_RESTARTED:
6011 case WMI_SCAN_EVENT_FOREIGN_CHAN_EXIT:
6012 default:
6013 break;
6014 }
6015
6016 spin_unlock_bh(&ar->data_lock);
6017
6018 rcu_read_unlock();
6019 }
6020
ath12k_peer_sta_kickout_event(struct ath12k_base * ab,struct sk_buff * skb)6021 static void ath12k_peer_sta_kickout_event(struct ath12k_base *ab, struct sk_buff *skb)
6022 {
6023 struct wmi_peer_sta_kickout_arg arg = {};
6024 struct ieee80211_sta *sta;
6025 struct ath12k_peer *peer;
6026 struct ath12k *ar;
6027
6028 if (ath12k_pull_peer_sta_kickout_ev(ab, skb, &arg) != 0) {
6029 ath12k_warn(ab, "failed to extract peer sta kickout event");
6030 return;
6031 }
6032
6033 rcu_read_lock();
6034
6035 spin_lock_bh(&ab->base_lock);
6036
6037 peer = ath12k_peer_find_by_addr(ab, arg.mac_addr);
6038
6039 if (!peer) {
6040 ath12k_warn(ab, "peer not found %pM\n",
6041 arg.mac_addr);
6042 goto exit;
6043 }
6044
6045 ar = ath12k_mac_get_ar_by_vdev_id(ab, peer->vdev_id);
6046 if (!ar) {
6047 ath12k_warn(ab, "invalid vdev id in peer sta kickout ev %d",
6048 peer->vdev_id);
6049 goto exit;
6050 }
6051
6052 sta = ieee80211_find_sta_by_ifaddr(ar->hw,
6053 arg.mac_addr, NULL);
6054 if (!sta) {
6055 ath12k_warn(ab, "Spurious quick kickout for STA %pM\n",
6056 arg.mac_addr);
6057 goto exit;
6058 }
6059
6060 ath12k_dbg(ab, ATH12K_DBG_WMI, "peer sta kickout event %pM",
6061 arg.mac_addr);
6062
6063 ieee80211_report_low_ack(sta, 10);
6064
6065 exit:
6066 spin_unlock_bh(&ab->base_lock);
6067 rcu_read_unlock();
6068 }
6069
ath12k_roam_event(struct ath12k_base * ab,struct sk_buff * skb)6070 static void ath12k_roam_event(struct ath12k_base *ab, struct sk_buff *skb)
6071 {
6072 struct wmi_roam_event roam_ev = {};
6073 struct ath12k *ar;
6074
6075 if (ath12k_pull_roam_ev(ab, skb, &roam_ev) != 0) {
6076 ath12k_warn(ab, "failed to extract roam event");
6077 return;
6078 }
6079
6080 ath12k_dbg(ab, ATH12K_DBG_WMI,
6081 "wmi roam event vdev %u reason 0x%08x rssi %d\n",
6082 roam_ev.vdev_id, roam_ev.reason, roam_ev.rssi);
6083
6084 rcu_read_lock();
6085 ar = ath12k_mac_get_ar_by_vdev_id(ab, le32_to_cpu(roam_ev.vdev_id));
6086 if (!ar) {
6087 ath12k_warn(ab, "invalid vdev id in roam ev %d",
6088 roam_ev.vdev_id);
6089 rcu_read_unlock();
6090 return;
6091 }
6092
6093 if (le32_to_cpu(roam_ev.reason) >= WMI_ROAM_REASON_MAX)
6094 ath12k_warn(ab, "ignoring unknown roam event reason %d on vdev %i\n",
6095 roam_ev.reason, roam_ev.vdev_id);
6096
6097 switch (le32_to_cpu(roam_ev.reason)) {
6098 case WMI_ROAM_REASON_BEACON_MISS:
6099 /* TODO: Pending beacon miss and connection_loss_work
6100 * implementation
6101 * ath12k_mac_handle_beacon_miss(ar, vdev_id);
6102 */
6103 break;
6104 case WMI_ROAM_REASON_BETTER_AP:
6105 case WMI_ROAM_REASON_LOW_RSSI:
6106 case WMI_ROAM_REASON_SUITABLE_AP_FOUND:
6107 case WMI_ROAM_REASON_HO_FAILED:
6108 ath12k_warn(ab, "ignoring not implemented roam event reason %d on vdev %i\n",
6109 roam_ev.reason, roam_ev.vdev_id);
6110 break;
6111 }
6112
6113 rcu_read_unlock();
6114 }
6115
ath12k_chan_info_event(struct ath12k_base * ab,struct sk_buff * skb)6116 static void ath12k_chan_info_event(struct ath12k_base *ab, struct sk_buff *skb)
6117 {
6118 struct wmi_chan_info_event ch_info_ev = {0};
6119 struct ath12k *ar;
6120 struct survey_info *survey;
6121 int idx;
6122 /* HW channel counters frequency value in hertz */
6123 u32 cc_freq_hz = ab->cc_freq_hz;
6124
6125 if (ath12k_pull_chan_info_ev(ab, skb->data, skb->len, &ch_info_ev) != 0) {
6126 ath12k_warn(ab, "failed to extract chan info event");
6127 return;
6128 }
6129
6130 ath12k_dbg(ab, ATH12K_DBG_WMI,
6131 "chan info vdev_id %d err_code %d freq %d cmd_flags %d noise_floor %d rx_clear_count %d cycle_count %d mac_clk_mhz %d\n",
6132 ch_info_ev.vdev_id, ch_info_ev.err_code, ch_info_ev.freq,
6133 ch_info_ev.cmd_flags, ch_info_ev.noise_floor,
6134 ch_info_ev.rx_clear_count, ch_info_ev.cycle_count,
6135 ch_info_ev.mac_clk_mhz);
6136
6137 if (le32_to_cpu(ch_info_ev.cmd_flags) == WMI_CHAN_INFO_END_RESP) {
6138 ath12k_dbg(ab, ATH12K_DBG_WMI, "chan info report completed\n");
6139 return;
6140 }
6141
6142 rcu_read_lock();
6143 ar = ath12k_mac_get_ar_by_vdev_id(ab, le32_to_cpu(ch_info_ev.vdev_id));
6144 if (!ar) {
6145 ath12k_warn(ab, "invalid vdev id in chan info ev %d",
6146 ch_info_ev.vdev_id);
6147 rcu_read_unlock();
6148 return;
6149 }
6150 spin_lock_bh(&ar->data_lock);
6151
6152 switch (ar->scan.state) {
6153 case ATH12K_SCAN_IDLE:
6154 case ATH12K_SCAN_STARTING:
6155 ath12k_warn(ab, "received chan info event without a scan request, ignoring\n");
6156 goto exit;
6157 case ATH12K_SCAN_RUNNING:
6158 case ATH12K_SCAN_ABORTING:
6159 break;
6160 }
6161
6162 idx = freq_to_idx(ar, le32_to_cpu(ch_info_ev.freq));
6163 if (idx >= ARRAY_SIZE(ar->survey)) {
6164 ath12k_warn(ab, "chan info: invalid frequency %d (idx %d out of bounds)\n",
6165 ch_info_ev.freq, idx);
6166 goto exit;
6167 }
6168
6169 /* If FW provides MAC clock frequency in Mhz, overriding the initialized
6170 * HW channel counters frequency value
6171 */
6172 if (ch_info_ev.mac_clk_mhz)
6173 cc_freq_hz = (le32_to_cpu(ch_info_ev.mac_clk_mhz) * 1000);
6174
6175 if (ch_info_ev.cmd_flags == WMI_CHAN_INFO_START_RESP) {
6176 survey = &ar->survey[idx];
6177 memset(survey, 0, sizeof(*survey));
6178 survey->noise = le32_to_cpu(ch_info_ev.noise_floor);
6179 survey->filled = SURVEY_INFO_NOISE_DBM | SURVEY_INFO_TIME |
6180 SURVEY_INFO_TIME_BUSY;
6181 survey->time = div_u64(le32_to_cpu(ch_info_ev.cycle_count), cc_freq_hz);
6182 survey->time_busy = div_u64(le32_to_cpu(ch_info_ev.rx_clear_count),
6183 cc_freq_hz);
6184 }
6185 exit:
6186 spin_unlock_bh(&ar->data_lock);
6187 rcu_read_unlock();
6188 }
6189
6190 static void
ath12k_pdev_bss_chan_info_event(struct ath12k_base * ab,struct sk_buff * skb)6191 ath12k_pdev_bss_chan_info_event(struct ath12k_base *ab, struct sk_buff *skb)
6192 {
6193 struct wmi_pdev_bss_chan_info_event bss_ch_info_ev = {};
6194 struct survey_info *survey;
6195 struct ath12k *ar;
6196 u32 cc_freq_hz = ab->cc_freq_hz;
6197 u64 busy, total, tx, rx, rx_bss;
6198 int idx;
6199
6200 if (ath12k_pull_pdev_bss_chan_info_ev(ab, skb, &bss_ch_info_ev) != 0) {
6201 ath12k_warn(ab, "failed to extract pdev bss chan info event");
6202 return;
6203 }
6204
6205 busy = (u64)(le32_to_cpu(bss_ch_info_ev.rx_clear_count_high)) << 32 |
6206 le32_to_cpu(bss_ch_info_ev.rx_clear_count_low);
6207
6208 total = (u64)(le32_to_cpu(bss_ch_info_ev.cycle_count_high)) << 32 |
6209 le32_to_cpu(bss_ch_info_ev.cycle_count_low);
6210
6211 tx = (u64)(le32_to_cpu(bss_ch_info_ev.tx_cycle_count_high)) << 32 |
6212 le32_to_cpu(bss_ch_info_ev.tx_cycle_count_low);
6213
6214 rx = (u64)(le32_to_cpu(bss_ch_info_ev.rx_cycle_count_high)) << 32 |
6215 le32_to_cpu(bss_ch_info_ev.rx_cycle_count_low);
6216
6217 rx_bss = (u64)(le32_to_cpu(bss_ch_info_ev.rx_bss_cycle_count_high)) << 32 |
6218 le32_to_cpu(bss_ch_info_ev.rx_bss_cycle_count_low);
6219
6220 ath12k_dbg(ab, ATH12K_DBG_WMI,
6221 "pdev bss chan info:\n pdev_id: %d freq: %d noise: %d cycle: busy %llu total %llu tx %llu rx %llu rx_bss %llu\n",
6222 bss_ch_info_ev.pdev_id, bss_ch_info_ev.freq,
6223 bss_ch_info_ev.noise_floor, busy, total,
6224 tx, rx, rx_bss);
6225
6226 rcu_read_lock();
6227 ar = ath12k_mac_get_ar_by_pdev_id(ab, le32_to_cpu(bss_ch_info_ev.pdev_id));
6228
6229 if (!ar) {
6230 ath12k_warn(ab, "invalid pdev id %d in bss_chan_info event\n",
6231 bss_ch_info_ev.pdev_id);
6232 rcu_read_unlock();
6233 return;
6234 }
6235
6236 spin_lock_bh(&ar->data_lock);
6237 idx = freq_to_idx(ar, le32_to_cpu(bss_ch_info_ev.freq));
6238 if (idx >= ARRAY_SIZE(ar->survey)) {
6239 ath12k_warn(ab, "bss chan info: invalid frequency %d (idx %d out of bounds)\n",
6240 bss_ch_info_ev.freq, idx);
6241 goto exit;
6242 }
6243
6244 survey = &ar->survey[idx];
6245
6246 survey->noise = le32_to_cpu(bss_ch_info_ev.noise_floor);
6247 survey->time = div_u64(total, cc_freq_hz);
6248 survey->time_busy = div_u64(busy, cc_freq_hz);
6249 survey->time_rx = div_u64(rx_bss, cc_freq_hz);
6250 survey->time_tx = div_u64(tx, cc_freq_hz);
6251 survey->filled |= (SURVEY_INFO_NOISE_DBM |
6252 SURVEY_INFO_TIME |
6253 SURVEY_INFO_TIME_BUSY |
6254 SURVEY_INFO_TIME_RX |
6255 SURVEY_INFO_TIME_TX);
6256 exit:
6257 spin_unlock_bh(&ar->data_lock);
6258 complete(&ar->bss_survey_done);
6259
6260 rcu_read_unlock();
6261 }
6262
ath12k_vdev_install_key_compl_event(struct ath12k_base * ab,struct sk_buff * skb)6263 static void ath12k_vdev_install_key_compl_event(struct ath12k_base *ab,
6264 struct sk_buff *skb)
6265 {
6266 struct wmi_vdev_install_key_complete_arg install_key_compl = {0};
6267 struct ath12k *ar;
6268
6269 if (ath12k_pull_vdev_install_key_compl_ev(ab, skb, &install_key_compl) != 0) {
6270 ath12k_warn(ab, "failed to extract install key compl event");
6271 return;
6272 }
6273
6274 ath12k_dbg(ab, ATH12K_DBG_WMI,
6275 "vdev install key ev idx %d flags %08x macaddr %pM status %d\n",
6276 install_key_compl.key_idx, install_key_compl.key_flags,
6277 install_key_compl.macaddr, install_key_compl.status);
6278
6279 rcu_read_lock();
6280 ar = ath12k_mac_get_ar_by_vdev_id(ab, install_key_compl.vdev_id);
6281 if (!ar) {
6282 ath12k_warn(ab, "invalid vdev id in install key compl ev %d",
6283 install_key_compl.vdev_id);
6284 rcu_read_unlock();
6285 return;
6286 }
6287
6288 ar->install_key_status = 0;
6289
6290 if (install_key_compl.status != WMI_VDEV_INSTALL_KEY_COMPL_STATUS_SUCCESS) {
6291 ath12k_warn(ab, "install key failed for %pM status %d\n",
6292 install_key_compl.macaddr, install_key_compl.status);
6293 ar->install_key_status = install_key_compl.status;
6294 }
6295
6296 complete(&ar->install_key_done);
6297 rcu_read_unlock();
6298 }
6299
ath12k_wmi_tlv_services_parser(struct ath12k_base * ab,u16 tag,u16 len,const void * ptr,void * data)6300 static int ath12k_wmi_tlv_services_parser(struct ath12k_base *ab,
6301 u16 tag, u16 len,
6302 const void *ptr,
6303 void *data)
6304 {
6305 const struct wmi_service_available_event *ev;
6306 u32 *wmi_ext2_service_bitmap;
6307 int i, j;
6308 u16 expected_len;
6309
6310 expected_len = WMI_SERVICE_SEGMENT_BM_SIZE32 * sizeof(u32);
6311 if (len < expected_len) {
6312 ath12k_warn(ab, "invalid length %d for the WMI services available tag 0x%x\n",
6313 len, tag);
6314 return -EINVAL;
6315 }
6316
6317 switch (tag) {
6318 case WMI_TAG_SERVICE_AVAILABLE_EVENT:
6319 ev = (struct wmi_service_available_event *)ptr;
6320 for (i = 0, j = WMI_MAX_SERVICE;
6321 i < WMI_SERVICE_SEGMENT_BM_SIZE32 && j < WMI_MAX_EXT_SERVICE;
6322 i++) {
6323 do {
6324 if (le32_to_cpu(ev->wmi_service_segment_bitmap[i]) &
6325 BIT(j % WMI_AVAIL_SERVICE_BITS_IN_SIZE32))
6326 set_bit(j, ab->wmi_ab.svc_map);
6327 } while (++j % WMI_AVAIL_SERVICE_BITS_IN_SIZE32);
6328 }
6329
6330 ath12k_dbg(ab, ATH12K_DBG_WMI,
6331 "wmi_ext_service_bitmap 0x%x 0x%x 0x%x 0x%x",
6332 ev->wmi_service_segment_bitmap[0],
6333 ev->wmi_service_segment_bitmap[1],
6334 ev->wmi_service_segment_bitmap[2],
6335 ev->wmi_service_segment_bitmap[3]);
6336 break;
6337 case WMI_TAG_ARRAY_UINT32:
6338 wmi_ext2_service_bitmap = (u32 *)ptr;
6339 for (i = 0, j = WMI_MAX_EXT_SERVICE;
6340 i < WMI_SERVICE_SEGMENT_BM_SIZE32 && j < WMI_MAX_EXT2_SERVICE;
6341 i++) {
6342 do {
6343 if (wmi_ext2_service_bitmap[i] &
6344 BIT(j % WMI_AVAIL_SERVICE_BITS_IN_SIZE32))
6345 set_bit(j, ab->wmi_ab.svc_map);
6346 } while (++j % WMI_AVAIL_SERVICE_BITS_IN_SIZE32);
6347 }
6348
6349 ath12k_dbg(ab, ATH12K_DBG_WMI,
6350 "wmi_ext2_service_bitmap 0x%04x 0x%04x 0x%04x 0x%04x",
6351 wmi_ext2_service_bitmap[0], wmi_ext2_service_bitmap[1],
6352 wmi_ext2_service_bitmap[2], wmi_ext2_service_bitmap[3]);
6353 break;
6354 }
6355 return 0;
6356 }
6357
ath12k_service_available_event(struct ath12k_base * ab,struct sk_buff * skb)6358 static int ath12k_service_available_event(struct ath12k_base *ab, struct sk_buff *skb)
6359 {
6360 int ret;
6361
6362 ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len,
6363 ath12k_wmi_tlv_services_parser,
6364 NULL);
6365 return ret;
6366 }
6367
ath12k_peer_assoc_conf_event(struct ath12k_base * ab,struct sk_buff * skb)6368 static void ath12k_peer_assoc_conf_event(struct ath12k_base *ab, struct sk_buff *skb)
6369 {
6370 struct wmi_peer_assoc_conf_arg peer_assoc_conf = {0};
6371 struct ath12k *ar;
6372
6373 if (ath12k_pull_peer_assoc_conf_ev(ab, skb, &peer_assoc_conf) != 0) {
6374 ath12k_warn(ab, "failed to extract peer assoc conf event");
6375 return;
6376 }
6377
6378 ath12k_dbg(ab, ATH12K_DBG_WMI,
6379 "peer assoc conf ev vdev id %d macaddr %pM\n",
6380 peer_assoc_conf.vdev_id, peer_assoc_conf.macaddr);
6381
6382 rcu_read_lock();
6383 ar = ath12k_mac_get_ar_by_vdev_id(ab, peer_assoc_conf.vdev_id);
6384
6385 if (!ar) {
6386 ath12k_warn(ab, "invalid vdev id in peer assoc conf ev %d",
6387 peer_assoc_conf.vdev_id);
6388 rcu_read_unlock();
6389 return;
6390 }
6391
6392 complete(&ar->peer_assoc_done);
6393 rcu_read_unlock();
6394 }
6395
ath12k_update_stats_event(struct ath12k_base * ab,struct sk_buff * skb)6396 static void ath12k_update_stats_event(struct ath12k_base *ab, struct sk_buff *skb)
6397 {
6398 }
6399
6400 /* PDEV_CTL_FAILSAFE_CHECK_EVENT is received from FW when the frequency scanned
6401 * is not part of BDF CTL(Conformance test limits) table entries.
6402 */
ath12k_pdev_ctl_failsafe_check_event(struct ath12k_base * ab,struct sk_buff * skb)6403 static void ath12k_pdev_ctl_failsafe_check_event(struct ath12k_base *ab,
6404 struct sk_buff *skb)
6405 {
6406 const void **tb;
6407 const struct wmi_pdev_ctl_failsafe_chk_event *ev;
6408 int ret;
6409
6410 tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC);
6411 if (IS_ERR(tb)) {
6412 ret = PTR_ERR(tb);
6413 ath12k_warn(ab, "failed to parse tlv: %d\n", ret);
6414 return;
6415 }
6416
6417 ev = tb[WMI_TAG_PDEV_CTL_FAILSAFE_CHECK_EVENT];
6418 if (!ev) {
6419 ath12k_warn(ab, "failed to fetch pdev ctl failsafe check ev");
6420 kfree(tb);
6421 return;
6422 }
6423
6424 ath12k_dbg(ab, ATH12K_DBG_WMI,
6425 "pdev ctl failsafe check ev status %d\n",
6426 ev->ctl_failsafe_status);
6427
6428 /* If ctl_failsafe_status is set to 1 FW will max out the Transmit power
6429 * to 10 dBm else the CTL power entry in the BDF would be picked up.
6430 */
6431 if (ev->ctl_failsafe_status != 0)
6432 ath12k_warn(ab, "pdev ctl failsafe failure status %d",
6433 ev->ctl_failsafe_status);
6434
6435 kfree(tb);
6436 }
6437
6438 static void
ath12k_wmi_process_csa_switch_count_event(struct ath12k_base * ab,const struct ath12k_wmi_pdev_csa_event * ev,const u32 * vdev_ids)6439 ath12k_wmi_process_csa_switch_count_event(struct ath12k_base *ab,
6440 const struct ath12k_wmi_pdev_csa_event *ev,
6441 const u32 *vdev_ids)
6442 {
6443 int i;
6444 struct ath12k_vif *arvif;
6445
6446 /* Finish CSA once the switch count becomes NULL */
6447 if (ev->current_switch_count)
6448 return;
6449
6450 rcu_read_lock();
6451 for (i = 0; i < le32_to_cpu(ev->num_vdevs); i++) {
6452 arvif = ath12k_mac_get_arvif_by_vdev_id(ab, vdev_ids[i]);
6453
6454 if (!arvif) {
6455 ath12k_warn(ab, "Recvd csa status for unknown vdev %d",
6456 vdev_ids[i]);
6457 continue;
6458 }
6459
6460 if (arvif->is_up && arvif->vif->bss_conf.csa_active)
6461 ieee80211_csa_finish(arvif->vif);
6462 }
6463 rcu_read_unlock();
6464 }
6465
6466 static void
ath12k_wmi_pdev_csa_switch_count_status_event(struct ath12k_base * ab,struct sk_buff * skb)6467 ath12k_wmi_pdev_csa_switch_count_status_event(struct ath12k_base *ab,
6468 struct sk_buff *skb)
6469 {
6470 const void **tb;
6471 const struct ath12k_wmi_pdev_csa_event *ev;
6472 const u32 *vdev_ids;
6473 int ret;
6474
6475 tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC);
6476 if (IS_ERR(tb)) {
6477 ret = PTR_ERR(tb);
6478 ath12k_warn(ab, "failed to parse tlv: %d\n", ret);
6479 return;
6480 }
6481
6482 ev = tb[WMI_TAG_PDEV_CSA_SWITCH_COUNT_STATUS_EVENT];
6483 vdev_ids = tb[WMI_TAG_ARRAY_UINT32];
6484
6485 if (!ev || !vdev_ids) {
6486 ath12k_warn(ab, "failed to fetch pdev csa switch count ev");
6487 kfree(tb);
6488 return;
6489 }
6490
6491 ath12k_dbg(ab, ATH12K_DBG_WMI,
6492 "pdev csa switch count %d for pdev %d, num_vdevs %d",
6493 ev->current_switch_count, ev->pdev_id,
6494 ev->num_vdevs);
6495
6496 ath12k_wmi_process_csa_switch_count_event(ab, ev, vdev_ids);
6497
6498 kfree(tb);
6499 }
6500
6501 static void
ath12k_wmi_pdev_dfs_radar_detected_event(struct ath12k_base * ab,struct sk_buff * skb)6502 ath12k_wmi_pdev_dfs_radar_detected_event(struct ath12k_base *ab, struct sk_buff *skb)
6503 {
6504 const void **tb;
6505 const struct ath12k_wmi_pdev_radar_event *ev;
6506 struct ath12k *ar;
6507 int ret;
6508
6509 tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC);
6510 if (IS_ERR(tb)) {
6511 ret = PTR_ERR(tb);
6512 ath12k_warn(ab, "failed to parse tlv: %d\n", ret);
6513 return;
6514 }
6515
6516 ev = tb[WMI_TAG_PDEV_DFS_RADAR_DETECTION_EVENT];
6517
6518 if (!ev) {
6519 ath12k_warn(ab, "failed to fetch pdev dfs radar detected ev");
6520 kfree(tb);
6521 return;
6522 }
6523
6524 ath12k_dbg(ab, ATH12K_DBG_WMI,
6525 "pdev dfs radar detected on pdev %d, detection mode %d, chan freq %d, chan_width %d, detector id %d, seg id %d, timestamp %d, chirp %d, freq offset %d, sidx %d",
6526 ev->pdev_id, ev->detection_mode, ev->chan_freq, ev->chan_width,
6527 ev->detector_id, ev->segment_id, ev->timestamp, ev->is_chirp,
6528 ev->freq_offset, ev->sidx);
6529
6530 rcu_read_lock();
6531
6532 ar = ath12k_mac_get_ar_by_pdev_id(ab, le32_to_cpu(ev->pdev_id));
6533
6534 if (!ar) {
6535 ath12k_warn(ab, "radar detected in invalid pdev %d\n",
6536 ev->pdev_id);
6537 goto exit;
6538 }
6539
6540 ath12k_dbg(ar->ab, ATH12K_DBG_REG, "DFS Radar Detected in pdev %d\n",
6541 ev->pdev_id);
6542
6543 if (ar->dfs_block_radar_events)
6544 ath12k_info(ab, "DFS Radar detected, but ignored as requested\n");
6545 else
6546 ieee80211_radar_detected(ar->hw);
6547
6548 exit:
6549 rcu_read_unlock();
6550
6551 kfree(tb);
6552 }
6553
6554 static void
ath12k_wmi_pdev_temperature_event(struct ath12k_base * ab,struct sk_buff * skb)6555 ath12k_wmi_pdev_temperature_event(struct ath12k_base *ab,
6556 struct sk_buff *skb)
6557 {
6558 struct ath12k *ar;
6559 struct wmi_pdev_temperature_event ev = {0};
6560
6561 if (ath12k_pull_pdev_temp_ev(ab, skb->data, skb->len, &ev) != 0) {
6562 ath12k_warn(ab, "failed to extract pdev temperature event");
6563 return;
6564 }
6565
6566 ath12k_dbg(ab, ATH12K_DBG_WMI,
6567 "pdev temperature ev temp %d pdev_id %d\n", ev.temp, ev.pdev_id);
6568
6569 rcu_read_lock();
6570
6571 ar = ath12k_mac_get_ar_by_pdev_id(ab, le32_to_cpu(ev.pdev_id));
6572 if (!ar) {
6573 ath12k_warn(ab, "invalid pdev id in pdev temperature ev %d", ev.pdev_id);
6574 goto exit;
6575 }
6576
6577 exit:
6578 rcu_read_unlock();
6579 }
6580
ath12k_fils_discovery_event(struct ath12k_base * ab,struct sk_buff * skb)6581 static void ath12k_fils_discovery_event(struct ath12k_base *ab,
6582 struct sk_buff *skb)
6583 {
6584 const void **tb;
6585 const struct wmi_fils_discovery_event *ev;
6586 int ret;
6587
6588 tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC);
6589 if (IS_ERR(tb)) {
6590 ret = PTR_ERR(tb);
6591 ath12k_warn(ab,
6592 "failed to parse FILS discovery event tlv %d\n",
6593 ret);
6594 return;
6595 }
6596
6597 ev = tb[WMI_TAG_HOST_SWFDA_EVENT];
6598 if (!ev) {
6599 ath12k_warn(ab, "failed to fetch FILS discovery event\n");
6600 kfree(tb);
6601 return;
6602 }
6603
6604 ath12k_warn(ab,
6605 "FILS discovery frame expected from host for vdev_id: %u, transmission scheduled at %u, next TBTT: %u\n",
6606 ev->vdev_id, ev->fils_tt, ev->tbtt);
6607
6608 kfree(tb);
6609 }
6610
ath12k_probe_resp_tx_status_event(struct ath12k_base * ab,struct sk_buff * skb)6611 static void ath12k_probe_resp_tx_status_event(struct ath12k_base *ab,
6612 struct sk_buff *skb)
6613 {
6614 const void **tb;
6615 const struct wmi_probe_resp_tx_status_event *ev;
6616 int ret;
6617
6618 tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC);
6619 if (IS_ERR(tb)) {
6620 ret = PTR_ERR(tb);
6621 ath12k_warn(ab,
6622 "failed to parse probe response transmission status event tlv: %d\n",
6623 ret);
6624 return;
6625 }
6626
6627 ev = tb[WMI_TAG_OFFLOAD_PRB_RSP_TX_STATUS_EVENT];
6628 if (!ev) {
6629 ath12k_warn(ab,
6630 "failed to fetch probe response transmission status event");
6631 kfree(tb);
6632 return;
6633 }
6634
6635 if (ev->tx_status)
6636 ath12k_warn(ab,
6637 "Probe response transmission failed for vdev_id %u, status %u\n",
6638 ev->vdev_id, ev->tx_status);
6639
6640 kfree(tb);
6641 }
6642
ath12k_wmi_op_rx(struct ath12k_base * ab,struct sk_buff * skb)6643 static void ath12k_wmi_op_rx(struct ath12k_base *ab, struct sk_buff *skb)
6644 {
6645 struct wmi_cmd_hdr *cmd_hdr;
6646 enum wmi_tlv_event_id id;
6647
6648 cmd_hdr = (struct wmi_cmd_hdr *)skb->data;
6649 id = le32_get_bits(cmd_hdr->cmd_id, WMI_CMD_HDR_CMD_ID);
6650
6651 if (!skb_pull(skb, sizeof(struct wmi_cmd_hdr)))
6652 goto out;
6653
6654 switch (id) {
6655 /* Process all the WMI events here */
6656 case WMI_SERVICE_READY_EVENTID:
6657 ath12k_service_ready_event(ab, skb);
6658 break;
6659 case WMI_SERVICE_READY_EXT_EVENTID:
6660 ath12k_service_ready_ext_event(ab, skb);
6661 break;
6662 case WMI_SERVICE_READY_EXT2_EVENTID:
6663 ath12k_service_ready_ext2_event(ab, skb);
6664 break;
6665 case WMI_REG_CHAN_LIST_CC_EXT_EVENTID:
6666 ath12k_reg_chan_list_event(ab, skb);
6667 break;
6668 case WMI_READY_EVENTID:
6669 ath12k_ready_event(ab, skb);
6670 break;
6671 case WMI_PEER_DELETE_RESP_EVENTID:
6672 ath12k_peer_delete_resp_event(ab, skb);
6673 break;
6674 case WMI_VDEV_START_RESP_EVENTID:
6675 ath12k_vdev_start_resp_event(ab, skb);
6676 break;
6677 case WMI_OFFLOAD_BCN_TX_STATUS_EVENTID:
6678 ath12k_bcn_tx_status_event(ab, skb);
6679 break;
6680 case WMI_VDEV_STOPPED_EVENTID:
6681 ath12k_vdev_stopped_event(ab, skb);
6682 break;
6683 case WMI_MGMT_RX_EVENTID:
6684 ath12k_mgmt_rx_event(ab, skb);
6685 /* mgmt_rx_event() owns the skb now! */
6686 return;
6687 case WMI_MGMT_TX_COMPLETION_EVENTID:
6688 ath12k_mgmt_tx_compl_event(ab, skb);
6689 break;
6690 case WMI_SCAN_EVENTID:
6691 ath12k_scan_event(ab, skb);
6692 break;
6693 case WMI_PEER_STA_KICKOUT_EVENTID:
6694 ath12k_peer_sta_kickout_event(ab, skb);
6695 break;
6696 case WMI_ROAM_EVENTID:
6697 ath12k_roam_event(ab, skb);
6698 break;
6699 case WMI_CHAN_INFO_EVENTID:
6700 ath12k_chan_info_event(ab, skb);
6701 break;
6702 case WMI_PDEV_BSS_CHAN_INFO_EVENTID:
6703 ath12k_pdev_bss_chan_info_event(ab, skb);
6704 break;
6705 case WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID:
6706 ath12k_vdev_install_key_compl_event(ab, skb);
6707 break;
6708 case WMI_SERVICE_AVAILABLE_EVENTID:
6709 ath12k_service_available_event(ab, skb);
6710 break;
6711 case WMI_PEER_ASSOC_CONF_EVENTID:
6712 ath12k_peer_assoc_conf_event(ab, skb);
6713 break;
6714 case WMI_UPDATE_STATS_EVENTID:
6715 ath12k_update_stats_event(ab, skb);
6716 break;
6717 case WMI_PDEV_CTL_FAILSAFE_CHECK_EVENTID:
6718 ath12k_pdev_ctl_failsafe_check_event(ab, skb);
6719 break;
6720 case WMI_PDEV_CSA_SWITCH_COUNT_STATUS_EVENTID:
6721 ath12k_wmi_pdev_csa_switch_count_status_event(ab, skb);
6722 break;
6723 case WMI_PDEV_TEMPERATURE_EVENTID:
6724 ath12k_wmi_pdev_temperature_event(ab, skb);
6725 break;
6726 case WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID:
6727 ath12k_wmi_pdev_dma_ring_buf_release_event(ab, skb);
6728 break;
6729 case WMI_HOST_FILS_DISCOVERY_EVENTID:
6730 ath12k_fils_discovery_event(ab, skb);
6731 break;
6732 case WMI_OFFLOAD_PROB_RESP_TX_STATUS_EVENTID:
6733 ath12k_probe_resp_tx_status_event(ab, skb);
6734 break;
6735 /* add Unsupported events here */
6736 case WMI_TBTTOFFSET_EXT_UPDATE_EVENTID:
6737 case WMI_PEER_OPER_MODE_CHANGE_EVENTID:
6738 case WMI_TWT_ENABLE_EVENTID:
6739 case WMI_TWT_DISABLE_EVENTID:
6740 case WMI_PDEV_DMA_RING_CFG_RSP_EVENTID:
6741 ath12k_dbg(ab, ATH12K_DBG_WMI,
6742 "ignoring unsupported event 0x%x\n", id);
6743 break;
6744 case WMI_PDEV_DFS_RADAR_DETECTION_EVENTID:
6745 ath12k_wmi_pdev_dfs_radar_detected_event(ab, skb);
6746 break;
6747 case WMI_VDEV_DELETE_RESP_EVENTID:
6748 ath12k_vdev_delete_resp_event(ab, skb);
6749 break;
6750 /* TODO: Add remaining events */
6751 default:
6752 ath12k_dbg(ab, ATH12K_DBG_WMI, "Unknown eventid: 0x%x\n", id);
6753 break;
6754 }
6755
6756 out:
6757 dev_kfree_skb(skb);
6758 }
6759
ath12k_connect_pdev_htc_service(struct ath12k_base * ab,u32 pdev_idx)6760 static int ath12k_connect_pdev_htc_service(struct ath12k_base *ab,
6761 u32 pdev_idx)
6762 {
6763 int status;
6764 u32 svc_id[] = { ATH12K_HTC_SVC_ID_WMI_CONTROL,
6765 ATH12K_HTC_SVC_ID_WMI_CONTROL_MAC1,
6766 ATH12K_HTC_SVC_ID_WMI_CONTROL_MAC2 };
6767 struct ath12k_htc_svc_conn_req conn_req = {};
6768 struct ath12k_htc_svc_conn_resp conn_resp = {};
6769
6770 /* these fields are the same for all service endpoints */
6771 conn_req.ep_ops.ep_tx_complete = ath12k_wmi_htc_tx_complete;
6772 conn_req.ep_ops.ep_rx_complete = ath12k_wmi_op_rx;
6773 conn_req.ep_ops.ep_tx_credits = ath12k_wmi_op_ep_tx_credits;
6774
6775 /* connect to control service */
6776 conn_req.service_id = svc_id[pdev_idx];
6777
6778 status = ath12k_htc_connect_service(&ab->htc, &conn_req, &conn_resp);
6779 if (status) {
6780 ath12k_warn(ab, "failed to connect to WMI CONTROL service status: %d\n",
6781 status);
6782 return status;
6783 }
6784
6785 ab->wmi_ab.wmi_endpoint_id[pdev_idx] = conn_resp.eid;
6786 ab->wmi_ab.wmi[pdev_idx].eid = conn_resp.eid;
6787 ab->wmi_ab.max_msg_len[pdev_idx] = conn_resp.max_msg_len;
6788
6789 return 0;
6790 }
6791
6792 static int
ath12k_wmi_send_unit_test_cmd(struct ath12k * ar,struct wmi_unit_test_cmd ut_cmd,u32 * test_args)6793 ath12k_wmi_send_unit_test_cmd(struct ath12k *ar,
6794 struct wmi_unit_test_cmd ut_cmd,
6795 u32 *test_args)
6796 {
6797 struct ath12k_wmi_pdev *wmi = ar->wmi;
6798 struct wmi_unit_test_cmd *cmd;
6799 struct sk_buff *skb;
6800 struct wmi_tlv *tlv;
6801 void *ptr;
6802 u32 *ut_cmd_args;
6803 int buf_len, arg_len;
6804 int ret;
6805 int i;
6806
6807 arg_len = sizeof(u32) * le32_to_cpu(ut_cmd.num_args);
6808 buf_len = sizeof(ut_cmd) + arg_len + TLV_HDR_SIZE;
6809
6810 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, buf_len);
6811 if (!skb)
6812 return -ENOMEM;
6813
6814 cmd = (struct wmi_unit_test_cmd *)skb->data;
6815 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_UNIT_TEST_CMD,
6816 sizeof(ut_cmd));
6817
6818 cmd->vdev_id = ut_cmd.vdev_id;
6819 cmd->module_id = ut_cmd.module_id;
6820 cmd->num_args = ut_cmd.num_args;
6821 cmd->diag_token = ut_cmd.diag_token;
6822
6823 ptr = skb->data + sizeof(ut_cmd);
6824
6825 tlv = ptr;
6826 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_UINT32, arg_len);
6827
6828 ptr += TLV_HDR_SIZE;
6829
6830 ut_cmd_args = ptr;
6831 for (i = 0; i < le32_to_cpu(ut_cmd.num_args); i++)
6832 ut_cmd_args[i] = test_args[i];
6833
6834 ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
6835 "WMI unit test : module %d vdev %d n_args %d token %d\n",
6836 cmd->module_id, cmd->vdev_id, cmd->num_args,
6837 cmd->diag_token);
6838
6839 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_UNIT_TEST_CMDID);
6840
6841 if (ret) {
6842 ath12k_warn(ar->ab, "failed to send WMI_UNIT_TEST CMD :%d\n",
6843 ret);
6844 dev_kfree_skb(skb);
6845 }
6846
6847 return ret;
6848 }
6849
ath12k_wmi_simulate_radar(struct ath12k * ar)6850 int ath12k_wmi_simulate_radar(struct ath12k *ar)
6851 {
6852 struct ath12k_vif *arvif;
6853 u32 dfs_args[DFS_MAX_TEST_ARGS];
6854 struct wmi_unit_test_cmd wmi_ut;
6855 bool arvif_found = false;
6856
6857 list_for_each_entry(arvif, &ar->arvifs, list) {
6858 if (arvif->is_started && arvif->vdev_type == WMI_VDEV_TYPE_AP) {
6859 arvif_found = true;
6860 break;
6861 }
6862 }
6863
6864 if (!arvif_found)
6865 return -EINVAL;
6866
6867 dfs_args[DFS_TEST_CMDID] = 0;
6868 dfs_args[DFS_TEST_PDEV_ID] = ar->pdev->pdev_id;
6869 /* Currently we could pass segment_id(b0 - b1), chirp(b2)
6870 * freq offset (b3 - b10) to unit test. For simulation
6871 * purpose this can be set to 0 which is valid.
6872 */
6873 dfs_args[DFS_TEST_RADAR_PARAM] = 0;
6874
6875 wmi_ut.vdev_id = cpu_to_le32(arvif->vdev_id);
6876 wmi_ut.module_id = cpu_to_le32(DFS_UNIT_TEST_MODULE);
6877 wmi_ut.num_args = cpu_to_le32(DFS_MAX_TEST_ARGS);
6878 wmi_ut.diag_token = cpu_to_le32(DFS_UNIT_TEST_TOKEN);
6879
6880 ath12k_dbg(ar->ab, ATH12K_DBG_REG, "Triggering Radar Simulation\n");
6881
6882 return ath12k_wmi_send_unit_test_cmd(ar, wmi_ut, dfs_args);
6883 }
6884
ath12k_wmi_connect(struct ath12k_base * ab)6885 int ath12k_wmi_connect(struct ath12k_base *ab)
6886 {
6887 u32 i;
6888 u8 wmi_ep_count;
6889
6890 wmi_ep_count = ab->htc.wmi_ep_count;
6891 if (wmi_ep_count > ab->hw_params->max_radios)
6892 return -1;
6893
6894 for (i = 0; i < wmi_ep_count; i++)
6895 ath12k_connect_pdev_htc_service(ab, i);
6896
6897 return 0;
6898 }
6899
ath12k_wmi_pdev_detach(struct ath12k_base * ab,u8 pdev_id)6900 static void ath12k_wmi_pdev_detach(struct ath12k_base *ab, u8 pdev_id)
6901 {
6902 if (WARN_ON(pdev_id >= MAX_RADIOS))
6903 return;
6904
6905 /* TODO: Deinit any pdev specific wmi resource */
6906 }
6907
ath12k_wmi_pdev_attach(struct ath12k_base * ab,u8 pdev_id)6908 int ath12k_wmi_pdev_attach(struct ath12k_base *ab,
6909 u8 pdev_id)
6910 {
6911 struct ath12k_wmi_pdev *wmi_handle;
6912
6913 if (pdev_id >= ab->hw_params->max_radios)
6914 return -EINVAL;
6915
6916 wmi_handle = &ab->wmi_ab.wmi[pdev_id];
6917
6918 wmi_handle->wmi_ab = &ab->wmi_ab;
6919
6920 ab->wmi_ab.ab = ab;
6921 /* TODO: Init remaining resource specific to pdev */
6922
6923 return 0;
6924 }
6925
ath12k_wmi_attach(struct ath12k_base * ab)6926 int ath12k_wmi_attach(struct ath12k_base *ab)
6927 {
6928 int ret;
6929
6930 ret = ath12k_wmi_pdev_attach(ab, 0);
6931 if (ret)
6932 return ret;
6933
6934 ab->wmi_ab.ab = ab;
6935 ab->wmi_ab.preferred_hw_mode = WMI_HOST_HW_MODE_MAX;
6936
6937 /* It's overwritten when service_ext_ready is handled */
6938 if (ab->hw_params->single_pdev_only)
6939 ab->wmi_ab.preferred_hw_mode = WMI_HOST_HW_MODE_SINGLE;
6940
6941 /* TODO: Init remaining wmi soc resources required */
6942 init_completion(&ab->wmi_ab.service_ready);
6943 init_completion(&ab->wmi_ab.unified_ready);
6944
6945 return 0;
6946 }
6947
ath12k_wmi_detach(struct ath12k_base * ab)6948 void ath12k_wmi_detach(struct ath12k_base *ab)
6949 {
6950 int i;
6951
6952 /* TODO: Deinit wmi resource specific to SOC as required */
6953
6954 for (i = 0; i < ab->htc.wmi_ep_count; i++)
6955 ath12k_wmi_pdev_detach(ab, i);
6956
6957 ath12k_wmi_free_dbring_caps(ab);
6958 }
6959