1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/module.h>
8 #include <linux/msi.h>
9 #include <linux/pci.h>
10
11 #include "pci.h"
12 #include "core.h"
13 #include "hif.h"
14 #include "mhi.h"
15 #include "debug.h"
16
17 #define ATH12K_PCI_BAR_NUM 0
18 #define ATH12K_PCI_DMA_MASK 32
19
20 #define ATH12K_PCI_IRQ_CE0_OFFSET 3
21
22 #define WINDOW_ENABLE_BIT 0x40000000
23 #define WINDOW_REG_ADDRESS 0x310c
24 #define WINDOW_VALUE_MASK GENMASK(24, 19)
25 #define WINDOW_START 0x80000
26 #define WINDOW_RANGE_MASK GENMASK(18, 0)
27 #define WINDOW_STATIC_MASK GENMASK(31, 6)
28
29 #define TCSR_SOC_HW_VERSION 0x1B00000
30 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8)
31 #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 4)
32
33 /* BAR0 + 4k is always accessible, and no
34 * need to force wakeup.
35 * 4K - 32 = 0xFE0
36 */
37 #define ACCESS_ALWAYS_OFF 0xFE0
38
39 #define QCN9274_DEVICE_ID 0x1109
40 #define WCN7850_DEVICE_ID 0x1107
41
42 static const struct pci_device_id ath12k_pci_id_table[] = {
43 { PCI_VDEVICE(QCOM, QCN9274_DEVICE_ID) },
44 { PCI_VDEVICE(QCOM, WCN7850_DEVICE_ID) },
45 {0}
46 };
47
48 MODULE_DEVICE_TABLE(pci, ath12k_pci_id_table);
49
50 /* TODO: revisit IRQ mapping for new SRNG's */
51 static const struct ath12k_msi_config ath12k_msi_config[] = {
52 {
53 .total_vectors = 16,
54 .total_users = 3,
55 .users = (struct ath12k_msi_user[]) {
56 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
57 { .name = "CE", .num_vectors = 5, .base_vector = 3 },
58 { .name = "DP", .num_vectors = 8, .base_vector = 8 },
59 },
60 },
61 };
62
63 static const char *irq_name[ATH12K_IRQ_NUM_MAX] = {
64 "bhi",
65 "mhi-er0",
66 "mhi-er1",
67 "ce0",
68 "ce1",
69 "ce2",
70 "ce3",
71 "ce4",
72 "ce5",
73 "ce6",
74 "ce7",
75 "ce8",
76 "ce9",
77 "ce10",
78 "ce11",
79 "ce12",
80 "ce13",
81 "ce14",
82 "ce15",
83 "host2wbm-desc-feed",
84 "host2reo-re-injection",
85 "host2reo-command",
86 "host2rxdma-monitor-ring3",
87 "host2rxdma-monitor-ring2",
88 "host2rxdma-monitor-ring1",
89 "reo2ost-exception",
90 "wbm2host-rx-release",
91 "reo2host-status",
92 "reo2host-destination-ring4",
93 "reo2host-destination-ring3",
94 "reo2host-destination-ring2",
95 "reo2host-destination-ring1",
96 "rxdma2host-monitor-destination-mac3",
97 "rxdma2host-monitor-destination-mac2",
98 "rxdma2host-monitor-destination-mac1",
99 "ppdu-end-interrupts-mac3",
100 "ppdu-end-interrupts-mac2",
101 "ppdu-end-interrupts-mac1",
102 "rxdma2host-monitor-status-ring-mac3",
103 "rxdma2host-monitor-status-ring-mac2",
104 "rxdma2host-monitor-status-ring-mac1",
105 "host2rxdma-host-buf-ring-mac3",
106 "host2rxdma-host-buf-ring-mac2",
107 "host2rxdma-host-buf-ring-mac1",
108 "rxdma2host-destination-ring-mac3",
109 "rxdma2host-destination-ring-mac2",
110 "rxdma2host-destination-ring-mac1",
111 "host2tcl-input-ring4",
112 "host2tcl-input-ring3",
113 "host2tcl-input-ring2",
114 "host2tcl-input-ring1",
115 "wbm2host-tx-completions-ring4",
116 "wbm2host-tx-completions-ring3",
117 "wbm2host-tx-completions-ring2",
118 "wbm2host-tx-completions-ring1",
119 "tcl2host-status-ring",
120 };
121
ath12k_pci_bus_wake_up(struct ath12k_base * ab)122 static int ath12k_pci_bus_wake_up(struct ath12k_base *ab)
123 {
124 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
125
126 return mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev);
127 }
128
ath12k_pci_bus_release(struct ath12k_base * ab)129 static void ath12k_pci_bus_release(struct ath12k_base *ab)
130 {
131 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
132
133 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev);
134 }
135
136 static const struct ath12k_pci_ops ath12k_pci_ops_qcn9274 = {
137 .wakeup = NULL,
138 .release = NULL,
139 };
140
141 static const struct ath12k_pci_ops ath12k_pci_ops_wcn7850 = {
142 .wakeup = ath12k_pci_bus_wake_up,
143 .release = ath12k_pci_bus_release,
144 };
145
ath12k_pci_select_window(struct ath12k_pci * ab_pci,u32 offset)146 static void ath12k_pci_select_window(struct ath12k_pci *ab_pci, u32 offset)
147 {
148 struct ath12k_base *ab = ab_pci->ab;
149
150 u32 window = u32_get_bits(offset, WINDOW_VALUE_MASK);
151 u32 static_window;
152
153 lockdep_assert_held(&ab_pci->window_lock);
154
155 /* Preserve the static window configuration and reset only dynamic window */
156 static_window = ab_pci->register_window & WINDOW_STATIC_MASK;
157 window |= static_window;
158
159 if (window != ab_pci->register_window) {
160 iowrite32(WINDOW_ENABLE_BIT | window,
161 ab->mem + WINDOW_REG_ADDRESS);
162 ioread32(ab->mem + WINDOW_REG_ADDRESS);
163 ab_pci->register_window = window;
164 }
165 }
166
ath12k_pci_select_static_window(struct ath12k_pci * ab_pci)167 static void ath12k_pci_select_static_window(struct ath12k_pci *ab_pci)
168 {
169 u32 umac_window = u32_get_bits(HAL_SEQ_WCSS_UMAC_OFFSET, WINDOW_VALUE_MASK);
170 u32 ce_window = u32_get_bits(HAL_CE_WFSS_CE_REG_BASE, WINDOW_VALUE_MASK);
171 u32 window;
172
173 window = (umac_window << 12) | (ce_window << 6);
174
175 spin_lock_bh(&ab_pci->window_lock);
176 ab_pci->register_window = window;
177 spin_unlock_bh(&ab_pci->window_lock);
178
179 iowrite32(WINDOW_ENABLE_BIT | window, ab_pci->ab->mem + WINDOW_REG_ADDRESS);
180 }
181
ath12k_pci_get_window_start(struct ath12k_base * ab,u32 offset)182 static u32 ath12k_pci_get_window_start(struct ath12k_base *ab,
183 u32 offset)
184 {
185 u32 window_start;
186
187 /* If offset lies within DP register range, use 3rd window */
188 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK)
189 window_start = 3 * WINDOW_START;
190 /* If offset lies within CE register range, use 2nd window */
191 else if ((offset ^ HAL_CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK)
192 window_start = 2 * WINDOW_START;
193 /* If offset lies within PCI_BAR_WINDOW0_BASE and within PCI_SOC_PCI_REG_BASE
194 * use 0th window
195 */
196 else if (((offset ^ PCI_BAR_WINDOW0_BASE) < WINDOW_RANGE_MASK) &&
197 !((offset ^ PCI_SOC_PCI_REG_BASE) < PCI_SOC_RANGE_MASK))
198 window_start = 0;
199 else
200 window_start = WINDOW_START;
201
202 return window_start;
203 }
204
ath12k_pci_soc_global_reset(struct ath12k_base * ab)205 static void ath12k_pci_soc_global_reset(struct ath12k_base *ab)
206 {
207 u32 val, delay;
208
209 val = ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET);
210
211 val |= PCIE_SOC_GLOBAL_RESET_V;
212
213 ath12k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
214
215 /* TODO: exact time to sleep is uncertain */
216 delay = 10;
217 mdelay(delay);
218
219 /* Need to toggle V bit back otherwise stuck in reset status */
220 val &= ~PCIE_SOC_GLOBAL_RESET_V;
221
222 ath12k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
223
224 mdelay(delay);
225
226 val = ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET);
227 if (val == 0xffffffff)
228 ath12k_warn(ab, "link down error during global reset\n");
229 }
230
ath12k_pci_clear_dbg_registers(struct ath12k_base * ab)231 static void ath12k_pci_clear_dbg_registers(struct ath12k_base *ab)
232 {
233 u32 val;
234
235 /* read cookie */
236 val = ath12k_pci_read32(ab, PCIE_Q6_COOKIE_ADDR);
237 ath12k_dbg(ab, ATH12K_DBG_PCI, "cookie:0x%x\n", val);
238
239 val = ath12k_pci_read32(ab, WLAON_WARM_SW_ENTRY);
240 ath12k_dbg(ab, ATH12K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val);
241
242 /* TODO: exact time to sleep is uncertain */
243 mdelay(10);
244
245 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from
246 * continuing warm path and entering dead loop.
247 */
248 ath12k_pci_write32(ab, WLAON_WARM_SW_ENTRY, 0);
249 mdelay(10);
250
251 val = ath12k_pci_read32(ab, WLAON_WARM_SW_ENTRY);
252 ath12k_dbg(ab, ATH12K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val);
253
254 /* A read clear register. clear the register to prevent
255 * Q6 from entering wrong code path.
256 */
257 val = ath12k_pci_read32(ab, WLAON_SOC_RESET_CAUSE_REG);
258 ath12k_dbg(ab, ATH12K_DBG_PCI, "soc reset cause:%d\n", val);
259 }
260
ath12k_pci_enable_ltssm(struct ath12k_base * ab)261 static void ath12k_pci_enable_ltssm(struct ath12k_base *ab)
262 {
263 u32 val;
264 int i;
265
266 val = ath12k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM);
267
268 /* PCIE link seems very unstable after the Hot Reset*/
269 for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) {
270 if (val == 0xffffffff)
271 mdelay(5);
272
273 ath12k_pci_write32(ab, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE);
274 val = ath12k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM);
275 }
276
277 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci ltssm 0x%x\n", val);
278
279 val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST);
280 val |= GCC_GCC_PCIE_HOT_RST_VAL;
281 ath12k_pci_write32(ab, GCC_GCC_PCIE_HOT_RST, val);
282 val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST);
283
284 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci pcie_hot_rst 0x%x\n", val);
285
286 mdelay(5);
287 }
288
ath12k_pci_clear_all_intrs(struct ath12k_base * ab)289 static void ath12k_pci_clear_all_intrs(struct ath12k_base *ab)
290 {
291 /* This is a WAR for PCIE Hotreset.
292 * When target receive Hotreset, but will set the interrupt.
293 * So when download SBL again, SBL will open Interrupt and
294 * receive it, and crash immediately.
295 */
296 ath12k_pci_write32(ab, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL);
297 }
298
ath12k_pci_set_wlaon_pwr_ctrl(struct ath12k_base * ab)299 static void ath12k_pci_set_wlaon_pwr_ctrl(struct ath12k_base *ab)
300 {
301 u32 val;
302
303 val = ath12k_pci_read32(ab, WLAON_QFPROM_PWR_CTRL_REG);
304 val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK;
305 ath12k_pci_write32(ab, WLAON_QFPROM_PWR_CTRL_REG, val);
306 }
307
ath12k_pci_force_wake(struct ath12k_base * ab)308 static void ath12k_pci_force_wake(struct ath12k_base *ab)
309 {
310 ath12k_pci_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1);
311 mdelay(5);
312 }
313
ath12k_pci_sw_reset(struct ath12k_base * ab,bool power_on)314 static void ath12k_pci_sw_reset(struct ath12k_base *ab, bool power_on)
315 {
316 if (power_on) {
317 ath12k_pci_enable_ltssm(ab);
318 ath12k_pci_clear_all_intrs(ab);
319 ath12k_pci_set_wlaon_pwr_ctrl(ab);
320 }
321
322 ath12k_mhi_clear_vector(ab);
323 ath12k_pci_clear_dbg_registers(ab);
324 ath12k_pci_soc_global_reset(ab);
325 ath12k_mhi_set_mhictrl_reset(ab);
326 }
327
ath12k_pci_free_ext_irq(struct ath12k_base * ab)328 static void ath12k_pci_free_ext_irq(struct ath12k_base *ab)
329 {
330 int i, j;
331
332 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
333 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
334
335 for (j = 0; j < irq_grp->num_irq; j++)
336 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp);
337
338 netif_napi_del(&irq_grp->napi);
339 }
340 }
341
ath12k_pci_free_irq(struct ath12k_base * ab)342 static void ath12k_pci_free_irq(struct ath12k_base *ab)
343 {
344 int i, irq_idx;
345
346 for (i = 0; i < ab->hw_params->ce_count; i++) {
347 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
348 continue;
349 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i;
350 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]);
351 }
352
353 ath12k_pci_free_ext_irq(ab);
354 }
355
ath12k_pci_ce_irq_enable(struct ath12k_base * ab,u16 ce_id)356 static void ath12k_pci_ce_irq_enable(struct ath12k_base *ab, u16 ce_id)
357 {
358 u32 irq_idx;
359
360 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_id;
361 enable_irq(ab->irq_num[irq_idx]);
362 }
363
ath12k_pci_ce_irq_disable(struct ath12k_base * ab,u16 ce_id)364 static void ath12k_pci_ce_irq_disable(struct ath12k_base *ab, u16 ce_id)
365 {
366 u32 irq_idx;
367
368 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_id;
369 disable_irq_nosync(ab->irq_num[irq_idx]);
370 }
371
ath12k_pci_ce_irqs_disable(struct ath12k_base * ab)372 static void ath12k_pci_ce_irqs_disable(struct ath12k_base *ab)
373 {
374 int i;
375
376 clear_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags);
377
378 for (i = 0; i < ab->hw_params->ce_count; i++) {
379 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
380 continue;
381 ath12k_pci_ce_irq_disable(ab, i);
382 }
383 }
384
ath12k_pci_sync_ce_irqs(struct ath12k_base * ab)385 static void ath12k_pci_sync_ce_irqs(struct ath12k_base *ab)
386 {
387 int i;
388 int irq_idx;
389
390 for (i = 0; i < ab->hw_params->ce_count; i++) {
391 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
392 continue;
393
394 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i;
395 synchronize_irq(ab->irq_num[irq_idx]);
396 }
397 }
398
ath12k_pci_ce_tasklet(struct tasklet_struct * t)399 static void ath12k_pci_ce_tasklet(struct tasklet_struct *t)
400 {
401 struct ath12k_ce_pipe *ce_pipe = from_tasklet(ce_pipe, t, intr_tq);
402
403 ath12k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num);
404
405 ath12k_pci_ce_irq_enable(ce_pipe->ab, ce_pipe->pipe_num);
406 }
407
ath12k_pci_ce_interrupt_handler(int irq,void * arg)408 static irqreturn_t ath12k_pci_ce_interrupt_handler(int irq, void *arg)
409 {
410 struct ath12k_ce_pipe *ce_pipe = arg;
411 struct ath12k_base *ab = ce_pipe->ab;
412
413 if (!test_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags))
414 return IRQ_HANDLED;
415
416 /* last interrupt received for this CE */
417 ce_pipe->timestamp = jiffies;
418
419 ath12k_pci_ce_irq_disable(ce_pipe->ab, ce_pipe->pipe_num);
420 tasklet_schedule(&ce_pipe->intr_tq);
421
422 return IRQ_HANDLED;
423 }
424
ath12k_pci_ext_grp_disable(struct ath12k_ext_irq_grp * irq_grp)425 static void ath12k_pci_ext_grp_disable(struct ath12k_ext_irq_grp *irq_grp)
426 {
427 int i;
428
429 for (i = 0; i < irq_grp->num_irq; i++)
430 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
431 }
432
__ath12k_pci_ext_irq_disable(struct ath12k_base * ab)433 static void __ath12k_pci_ext_irq_disable(struct ath12k_base *ab)
434 {
435 int i;
436
437 if (!test_and_clear_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags))
438 return;
439
440 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
441 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
442
443 ath12k_pci_ext_grp_disable(irq_grp);
444
445 if (irq_grp->napi_enabled) {
446 napi_synchronize(&irq_grp->napi);
447 napi_disable(&irq_grp->napi);
448 irq_grp->napi_enabled = false;
449 }
450 }
451 }
452
ath12k_pci_ext_grp_enable(struct ath12k_ext_irq_grp * irq_grp)453 static void ath12k_pci_ext_grp_enable(struct ath12k_ext_irq_grp *irq_grp)
454 {
455 int i;
456
457 for (i = 0; i < irq_grp->num_irq; i++)
458 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
459 }
460
ath12k_pci_sync_ext_irqs(struct ath12k_base * ab)461 static void ath12k_pci_sync_ext_irqs(struct ath12k_base *ab)
462 {
463 int i, j, irq_idx;
464
465 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
466 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
467
468 for (j = 0; j < irq_grp->num_irq; j++) {
469 irq_idx = irq_grp->irqs[j];
470 synchronize_irq(ab->irq_num[irq_idx]);
471 }
472 }
473 }
474
ath12k_pci_ext_grp_napi_poll(struct napi_struct * napi,int budget)475 static int ath12k_pci_ext_grp_napi_poll(struct napi_struct *napi, int budget)
476 {
477 struct ath12k_ext_irq_grp *irq_grp = container_of(napi,
478 struct ath12k_ext_irq_grp,
479 napi);
480 struct ath12k_base *ab = irq_grp->ab;
481 int work_done;
482
483 work_done = ath12k_dp_service_srng(ab, irq_grp, budget);
484 if (work_done < budget) {
485 napi_complete_done(napi, work_done);
486 ath12k_pci_ext_grp_enable(irq_grp);
487 }
488
489 if (work_done > budget)
490 work_done = budget;
491
492 return work_done;
493 }
494
ath12k_pci_ext_interrupt_handler(int irq,void * arg)495 static irqreturn_t ath12k_pci_ext_interrupt_handler(int irq, void *arg)
496 {
497 struct ath12k_ext_irq_grp *irq_grp = arg;
498 struct ath12k_base *ab = irq_grp->ab;
499
500 if (!test_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags))
501 return IRQ_HANDLED;
502
503 ath12k_dbg(irq_grp->ab, ATH12K_DBG_PCI, "ext irq:%d\n", irq);
504
505 /* last interrupt received for this group */
506 irq_grp->timestamp = jiffies;
507
508 ath12k_pci_ext_grp_disable(irq_grp);
509
510 napi_schedule(&irq_grp->napi);
511
512 return IRQ_HANDLED;
513 }
514
ath12k_pci_ext_irq_config(struct ath12k_base * ab)515 static int ath12k_pci_ext_irq_config(struct ath12k_base *ab)
516 {
517 int i, j, ret, num_vectors = 0;
518 u32 user_base_data = 0, base_vector = 0, base_idx;
519
520 base_idx = ATH12K_PCI_IRQ_CE0_OFFSET + CE_COUNT_MAX;
521 ret = ath12k_pci_get_user_msi_assignment(ab, "DP",
522 &num_vectors,
523 &user_base_data,
524 &base_vector);
525 if (ret < 0)
526 return ret;
527
528 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
529 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
530 u32 num_irq = 0;
531
532 irq_grp->ab = ab;
533 irq_grp->grp_id = i;
534 init_dummy_netdev(&irq_grp->napi_ndev);
535 netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi,
536 ath12k_pci_ext_grp_napi_poll);
537
538 if (ab->hw_params->ring_mask->tx[i] ||
539 ab->hw_params->ring_mask->rx[i] ||
540 ab->hw_params->ring_mask->rx_err[i] ||
541 ab->hw_params->ring_mask->rx_wbm_rel[i] ||
542 ab->hw_params->ring_mask->reo_status[i] ||
543 ab->hw_params->ring_mask->host2rxdma[i] ||
544 ab->hw_params->ring_mask->rx_mon_dest[i]) {
545 num_irq = 1;
546 }
547
548 irq_grp->num_irq = num_irq;
549 irq_grp->irqs[0] = base_idx + i;
550
551 for (j = 0; j < irq_grp->num_irq; j++) {
552 int irq_idx = irq_grp->irqs[j];
553 int vector = (i % num_vectors) + base_vector;
554 int irq = ath12k_pci_get_msi_irq(ab->dev, vector);
555
556 ab->irq_num[irq_idx] = irq;
557
558 ath12k_dbg(ab, ATH12K_DBG_PCI,
559 "irq:%d group:%d\n", irq, i);
560
561 irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY);
562 ret = request_irq(irq, ath12k_pci_ext_interrupt_handler,
563 IRQF_SHARED,
564 "DP_EXT_IRQ", irq_grp);
565 if (ret) {
566 ath12k_err(ab, "failed request irq %d: %d\n",
567 vector, ret);
568 return ret;
569 }
570
571 disable_irq_nosync(ab->irq_num[irq_idx]);
572 }
573 }
574
575 return 0;
576 }
577
ath12k_pci_config_irq(struct ath12k_base * ab)578 static int ath12k_pci_config_irq(struct ath12k_base *ab)
579 {
580 struct ath12k_ce_pipe *ce_pipe;
581 u32 msi_data_start;
582 u32 msi_data_count, msi_data_idx;
583 u32 msi_irq_start;
584 unsigned int msi_data;
585 int irq, i, ret, irq_idx;
586
587 ret = ath12k_pci_get_user_msi_assignment(ab,
588 "CE", &msi_data_count,
589 &msi_data_start, &msi_irq_start);
590 if (ret)
591 return ret;
592
593 /* Configure CE irqs */
594
595 for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) {
596 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
597 continue;
598
599 msi_data = (msi_data_idx % msi_data_count) + msi_irq_start;
600 irq = ath12k_pci_get_msi_irq(ab->dev, msi_data);
601 ce_pipe = &ab->ce.ce_pipe[i];
602
603 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i;
604
605 tasklet_setup(&ce_pipe->intr_tq, ath12k_pci_ce_tasklet);
606
607 ret = request_irq(irq, ath12k_pci_ce_interrupt_handler,
608 IRQF_SHARED, irq_name[irq_idx],
609 ce_pipe);
610 if (ret) {
611 ath12k_err(ab, "failed to request irq %d: %d\n",
612 irq_idx, ret);
613 return ret;
614 }
615
616 ab->irq_num[irq_idx] = irq;
617 msi_data_idx++;
618
619 ath12k_pci_ce_irq_disable(ab, i);
620 }
621
622 ret = ath12k_pci_ext_irq_config(ab);
623 if (ret)
624 return ret;
625
626 return 0;
627 }
628
ath12k_pci_init_qmi_ce_config(struct ath12k_base * ab)629 static void ath12k_pci_init_qmi_ce_config(struct ath12k_base *ab)
630 {
631 struct ath12k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg;
632
633 cfg->tgt_ce = ab->hw_params->target_ce_config;
634 cfg->tgt_ce_len = ab->hw_params->target_ce_count;
635
636 cfg->svc_to_ce_map = ab->hw_params->svc_to_ce_map;
637 cfg->svc_to_ce_map_len = ab->hw_params->svc_to_ce_map_len;
638 ab->qmi.service_ins_id = ab->hw_params->qmi_service_ins_id;
639 }
640
ath12k_pci_ce_irqs_enable(struct ath12k_base * ab)641 static void ath12k_pci_ce_irqs_enable(struct ath12k_base *ab)
642 {
643 int i;
644
645 set_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags);
646
647 for (i = 0; i < ab->hw_params->ce_count; i++) {
648 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
649 continue;
650 ath12k_pci_ce_irq_enable(ab, i);
651 }
652 }
653
ath12k_pci_msi_config(struct ath12k_pci * ab_pci,bool enable)654 static void ath12k_pci_msi_config(struct ath12k_pci *ab_pci, bool enable)
655 {
656 struct pci_dev *dev = ab_pci->pdev;
657 u16 control;
658
659 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
660
661 if (enable)
662 control |= PCI_MSI_FLAGS_ENABLE;
663 else
664 control &= ~PCI_MSI_FLAGS_ENABLE;
665
666 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
667 }
668
ath12k_pci_msi_enable(struct ath12k_pci * ab_pci)669 static void ath12k_pci_msi_enable(struct ath12k_pci *ab_pci)
670 {
671 ath12k_pci_msi_config(ab_pci, true);
672 }
673
ath12k_pci_msi_disable(struct ath12k_pci * ab_pci)674 static void ath12k_pci_msi_disable(struct ath12k_pci *ab_pci)
675 {
676 ath12k_pci_msi_config(ab_pci, false);
677 }
678
ath12k_pci_msi_alloc(struct ath12k_pci * ab_pci)679 static int ath12k_pci_msi_alloc(struct ath12k_pci *ab_pci)
680 {
681 struct ath12k_base *ab = ab_pci->ab;
682 const struct ath12k_msi_config *msi_config = ab_pci->msi_config;
683 struct msi_desc *msi_desc;
684 int num_vectors;
685 int ret;
686
687 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev,
688 msi_config->total_vectors,
689 msi_config->total_vectors,
690 PCI_IRQ_MSI);
691 if (num_vectors != msi_config->total_vectors) {
692 ath12k_err(ab, "failed to get %d MSI vectors, only %d available",
693 msi_config->total_vectors, num_vectors);
694
695 if (num_vectors >= 0)
696 return -EINVAL;
697 else
698 return num_vectors;
699 }
700
701 ath12k_pci_msi_disable(ab_pci);
702
703 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq);
704 if (!msi_desc) {
705 ath12k_err(ab, "msi_desc is NULL!\n");
706 ret = -EINVAL;
707 goto free_msi_vector;
708 }
709
710 ab_pci->msi_ep_base_data = msi_desc->msg.data;
711 if (msi_desc->pci.msi_attrib.is_64)
712 set_bit(ATH12K_PCI_FLAG_IS_MSI_64, &ab_pci->flags);
713
714 ath12k_dbg(ab, ATH12K_DBG_PCI, "msi base data is %d\n", ab_pci->msi_ep_base_data);
715
716 return 0;
717
718 free_msi_vector:
719 pci_free_irq_vectors(ab_pci->pdev);
720
721 return ret;
722 }
723
ath12k_pci_msi_free(struct ath12k_pci * ab_pci)724 static void ath12k_pci_msi_free(struct ath12k_pci *ab_pci)
725 {
726 pci_free_irq_vectors(ab_pci->pdev);
727 }
728
ath12k_pci_claim(struct ath12k_pci * ab_pci,struct pci_dev * pdev)729 static int ath12k_pci_claim(struct ath12k_pci *ab_pci, struct pci_dev *pdev)
730 {
731 struct ath12k_base *ab = ab_pci->ab;
732 u16 device_id;
733 int ret = 0;
734
735 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
736 if (device_id != ab_pci->dev_id) {
737 ath12k_err(ab, "pci device id mismatch: 0x%x 0x%x\n",
738 device_id, ab_pci->dev_id);
739 ret = -EIO;
740 goto out;
741 }
742
743 ret = pci_assign_resource(pdev, ATH12K_PCI_BAR_NUM);
744 if (ret) {
745 ath12k_err(ab, "failed to assign pci resource: %d\n", ret);
746 goto out;
747 }
748
749 ret = pci_enable_device(pdev);
750 if (ret) {
751 ath12k_err(ab, "failed to enable pci device: %d\n", ret);
752 goto out;
753 }
754
755 ret = pci_request_region(pdev, ATH12K_PCI_BAR_NUM, "ath12k_pci");
756 if (ret) {
757 ath12k_err(ab, "failed to request pci region: %d\n", ret);
758 goto disable_device;
759 }
760
761 ret = dma_set_mask_and_coherent(&pdev->dev,
762 DMA_BIT_MASK(ATH12K_PCI_DMA_MASK));
763 if (ret) {
764 ath12k_err(ab, "failed to set pci dma mask to %d: %d\n",
765 ATH12K_PCI_DMA_MASK, ret);
766 goto release_region;
767 }
768
769 pci_set_master(pdev);
770
771 ab->mem_len = pci_resource_len(pdev, ATH12K_PCI_BAR_NUM);
772 ab->mem = pci_iomap(pdev, ATH12K_PCI_BAR_NUM, 0);
773 if (!ab->mem) {
774 ath12k_err(ab, "failed to map pci bar %d\n", ATH12K_PCI_BAR_NUM);
775 ret = -EIO;
776 goto release_region;
777 }
778
779 ath12k_dbg(ab, ATH12K_DBG_BOOT, "boot pci_mem 0x%pK\n", ab->mem);
780 return 0;
781
782 release_region:
783 pci_release_region(pdev, ATH12K_PCI_BAR_NUM);
784 disable_device:
785 pci_disable_device(pdev);
786 out:
787 return ret;
788 }
789
ath12k_pci_free_region(struct ath12k_pci * ab_pci)790 static void ath12k_pci_free_region(struct ath12k_pci *ab_pci)
791 {
792 struct ath12k_base *ab = ab_pci->ab;
793 struct pci_dev *pci_dev = ab_pci->pdev;
794
795 pci_iounmap(pci_dev, ab->mem);
796 ab->mem = NULL;
797 pci_release_region(pci_dev, ATH12K_PCI_BAR_NUM);
798 if (pci_is_enabled(pci_dev))
799 pci_disable_device(pci_dev);
800 }
801
ath12k_pci_aspm_disable(struct ath12k_pci * ab_pci)802 static void ath12k_pci_aspm_disable(struct ath12k_pci *ab_pci)
803 {
804 struct ath12k_base *ab = ab_pci->ab;
805
806 pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL,
807 &ab_pci->link_ctl);
808
809 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci link_ctl 0x%04x L0s %d L1 %d\n",
810 ab_pci->link_ctl,
811 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S),
812 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1));
813
814 /* disable L0s and L1 */
815 pcie_capability_clear_word(ab_pci->pdev, PCI_EXP_LNKCTL,
816 PCI_EXP_LNKCTL_ASPMC);
817
818 set_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags);
819 }
820
ath12k_pci_aspm_restore(struct ath12k_pci * ab_pci)821 static void ath12k_pci_aspm_restore(struct ath12k_pci *ab_pci)
822 {
823 if (test_and_clear_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags))
824 pcie_capability_clear_and_set_word(ab_pci->pdev, PCI_EXP_LNKCTL,
825 PCI_EXP_LNKCTL_ASPMC,
826 ab_pci->link_ctl &
827 PCI_EXP_LNKCTL_ASPMC);
828 }
829
ath12k_pci_kill_tasklets(struct ath12k_base * ab)830 static void ath12k_pci_kill_tasklets(struct ath12k_base *ab)
831 {
832 int i;
833
834 for (i = 0; i < ab->hw_params->ce_count; i++) {
835 struct ath12k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i];
836
837 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
838 continue;
839
840 tasklet_kill(&ce_pipe->intr_tq);
841 }
842 }
843
ath12k_pci_ce_irq_disable_sync(struct ath12k_base * ab)844 static void ath12k_pci_ce_irq_disable_sync(struct ath12k_base *ab)
845 {
846 ath12k_pci_ce_irqs_disable(ab);
847 ath12k_pci_sync_ce_irqs(ab);
848 ath12k_pci_kill_tasklets(ab);
849 }
850
ath12k_pci_map_service_to_pipe(struct ath12k_base * ab,u16 service_id,u8 * ul_pipe,u8 * dl_pipe)851 int ath12k_pci_map_service_to_pipe(struct ath12k_base *ab, u16 service_id,
852 u8 *ul_pipe, u8 *dl_pipe)
853 {
854 const struct service_to_pipe *entry;
855 bool ul_set = false, dl_set = false;
856 int i;
857
858 for (i = 0; i < ab->hw_params->svc_to_ce_map_len; i++) {
859 entry = &ab->hw_params->svc_to_ce_map[i];
860
861 if (__le32_to_cpu(entry->service_id) != service_id)
862 continue;
863
864 switch (__le32_to_cpu(entry->pipedir)) {
865 case PIPEDIR_NONE:
866 break;
867 case PIPEDIR_IN:
868 WARN_ON(dl_set);
869 *dl_pipe = __le32_to_cpu(entry->pipenum);
870 dl_set = true;
871 break;
872 case PIPEDIR_OUT:
873 WARN_ON(ul_set);
874 *ul_pipe = __le32_to_cpu(entry->pipenum);
875 ul_set = true;
876 break;
877 case PIPEDIR_INOUT:
878 WARN_ON(dl_set);
879 WARN_ON(ul_set);
880 *dl_pipe = __le32_to_cpu(entry->pipenum);
881 *ul_pipe = __le32_to_cpu(entry->pipenum);
882 dl_set = true;
883 ul_set = true;
884 break;
885 }
886 }
887
888 if (WARN_ON(!ul_set || !dl_set))
889 return -ENOENT;
890
891 return 0;
892 }
893
ath12k_pci_get_msi_irq(struct device * dev,unsigned int vector)894 int ath12k_pci_get_msi_irq(struct device *dev, unsigned int vector)
895 {
896 struct pci_dev *pci_dev = to_pci_dev(dev);
897
898 return pci_irq_vector(pci_dev, vector);
899 }
900
ath12k_pci_get_user_msi_assignment(struct ath12k_base * ab,char * user_name,int * num_vectors,u32 * user_base_data,u32 * base_vector)901 int ath12k_pci_get_user_msi_assignment(struct ath12k_base *ab, char *user_name,
902 int *num_vectors, u32 *user_base_data,
903 u32 *base_vector)
904 {
905 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
906 const struct ath12k_msi_config *msi_config = ab_pci->msi_config;
907 int idx;
908
909 for (idx = 0; idx < msi_config->total_users; idx++) {
910 if (strcmp(user_name, msi_config->users[idx].name) == 0) {
911 *num_vectors = msi_config->users[idx].num_vectors;
912 *user_base_data = msi_config->users[idx].base_vector
913 + ab_pci->msi_ep_base_data;
914 *base_vector = msi_config->users[idx].base_vector;
915
916 ath12k_dbg(ab, ATH12K_DBG_PCI, "Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n",
917 user_name, *num_vectors, *user_base_data,
918 *base_vector);
919
920 return 0;
921 }
922 }
923
924 ath12k_err(ab, "Failed to find MSI assignment for %s!\n", user_name);
925
926 return -EINVAL;
927 }
928
ath12k_pci_get_msi_address(struct ath12k_base * ab,u32 * msi_addr_lo,u32 * msi_addr_hi)929 void ath12k_pci_get_msi_address(struct ath12k_base *ab, u32 *msi_addr_lo,
930 u32 *msi_addr_hi)
931 {
932 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
933 struct pci_dev *pci_dev = to_pci_dev(ab->dev);
934
935 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO,
936 msi_addr_lo);
937
938 if (test_bit(ATH12K_PCI_FLAG_IS_MSI_64, &ab_pci->flags)) {
939 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI,
940 msi_addr_hi);
941 } else {
942 *msi_addr_hi = 0;
943 }
944 }
945
ath12k_pci_get_ce_msi_idx(struct ath12k_base * ab,u32 ce_id,u32 * msi_idx)946 void ath12k_pci_get_ce_msi_idx(struct ath12k_base *ab, u32 ce_id,
947 u32 *msi_idx)
948 {
949 u32 i, msi_data_idx;
950
951 for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) {
952 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
953 continue;
954
955 if (ce_id == i)
956 break;
957
958 msi_data_idx++;
959 }
960 *msi_idx = msi_data_idx;
961 }
962
ath12k_pci_hif_ce_irq_enable(struct ath12k_base * ab)963 void ath12k_pci_hif_ce_irq_enable(struct ath12k_base *ab)
964 {
965 ath12k_pci_ce_irqs_enable(ab);
966 }
967
ath12k_pci_hif_ce_irq_disable(struct ath12k_base * ab)968 void ath12k_pci_hif_ce_irq_disable(struct ath12k_base *ab)
969 {
970 ath12k_pci_ce_irq_disable_sync(ab);
971 }
972
ath12k_pci_ext_irq_enable(struct ath12k_base * ab)973 void ath12k_pci_ext_irq_enable(struct ath12k_base *ab)
974 {
975 int i;
976
977 set_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags);
978
979 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
980 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
981
982 if (!irq_grp->napi_enabled) {
983 napi_enable(&irq_grp->napi);
984 irq_grp->napi_enabled = true;
985 }
986
987 ath12k_pci_ext_grp_enable(irq_grp);
988 }
989 }
990
ath12k_pci_ext_irq_disable(struct ath12k_base * ab)991 void ath12k_pci_ext_irq_disable(struct ath12k_base *ab)
992 {
993 __ath12k_pci_ext_irq_disable(ab);
994 ath12k_pci_sync_ext_irqs(ab);
995 }
996
ath12k_pci_hif_suspend(struct ath12k_base * ab)997 int ath12k_pci_hif_suspend(struct ath12k_base *ab)
998 {
999 struct ath12k_pci *ar_pci = ath12k_pci_priv(ab);
1000
1001 ath12k_mhi_suspend(ar_pci);
1002
1003 return 0;
1004 }
1005
ath12k_pci_hif_resume(struct ath12k_base * ab)1006 int ath12k_pci_hif_resume(struct ath12k_base *ab)
1007 {
1008 struct ath12k_pci *ar_pci = ath12k_pci_priv(ab);
1009
1010 ath12k_mhi_resume(ar_pci);
1011
1012 return 0;
1013 }
1014
ath12k_pci_stop(struct ath12k_base * ab)1015 void ath12k_pci_stop(struct ath12k_base *ab)
1016 {
1017 ath12k_pci_ce_irq_disable_sync(ab);
1018 ath12k_ce_cleanup_pipes(ab);
1019 }
1020
ath12k_pci_start(struct ath12k_base * ab)1021 int ath12k_pci_start(struct ath12k_base *ab)
1022 {
1023 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1024
1025 set_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
1026
1027 ath12k_pci_aspm_restore(ab_pci);
1028
1029 ath12k_pci_ce_irqs_enable(ab);
1030 ath12k_ce_rx_post_buf(ab);
1031
1032 return 0;
1033 }
1034
ath12k_pci_read32(struct ath12k_base * ab,u32 offset)1035 u32 ath12k_pci_read32(struct ath12k_base *ab, u32 offset)
1036 {
1037 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1038 u32 val, window_start;
1039 int ret = 0;
1040
1041 /* for offset beyond BAR + 4K - 32, may
1042 * need to wakeup MHI to access.
1043 */
1044 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
1045 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup)
1046 ret = ab_pci->pci_ops->wakeup(ab);
1047
1048 if (offset < WINDOW_START) {
1049 val = ioread32(ab->mem + offset);
1050 } else {
1051 if (ab->static_window_map)
1052 window_start = ath12k_pci_get_window_start(ab, offset);
1053 else
1054 window_start = WINDOW_START;
1055
1056 if (window_start == WINDOW_START) {
1057 spin_lock_bh(&ab_pci->window_lock);
1058 ath12k_pci_select_window(ab_pci, offset);
1059 val = ioread32(ab->mem + window_start +
1060 (offset & WINDOW_RANGE_MASK));
1061 spin_unlock_bh(&ab_pci->window_lock);
1062 } else {
1063 if ((!window_start) &&
1064 (offset >= PCI_MHIREGLEN_REG &&
1065 offset <= PCI_MHI_REGION_END))
1066 offset = offset - PCI_MHIREGLEN_REG;
1067
1068 val = ioread32(ab->mem + window_start +
1069 (offset & WINDOW_RANGE_MASK));
1070 }
1071 }
1072
1073 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
1074 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->release &&
1075 !ret)
1076 ab_pci->pci_ops->release(ab);
1077 return val;
1078 }
1079
ath12k_pci_write32(struct ath12k_base * ab,u32 offset,u32 value)1080 void ath12k_pci_write32(struct ath12k_base *ab, u32 offset, u32 value)
1081 {
1082 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1083 u32 window_start;
1084 int ret = 0;
1085
1086 /* for offset beyond BAR + 4K - 32, may
1087 * need to wakeup MHI to access.
1088 */
1089 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
1090 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup)
1091 ret = ab_pci->pci_ops->wakeup(ab);
1092
1093 if (offset < WINDOW_START) {
1094 iowrite32(value, ab->mem + offset);
1095 } else {
1096 if (ab->static_window_map)
1097 window_start = ath12k_pci_get_window_start(ab, offset);
1098 else
1099 window_start = WINDOW_START;
1100
1101 if (window_start == WINDOW_START) {
1102 spin_lock_bh(&ab_pci->window_lock);
1103 ath12k_pci_select_window(ab_pci, offset);
1104 iowrite32(value, ab->mem + window_start +
1105 (offset & WINDOW_RANGE_MASK));
1106 spin_unlock_bh(&ab_pci->window_lock);
1107 } else {
1108 if ((!window_start) &&
1109 (offset >= PCI_MHIREGLEN_REG &&
1110 offset <= PCI_MHI_REGION_END))
1111 offset = offset - PCI_MHIREGLEN_REG;
1112
1113 iowrite32(value, ab->mem + window_start +
1114 (offset & WINDOW_RANGE_MASK));
1115 }
1116 }
1117
1118 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
1119 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->release &&
1120 !ret)
1121 ab_pci->pci_ops->release(ab);
1122 }
1123
ath12k_pci_power_up(struct ath12k_base * ab)1124 int ath12k_pci_power_up(struct ath12k_base *ab)
1125 {
1126 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1127 int ret;
1128
1129 ab_pci->register_window = 0;
1130 clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
1131 ath12k_pci_sw_reset(ab_pci->ab, true);
1132
1133 /* Disable ASPM during firmware download due to problems switching
1134 * to AMSS state.
1135 */
1136 ath12k_pci_aspm_disable(ab_pci);
1137
1138 ath12k_pci_msi_enable(ab_pci);
1139
1140 ret = ath12k_mhi_start(ab_pci);
1141 if (ret) {
1142 ath12k_err(ab, "failed to start mhi: %d\n", ret);
1143 return ret;
1144 }
1145
1146 if (ab->static_window_map)
1147 ath12k_pci_select_static_window(ab_pci);
1148
1149 return 0;
1150 }
1151
ath12k_pci_power_down(struct ath12k_base * ab)1152 void ath12k_pci_power_down(struct ath12k_base *ab)
1153 {
1154 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1155
1156 /* restore aspm in case firmware bootup fails */
1157 ath12k_pci_aspm_restore(ab_pci);
1158
1159 ath12k_pci_force_wake(ab_pci->ab);
1160 ath12k_pci_msi_disable(ab_pci);
1161 ath12k_mhi_stop(ab_pci);
1162 clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
1163 ath12k_pci_sw_reset(ab_pci->ab, false);
1164 }
1165
1166 static const struct ath12k_hif_ops ath12k_pci_hif_ops = {
1167 .start = ath12k_pci_start,
1168 .stop = ath12k_pci_stop,
1169 .read32 = ath12k_pci_read32,
1170 .write32 = ath12k_pci_write32,
1171 .power_down = ath12k_pci_power_down,
1172 .power_up = ath12k_pci_power_up,
1173 .suspend = ath12k_pci_hif_suspend,
1174 .resume = ath12k_pci_hif_resume,
1175 .irq_enable = ath12k_pci_ext_irq_enable,
1176 .irq_disable = ath12k_pci_ext_irq_disable,
1177 .get_msi_address = ath12k_pci_get_msi_address,
1178 .get_user_msi_vector = ath12k_pci_get_user_msi_assignment,
1179 .map_service_to_pipe = ath12k_pci_map_service_to_pipe,
1180 .ce_irq_enable = ath12k_pci_hif_ce_irq_enable,
1181 .ce_irq_disable = ath12k_pci_hif_ce_irq_disable,
1182 .get_ce_msi_idx = ath12k_pci_get_ce_msi_idx,
1183 };
1184
1185 static
ath12k_pci_read_hw_version(struct ath12k_base * ab,u32 * major,u32 * minor)1186 void ath12k_pci_read_hw_version(struct ath12k_base *ab, u32 *major, u32 *minor)
1187 {
1188 u32 soc_hw_version;
1189
1190 soc_hw_version = ath12k_pci_read32(ab, TCSR_SOC_HW_VERSION);
1191 *major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK,
1192 soc_hw_version);
1193 *minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK,
1194 soc_hw_version);
1195
1196 ath12k_dbg(ab, ATH12K_DBG_PCI,
1197 "pci tcsr_soc_hw_version major %d minor %d\n",
1198 *major, *minor);
1199 }
1200
ath12k_pci_probe(struct pci_dev * pdev,const struct pci_device_id * pci_dev)1201 static int ath12k_pci_probe(struct pci_dev *pdev,
1202 const struct pci_device_id *pci_dev)
1203 {
1204 struct ath12k_base *ab;
1205 struct ath12k_pci *ab_pci;
1206 u32 soc_hw_version_major, soc_hw_version_minor;
1207 int ret;
1208
1209 ab = ath12k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH12K_BUS_PCI);
1210 if (!ab) {
1211 dev_err(&pdev->dev, "failed to allocate ath12k base\n");
1212 return -ENOMEM;
1213 }
1214
1215 ab->dev = &pdev->dev;
1216 pci_set_drvdata(pdev, ab);
1217 ab_pci = ath12k_pci_priv(ab);
1218 ab_pci->dev_id = pci_dev->device;
1219 ab_pci->ab = ab;
1220 ab_pci->pdev = pdev;
1221 ab->hif.ops = &ath12k_pci_hif_ops;
1222 pci_set_drvdata(pdev, ab);
1223 spin_lock_init(&ab_pci->window_lock);
1224
1225 ret = ath12k_pci_claim(ab_pci, pdev);
1226 if (ret) {
1227 ath12k_err(ab, "failed to claim device: %d\n", ret);
1228 goto err_free_core;
1229 }
1230
1231 switch (pci_dev->device) {
1232 case QCN9274_DEVICE_ID:
1233 ab_pci->msi_config = &ath12k_msi_config[0];
1234 ab->static_window_map = true;
1235 ab_pci->pci_ops = &ath12k_pci_ops_qcn9274;
1236 ath12k_pci_read_hw_version(ab, &soc_hw_version_major,
1237 &soc_hw_version_minor);
1238 switch (soc_hw_version_major) {
1239 case ATH12K_PCI_SOC_HW_VERSION_2:
1240 ab->hw_rev = ATH12K_HW_QCN9274_HW20;
1241 break;
1242 case ATH12K_PCI_SOC_HW_VERSION_1:
1243 ab->hw_rev = ATH12K_HW_QCN9274_HW10;
1244 break;
1245 default:
1246 dev_err(&pdev->dev,
1247 "Unknown hardware version found for QCN9274: 0x%x\n",
1248 soc_hw_version_major);
1249 ret = -EOPNOTSUPP;
1250 goto err_pci_free_region;
1251 }
1252 break;
1253 case WCN7850_DEVICE_ID:
1254 ab_pci->msi_config = &ath12k_msi_config[0];
1255 ab->static_window_map = false;
1256 ab_pci->pci_ops = &ath12k_pci_ops_wcn7850;
1257 ath12k_pci_read_hw_version(ab, &soc_hw_version_major,
1258 &soc_hw_version_minor);
1259 switch (soc_hw_version_major) {
1260 case ATH12K_PCI_SOC_HW_VERSION_2:
1261 ab->hw_rev = ATH12K_HW_WCN7850_HW20;
1262 break;
1263 default:
1264 dev_err(&pdev->dev,
1265 "Unknown hardware version found for WCN7850: 0x%x\n",
1266 soc_hw_version_major);
1267 ret = -EOPNOTSUPP;
1268 goto err_pci_free_region;
1269 }
1270 break;
1271
1272 default:
1273 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n",
1274 pci_dev->device);
1275 ret = -EOPNOTSUPP;
1276 goto err_pci_free_region;
1277 }
1278
1279 ret = ath12k_pci_msi_alloc(ab_pci);
1280 if (ret) {
1281 ath12k_err(ab, "failed to alloc msi: %d\n", ret);
1282 goto err_pci_free_region;
1283 }
1284
1285 ret = ath12k_core_pre_init(ab);
1286 if (ret)
1287 goto err_pci_msi_free;
1288
1289 ret = ath12k_mhi_register(ab_pci);
1290 if (ret) {
1291 ath12k_err(ab, "failed to register mhi: %d\n", ret);
1292 goto err_pci_msi_free;
1293 }
1294
1295 ret = ath12k_hal_srng_init(ab);
1296 if (ret)
1297 goto err_mhi_unregister;
1298
1299 ret = ath12k_ce_alloc_pipes(ab);
1300 if (ret) {
1301 ath12k_err(ab, "failed to allocate ce pipes: %d\n", ret);
1302 goto err_hal_srng_deinit;
1303 }
1304
1305 ath12k_pci_init_qmi_ce_config(ab);
1306
1307 ret = ath12k_pci_config_irq(ab);
1308 if (ret) {
1309 ath12k_err(ab, "failed to config irq: %d\n", ret);
1310 goto err_ce_free;
1311 }
1312
1313 ret = ath12k_core_init(ab);
1314 if (ret) {
1315 ath12k_err(ab, "failed to init core: %d\n", ret);
1316 goto err_free_irq;
1317 }
1318 return 0;
1319
1320 err_free_irq:
1321 ath12k_pci_free_irq(ab);
1322
1323 err_ce_free:
1324 ath12k_ce_free_pipes(ab);
1325
1326 err_hal_srng_deinit:
1327 ath12k_hal_srng_deinit(ab);
1328
1329 err_mhi_unregister:
1330 ath12k_mhi_unregister(ab_pci);
1331
1332 err_pci_msi_free:
1333 ath12k_pci_msi_free(ab_pci);
1334
1335 err_pci_free_region:
1336 ath12k_pci_free_region(ab_pci);
1337
1338 err_free_core:
1339 ath12k_core_free(ab);
1340
1341 return ret;
1342 }
1343
ath12k_pci_remove(struct pci_dev * pdev)1344 static void ath12k_pci_remove(struct pci_dev *pdev)
1345 {
1346 struct ath12k_base *ab = pci_get_drvdata(pdev);
1347 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1348
1349 if (test_bit(ATH12K_FLAG_QMI_FAIL, &ab->dev_flags)) {
1350 ath12k_pci_power_down(ab);
1351 ath12k_qmi_deinit_service(ab);
1352 goto qmi_fail;
1353 }
1354
1355 set_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags);
1356
1357 cancel_work_sync(&ab->reset_work);
1358 ath12k_core_deinit(ab);
1359
1360 qmi_fail:
1361 ath12k_mhi_unregister(ab_pci);
1362
1363 ath12k_pci_free_irq(ab);
1364 ath12k_pci_msi_free(ab_pci);
1365 ath12k_pci_free_region(ab_pci);
1366
1367 ath12k_hal_srng_deinit(ab);
1368 ath12k_ce_free_pipes(ab);
1369 ath12k_core_free(ab);
1370 }
1371
ath12k_pci_shutdown(struct pci_dev * pdev)1372 static void ath12k_pci_shutdown(struct pci_dev *pdev)
1373 {
1374 struct ath12k_base *ab = pci_get_drvdata(pdev);
1375
1376 ath12k_pci_power_down(ab);
1377 }
1378
ath12k_pci_pm_suspend(struct device * dev)1379 static __maybe_unused int ath12k_pci_pm_suspend(struct device *dev)
1380 {
1381 struct ath12k_base *ab = dev_get_drvdata(dev);
1382 int ret;
1383
1384 ret = ath12k_core_suspend(ab);
1385 if (ret)
1386 ath12k_warn(ab, "failed to suspend core: %d\n", ret);
1387
1388 return ret;
1389 }
1390
ath12k_pci_pm_resume(struct device * dev)1391 static __maybe_unused int ath12k_pci_pm_resume(struct device *dev)
1392 {
1393 struct ath12k_base *ab = dev_get_drvdata(dev);
1394 int ret;
1395
1396 ret = ath12k_core_resume(ab);
1397 if (ret)
1398 ath12k_warn(ab, "failed to resume core: %d\n", ret);
1399
1400 return ret;
1401 }
1402
1403 static SIMPLE_DEV_PM_OPS(ath12k_pci_pm_ops,
1404 ath12k_pci_pm_suspend,
1405 ath12k_pci_pm_resume);
1406
1407 static struct pci_driver ath12k_pci_driver = {
1408 .name = "ath12k_pci",
1409 .id_table = ath12k_pci_id_table,
1410 .probe = ath12k_pci_probe,
1411 .remove = ath12k_pci_remove,
1412 .shutdown = ath12k_pci_shutdown,
1413 .driver.pm = &ath12k_pci_pm_ops,
1414 };
1415
ath12k_pci_init(void)1416 static int ath12k_pci_init(void)
1417 {
1418 int ret;
1419
1420 ret = pci_register_driver(&ath12k_pci_driver);
1421 if (ret) {
1422 pr_err("failed to register ath12k pci driver: %d\n",
1423 ret);
1424 return ret;
1425 }
1426
1427 return 0;
1428 }
1429 module_init(ath12k_pci_init);
1430
ath12k_pci_exit(void)1431 static void ath12k_pci_exit(void)
1432 {
1433 pci_unregister_driver(&ath12k_pci_driver);
1434 }
1435
1436 module_exit(ath12k_pci_exit);
1437
1438 MODULE_DESCRIPTION("Driver support for Qualcomm Technologies PCIe 802.11be WLAN devices");
1439 MODULE_LICENSE("Dual BSD/GPL");
1440