1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/msi.h>
8 #include <linux/pci.h>
9
10 #include "core.h"
11 #include "debug.h"
12 #include "mhi.h"
13 #include "pci.h"
14
15 #define MHI_TIMEOUT_DEFAULT_MS 90000
16
17 static const struct mhi_channel_config ath12k_mhi_channels_qcn9274[] = {
18 {
19 .num = 0,
20 .name = "LOOPBACK",
21 .num_elements = 32,
22 .event_ring = 1,
23 .dir = DMA_TO_DEVICE,
24 .ee_mask = 0x4,
25 .pollcfg = 0,
26 .doorbell = MHI_DB_BRST_DISABLE,
27 .lpm_notify = false,
28 .offload_channel = false,
29 .doorbell_mode_switch = false,
30 .auto_queue = false,
31 },
32 {
33 .num = 1,
34 .name = "LOOPBACK",
35 .num_elements = 32,
36 .event_ring = 1,
37 .dir = DMA_FROM_DEVICE,
38 .ee_mask = 0x4,
39 .pollcfg = 0,
40 .doorbell = MHI_DB_BRST_DISABLE,
41 .lpm_notify = false,
42 .offload_channel = false,
43 .doorbell_mode_switch = false,
44 .auto_queue = false,
45 },
46 {
47 .num = 20,
48 .name = "IPCR",
49 .num_elements = 32,
50 .event_ring = 1,
51 .dir = DMA_TO_DEVICE,
52 .ee_mask = 0x4,
53 .pollcfg = 0,
54 .doorbell = MHI_DB_BRST_DISABLE,
55 .lpm_notify = false,
56 .offload_channel = false,
57 .doorbell_mode_switch = false,
58 .auto_queue = false,
59 },
60 {
61 .num = 21,
62 .name = "IPCR",
63 .num_elements = 32,
64 .event_ring = 1,
65 .dir = DMA_FROM_DEVICE,
66 .ee_mask = 0x4,
67 .pollcfg = 0,
68 .doorbell = MHI_DB_BRST_DISABLE,
69 .lpm_notify = false,
70 .offload_channel = false,
71 .doorbell_mode_switch = false,
72 .auto_queue = true,
73 },
74 };
75
76 static struct mhi_event_config ath12k_mhi_events_qcn9274[] = {
77 {
78 .num_elements = 32,
79 .irq_moderation_ms = 0,
80 .irq = 1,
81 .data_type = MHI_ER_CTRL,
82 .mode = MHI_DB_BRST_DISABLE,
83 .hardware_event = false,
84 .client_managed = false,
85 .offload_channel = false,
86 },
87 {
88 .num_elements = 256,
89 .irq_moderation_ms = 1,
90 .irq = 2,
91 .mode = MHI_DB_BRST_DISABLE,
92 .priority = 1,
93 .hardware_event = false,
94 .client_managed = false,
95 .offload_channel = false,
96 },
97 };
98
99 const struct mhi_controller_config ath12k_mhi_config_qcn9274 = {
100 .max_channels = 30,
101 .timeout_ms = 10000,
102 .use_bounce_buf = false,
103 .buf_len = 0,
104 .num_channels = ARRAY_SIZE(ath12k_mhi_channels_qcn9274),
105 .ch_cfg = ath12k_mhi_channels_qcn9274,
106 .num_events = ARRAY_SIZE(ath12k_mhi_events_qcn9274),
107 .event_cfg = ath12k_mhi_events_qcn9274,
108 };
109
110 static const struct mhi_channel_config ath12k_mhi_channels_wcn7850[] = {
111 {
112 .num = 0,
113 .name = "LOOPBACK",
114 .num_elements = 32,
115 .event_ring = 0,
116 .dir = DMA_TO_DEVICE,
117 .ee_mask = 0x4,
118 .pollcfg = 0,
119 .doorbell = MHI_DB_BRST_DISABLE,
120 .lpm_notify = false,
121 .offload_channel = false,
122 .doorbell_mode_switch = false,
123 .auto_queue = false,
124 },
125 {
126 .num = 1,
127 .name = "LOOPBACK",
128 .num_elements = 32,
129 .event_ring = 0,
130 .dir = DMA_FROM_DEVICE,
131 .ee_mask = 0x4,
132 .pollcfg = 0,
133 .doorbell = MHI_DB_BRST_DISABLE,
134 .lpm_notify = false,
135 .offload_channel = false,
136 .doorbell_mode_switch = false,
137 .auto_queue = false,
138 },
139 {
140 .num = 20,
141 .name = "IPCR",
142 .num_elements = 64,
143 .event_ring = 1,
144 .dir = DMA_TO_DEVICE,
145 .ee_mask = 0x4,
146 .pollcfg = 0,
147 .doorbell = MHI_DB_BRST_DISABLE,
148 .lpm_notify = false,
149 .offload_channel = false,
150 .doorbell_mode_switch = false,
151 .auto_queue = false,
152 },
153 {
154 .num = 21,
155 .name = "IPCR",
156 .num_elements = 64,
157 .event_ring = 1,
158 .dir = DMA_FROM_DEVICE,
159 .ee_mask = 0x4,
160 .pollcfg = 0,
161 .doorbell = MHI_DB_BRST_DISABLE,
162 .lpm_notify = false,
163 .offload_channel = false,
164 .doorbell_mode_switch = false,
165 .auto_queue = true,
166 },
167 };
168
169 static struct mhi_event_config ath12k_mhi_events_wcn7850[] = {
170 {
171 .num_elements = 32,
172 .irq_moderation_ms = 0,
173 .irq = 1,
174 .mode = MHI_DB_BRST_DISABLE,
175 .data_type = MHI_ER_CTRL,
176 .hardware_event = false,
177 .client_managed = false,
178 .offload_channel = false,
179 },
180 {
181 .num_elements = 256,
182 .irq_moderation_ms = 1,
183 .irq = 2,
184 .mode = MHI_DB_BRST_DISABLE,
185 .priority = 1,
186 .hardware_event = false,
187 .client_managed = false,
188 .offload_channel = false,
189 },
190 };
191
192 const struct mhi_controller_config ath12k_mhi_config_wcn7850 = {
193 .max_channels = 128,
194 .timeout_ms = 2000,
195 .use_bounce_buf = false,
196 .buf_len = 0,
197 .num_channels = ARRAY_SIZE(ath12k_mhi_channels_wcn7850),
198 .ch_cfg = ath12k_mhi_channels_wcn7850,
199 .num_events = ARRAY_SIZE(ath12k_mhi_events_wcn7850),
200 .event_cfg = ath12k_mhi_events_wcn7850,
201 };
202
ath12k_mhi_set_mhictrl_reset(struct ath12k_base * ab)203 void ath12k_mhi_set_mhictrl_reset(struct ath12k_base *ab)
204 {
205 u32 val;
206
207 val = ath12k_pci_read32(ab, MHISTATUS);
208
209 ath12k_dbg(ab, ATH12K_DBG_PCI, "MHISTATUS 0x%x\n", val);
210
211 /* Observed on some targets that after SOC_GLOBAL_RESET, MHISTATUS
212 * has SYSERR bit set and thus need to set MHICTRL_RESET
213 * to clear SYSERR.
214 */
215 ath12k_pci_write32(ab, MHICTRL, MHICTRL_RESET_MASK);
216
217 mdelay(10);
218 }
219
ath12k_mhi_reset_txvecdb(struct ath12k_base * ab)220 static void ath12k_mhi_reset_txvecdb(struct ath12k_base *ab)
221 {
222 ath12k_pci_write32(ab, PCIE_TXVECDB, 0);
223 }
224
ath12k_mhi_reset_txvecstatus(struct ath12k_base * ab)225 static void ath12k_mhi_reset_txvecstatus(struct ath12k_base *ab)
226 {
227 ath12k_pci_write32(ab, PCIE_TXVECSTATUS, 0);
228 }
229
ath12k_mhi_reset_rxvecdb(struct ath12k_base * ab)230 static void ath12k_mhi_reset_rxvecdb(struct ath12k_base *ab)
231 {
232 ath12k_pci_write32(ab, PCIE_RXVECDB, 0);
233 }
234
ath12k_mhi_reset_rxvecstatus(struct ath12k_base * ab)235 static void ath12k_mhi_reset_rxvecstatus(struct ath12k_base *ab)
236 {
237 ath12k_pci_write32(ab, PCIE_RXVECSTATUS, 0);
238 }
239
ath12k_mhi_clear_vector(struct ath12k_base * ab)240 void ath12k_mhi_clear_vector(struct ath12k_base *ab)
241 {
242 ath12k_mhi_reset_txvecdb(ab);
243 ath12k_mhi_reset_txvecstatus(ab);
244 ath12k_mhi_reset_rxvecdb(ab);
245 ath12k_mhi_reset_rxvecstatus(ab);
246 }
247
ath12k_mhi_get_msi(struct ath12k_pci * ab_pci)248 static int ath12k_mhi_get_msi(struct ath12k_pci *ab_pci)
249 {
250 struct ath12k_base *ab = ab_pci->ab;
251 u32 user_base_data, base_vector;
252 int ret, num_vectors, i;
253 int *irq;
254
255 ret = ath12k_pci_get_user_msi_assignment(ab,
256 "MHI", &num_vectors,
257 &user_base_data, &base_vector);
258 if (ret)
259 return ret;
260
261 ath12k_dbg(ab, ATH12K_DBG_PCI, "Number of assigned MSI for MHI is %d, base vector is %d\n",
262 num_vectors, base_vector);
263
264 irq = kcalloc(num_vectors, sizeof(*irq), GFP_KERNEL);
265 if (!irq)
266 return -ENOMEM;
267
268 for (i = 0; i < num_vectors; i++)
269 irq[i] = ath12k_pci_get_msi_irq(ab->dev,
270 base_vector + i);
271
272 ab_pci->mhi_ctrl->irq = irq;
273 ab_pci->mhi_ctrl->nr_irqs = num_vectors;
274
275 return 0;
276 }
277
ath12k_mhi_op_runtime_get(struct mhi_controller * mhi_cntrl)278 static int ath12k_mhi_op_runtime_get(struct mhi_controller *mhi_cntrl)
279 {
280 return 0;
281 }
282
ath12k_mhi_op_runtime_put(struct mhi_controller * mhi_cntrl)283 static void ath12k_mhi_op_runtime_put(struct mhi_controller *mhi_cntrl)
284 {
285 }
286
ath12k_mhi_op_callback_to_str(enum mhi_callback reason)287 static char *ath12k_mhi_op_callback_to_str(enum mhi_callback reason)
288 {
289 switch (reason) {
290 case MHI_CB_IDLE:
291 return "MHI_CB_IDLE";
292 case MHI_CB_PENDING_DATA:
293 return "MHI_CB_PENDING_DATA";
294 case MHI_CB_LPM_ENTER:
295 return "MHI_CB_LPM_ENTER";
296 case MHI_CB_LPM_EXIT:
297 return "MHI_CB_LPM_EXIT";
298 case MHI_CB_EE_RDDM:
299 return "MHI_CB_EE_RDDM";
300 case MHI_CB_EE_MISSION_MODE:
301 return "MHI_CB_EE_MISSION_MODE";
302 case MHI_CB_SYS_ERROR:
303 return "MHI_CB_SYS_ERROR";
304 case MHI_CB_FATAL_ERROR:
305 return "MHI_CB_FATAL_ERROR";
306 case MHI_CB_BW_REQ:
307 return "MHI_CB_BW_REQ";
308 default:
309 return "UNKNOWN";
310 }
311 }
312
ath12k_mhi_op_status_cb(struct mhi_controller * mhi_cntrl,enum mhi_callback cb)313 static void ath12k_mhi_op_status_cb(struct mhi_controller *mhi_cntrl,
314 enum mhi_callback cb)
315 {
316 struct ath12k_base *ab = dev_get_drvdata(mhi_cntrl->cntrl_dev);
317
318 ath12k_dbg(ab, ATH12K_DBG_BOOT, "mhi notify status reason %s\n",
319 ath12k_mhi_op_callback_to_str(cb));
320
321 switch (cb) {
322 case MHI_CB_SYS_ERROR:
323 ath12k_warn(ab, "firmware crashed: MHI_CB_SYS_ERROR\n");
324 break;
325 case MHI_CB_EE_RDDM:
326 if (!(test_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags)))
327 queue_work(ab->workqueue_aux, &ab->reset_work);
328 break;
329 default:
330 break;
331 }
332 }
333
ath12k_mhi_op_read_reg(struct mhi_controller * mhi_cntrl,void __iomem * addr,u32 * out)334 static int ath12k_mhi_op_read_reg(struct mhi_controller *mhi_cntrl,
335 void __iomem *addr,
336 u32 *out)
337 {
338 *out = readl(addr);
339
340 return 0;
341 }
342
ath12k_mhi_op_write_reg(struct mhi_controller * mhi_cntrl,void __iomem * addr,u32 val)343 static void ath12k_mhi_op_write_reg(struct mhi_controller *mhi_cntrl,
344 void __iomem *addr,
345 u32 val)
346 {
347 writel(val, addr);
348 }
349
ath12k_mhi_register(struct ath12k_pci * ab_pci)350 int ath12k_mhi_register(struct ath12k_pci *ab_pci)
351 {
352 struct ath12k_base *ab = ab_pci->ab;
353 struct mhi_controller *mhi_ctrl;
354 int ret;
355
356 mhi_ctrl = mhi_alloc_controller();
357 if (!mhi_ctrl)
358 return -ENOMEM;
359
360 ath12k_core_create_firmware_path(ab, ATH12K_AMSS_FILE,
361 ab_pci->amss_path,
362 sizeof(ab_pci->amss_path));
363
364 ab_pci->mhi_ctrl = mhi_ctrl;
365 mhi_ctrl->cntrl_dev = ab->dev;
366 mhi_ctrl->fw_image = ab_pci->amss_path;
367 mhi_ctrl->regs = ab->mem;
368 mhi_ctrl->reg_len = ab->mem_len;
369
370 ret = ath12k_mhi_get_msi(ab_pci);
371 if (ret) {
372 ath12k_err(ab, "failed to get msi for mhi\n");
373 goto free_controller;
374 }
375
376 mhi_ctrl->iova_start = 0;
377 mhi_ctrl->iova_stop = 0xffffffff;
378 mhi_ctrl->sbl_size = SZ_512K;
379 mhi_ctrl->seg_len = SZ_512K;
380 mhi_ctrl->fbc_download = true;
381 mhi_ctrl->runtime_get = ath12k_mhi_op_runtime_get;
382 mhi_ctrl->runtime_put = ath12k_mhi_op_runtime_put;
383 mhi_ctrl->status_cb = ath12k_mhi_op_status_cb;
384 mhi_ctrl->read_reg = ath12k_mhi_op_read_reg;
385 mhi_ctrl->write_reg = ath12k_mhi_op_write_reg;
386
387 ret = mhi_register_controller(mhi_ctrl, ab->hw_params->mhi_config);
388 if (ret) {
389 ath12k_err(ab, "failed to register to mhi bus, err = %d\n", ret);
390 goto free_controller;
391 }
392
393 return 0;
394
395 free_controller:
396 mhi_free_controller(mhi_ctrl);
397 ab_pci->mhi_ctrl = NULL;
398 return ret;
399 }
400
ath12k_mhi_unregister(struct ath12k_pci * ab_pci)401 void ath12k_mhi_unregister(struct ath12k_pci *ab_pci)
402 {
403 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl;
404
405 mhi_unregister_controller(mhi_ctrl);
406 kfree(mhi_ctrl->irq);
407 mhi_free_controller(mhi_ctrl);
408 ab_pci->mhi_ctrl = NULL;
409 }
410
ath12k_mhi_state_to_str(enum ath12k_mhi_state mhi_state)411 static char *ath12k_mhi_state_to_str(enum ath12k_mhi_state mhi_state)
412 {
413 switch (mhi_state) {
414 case ATH12K_MHI_INIT:
415 return "INIT";
416 case ATH12K_MHI_DEINIT:
417 return "DEINIT";
418 case ATH12K_MHI_POWER_ON:
419 return "POWER_ON";
420 case ATH12K_MHI_POWER_OFF:
421 return "POWER_OFF";
422 case ATH12K_MHI_FORCE_POWER_OFF:
423 return "FORCE_POWER_OFF";
424 case ATH12K_MHI_SUSPEND:
425 return "SUSPEND";
426 case ATH12K_MHI_RESUME:
427 return "RESUME";
428 case ATH12K_MHI_TRIGGER_RDDM:
429 return "TRIGGER_RDDM";
430 case ATH12K_MHI_RDDM_DONE:
431 return "RDDM_DONE";
432 default:
433 return "UNKNOWN";
434 }
435 };
436
ath12k_mhi_set_state_bit(struct ath12k_pci * ab_pci,enum ath12k_mhi_state mhi_state)437 static void ath12k_mhi_set_state_bit(struct ath12k_pci *ab_pci,
438 enum ath12k_mhi_state mhi_state)
439 {
440 struct ath12k_base *ab = ab_pci->ab;
441
442 switch (mhi_state) {
443 case ATH12K_MHI_INIT:
444 set_bit(ATH12K_MHI_INIT, &ab_pci->mhi_state);
445 break;
446 case ATH12K_MHI_DEINIT:
447 clear_bit(ATH12K_MHI_INIT, &ab_pci->mhi_state);
448 break;
449 case ATH12K_MHI_POWER_ON:
450 set_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state);
451 break;
452 case ATH12K_MHI_POWER_OFF:
453 case ATH12K_MHI_FORCE_POWER_OFF:
454 clear_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state);
455 clear_bit(ATH12K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state);
456 clear_bit(ATH12K_MHI_RDDM_DONE, &ab_pci->mhi_state);
457 break;
458 case ATH12K_MHI_SUSPEND:
459 set_bit(ATH12K_MHI_SUSPEND, &ab_pci->mhi_state);
460 break;
461 case ATH12K_MHI_RESUME:
462 clear_bit(ATH12K_MHI_SUSPEND, &ab_pci->mhi_state);
463 break;
464 case ATH12K_MHI_TRIGGER_RDDM:
465 set_bit(ATH12K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state);
466 break;
467 case ATH12K_MHI_RDDM_DONE:
468 set_bit(ATH12K_MHI_RDDM_DONE, &ab_pci->mhi_state);
469 break;
470 default:
471 ath12k_err(ab, "unhandled mhi state (%d)\n", mhi_state);
472 }
473 }
474
ath12k_mhi_check_state_bit(struct ath12k_pci * ab_pci,enum ath12k_mhi_state mhi_state)475 static int ath12k_mhi_check_state_bit(struct ath12k_pci *ab_pci,
476 enum ath12k_mhi_state mhi_state)
477 {
478 struct ath12k_base *ab = ab_pci->ab;
479
480 switch (mhi_state) {
481 case ATH12K_MHI_INIT:
482 if (!test_bit(ATH12K_MHI_INIT, &ab_pci->mhi_state))
483 return 0;
484 break;
485 case ATH12K_MHI_DEINIT:
486 case ATH12K_MHI_POWER_ON:
487 if (test_bit(ATH12K_MHI_INIT, &ab_pci->mhi_state) &&
488 !test_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state))
489 return 0;
490 break;
491 case ATH12K_MHI_FORCE_POWER_OFF:
492 if (test_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state))
493 return 0;
494 break;
495 case ATH12K_MHI_POWER_OFF:
496 case ATH12K_MHI_SUSPEND:
497 if (test_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state) &&
498 !test_bit(ATH12K_MHI_SUSPEND, &ab_pci->mhi_state))
499 return 0;
500 break;
501 case ATH12K_MHI_RESUME:
502 if (test_bit(ATH12K_MHI_SUSPEND, &ab_pci->mhi_state))
503 return 0;
504 break;
505 case ATH12K_MHI_TRIGGER_RDDM:
506 if (test_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state) &&
507 !test_bit(ATH12K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state))
508 return 0;
509 break;
510 case ATH12K_MHI_RDDM_DONE:
511 return 0;
512 default:
513 ath12k_err(ab, "unhandled mhi state: %s(%d)\n",
514 ath12k_mhi_state_to_str(mhi_state), mhi_state);
515 }
516
517 ath12k_err(ab, "failed to set mhi state %s(%d) in current mhi state (0x%lx)\n",
518 ath12k_mhi_state_to_str(mhi_state), mhi_state,
519 ab_pci->mhi_state);
520
521 return -EINVAL;
522 }
523
ath12k_mhi_set_state(struct ath12k_pci * ab_pci,enum ath12k_mhi_state mhi_state)524 static int ath12k_mhi_set_state(struct ath12k_pci *ab_pci,
525 enum ath12k_mhi_state mhi_state)
526 {
527 struct ath12k_base *ab = ab_pci->ab;
528 int ret;
529
530 ret = ath12k_mhi_check_state_bit(ab_pci, mhi_state);
531 if (ret)
532 goto out;
533
534 ath12k_dbg(ab, ATH12K_DBG_PCI, "setting mhi state: %s(%d)\n",
535 ath12k_mhi_state_to_str(mhi_state), mhi_state);
536
537 switch (mhi_state) {
538 case ATH12K_MHI_INIT:
539 ret = mhi_prepare_for_power_up(ab_pci->mhi_ctrl);
540 break;
541 case ATH12K_MHI_DEINIT:
542 mhi_unprepare_after_power_down(ab_pci->mhi_ctrl);
543 ret = 0;
544 break;
545 case ATH12K_MHI_POWER_ON:
546 ret = mhi_async_power_up(ab_pci->mhi_ctrl);
547 break;
548 case ATH12K_MHI_POWER_OFF:
549 mhi_power_down(ab_pci->mhi_ctrl, true);
550 ret = 0;
551 break;
552 case ATH12K_MHI_FORCE_POWER_OFF:
553 mhi_power_down(ab_pci->mhi_ctrl, false);
554 ret = 0;
555 break;
556 case ATH12K_MHI_SUSPEND:
557 ret = mhi_pm_suspend(ab_pci->mhi_ctrl);
558 break;
559 case ATH12K_MHI_RESUME:
560 ret = mhi_pm_resume(ab_pci->mhi_ctrl);
561 break;
562 case ATH12K_MHI_TRIGGER_RDDM:
563 ret = mhi_force_rddm_mode(ab_pci->mhi_ctrl);
564 break;
565 case ATH12K_MHI_RDDM_DONE:
566 break;
567 default:
568 ath12k_err(ab, "unhandled MHI state (%d)\n", mhi_state);
569 ret = -EINVAL;
570 }
571
572 if (ret)
573 goto out;
574
575 ath12k_mhi_set_state_bit(ab_pci, mhi_state);
576
577 return 0;
578
579 out:
580 ath12k_err(ab, "failed to set mhi state: %s(%d)\n",
581 ath12k_mhi_state_to_str(mhi_state), mhi_state);
582 return ret;
583 }
584
ath12k_mhi_start(struct ath12k_pci * ab_pci)585 int ath12k_mhi_start(struct ath12k_pci *ab_pci)
586 {
587 int ret;
588
589 ab_pci->mhi_ctrl->timeout_ms = MHI_TIMEOUT_DEFAULT_MS;
590
591 ret = ath12k_mhi_set_state(ab_pci, ATH12K_MHI_INIT);
592 if (ret)
593 goto out;
594
595 ret = ath12k_mhi_set_state(ab_pci, ATH12K_MHI_POWER_ON);
596 if (ret)
597 goto out;
598
599 return 0;
600
601 out:
602 return ret;
603 }
604
ath12k_mhi_stop(struct ath12k_pci * ab_pci)605 void ath12k_mhi_stop(struct ath12k_pci *ab_pci)
606 {
607 ath12k_mhi_set_state(ab_pci, ATH12K_MHI_POWER_OFF);
608 ath12k_mhi_set_state(ab_pci, ATH12K_MHI_DEINIT);
609 }
610
ath12k_mhi_suspend(struct ath12k_pci * ab_pci)611 void ath12k_mhi_suspend(struct ath12k_pci *ab_pci)
612 {
613 ath12k_mhi_set_state(ab_pci, ATH12K_MHI_SUSPEND);
614 }
615
ath12k_mhi_resume(struct ath12k_pci * ab_pci)616 void ath12k_mhi_resume(struct ath12k_pci *ab_pci)
617 {
618 ath12k_mhi_set_state(ab_pci, ATH12K_MHI_RESUME);
619 }
620