1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include "debug.h"
8 #include "hal.h"
9 #include "hal_tx.h"
10 #include "hal_rx.h"
11 #include "hal_desc.h"
12 #include "hif.h"
13
ath11k_hal_reo_set_desc_hdr(struct hal_desc_header * hdr,u8 owner,u8 buffer_type,u32 magic)14 static void ath11k_hal_reo_set_desc_hdr(struct hal_desc_header *hdr,
15 u8 owner, u8 buffer_type, u32 magic)
16 {
17 hdr->info0 = FIELD_PREP(HAL_DESC_HDR_INFO0_OWNER, owner) |
18 FIELD_PREP(HAL_DESC_HDR_INFO0_BUF_TYPE, buffer_type);
19
20 /* Magic pattern in reserved bits for debugging */
21 hdr->info0 |= FIELD_PREP(HAL_DESC_HDR_INFO0_DBG_RESERVED, magic);
22 }
23
ath11k_hal_reo_cmd_queue_stats(struct hal_tlv_hdr * tlv,struct ath11k_hal_reo_cmd * cmd)24 static int ath11k_hal_reo_cmd_queue_stats(struct hal_tlv_hdr *tlv,
25 struct ath11k_hal_reo_cmd *cmd)
26 {
27 struct hal_reo_get_queue_stats *desc;
28
29 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_REO_GET_QUEUE_STATS) |
30 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc));
31
32 desc = (struct hal_reo_get_queue_stats *)tlv->value;
33 memset_startat(desc, 0, queue_addr_lo);
34
35 desc->cmd.info0 &= ~HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
36 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS)
37 desc->cmd.info0 |= HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
38
39 desc->queue_addr_lo = cmd->addr_lo;
40 desc->info0 = FIELD_PREP(HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI,
41 cmd->addr_hi);
42 if (cmd->flag & HAL_REO_CMD_FLG_STATS_CLEAR)
43 desc->info0 |= HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS;
44
45 return FIELD_GET(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, desc->cmd.info0);
46 }
47
ath11k_hal_reo_cmd_flush_cache(struct ath11k_hal * hal,struct hal_tlv_hdr * tlv,struct ath11k_hal_reo_cmd * cmd)48 static int ath11k_hal_reo_cmd_flush_cache(struct ath11k_hal *hal, struct hal_tlv_hdr *tlv,
49 struct ath11k_hal_reo_cmd *cmd)
50 {
51 struct hal_reo_flush_cache *desc;
52 u8 avail_slot = ffz(hal->avail_blk_resource);
53
54 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER) {
55 if (avail_slot >= HAL_MAX_AVAIL_BLK_RES)
56 return -ENOSPC;
57
58 hal->current_blk_index = avail_slot;
59 }
60
61 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_REO_FLUSH_CACHE) |
62 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc));
63
64 desc = (struct hal_reo_flush_cache *)tlv->value;
65 memset_startat(desc, 0, cache_addr_lo);
66
67 desc->cmd.info0 &= ~HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
68 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS)
69 desc->cmd.info0 |= HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
70
71 desc->cache_addr_lo = cmd->addr_lo;
72 desc->info0 = FIELD_PREP(HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI,
73 cmd->addr_hi);
74
75 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS)
76 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS;
77
78 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER) {
79 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE;
80 desc->info0 |=
81 FIELD_PREP(HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX,
82 avail_slot);
83 }
84
85 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_NO_INVAL)
86 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE;
87
88 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_ALL)
89 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL;
90
91 return FIELD_GET(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, desc->cmd.info0);
92 }
93
ath11k_hal_reo_cmd_update_rx_queue(struct hal_tlv_hdr * tlv,struct ath11k_hal_reo_cmd * cmd)94 static int ath11k_hal_reo_cmd_update_rx_queue(struct hal_tlv_hdr *tlv,
95 struct ath11k_hal_reo_cmd *cmd)
96 {
97 struct hal_reo_update_rx_queue *desc;
98
99 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_REO_UPDATE_RX_REO_QUEUE) |
100 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc));
101
102 desc = (struct hal_reo_update_rx_queue *)tlv->value;
103 memset_startat(desc, 0, queue_addr_lo);
104
105 desc->cmd.info0 &= ~HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
106 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS)
107 desc->cmd.info0 |= HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
108
109 desc->queue_addr_lo = cmd->addr_lo;
110 desc->info0 =
111 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI,
112 cmd->addr_hi) |
113 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM,
114 !!(cmd->upd0 & HAL_REO_CMD_UPD0_RX_QUEUE_NUM)) |
115 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD,
116 !!(cmd->upd0 & HAL_REO_CMD_UPD0_VLD)) |
117 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT,
118 !!(cmd->upd0 & HAL_REO_CMD_UPD0_ALDC)) |
119 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION,
120 !!(cmd->upd0 & HAL_REO_CMD_UPD0_DIS_DUP_DETECTION)) |
121 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN,
122 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SOFT_REORDER_EN)) |
123 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC,
124 !!(cmd->upd0 & HAL_REO_CMD_UPD0_AC)) |
125 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR,
126 !!(cmd->upd0 & HAL_REO_CMD_UPD0_BAR)) |
127 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY,
128 !!(cmd->upd0 & HAL_REO_CMD_UPD0_RETRY)) |
129 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE,
130 !!(cmd->upd0 & HAL_REO_CMD_UPD0_CHECK_2K_MODE)) |
131 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE,
132 !!(cmd->upd0 & HAL_REO_CMD_UPD0_OOR_MODE)) |
133 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE,
134 !!(cmd->upd0 & HAL_REO_CMD_UPD0_BA_WINDOW_SIZE)) |
135 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK,
136 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_CHECK)) |
137 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN,
138 !!(cmd->upd0 & HAL_REO_CMD_UPD0_EVEN_PN)) |
139 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN,
140 !!(cmd->upd0 & HAL_REO_CMD_UPD0_UNEVEN_PN)) |
141 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE,
142 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE)) |
143 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE,
144 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_SIZE)) |
145 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG,
146 !!(cmd->upd0 & HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG)) |
147 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD,
148 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SVLD)) |
149 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN,
150 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SSN)) |
151 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR,
152 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SEQ_2K_ERR)) |
153 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID,
154 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_VALID)) |
155 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN,
156 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN));
157
158 desc->info1 =
159 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER,
160 cmd->rx_queue_num) |
161 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_VLD,
162 !!(cmd->upd1 & HAL_REO_CMD_UPD1_VLD)) |
163 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER,
164 FIELD_GET(HAL_REO_CMD_UPD1_ALDC, cmd->upd1)) |
165 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION,
166 !!(cmd->upd1 & HAL_REO_CMD_UPD1_DIS_DUP_DETECTION)) |
167 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN,
168 !!(cmd->upd1 & HAL_REO_CMD_UPD1_SOFT_REORDER_EN)) |
169 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_AC,
170 FIELD_GET(HAL_REO_CMD_UPD1_AC, cmd->upd1)) |
171 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_BAR,
172 !!(cmd->upd1 & HAL_REO_CMD_UPD1_BAR)) |
173 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE,
174 !!(cmd->upd1 & HAL_REO_CMD_UPD1_CHECK_2K_MODE)) |
175 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_RETRY,
176 !!(cmd->upd1 & HAL_REO_CMD_UPD1_RETRY)) |
177 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE,
178 !!(cmd->upd1 & HAL_REO_CMD_UPD1_OOR_MODE)) |
179 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK,
180 !!(cmd->upd1 & HAL_REO_CMD_UPD1_PN_CHECK)) |
181 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN,
182 !!(cmd->upd1 & HAL_REO_CMD_UPD1_EVEN_PN)) |
183 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN,
184 !!(cmd->upd1 & HAL_REO_CMD_UPD1_UNEVEN_PN)) |
185 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE,
186 !!(cmd->upd1 & HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE)) |
187 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG,
188 !!(cmd->upd1 & HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG));
189
190 if (cmd->pn_size == 24)
191 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_24;
192 else if (cmd->pn_size == 48)
193 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_48;
194 else if (cmd->pn_size == 128)
195 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_128;
196
197 if (cmd->ba_window_size < 1)
198 cmd->ba_window_size = 1;
199
200 if (cmd->ba_window_size == 1)
201 cmd->ba_window_size++;
202
203 desc->info2 =
204 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE,
205 cmd->ba_window_size - 1) |
206 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE, cmd->pn_size) |
207 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_SVLD,
208 !!(cmd->upd2 & HAL_REO_CMD_UPD2_SVLD)) |
209 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_SSN,
210 FIELD_GET(HAL_REO_CMD_UPD2_SSN, cmd->upd2)) |
211 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR,
212 !!(cmd->upd2 & HAL_REO_CMD_UPD2_SEQ_2K_ERR)) |
213 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR,
214 !!(cmd->upd2 & HAL_REO_CMD_UPD2_PN_ERR));
215
216 return FIELD_GET(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, desc->cmd.info0);
217 }
218
ath11k_hal_reo_cmd_send(struct ath11k_base * ab,struct hal_srng * srng,enum hal_reo_cmd_type type,struct ath11k_hal_reo_cmd * cmd)219 int ath11k_hal_reo_cmd_send(struct ath11k_base *ab, struct hal_srng *srng,
220 enum hal_reo_cmd_type type,
221 struct ath11k_hal_reo_cmd *cmd)
222 {
223 struct hal_tlv_hdr *reo_desc;
224 int ret;
225
226 spin_lock_bh(&srng->lock);
227
228 ath11k_hal_srng_access_begin(ab, srng);
229 reo_desc = (struct hal_tlv_hdr *)ath11k_hal_srng_src_get_next_entry(ab, srng);
230 if (!reo_desc) {
231 ret = -ENOBUFS;
232 goto out;
233 }
234
235 switch (type) {
236 case HAL_REO_CMD_GET_QUEUE_STATS:
237 ret = ath11k_hal_reo_cmd_queue_stats(reo_desc, cmd);
238 break;
239 case HAL_REO_CMD_FLUSH_CACHE:
240 ret = ath11k_hal_reo_cmd_flush_cache(&ab->hal, reo_desc, cmd);
241 break;
242 case HAL_REO_CMD_UPDATE_RX_QUEUE:
243 ret = ath11k_hal_reo_cmd_update_rx_queue(reo_desc, cmd);
244 break;
245 case HAL_REO_CMD_FLUSH_QUEUE:
246 case HAL_REO_CMD_UNBLOCK_CACHE:
247 case HAL_REO_CMD_FLUSH_TIMEOUT_LIST:
248 ath11k_warn(ab, "Unsupported reo command %d\n", type);
249 ret = -ENOTSUPP;
250 break;
251 default:
252 ath11k_warn(ab, "Unknown reo command %d\n", type);
253 ret = -EINVAL;
254 break;
255 }
256
257 ath11k_dp_shadow_start_timer(ab, srng, &ab->dp.reo_cmd_timer);
258
259 out:
260 ath11k_hal_srng_access_end(ab, srng);
261 spin_unlock_bh(&srng->lock);
262
263 return ret;
264 }
265
ath11k_hal_rx_buf_addr_info_set(void * desc,dma_addr_t paddr,u32 cookie,u8 manager)266 void ath11k_hal_rx_buf_addr_info_set(void *desc, dma_addr_t paddr,
267 u32 cookie, u8 manager)
268 {
269 struct ath11k_buffer_addr *binfo = (struct ath11k_buffer_addr *)desc;
270 u32 paddr_lo, paddr_hi;
271
272 paddr_lo = lower_32_bits(paddr);
273 paddr_hi = upper_32_bits(paddr);
274 binfo->info0 = FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, paddr_lo);
275 binfo->info1 = FIELD_PREP(BUFFER_ADDR_INFO1_ADDR, paddr_hi) |
276 FIELD_PREP(BUFFER_ADDR_INFO1_SW_COOKIE, cookie) |
277 FIELD_PREP(BUFFER_ADDR_INFO1_RET_BUF_MGR, manager);
278 }
279
ath11k_hal_rx_buf_addr_info_get(void * desc,dma_addr_t * paddr,u32 * cookie,u8 * rbm)280 void ath11k_hal_rx_buf_addr_info_get(void *desc, dma_addr_t *paddr,
281 u32 *cookie, u8 *rbm)
282 {
283 struct ath11k_buffer_addr *binfo = (struct ath11k_buffer_addr *)desc;
284
285 *paddr =
286 (((u64)FIELD_GET(BUFFER_ADDR_INFO1_ADDR, binfo->info1)) << 32) |
287 FIELD_GET(BUFFER_ADDR_INFO0_ADDR, binfo->info0);
288 *cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, binfo->info1);
289 *rbm = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR, binfo->info1);
290 }
291
ath11k_hal_rx_msdu_link_info_get(void * link_desc,u32 * num_msdus,u32 * msdu_cookies,enum hal_rx_buf_return_buf_manager * rbm)292 void ath11k_hal_rx_msdu_link_info_get(void *link_desc, u32 *num_msdus,
293 u32 *msdu_cookies,
294 enum hal_rx_buf_return_buf_manager *rbm)
295 {
296 struct hal_rx_msdu_link *link = (struct hal_rx_msdu_link *)link_desc;
297 struct hal_rx_msdu_details *msdu;
298 int i;
299
300 *num_msdus = HAL_NUM_RX_MSDUS_PER_LINK_DESC;
301
302 msdu = &link->msdu_link[0];
303 *rbm = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
304 msdu->buf_addr_info.info1);
305
306 for (i = 0; i < *num_msdus; i++) {
307 msdu = &link->msdu_link[i];
308
309 if (!FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
310 msdu->buf_addr_info.info0)) {
311 *num_msdus = i;
312 break;
313 }
314 *msdu_cookies = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
315 msdu->buf_addr_info.info1);
316 msdu_cookies++;
317 }
318 }
319
ath11k_hal_desc_reo_parse_err(struct ath11k_base * ab,u32 * rx_desc,dma_addr_t * paddr,u32 * desc_bank)320 int ath11k_hal_desc_reo_parse_err(struct ath11k_base *ab, u32 *rx_desc,
321 dma_addr_t *paddr, u32 *desc_bank)
322 {
323 struct hal_reo_dest_ring *desc = (struct hal_reo_dest_ring *)rx_desc;
324 enum hal_reo_dest_ring_push_reason push_reason;
325 enum hal_reo_dest_ring_error_code err_code;
326
327 push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON,
328 desc->info0);
329 err_code = FIELD_GET(HAL_REO_DEST_RING_INFO0_ERROR_CODE,
330 desc->info0);
331 ab->soc_stats.reo_error[err_code]++;
332
333 if (push_reason != HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED &&
334 push_reason != HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) {
335 ath11k_warn(ab, "expected error push reason code, received %d\n",
336 push_reason);
337 return -EINVAL;
338 }
339
340 if (FIELD_GET(HAL_REO_DEST_RING_INFO0_BUFFER_TYPE, desc->info0) !=
341 HAL_REO_DEST_RING_BUFFER_TYPE_LINK_DESC) {
342 ath11k_warn(ab, "expected buffer type link_desc");
343 return -EINVAL;
344 }
345
346 ath11k_hal_rx_reo_ent_paddr_get(ab, rx_desc, paddr, desc_bank);
347
348 return 0;
349 }
350
ath11k_hal_wbm_desc_parse_err(struct ath11k_base * ab,void * desc,struct hal_rx_wbm_rel_info * rel_info)351 int ath11k_hal_wbm_desc_parse_err(struct ath11k_base *ab, void *desc,
352 struct hal_rx_wbm_rel_info *rel_info)
353 {
354 struct hal_wbm_release_ring *wbm_desc = desc;
355 enum hal_wbm_rel_desc_type type;
356 enum hal_wbm_rel_src_module rel_src;
357 enum hal_rx_buf_return_buf_manager ret_buf_mgr;
358
359 type = FIELD_GET(HAL_WBM_RELEASE_INFO0_DESC_TYPE,
360 wbm_desc->info0);
361 /* We expect only WBM_REL buffer type */
362 if (type != HAL_WBM_REL_DESC_TYPE_REL_MSDU) {
363 WARN_ON(1);
364 return -EINVAL;
365 }
366
367 rel_src = FIELD_GET(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE,
368 wbm_desc->info0);
369 if (rel_src != HAL_WBM_REL_SRC_MODULE_RXDMA &&
370 rel_src != HAL_WBM_REL_SRC_MODULE_REO)
371 return -EINVAL;
372
373 ret_buf_mgr = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
374 wbm_desc->buf_addr_info.info1);
375 if (ret_buf_mgr != HAL_RX_BUF_RBM_SW3_BM) {
376 ab->soc_stats.invalid_rbm++;
377 return -EINVAL;
378 }
379
380 rel_info->cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
381 wbm_desc->buf_addr_info.info1);
382 rel_info->err_rel_src = rel_src;
383 if (rel_src == HAL_WBM_REL_SRC_MODULE_REO) {
384 rel_info->push_reason =
385 FIELD_GET(HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON,
386 wbm_desc->info0);
387 rel_info->err_code =
388 FIELD_GET(HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE,
389 wbm_desc->info0);
390 } else {
391 rel_info->push_reason =
392 FIELD_GET(HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON,
393 wbm_desc->info0);
394 rel_info->err_code =
395 FIELD_GET(HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE,
396 wbm_desc->info0);
397 }
398
399 rel_info->first_msdu = FIELD_GET(HAL_WBM_RELEASE_INFO2_FIRST_MSDU,
400 wbm_desc->info2);
401 rel_info->last_msdu = FIELD_GET(HAL_WBM_RELEASE_INFO2_LAST_MSDU,
402 wbm_desc->info2);
403 return 0;
404 }
405
ath11k_hal_rx_reo_ent_paddr_get(struct ath11k_base * ab,void * desc,dma_addr_t * paddr,u32 * desc_bank)406 void ath11k_hal_rx_reo_ent_paddr_get(struct ath11k_base *ab, void *desc,
407 dma_addr_t *paddr, u32 *desc_bank)
408 {
409 struct ath11k_buffer_addr *buff_addr = desc;
410
411 *paddr = ((u64)(FIELD_GET(BUFFER_ADDR_INFO1_ADDR, buff_addr->info1)) << 32) |
412 FIELD_GET(BUFFER_ADDR_INFO0_ADDR, buff_addr->info0);
413
414 *desc_bank = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, buff_addr->info1);
415 }
416
ath11k_hal_rx_msdu_link_desc_set(struct ath11k_base * ab,void * desc,void * link_desc,enum hal_wbm_rel_bm_act action)417 void ath11k_hal_rx_msdu_link_desc_set(struct ath11k_base *ab, void *desc,
418 void *link_desc,
419 enum hal_wbm_rel_bm_act action)
420 {
421 struct hal_wbm_release_ring *dst_desc = desc;
422 struct hal_wbm_release_ring *src_desc = link_desc;
423
424 dst_desc->buf_addr_info = src_desc->buf_addr_info;
425 dst_desc->info0 |= FIELD_PREP(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE,
426 HAL_WBM_REL_SRC_MODULE_SW) |
427 FIELD_PREP(HAL_WBM_RELEASE_INFO0_BM_ACTION, action) |
428 FIELD_PREP(HAL_WBM_RELEASE_INFO0_DESC_TYPE,
429 HAL_WBM_REL_DESC_TYPE_MSDU_LINK);
430 }
431
ath11k_hal_reo_status_queue_stats(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)432 void ath11k_hal_reo_status_queue_stats(struct ath11k_base *ab, u32 *reo_desc,
433 struct hal_reo_status *status)
434 {
435 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
436 struct hal_reo_get_queue_stats_status *desc =
437 (struct hal_reo_get_queue_stats_status *)tlv->value;
438
439 status->uniform_hdr.cmd_num =
440 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
441 desc->hdr.info0);
442 status->uniform_hdr.cmd_status =
443 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
444 desc->hdr.info0);
445
446 ath11k_dbg(ab, ATH11K_DBG_HAL, "Queue stats status:\n");
447 ath11k_dbg(ab, ATH11K_DBG_HAL, "header: cmd_num %d status %d\n",
448 status->uniform_hdr.cmd_num,
449 status->uniform_hdr.cmd_status);
450 ath11k_dbg(ab, ATH11K_DBG_HAL, "ssn %ld cur_idx %ld\n",
451 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN,
452 desc->info0),
453 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX,
454 desc->info0));
455 ath11k_dbg(ab, ATH11K_DBG_HAL, "pn = [%08x, %08x, %08x, %08x]\n",
456 desc->pn[0], desc->pn[1], desc->pn[2], desc->pn[3]);
457 ath11k_dbg(ab, ATH11K_DBG_HAL,
458 "last_rx: enqueue_tstamp %08x dequeue_tstamp %08x\n",
459 desc->last_rx_enqueue_timestamp,
460 desc->last_rx_dequeue_timestamp);
461 ath11k_dbg(ab, ATH11K_DBG_HAL,
462 "rx_bitmap [%08x %08x %08x %08x %08x %08x %08x %08x]\n",
463 desc->rx_bitmap[0], desc->rx_bitmap[1], desc->rx_bitmap[2],
464 desc->rx_bitmap[3], desc->rx_bitmap[4], desc->rx_bitmap[5],
465 desc->rx_bitmap[6], desc->rx_bitmap[7]);
466 ath11k_dbg(ab, ATH11K_DBG_HAL, "count: cur_mpdu %ld cur_msdu %ld\n",
467 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT,
468 desc->info1),
469 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT,
470 desc->info1));
471 ath11k_dbg(ab, ATH11K_DBG_HAL, "fwd_timeout %ld fwd_bar %ld dup_count %ld\n",
472 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT,
473 desc->info2),
474 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT,
475 desc->info2),
476 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT,
477 desc->info2));
478 ath11k_dbg(ab, ATH11K_DBG_HAL, "frames_in_order %ld bar_rcvd %ld\n",
479 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT,
480 desc->info3),
481 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT,
482 desc->info3));
483 ath11k_dbg(ab, ATH11K_DBG_HAL, "num_mpdus %d num_msdus %d total_bytes %d\n",
484 desc->num_mpdu_frames, desc->num_msdu_frames,
485 desc->total_bytes);
486 ath11k_dbg(ab, ATH11K_DBG_HAL, "late_rcvd %ld win_jump_2k %ld hole_cnt %ld\n",
487 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU,
488 desc->info4),
489 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_WINDOW_JMP2K,
490 desc->info4),
491 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT,
492 desc->info4));
493 ath11k_dbg(ab, ATH11K_DBG_HAL, "looping count %ld\n",
494 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT,
495 desc->info5));
496 }
497
ath11k_hal_reo_process_status(u8 * reo_desc,u8 * status)498 int ath11k_hal_reo_process_status(u8 *reo_desc, u8 *status)
499 {
500 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
501 struct hal_reo_status_hdr *hdr;
502
503 hdr = (struct hal_reo_status_hdr *)tlv->value;
504 *status = FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, hdr->info0);
505
506 return FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, hdr->info0);
507 }
508
ath11k_hal_reo_flush_queue_status(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)509 void ath11k_hal_reo_flush_queue_status(struct ath11k_base *ab, u32 *reo_desc,
510 struct hal_reo_status *status)
511 {
512 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
513 struct hal_reo_flush_queue_status *desc =
514 (struct hal_reo_flush_queue_status *)tlv->value;
515
516 status->uniform_hdr.cmd_num =
517 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
518 desc->hdr.info0);
519 status->uniform_hdr.cmd_status =
520 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
521 desc->hdr.info0);
522 status->u.flush_queue.err_detected =
523 FIELD_GET(HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED,
524 desc->info0);
525 }
526
ath11k_hal_reo_flush_cache_status(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)527 void ath11k_hal_reo_flush_cache_status(struct ath11k_base *ab, u32 *reo_desc,
528 struct hal_reo_status *status)
529 {
530 struct ath11k_hal *hal = &ab->hal;
531 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
532 struct hal_reo_flush_cache_status *desc =
533 (struct hal_reo_flush_cache_status *)tlv->value;
534
535 status->uniform_hdr.cmd_num =
536 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
537 desc->hdr.info0);
538 status->uniform_hdr.cmd_status =
539 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
540 desc->hdr.info0);
541
542 status->u.flush_cache.err_detected =
543 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR,
544 desc->info0);
545 status->u.flush_cache.err_code =
546 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE,
547 desc->info0);
548 if (!status->u.flush_cache.err_code)
549 hal->avail_blk_resource |= BIT(hal->current_blk_index);
550
551 status->u.flush_cache.cache_controller_flush_status_hit =
552 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT,
553 desc->info0);
554
555 status->u.flush_cache.cache_controller_flush_status_desc_type =
556 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE,
557 desc->info0);
558 status->u.flush_cache.cache_controller_flush_status_client_id =
559 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID,
560 desc->info0);
561 status->u.flush_cache.cache_controller_flush_status_err =
562 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR,
563 desc->info0);
564 status->u.flush_cache.cache_controller_flush_status_cnt =
565 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT,
566 desc->info0);
567 }
568
ath11k_hal_reo_unblk_cache_status(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)569 void ath11k_hal_reo_unblk_cache_status(struct ath11k_base *ab, u32 *reo_desc,
570 struct hal_reo_status *status)
571 {
572 struct ath11k_hal *hal = &ab->hal;
573 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
574 struct hal_reo_unblock_cache_status *desc =
575 (struct hal_reo_unblock_cache_status *)tlv->value;
576
577 status->uniform_hdr.cmd_num =
578 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
579 desc->hdr.info0);
580 status->uniform_hdr.cmd_status =
581 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
582 desc->hdr.info0);
583
584 status->u.unblock_cache.err_detected =
585 FIELD_GET(HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR,
586 desc->info0);
587 status->u.unblock_cache.unblock_type =
588 FIELD_GET(HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE,
589 desc->info0);
590
591 if (!status->u.unblock_cache.err_detected &&
592 status->u.unblock_cache.unblock_type ==
593 HAL_REO_STATUS_UNBLOCK_BLOCKING_RESOURCE)
594 hal->avail_blk_resource &= ~BIT(hal->current_blk_index);
595 }
596
ath11k_hal_reo_flush_timeout_list_status(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)597 void ath11k_hal_reo_flush_timeout_list_status(struct ath11k_base *ab,
598 u32 *reo_desc,
599 struct hal_reo_status *status)
600 {
601 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
602 struct hal_reo_flush_timeout_list_status *desc =
603 (struct hal_reo_flush_timeout_list_status *)tlv->value;
604
605 status->uniform_hdr.cmd_num =
606 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
607 desc->hdr.info0);
608 status->uniform_hdr.cmd_status =
609 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
610 desc->hdr.info0);
611
612 status->u.timeout_list.err_detected =
613 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR,
614 desc->info0);
615 status->u.timeout_list.list_empty =
616 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY,
617 desc->info0);
618
619 status->u.timeout_list.release_desc_cnt =
620 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT,
621 desc->info1);
622 status->u.timeout_list.fwd_buf_cnt =
623 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT,
624 desc->info1);
625 }
626
ath11k_hal_reo_desc_thresh_reached_status(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)627 void ath11k_hal_reo_desc_thresh_reached_status(struct ath11k_base *ab,
628 u32 *reo_desc,
629 struct hal_reo_status *status)
630 {
631 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
632 struct hal_reo_desc_thresh_reached_status *desc =
633 (struct hal_reo_desc_thresh_reached_status *)tlv->value;
634
635 status->uniform_hdr.cmd_num =
636 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
637 desc->hdr.info0);
638 status->uniform_hdr.cmd_status =
639 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
640 desc->hdr.info0);
641
642 status->u.desc_thresh_reached.threshold_idx =
643 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX,
644 desc->info0);
645
646 status->u.desc_thresh_reached.link_desc_counter0 =
647 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0,
648 desc->info1);
649
650 status->u.desc_thresh_reached.link_desc_counter1 =
651 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1,
652 desc->info2);
653
654 status->u.desc_thresh_reached.link_desc_counter2 =
655 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2,
656 desc->info3);
657
658 status->u.desc_thresh_reached.link_desc_counter_sum =
659 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM,
660 desc->info4);
661 }
662
ath11k_hal_reo_update_rx_reo_queue_status(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)663 void ath11k_hal_reo_update_rx_reo_queue_status(struct ath11k_base *ab,
664 u32 *reo_desc,
665 struct hal_reo_status *status)
666 {
667 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
668 struct hal_reo_status_hdr *desc =
669 (struct hal_reo_status_hdr *)tlv->value;
670
671 status->uniform_hdr.cmd_num =
672 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
673 desc->info0);
674 status->uniform_hdr.cmd_status =
675 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
676 desc->info0);
677 }
678
ath11k_hal_reo_qdesc_size(u32 ba_window_size,u8 tid)679 u32 ath11k_hal_reo_qdesc_size(u32 ba_window_size, u8 tid)
680 {
681 u32 num_ext_desc;
682
683 if (ba_window_size <= 1) {
684 if (tid != HAL_DESC_REO_NON_QOS_TID)
685 num_ext_desc = 1;
686 else
687 num_ext_desc = 0;
688 } else if (ba_window_size <= 105) {
689 num_ext_desc = 1;
690 } else if (ba_window_size <= 210) {
691 num_ext_desc = 2;
692 } else {
693 num_ext_desc = 3;
694 }
695
696 return sizeof(struct hal_rx_reo_queue) +
697 (num_ext_desc * sizeof(struct hal_rx_reo_queue_ext));
698 }
699
ath11k_hal_reo_qdesc_setup(void * vaddr,int tid,u32 ba_window_size,u32 start_seq,enum hal_pn_type type)700 void ath11k_hal_reo_qdesc_setup(void *vaddr, int tid, u32 ba_window_size,
701 u32 start_seq, enum hal_pn_type type)
702 {
703 struct hal_rx_reo_queue *qdesc = (struct hal_rx_reo_queue *)vaddr;
704 struct hal_rx_reo_queue_ext *ext_desc;
705
706 memset(qdesc, 0, sizeof(*qdesc));
707
708 ath11k_hal_reo_set_desc_hdr(&qdesc->desc_hdr, HAL_DESC_REO_OWNED,
709 HAL_DESC_REO_QUEUE_DESC,
710 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0);
711
712 qdesc->rx_queue_num = FIELD_PREP(HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER, tid);
713
714 qdesc->info0 =
715 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_VLD, 1) |
716 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER, 1) |
717 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_AC, ath11k_tid_to_ac(tid));
718
719 if (ba_window_size < 1)
720 ba_window_size = 1;
721
722 if (ba_window_size == 1 && tid != HAL_DESC_REO_NON_QOS_TID)
723 ba_window_size++;
724
725 if (ba_window_size == 1)
726 qdesc->info0 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_RETRY, 1);
727
728 qdesc->info0 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE,
729 ba_window_size - 1);
730 switch (type) {
731 case HAL_PN_TYPE_NONE:
732 case HAL_PN_TYPE_WAPI_EVEN:
733 case HAL_PN_TYPE_WAPI_UNEVEN:
734 break;
735 case HAL_PN_TYPE_WPA:
736 qdesc->info0 |=
737 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_PN_CHECK, 1) |
738 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_PN_SIZE,
739 HAL_RX_REO_QUEUE_PN_SIZE_48);
740 break;
741 }
742
743 /* TODO: Set Ignore ampdu flags based on BA window size and/or
744 * AMPDU capabilities
745 */
746 qdesc->info0 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG, 1);
747
748 qdesc->info1 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO1_SVLD, 0);
749
750 if (start_seq <= 0xfff)
751 qdesc->info1 = FIELD_PREP(HAL_RX_REO_QUEUE_INFO1_SSN,
752 start_seq);
753
754 if (tid == HAL_DESC_REO_NON_QOS_TID)
755 return;
756
757 ext_desc = qdesc->ext_desc;
758
759 /* TODO: HW queue descriptors are currently allocated for max BA
760 * window size for all QOS TIDs so that same descriptor can be used
761 * later when ADDBA request is received. This should be changed to
762 * allocate HW queue descriptors based on BA window size being
763 * negotiated (0 for non BA cases), and reallocate when BA window
764 * size changes and also send WMI message to FW to change the REO
765 * queue descriptor in Rx peer entry as part of dp_rx_tid_update.
766 */
767 memset(ext_desc, 0, sizeof(*ext_desc));
768 ath11k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED,
769 HAL_DESC_REO_QUEUE_EXT_DESC,
770 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1);
771 ext_desc++;
772 memset(ext_desc, 0, sizeof(*ext_desc));
773 ath11k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED,
774 HAL_DESC_REO_QUEUE_EXT_DESC,
775 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2);
776 ext_desc++;
777 memset(ext_desc, 0, sizeof(*ext_desc));
778 ath11k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED,
779 HAL_DESC_REO_QUEUE_EXT_DESC,
780 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3);
781 }
782
ath11k_hal_reo_init_cmd_ring(struct ath11k_base * ab,struct hal_srng * srng)783 void ath11k_hal_reo_init_cmd_ring(struct ath11k_base *ab,
784 struct hal_srng *srng)
785 {
786 struct hal_srng_params params;
787 struct hal_tlv_hdr *tlv;
788 struct hal_reo_get_queue_stats *desc;
789 int i, cmd_num = 1;
790 int entry_size;
791 u8 *entry;
792
793 memset(¶ms, 0, sizeof(params));
794
795 entry_size = ath11k_hal_srng_get_entrysize(ab, HAL_REO_CMD);
796 ath11k_hal_srng_get_params(ab, srng, ¶ms);
797 entry = (u8 *)params.ring_base_vaddr;
798
799 for (i = 0; i < params.num_entries; i++) {
800 tlv = (struct hal_tlv_hdr *)entry;
801 desc = (struct hal_reo_get_queue_stats *)tlv->value;
802 desc->cmd.info0 =
803 FIELD_PREP(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, cmd_num++);
804 entry += entry_size;
805 }
806 }
807
808 #define HAL_MAX_UL_MU_USERS 37
809 static inline void
ath11k_hal_rx_handle_ofdma_info(void * rx_tlv,struct hal_rx_user_status * rx_user_status)810 ath11k_hal_rx_handle_ofdma_info(void *rx_tlv,
811 struct hal_rx_user_status *rx_user_status)
812 {
813 struct hal_rx_ppdu_end_user_stats *ppdu_end_user =
814 (struct hal_rx_ppdu_end_user_stats *)rx_tlv;
815
816 rx_user_status->ul_ofdma_user_v0_word0 = __le32_to_cpu(ppdu_end_user->info6);
817
818 rx_user_status->ul_ofdma_user_v0_word1 = __le32_to_cpu(ppdu_end_user->rsvd2[10]);
819 }
820
821 static inline void
ath11k_hal_rx_populate_byte_count(void * rx_tlv,void * ppduinfo,struct hal_rx_user_status * rx_user_status)822 ath11k_hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo,
823 struct hal_rx_user_status *rx_user_status)
824 {
825 struct hal_rx_ppdu_end_user_stats *ppdu_end_user =
826 (struct hal_rx_ppdu_end_user_stats *)rx_tlv;
827
828 rx_user_status->mpdu_ok_byte_count =
829 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_RSVD2_6_MPDU_OK_BYTE_COUNT,
830 __le32_to_cpu(ppdu_end_user->rsvd2[6]));
831 rx_user_status->mpdu_err_byte_count =
832 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_RSVD2_8_MPDU_ERR_BYTE_COUNT,
833 __le32_to_cpu(ppdu_end_user->rsvd2[8]));
834 }
835
836 static inline void
ath11k_hal_rx_populate_mu_user_info(void * rx_tlv,struct hal_rx_mon_ppdu_info * ppdu_info,struct hal_rx_user_status * rx_user_status)837 ath11k_hal_rx_populate_mu_user_info(void *rx_tlv, struct hal_rx_mon_ppdu_info *ppdu_info,
838 struct hal_rx_user_status *rx_user_status)
839 {
840 rx_user_status->ast_index = ppdu_info->ast_index;
841 rx_user_status->tid = ppdu_info->tid;
842 rx_user_status->tcp_msdu_count =
843 ppdu_info->tcp_msdu_count;
844 rx_user_status->udp_msdu_count =
845 ppdu_info->udp_msdu_count;
846 rx_user_status->other_msdu_count =
847 ppdu_info->other_msdu_count;
848 rx_user_status->frame_control = ppdu_info->frame_control;
849 rx_user_status->frame_control_info_valid =
850 ppdu_info->frame_control_info_valid;
851 rx_user_status->data_sequence_control_info_valid =
852 ppdu_info->data_sequence_control_info_valid;
853 rx_user_status->first_data_seq_ctrl =
854 ppdu_info->first_data_seq_ctrl;
855 rx_user_status->preamble_type = ppdu_info->preamble_type;
856 rx_user_status->ht_flags = ppdu_info->ht_flags;
857 rx_user_status->vht_flags = ppdu_info->vht_flags;
858 rx_user_status->he_flags = ppdu_info->he_flags;
859 rx_user_status->rs_flags = ppdu_info->rs_flags;
860
861 rx_user_status->mpdu_cnt_fcs_ok =
862 ppdu_info->num_mpdu_fcs_ok;
863 rx_user_status->mpdu_cnt_fcs_err =
864 ppdu_info->num_mpdu_fcs_err;
865
866 ath11k_hal_rx_populate_byte_count(rx_tlv, ppdu_info, rx_user_status);
867 }
868
ath11k_hal_rx_mpduinfo_get_peerid(struct ath11k_base * ab,struct hal_rx_mpdu_info * mpdu_info)869 static u16 ath11k_hal_rx_mpduinfo_get_peerid(struct ath11k_base *ab,
870 struct hal_rx_mpdu_info *mpdu_info)
871 {
872 return ab->hw_params.hw_ops->mpdu_info_get_peerid(mpdu_info);
873 }
874
875 static enum hal_rx_mon_status
ath11k_hal_rx_parse_mon_status_tlv(struct ath11k_base * ab,struct hal_rx_mon_ppdu_info * ppdu_info,u32 tlv_tag,u8 * tlv_data,u32 userid)876 ath11k_hal_rx_parse_mon_status_tlv(struct ath11k_base *ab,
877 struct hal_rx_mon_ppdu_info *ppdu_info,
878 u32 tlv_tag, u8 *tlv_data, u32 userid)
879 {
880 u32 info0, info1, value;
881 u8 he_dcm = 0, he_stbc = 0;
882 u16 he_gi = 0, he_ltf = 0;
883
884 switch (tlv_tag) {
885 case HAL_RX_PPDU_START: {
886 struct hal_rx_ppdu_start *ppdu_start =
887 (struct hal_rx_ppdu_start *)tlv_data;
888
889 ppdu_info->ppdu_id =
890 FIELD_GET(HAL_RX_PPDU_START_INFO0_PPDU_ID,
891 __le32_to_cpu(ppdu_start->info0));
892 ppdu_info->chan_num = __le32_to_cpu(ppdu_start->chan_num);
893 ppdu_info->ppdu_ts = __le32_to_cpu(ppdu_start->ppdu_start_ts);
894 break;
895 }
896 case HAL_RX_PPDU_END_USER_STATS: {
897 struct hal_rx_ppdu_end_user_stats *eu_stats =
898 (struct hal_rx_ppdu_end_user_stats *)tlv_data;
899
900 info0 = __le32_to_cpu(eu_stats->info0);
901 info1 = __le32_to_cpu(eu_stats->info1);
902
903 ppdu_info->ast_index =
904 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX,
905 __le32_to_cpu(eu_stats->info2));
906 ppdu_info->tid =
907 ffs(FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP,
908 __le32_to_cpu(eu_stats->info6))) - 1;
909 ppdu_info->tcp_msdu_count =
910 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT,
911 __le32_to_cpu(eu_stats->info4));
912 ppdu_info->udp_msdu_count =
913 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT,
914 __le32_to_cpu(eu_stats->info4));
915 ppdu_info->other_msdu_count =
916 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT,
917 __le32_to_cpu(eu_stats->info5));
918 ppdu_info->tcp_ack_msdu_count =
919 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT,
920 __le32_to_cpu(eu_stats->info5));
921 ppdu_info->preamble_type =
922 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE, info1);
923 ppdu_info->num_mpdu_fcs_ok =
924 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK,
925 info1);
926 ppdu_info->num_mpdu_fcs_err =
927 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR,
928 info0);
929 switch (ppdu_info->preamble_type) {
930 case HAL_RX_PREAMBLE_11N:
931 ppdu_info->ht_flags = 1;
932 break;
933 case HAL_RX_PREAMBLE_11AC:
934 ppdu_info->vht_flags = 1;
935 break;
936 case HAL_RX_PREAMBLE_11AX:
937 ppdu_info->he_flags = 1;
938 break;
939 default:
940 break;
941 }
942
943 if (userid < HAL_MAX_UL_MU_USERS) {
944 struct hal_rx_user_status *rxuser_stats =
945 &ppdu_info->userstats;
946
947 ath11k_hal_rx_handle_ofdma_info(tlv_data, rxuser_stats);
948 ath11k_hal_rx_populate_mu_user_info(tlv_data, ppdu_info,
949 rxuser_stats);
950 }
951 ppdu_info->userstats.mpdu_fcs_ok_bitmap[0] =
952 __le32_to_cpu(eu_stats->rsvd1[0]);
953 ppdu_info->userstats.mpdu_fcs_ok_bitmap[1] =
954 __le32_to_cpu(eu_stats->rsvd1[1]);
955
956 break;
957 }
958 case HAL_RX_PPDU_END_USER_STATS_EXT: {
959 struct hal_rx_ppdu_end_user_stats_ext *eu_stats =
960 (struct hal_rx_ppdu_end_user_stats_ext *)tlv_data;
961 ppdu_info->userstats.mpdu_fcs_ok_bitmap[2] = eu_stats->info1;
962 ppdu_info->userstats.mpdu_fcs_ok_bitmap[3] = eu_stats->info2;
963 ppdu_info->userstats.mpdu_fcs_ok_bitmap[4] = eu_stats->info3;
964 ppdu_info->userstats.mpdu_fcs_ok_bitmap[5] = eu_stats->info4;
965 ppdu_info->userstats.mpdu_fcs_ok_bitmap[6] = eu_stats->info5;
966 ppdu_info->userstats.mpdu_fcs_ok_bitmap[7] = eu_stats->info6;
967 break;
968 }
969 case HAL_PHYRX_HT_SIG: {
970 struct hal_rx_ht_sig_info *ht_sig =
971 (struct hal_rx_ht_sig_info *)tlv_data;
972
973 info0 = __le32_to_cpu(ht_sig->info0);
974 info1 = __le32_to_cpu(ht_sig->info1);
975
976 ppdu_info->mcs = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO0_MCS, info0);
977 ppdu_info->bw = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO0_BW, info0);
978 ppdu_info->is_stbc = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO1_STBC,
979 info1);
980 ppdu_info->ldpc = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING, info1);
981 ppdu_info->gi = info1 & HAL_RX_HT_SIG_INFO_INFO1_GI;
982
983 switch (ppdu_info->mcs) {
984 case 0 ... 7:
985 ppdu_info->nss = 1;
986 break;
987 case 8 ... 15:
988 ppdu_info->nss = 2;
989 break;
990 case 16 ... 23:
991 ppdu_info->nss = 3;
992 break;
993 case 24 ... 31:
994 ppdu_info->nss = 4;
995 break;
996 }
997
998 if (ppdu_info->nss > 1)
999 ppdu_info->mcs = ppdu_info->mcs % 8;
1000
1001 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
1002 break;
1003 }
1004 case HAL_PHYRX_L_SIG_B: {
1005 struct hal_rx_lsig_b_info *lsigb =
1006 (struct hal_rx_lsig_b_info *)tlv_data;
1007
1008 ppdu_info->rate = FIELD_GET(HAL_RX_LSIG_B_INFO_INFO0_RATE,
1009 __le32_to_cpu(lsigb->info0));
1010 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
1011 break;
1012 }
1013 case HAL_PHYRX_L_SIG_A: {
1014 struct hal_rx_lsig_a_info *lsiga =
1015 (struct hal_rx_lsig_a_info *)tlv_data;
1016
1017 ppdu_info->rate = FIELD_GET(HAL_RX_LSIG_A_INFO_INFO0_RATE,
1018 __le32_to_cpu(lsiga->info0));
1019 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
1020 break;
1021 }
1022 case HAL_PHYRX_VHT_SIG_A: {
1023 struct hal_rx_vht_sig_a_info *vht_sig =
1024 (struct hal_rx_vht_sig_a_info *)tlv_data;
1025 u32 nsts;
1026 u32 group_id;
1027 u8 gi_setting;
1028
1029 info0 = __le32_to_cpu(vht_sig->info0);
1030 info1 = __le32_to_cpu(vht_sig->info1);
1031
1032 ppdu_info->ldpc = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING,
1033 info1);
1034 ppdu_info->mcs = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_MCS,
1035 info1);
1036 gi_setting = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING,
1037 info1);
1038 switch (gi_setting) {
1039 case HAL_RX_VHT_SIG_A_NORMAL_GI:
1040 ppdu_info->gi = HAL_RX_GI_0_8_US;
1041 break;
1042 case HAL_RX_VHT_SIG_A_SHORT_GI:
1043 case HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY:
1044 ppdu_info->gi = HAL_RX_GI_0_4_US;
1045 break;
1046 }
1047
1048 ppdu_info->is_stbc = info0 & HAL_RX_VHT_SIG_A_INFO_INFO0_STBC;
1049 nsts = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS, info0);
1050 if (ppdu_info->is_stbc && nsts > 0)
1051 nsts = ((nsts + 1) >> 1) - 1;
1052
1053 ppdu_info->nss = (nsts & VHT_SIG_SU_NSS_MASK) + 1;
1054 ppdu_info->bw = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO0_BW,
1055 info0);
1056 ppdu_info->beamformed = info1 &
1057 HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED;
1058 group_id = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID,
1059 info0);
1060 if (group_id == 0 || group_id == 63)
1061 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
1062 else
1063 ppdu_info->reception_type =
1064 HAL_RX_RECEPTION_TYPE_MU_MIMO;
1065 ppdu_info->vht_flag_values5 = group_id;
1066 ppdu_info->vht_flag_values3[0] = (((ppdu_info->mcs) << 4) |
1067 ppdu_info->nss);
1068 ppdu_info->vht_flag_values2 = ppdu_info->bw;
1069 ppdu_info->vht_flag_values4 =
1070 FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING, info1);
1071 break;
1072 }
1073 case HAL_PHYRX_HE_SIG_A_SU: {
1074 struct hal_rx_he_sig_a_su_info *he_sig_a =
1075 (struct hal_rx_he_sig_a_su_info *)tlv_data;
1076
1077 ppdu_info->he_flags = 1;
1078 info0 = __le32_to_cpu(he_sig_a->info0);
1079 info1 = __le32_to_cpu(he_sig_a->info1);
1080
1081 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND, info0);
1082
1083 if (value == 0)
1084 ppdu_info->he_data1 = IEEE80211_RADIOTAP_HE_DATA1_FORMAT_TRIG;
1085 else
1086 ppdu_info->he_data1 = IEEE80211_RADIOTAP_HE_DATA1_FORMAT_SU;
1087
1088 ppdu_info->he_data1 |=
1089 IEEE80211_RADIOTAP_HE_DATA1_BSS_COLOR_KNOWN |
1090 IEEE80211_RADIOTAP_HE_DATA1_BEAM_CHANGE_KNOWN |
1091 IEEE80211_RADIOTAP_HE_DATA1_UL_DL_KNOWN |
1092 IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
1093 IEEE80211_RADIOTAP_HE_DATA1_DATA_DCM_KNOWN |
1094 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN |
1095 IEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN |
1096 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN |
1097 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN |
1098 IEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN;
1099
1100 ppdu_info->he_data2 |=
1101 IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN |
1102 IEEE80211_RADIOTAP_HE_DATA2_TXBF_KNOWN |
1103 IEEE80211_RADIOTAP_HE_DATA2_PE_DISAMBIG_KNOWN |
1104 IEEE80211_RADIOTAP_HE_DATA2_TXOP_KNOWN |
1105 IEEE80211_RADIOTAP_HE_DATA2_NUM_LTF_SYMS_KNOWN |
1106 IEEE80211_RADIOTAP_HE_DATA2_PRE_FEC_PAD_KNOWN |
1107 IEEE80211_RADIOTAP_HE_DATA2_MIDAMBLE_KNOWN;
1108
1109 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR, info0);
1110 ppdu_info->he_data3 =
1111 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_BSS_COLOR, value);
1112 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE, info0);
1113 ppdu_info->he_data3 |=
1114 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_BEAM_CHANGE, value);
1115 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG, info0);
1116 ppdu_info->he_data3 |=
1117 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_UL_DL, value);
1118 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS, info0);
1119 ppdu_info->mcs = value;
1120 ppdu_info->he_data3 |=
1121 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_DATA_MCS, value);
1122
1123 he_dcm = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM, info0);
1124 ppdu_info->dcm = he_dcm;
1125 ppdu_info->he_data3 |=
1126 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_DATA_DCM, he_dcm);
1127 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING, info1);
1128 ppdu_info->ldpc = (value == HAL_RX_SU_MU_CODING_LDPC) ? 1 : 0;
1129 ppdu_info->he_data3 |=
1130 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_CODING, value);
1131 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA, info1);
1132 ppdu_info->he_data3 |=
1133 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_LDPC_XSYMSEG, value);
1134 he_stbc = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC, info1);
1135 ppdu_info->is_stbc = he_stbc;
1136 ppdu_info->he_data3 |=
1137 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_STBC, he_stbc);
1138
1139 /* data4 */
1140 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE, info0);
1141 ppdu_info->he_data4 =
1142 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA4_SU_MU_SPTL_REUSE, value);
1143
1144 /* data5 */
1145 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW, info0);
1146 ppdu_info->bw = value;
1147 ppdu_info->he_data5 =
1148 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC, value);
1149 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE, info0);
1150 switch (value) {
1151 case 0:
1152 he_gi = HE_GI_0_8;
1153 he_ltf = HE_LTF_1_X;
1154 break;
1155 case 1:
1156 he_gi = HE_GI_0_8;
1157 he_ltf = HE_LTF_2_X;
1158 break;
1159 case 2:
1160 he_gi = HE_GI_1_6;
1161 he_ltf = HE_LTF_2_X;
1162 break;
1163 case 3:
1164 if (he_dcm && he_stbc) {
1165 he_gi = HE_GI_0_8;
1166 he_ltf = HE_LTF_4_X;
1167 } else {
1168 he_gi = HE_GI_3_2;
1169 he_ltf = HE_LTF_4_X;
1170 }
1171 break;
1172 }
1173 ppdu_info->gi = he_gi;
1174 he_gi = (he_gi != 0) ? he_gi - 1 : 0;
1175 ppdu_info->he_data5 |= FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_GI, he_gi);
1176 ppdu_info->ltf_size = he_ltf;
1177 ppdu_info->he_data5 |=
1178 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE,
1179 (he_ltf == HE_LTF_4_X) ? he_ltf - 1 : he_ltf);
1180
1181 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS, info0);
1182 ppdu_info->he_data5 |=
1183 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_NUM_LTF_SYMS, value);
1184
1185 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR, info1);
1186 ppdu_info->he_data5 |=
1187 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_PRE_FEC_PAD, value);
1188
1189 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF, info1);
1190 ppdu_info->beamformed = value;
1191 ppdu_info->he_data5 |=
1192 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_TXBF, value);
1193 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM, info1);
1194 ppdu_info->he_data5 |=
1195 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_PE_DISAMBIG, value);
1196
1197 /* data6 */
1198 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS, info0);
1199 value++;
1200 ppdu_info->nss = value;
1201 ppdu_info->he_data6 =
1202 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA6_NSTS, value);
1203 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND, info1);
1204 ppdu_info->he_data6 |=
1205 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA6_DOPPLER, value);
1206 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION, info1);
1207 ppdu_info->he_data6 |=
1208 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA6_TXOP, value);
1209
1210 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
1211 break;
1212 }
1213 case HAL_PHYRX_HE_SIG_A_MU_DL: {
1214 struct hal_rx_he_sig_a_mu_dl_info *he_sig_a_mu_dl =
1215 (struct hal_rx_he_sig_a_mu_dl_info *)tlv_data;
1216
1217 info0 = __le32_to_cpu(he_sig_a_mu_dl->info0);
1218 info1 = __le32_to_cpu(he_sig_a_mu_dl->info1);
1219
1220 ppdu_info->he_mu_flags = 1;
1221
1222 ppdu_info->he_data1 = IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MU;
1223 ppdu_info->he_data1 |=
1224 IEEE80211_RADIOTAP_HE_DATA1_BSS_COLOR_KNOWN |
1225 IEEE80211_RADIOTAP_HE_DATA1_UL_DL_KNOWN |
1226 IEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN |
1227 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN |
1228 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN |
1229 IEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN;
1230
1231 ppdu_info->he_data2 =
1232 IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN |
1233 IEEE80211_RADIOTAP_HE_DATA2_NUM_LTF_SYMS_KNOWN |
1234 IEEE80211_RADIOTAP_HE_DATA2_PRE_FEC_PAD_KNOWN |
1235 IEEE80211_RADIOTAP_HE_DATA2_PE_DISAMBIG_KNOWN |
1236 IEEE80211_RADIOTAP_HE_DATA2_TXOP_KNOWN |
1237 IEEE80211_RADIOTAP_HE_DATA2_MIDAMBLE_KNOWN;
1238
1239 /*data3*/
1240 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_BSS_COLOR, info0);
1241 ppdu_info->he_data3 =
1242 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_BSS_COLOR, value);
1243
1244 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_UL_FLAG, info0);
1245 ppdu_info->he_data3 |=
1246 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_UL_DL, value);
1247
1248 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_LDPC_EXTRA, info1);
1249 ppdu_info->he_data3 |=
1250 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_LDPC_XSYMSEG, value);
1251
1252 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_STBC, info1);
1253 he_stbc = value;
1254 ppdu_info->he_data3 |=
1255 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_STBC, value);
1256
1257 /*data4*/
1258 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_SPATIAL_REUSE, info0);
1259 ppdu_info->he_data4 =
1260 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA4_SU_MU_SPTL_REUSE, value);
1261
1262 /*data5*/
1263 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_TRANSMIT_BW, info0);
1264 ppdu_info->bw = value;
1265 ppdu_info->he_data5 =
1266 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC, value);
1267
1268 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_CP_LTF_SIZE, info0);
1269 switch (value) {
1270 case 0:
1271 he_gi = HE_GI_0_8;
1272 he_ltf = HE_LTF_4_X;
1273 break;
1274 case 1:
1275 he_gi = HE_GI_0_8;
1276 he_ltf = HE_LTF_2_X;
1277 break;
1278 case 2:
1279 he_gi = HE_GI_1_6;
1280 he_ltf = HE_LTF_2_X;
1281 break;
1282 case 3:
1283 he_gi = HE_GI_3_2;
1284 he_ltf = HE_LTF_4_X;
1285 break;
1286 }
1287 ppdu_info->gi = he_gi;
1288 he_gi = (he_gi != 0) ? he_gi - 1 : 0;
1289 ppdu_info->he_data5 |= FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_GI, he_gi);
1290 ppdu_info->ltf_size = he_ltf;
1291 ppdu_info->he_data5 |=
1292 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE,
1293 (he_ltf == HE_LTF_4_X) ? he_ltf - 1 : he_ltf);
1294
1295 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_NUM_LTF_SYMB, info1);
1296 ppdu_info->he_data5 |=
1297 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_NUM_LTF_SYMS, value);
1298
1299 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_PKT_EXT_FACTOR,
1300 info1);
1301 ppdu_info->he_data5 |=
1302 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_PRE_FEC_PAD, value);
1303
1304 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_PKT_EXT_PE_DISAM,
1305 info1);
1306 ppdu_info->he_data5 |=
1307 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_PE_DISAMBIG, value);
1308
1309 /*data6*/
1310 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_DOPPLER_INDICATION,
1311 info0);
1312 ppdu_info->he_data6 |=
1313 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA6_DOPPLER, value);
1314
1315 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_TXOP_DURATION, info1);
1316 ppdu_info->he_data6 |=
1317 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA6_TXOP, value);
1318
1319 /* HE-MU Flags */
1320 /* HE-MU-flags1 */
1321 ppdu_info->he_flags1 =
1322 IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS_KNOWN |
1323 IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM_KNOWN |
1324 IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_COMP_KNOWN |
1325 IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_SYMS_USERS_KNOWN |
1326 IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_RU_KNOWN;
1327
1328 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_MCS_OF_SIGB, info0);
1329 ppdu_info->he_flags1 |=
1330 FIELD_PREP(IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS_KNOWN,
1331 value);
1332 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_DCM_OF_SIGB, info0);
1333 ppdu_info->he_flags1 |=
1334 FIELD_PREP(IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM_KNOWN,
1335 value);
1336
1337 /* HE-MU-flags2 */
1338 ppdu_info->he_flags2 =
1339 IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_KNOWN;
1340
1341 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_TRANSMIT_BW, info0);
1342 ppdu_info->he_flags2 |=
1343 FIELD_PREP(IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW,
1344 value);
1345 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_COMP_MODE_SIGB, info0);
1346 ppdu_info->he_flags2 |=
1347 FIELD_PREP(IEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_COMP, value);
1348 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_NUM_SIGB_SYMB, info0);
1349 value = value - 1;
1350 ppdu_info->he_flags2 |=
1351 FIELD_PREP(IEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_SYMS_USERS,
1352 value);
1353
1354 ppdu_info->is_stbc = info1 &
1355 HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_STBC;
1356 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO;
1357 break;
1358 }
1359 case HAL_PHYRX_HE_SIG_B1_MU: {
1360 struct hal_rx_he_sig_b1_mu_info *he_sig_b1_mu =
1361 (struct hal_rx_he_sig_b1_mu_info *)tlv_data;
1362 u16 ru_tones;
1363
1364 info0 = __le32_to_cpu(he_sig_b1_mu->info0);
1365
1366 ru_tones = FIELD_GET(HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION,
1367 info0);
1368 ppdu_info->ru_alloc =
1369 ath11k_mac_phy_he_ru_to_nl80211_he_ru_alloc(ru_tones);
1370 ppdu_info->he_RU[0] = ru_tones;
1371 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO;
1372 break;
1373 }
1374 case HAL_PHYRX_HE_SIG_B2_MU: {
1375 struct hal_rx_he_sig_b2_mu_info *he_sig_b2_mu =
1376 (struct hal_rx_he_sig_b2_mu_info *)tlv_data;
1377
1378 info0 = __le32_to_cpu(he_sig_b2_mu->info0);
1379
1380 ppdu_info->he_data1 |= IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
1381 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN;
1382
1383 ppdu_info->mcs =
1384 FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS, info0);
1385 ppdu_info->he_data3 |=
1386 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_DATA_MCS, ppdu_info->mcs);
1387
1388 value = FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING, info0);
1389 ppdu_info->ldpc = value;
1390 ppdu_info->he_data3 |=
1391 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_CODING, value);
1392
1393 value = FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID, info0);
1394 ppdu_info->he_data4 |=
1395 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA4_MU_STA_ID, value);
1396
1397 ppdu_info->nss =
1398 FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS, info0) + 1;
1399 break;
1400 }
1401 case HAL_PHYRX_HE_SIG_B2_OFDMA: {
1402 struct hal_rx_he_sig_b2_ofdma_info *he_sig_b2_ofdma =
1403 (struct hal_rx_he_sig_b2_ofdma_info *)tlv_data;
1404
1405 info0 = __le32_to_cpu(he_sig_b2_ofdma->info0);
1406
1407 ppdu_info->he_data1 |=
1408 IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
1409 IEEE80211_RADIOTAP_HE_DATA1_DATA_DCM_KNOWN |
1410 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN;
1411
1412 /* HE-data2 */
1413 ppdu_info->he_data2 |= IEEE80211_RADIOTAP_HE_DATA2_TXBF_KNOWN;
1414
1415 ppdu_info->mcs =
1416 FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS,
1417 info0);
1418 ppdu_info->he_data3 |=
1419 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_DATA_MCS, ppdu_info->mcs);
1420
1421 value = FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM, info0);
1422 he_dcm = value;
1423 ppdu_info->he_data3 |=
1424 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_DATA_DCM, value);
1425
1426 value = FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING, info0);
1427 ppdu_info->ldpc = value;
1428 ppdu_info->he_data3 |=
1429 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_CODING, value);
1430
1431 /* HE-data4 */
1432 value = FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID, info0);
1433 ppdu_info->he_data4 |=
1434 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA4_MU_STA_ID, value);
1435
1436 ppdu_info->nss =
1437 FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS,
1438 info0) + 1;
1439 ppdu_info->beamformed =
1440 info0 & HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF;
1441 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA;
1442 break;
1443 }
1444 case HAL_PHYRX_RSSI_LEGACY: {
1445 int i;
1446 bool db2dbm = test_bit(WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT,
1447 ab->wmi_ab.svc_map);
1448 struct hal_rx_phyrx_rssi_legacy_info *rssi =
1449 (struct hal_rx_phyrx_rssi_legacy_info *)tlv_data;
1450
1451 /* TODO: Please note that the combined rssi will not be accurate
1452 * in MU case. Rssi in MU needs to be retrieved from
1453 * PHYRX_OTHER_RECEIVE_INFO TLV.
1454 */
1455 ppdu_info->rssi_comb =
1456 FIELD_GET(HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RSSI_COMB,
1457 __le32_to_cpu(rssi->info0));
1458
1459 if (db2dbm) {
1460 for (i = 0; i < ARRAY_SIZE(rssi->preamble); i++) {
1461 ppdu_info->rssi_chain_pri20[i] =
1462 le32_get_bits(rssi->preamble[i].rssi_2040,
1463 HAL_RX_PHYRX_RSSI_PREAMBLE_PRI20);
1464 }
1465 }
1466 break;
1467 }
1468 case HAL_RX_MPDU_START: {
1469 struct hal_rx_mpdu_info *mpdu_info =
1470 (struct hal_rx_mpdu_info *)tlv_data;
1471 u16 peer_id;
1472
1473 peer_id = ath11k_hal_rx_mpduinfo_get_peerid(ab, mpdu_info);
1474 if (peer_id)
1475 ppdu_info->peer_id = peer_id;
1476 break;
1477 }
1478 case HAL_RXPCU_PPDU_END_INFO: {
1479 struct hal_rx_ppdu_end_duration *ppdu_rx_duration =
1480 (struct hal_rx_ppdu_end_duration *)tlv_data;
1481 ppdu_info->rx_duration =
1482 FIELD_GET(HAL_RX_PPDU_END_DURATION,
1483 __le32_to_cpu(ppdu_rx_duration->info0));
1484 ppdu_info->tsft = __le32_to_cpu(ppdu_rx_duration->rsvd0[1]);
1485 ppdu_info->tsft = (ppdu_info->tsft << 32) |
1486 __le32_to_cpu(ppdu_rx_duration->rsvd0[0]);
1487 break;
1488 }
1489 case HAL_DUMMY:
1490 return HAL_RX_MON_STATUS_BUF_DONE;
1491 case HAL_RX_PPDU_END_STATUS_DONE:
1492 case 0:
1493 return HAL_RX_MON_STATUS_PPDU_DONE;
1494 default:
1495 break;
1496 }
1497
1498 return HAL_RX_MON_STATUS_PPDU_NOT_DONE;
1499 }
1500
1501 enum hal_rx_mon_status
ath11k_hal_rx_parse_mon_status(struct ath11k_base * ab,struct hal_rx_mon_ppdu_info * ppdu_info,struct sk_buff * skb)1502 ath11k_hal_rx_parse_mon_status(struct ath11k_base *ab,
1503 struct hal_rx_mon_ppdu_info *ppdu_info,
1504 struct sk_buff *skb)
1505 {
1506 struct hal_tlv_hdr *tlv;
1507 enum hal_rx_mon_status hal_status = HAL_RX_MON_STATUS_BUF_DONE;
1508 u16 tlv_tag;
1509 u16 tlv_len;
1510 u32 tlv_userid = 0;
1511 u8 *ptr = skb->data;
1512
1513 do {
1514 tlv = (struct hal_tlv_hdr *)ptr;
1515 tlv_tag = FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl);
1516 tlv_len = FIELD_GET(HAL_TLV_HDR_LEN, tlv->tl);
1517 tlv_userid = FIELD_GET(HAL_TLV_USR_ID, tlv->tl);
1518 ptr += sizeof(*tlv);
1519
1520 /* The actual length of PPDU_END is the combined length of many PHY
1521 * TLVs that follow. Skip the TLV header and
1522 * rx_rxpcu_classification_overview that follows the header to get to
1523 * next TLV.
1524 */
1525 if (tlv_tag == HAL_RX_PPDU_END)
1526 tlv_len = sizeof(struct hal_rx_rxpcu_classification_overview);
1527
1528 hal_status = ath11k_hal_rx_parse_mon_status_tlv(ab, ppdu_info,
1529 tlv_tag, ptr, tlv_userid);
1530 ptr += tlv_len;
1531 ptr = PTR_ALIGN(ptr, HAL_TLV_ALIGN);
1532
1533 if ((ptr - skb->data) >= DP_RX_BUFFER_SIZE)
1534 break;
1535 } while (hal_status == HAL_RX_MON_STATUS_PPDU_NOT_DONE);
1536
1537 return hal_status;
1538 }
1539
ath11k_hal_rx_reo_ent_buf_paddr_get(void * rx_desc,dma_addr_t * paddr,u32 * sw_cookie,void ** pp_buf_addr,u8 * rbm,u32 * msdu_cnt)1540 void ath11k_hal_rx_reo_ent_buf_paddr_get(void *rx_desc, dma_addr_t *paddr,
1541 u32 *sw_cookie, void **pp_buf_addr,
1542 u8 *rbm, u32 *msdu_cnt)
1543 {
1544 struct hal_reo_entrance_ring *reo_ent_ring =
1545 (struct hal_reo_entrance_ring *)rx_desc;
1546 struct ath11k_buffer_addr *buf_addr_info;
1547 struct rx_mpdu_desc *rx_mpdu_desc_info_details;
1548
1549 rx_mpdu_desc_info_details =
1550 (struct rx_mpdu_desc *)&reo_ent_ring->rx_mpdu_info;
1551
1552 *msdu_cnt = FIELD_GET(RX_MPDU_DESC_INFO0_MSDU_COUNT,
1553 rx_mpdu_desc_info_details->info0);
1554
1555 buf_addr_info = (struct ath11k_buffer_addr *)&reo_ent_ring->buf_addr_info;
1556
1557 *paddr = (((u64)FIELD_GET(BUFFER_ADDR_INFO1_ADDR,
1558 buf_addr_info->info1)) << 32) |
1559 FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
1560 buf_addr_info->info0);
1561
1562 *sw_cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
1563 buf_addr_info->info1);
1564 *rbm = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
1565 buf_addr_info->info1);
1566
1567 *pp_buf_addr = (void *)buf_addr_info;
1568 }
1569
1570 void
ath11k_hal_rx_sw_mon_ring_buf_paddr_get(void * rx_desc,struct hal_sw_mon_ring_entries * sw_mon_entries)1571 ath11k_hal_rx_sw_mon_ring_buf_paddr_get(void *rx_desc,
1572 struct hal_sw_mon_ring_entries *sw_mon_entries)
1573 {
1574 struct hal_sw_monitor_ring *sw_mon_ring = rx_desc;
1575 struct ath11k_buffer_addr *buf_addr_info;
1576 struct ath11k_buffer_addr *status_buf_addr_info;
1577 struct rx_mpdu_desc *rx_mpdu_desc_info_details;
1578
1579 rx_mpdu_desc_info_details = &sw_mon_ring->rx_mpdu_info;
1580
1581 sw_mon_entries->msdu_cnt = FIELD_GET(RX_MPDU_DESC_INFO0_MSDU_COUNT,
1582 rx_mpdu_desc_info_details->info0);
1583
1584 buf_addr_info = &sw_mon_ring->buf_addr_info;
1585 status_buf_addr_info = &sw_mon_ring->status_buf_addr_info;
1586
1587 sw_mon_entries->mon_dst_paddr = (((u64)FIELD_GET(BUFFER_ADDR_INFO1_ADDR,
1588 buf_addr_info->info1)) << 32) |
1589 FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
1590 buf_addr_info->info0);
1591
1592 sw_mon_entries->mon_status_paddr =
1593 (((u64)FIELD_GET(BUFFER_ADDR_INFO1_ADDR,
1594 status_buf_addr_info->info1)) << 32) |
1595 FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
1596 status_buf_addr_info->info0);
1597
1598 sw_mon_entries->mon_dst_sw_cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
1599 buf_addr_info->info1);
1600
1601 sw_mon_entries->mon_status_sw_cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
1602 status_buf_addr_info->info1);
1603
1604 sw_mon_entries->status_buf_count = FIELD_GET(HAL_SW_MON_RING_INFO0_STATUS_BUF_CNT,
1605 sw_mon_ring->info0);
1606
1607 sw_mon_entries->dst_buf_addr_info = buf_addr_info;
1608 sw_mon_entries->status_buf_addr_info = status_buf_addr_info;
1609
1610 sw_mon_entries->ppdu_id =
1611 FIELD_GET(HAL_SW_MON_RING_INFO1_PHY_PPDU_ID, sw_mon_ring->info1);
1612 }
1613