1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include "debug.h"
8 #include "hal.h"
9 #include "hal_tx.h"
10 #include "hal_rx.h"
11 #include "hal_desc.h"
12 #include "hif.h"
13
ath11k_hal_reo_set_desc_hdr(struct hal_desc_header * hdr,u8 owner,u8 buffer_type,u32 magic)14 static void ath11k_hal_reo_set_desc_hdr(struct hal_desc_header *hdr,
15 u8 owner, u8 buffer_type, u32 magic)
16 {
17 hdr->info0 = FIELD_PREP(HAL_DESC_HDR_INFO0_OWNER, owner) |
18 FIELD_PREP(HAL_DESC_HDR_INFO0_BUF_TYPE, buffer_type);
19
20 /* Magic pattern in reserved bits for debugging */
21 hdr->info0 |= FIELD_PREP(HAL_DESC_HDR_INFO0_DBG_RESERVED, magic);
22 }
23
ath11k_hal_reo_cmd_queue_stats(struct hal_tlv_hdr * tlv,struct ath11k_hal_reo_cmd * cmd)24 static int ath11k_hal_reo_cmd_queue_stats(struct hal_tlv_hdr *tlv,
25 struct ath11k_hal_reo_cmd *cmd)
26 {
27 struct hal_reo_get_queue_stats *desc;
28
29 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_REO_GET_QUEUE_STATS) |
30 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc));
31
32 desc = (struct hal_reo_get_queue_stats *)tlv->value;
33 memset_startat(desc, 0, queue_addr_lo);
34
35 desc->cmd.info0 &= ~HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
36 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS)
37 desc->cmd.info0 |= HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
38
39 desc->queue_addr_lo = cmd->addr_lo;
40 desc->info0 = FIELD_PREP(HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI,
41 cmd->addr_hi);
42 if (cmd->flag & HAL_REO_CMD_FLG_STATS_CLEAR)
43 desc->info0 |= HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS;
44
45 return FIELD_GET(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, desc->cmd.info0);
46 }
47
ath11k_hal_reo_cmd_flush_cache(struct ath11k_hal * hal,struct hal_tlv_hdr * tlv,struct ath11k_hal_reo_cmd * cmd)48 static int ath11k_hal_reo_cmd_flush_cache(struct ath11k_hal *hal, struct hal_tlv_hdr *tlv,
49 struct ath11k_hal_reo_cmd *cmd)
50 {
51 struct hal_reo_flush_cache *desc;
52 u8 avail_slot = ffz(hal->avail_blk_resource);
53
54 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER) {
55 if (avail_slot >= HAL_MAX_AVAIL_BLK_RES)
56 return -ENOSPC;
57
58 hal->current_blk_index = avail_slot;
59 }
60
61 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_REO_FLUSH_CACHE) |
62 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc));
63
64 desc = (struct hal_reo_flush_cache *)tlv->value;
65 memset_startat(desc, 0, cache_addr_lo);
66
67 desc->cmd.info0 &= ~HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
68 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS)
69 desc->cmd.info0 |= HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
70
71 desc->cache_addr_lo = cmd->addr_lo;
72 desc->info0 = FIELD_PREP(HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI,
73 cmd->addr_hi);
74
75 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS)
76 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS;
77
78 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER) {
79 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE;
80 desc->info0 |=
81 FIELD_PREP(HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX,
82 avail_slot);
83 }
84
85 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_NO_INVAL)
86 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE;
87
88 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_ALL)
89 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL;
90
91 return FIELD_GET(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, desc->cmd.info0);
92 }
93
ath11k_hal_reo_cmd_update_rx_queue(struct hal_tlv_hdr * tlv,struct ath11k_hal_reo_cmd * cmd)94 static int ath11k_hal_reo_cmd_update_rx_queue(struct hal_tlv_hdr *tlv,
95 struct ath11k_hal_reo_cmd *cmd)
96 {
97 struct hal_reo_update_rx_queue *desc;
98
99 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_REO_UPDATE_RX_REO_QUEUE) |
100 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc));
101
102 desc = (struct hal_reo_update_rx_queue *)tlv->value;
103 memset_startat(desc, 0, queue_addr_lo);
104
105 desc->cmd.info0 &= ~HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
106 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS)
107 desc->cmd.info0 |= HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
108
109 desc->queue_addr_lo = cmd->addr_lo;
110 desc->info0 =
111 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI,
112 cmd->addr_hi) |
113 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM,
114 !!(cmd->upd0 & HAL_REO_CMD_UPD0_RX_QUEUE_NUM)) |
115 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD,
116 !!(cmd->upd0 & HAL_REO_CMD_UPD0_VLD)) |
117 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT,
118 !!(cmd->upd0 & HAL_REO_CMD_UPD0_ALDC)) |
119 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION,
120 !!(cmd->upd0 & HAL_REO_CMD_UPD0_DIS_DUP_DETECTION)) |
121 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN,
122 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SOFT_REORDER_EN)) |
123 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC,
124 !!(cmd->upd0 & HAL_REO_CMD_UPD0_AC)) |
125 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR,
126 !!(cmd->upd0 & HAL_REO_CMD_UPD0_BAR)) |
127 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY,
128 !!(cmd->upd0 & HAL_REO_CMD_UPD0_RETRY)) |
129 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE,
130 !!(cmd->upd0 & HAL_REO_CMD_UPD0_CHECK_2K_MODE)) |
131 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE,
132 !!(cmd->upd0 & HAL_REO_CMD_UPD0_OOR_MODE)) |
133 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE,
134 !!(cmd->upd0 & HAL_REO_CMD_UPD0_BA_WINDOW_SIZE)) |
135 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK,
136 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_CHECK)) |
137 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN,
138 !!(cmd->upd0 & HAL_REO_CMD_UPD0_EVEN_PN)) |
139 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN,
140 !!(cmd->upd0 & HAL_REO_CMD_UPD0_UNEVEN_PN)) |
141 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE,
142 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE)) |
143 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE,
144 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_SIZE)) |
145 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG,
146 !!(cmd->upd0 & HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG)) |
147 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD,
148 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SVLD)) |
149 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN,
150 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SSN)) |
151 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR,
152 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SEQ_2K_ERR)) |
153 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID,
154 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_VALID)) |
155 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN,
156 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN));
157
158 desc->info1 =
159 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER,
160 cmd->rx_queue_num) |
161 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_VLD,
162 !!(cmd->upd1 & HAL_REO_CMD_UPD1_VLD)) |
163 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER,
164 FIELD_GET(HAL_REO_CMD_UPD1_ALDC, cmd->upd1)) |
165 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION,
166 !!(cmd->upd1 & HAL_REO_CMD_UPD1_DIS_DUP_DETECTION)) |
167 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN,
168 !!(cmd->upd1 & HAL_REO_CMD_UPD1_SOFT_REORDER_EN)) |
169 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_AC,
170 FIELD_GET(HAL_REO_CMD_UPD1_AC, cmd->upd1)) |
171 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_BAR,
172 !!(cmd->upd1 & HAL_REO_CMD_UPD1_BAR)) |
173 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE,
174 !!(cmd->upd1 & HAL_REO_CMD_UPD1_CHECK_2K_MODE)) |
175 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_RETRY,
176 !!(cmd->upd1 & HAL_REO_CMD_UPD1_RETRY)) |
177 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE,
178 !!(cmd->upd1 & HAL_REO_CMD_UPD1_OOR_MODE)) |
179 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK,
180 !!(cmd->upd1 & HAL_REO_CMD_UPD1_PN_CHECK)) |
181 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN,
182 !!(cmd->upd1 & HAL_REO_CMD_UPD1_EVEN_PN)) |
183 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN,
184 !!(cmd->upd1 & HAL_REO_CMD_UPD1_UNEVEN_PN)) |
185 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE,
186 !!(cmd->upd1 & HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE)) |
187 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG,
188 !!(cmd->upd1 & HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG));
189
190 if (cmd->pn_size == 24)
191 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_24;
192 else if (cmd->pn_size == 48)
193 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_48;
194 else if (cmd->pn_size == 128)
195 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_128;
196
197 if (cmd->ba_window_size < 1)
198 cmd->ba_window_size = 1;
199
200 if (cmd->ba_window_size == 1)
201 cmd->ba_window_size++;
202
203 desc->info2 =
204 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE,
205 cmd->ba_window_size - 1) |
206 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE, cmd->pn_size) |
207 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_SVLD,
208 !!(cmd->upd2 & HAL_REO_CMD_UPD2_SVLD)) |
209 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_SSN,
210 FIELD_GET(HAL_REO_CMD_UPD2_SSN, cmd->upd2)) |
211 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR,
212 !!(cmd->upd2 & HAL_REO_CMD_UPD2_SEQ_2K_ERR)) |
213 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR,
214 !!(cmd->upd2 & HAL_REO_CMD_UPD2_PN_ERR));
215
216 return FIELD_GET(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, desc->cmd.info0);
217 }
218
ath11k_hal_reo_cmd_send(struct ath11k_base * ab,struct hal_srng * srng,enum hal_reo_cmd_type type,struct ath11k_hal_reo_cmd * cmd)219 int ath11k_hal_reo_cmd_send(struct ath11k_base *ab, struct hal_srng *srng,
220 enum hal_reo_cmd_type type,
221 struct ath11k_hal_reo_cmd *cmd)
222 {
223 struct hal_tlv_hdr *reo_desc;
224 int ret;
225
226 spin_lock_bh(&srng->lock);
227
228 ath11k_hal_srng_access_begin(ab, srng);
229 reo_desc = (struct hal_tlv_hdr *)ath11k_hal_srng_src_get_next_entry(ab, srng);
230 if (!reo_desc) {
231 ret = -ENOBUFS;
232 goto out;
233 }
234
235 switch (type) {
236 case HAL_REO_CMD_GET_QUEUE_STATS:
237 ret = ath11k_hal_reo_cmd_queue_stats(reo_desc, cmd);
238 break;
239 case HAL_REO_CMD_FLUSH_CACHE:
240 ret = ath11k_hal_reo_cmd_flush_cache(&ab->hal, reo_desc, cmd);
241 break;
242 case HAL_REO_CMD_UPDATE_RX_QUEUE:
243 ret = ath11k_hal_reo_cmd_update_rx_queue(reo_desc, cmd);
244 break;
245 case HAL_REO_CMD_FLUSH_QUEUE:
246 case HAL_REO_CMD_UNBLOCK_CACHE:
247 case HAL_REO_CMD_FLUSH_TIMEOUT_LIST:
248 ath11k_warn(ab, "Unsupported reo command %d\n", type);
249 ret = -ENOTSUPP;
250 break;
251 default:
252 ath11k_warn(ab, "Unknown reo command %d\n", type);
253 ret = -EINVAL;
254 break;
255 }
256
257 ath11k_dp_shadow_start_timer(ab, srng, &ab->dp.reo_cmd_timer);
258
259 out:
260 ath11k_hal_srng_access_end(ab, srng);
261 spin_unlock_bh(&srng->lock);
262
263 return ret;
264 }
265
ath11k_hal_rx_buf_addr_info_set(void * desc,dma_addr_t paddr,u32 cookie,u8 manager)266 void ath11k_hal_rx_buf_addr_info_set(void *desc, dma_addr_t paddr,
267 u32 cookie, u8 manager)
268 {
269 struct ath11k_buffer_addr *binfo = (struct ath11k_buffer_addr *)desc;
270 u32 paddr_lo, paddr_hi;
271
272 paddr_lo = lower_32_bits(paddr);
273 paddr_hi = upper_32_bits(paddr);
274 binfo->info0 = FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, paddr_lo);
275 binfo->info1 = FIELD_PREP(BUFFER_ADDR_INFO1_ADDR, paddr_hi) |
276 FIELD_PREP(BUFFER_ADDR_INFO1_SW_COOKIE, cookie) |
277 FIELD_PREP(BUFFER_ADDR_INFO1_RET_BUF_MGR, manager);
278 }
279
ath11k_hal_rx_buf_addr_info_get(void * desc,dma_addr_t * paddr,u32 * cookie,u8 * rbm)280 void ath11k_hal_rx_buf_addr_info_get(void *desc, dma_addr_t *paddr,
281 u32 *cookie, u8 *rbm)
282 {
283 struct ath11k_buffer_addr *binfo = (struct ath11k_buffer_addr *)desc;
284
285 *paddr =
286 (((u64)FIELD_GET(BUFFER_ADDR_INFO1_ADDR, binfo->info1)) << 32) |
287 FIELD_GET(BUFFER_ADDR_INFO0_ADDR, binfo->info0);
288 *cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, binfo->info1);
289 *rbm = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR, binfo->info1);
290 }
291
ath11k_hal_rx_msdu_link_info_get(void * link_desc,u32 * num_msdus,u32 * msdu_cookies,enum hal_rx_buf_return_buf_manager * rbm)292 void ath11k_hal_rx_msdu_link_info_get(void *link_desc, u32 *num_msdus,
293 u32 *msdu_cookies,
294 enum hal_rx_buf_return_buf_manager *rbm)
295 {
296 struct hal_rx_msdu_link *link = (struct hal_rx_msdu_link *)link_desc;
297 struct hal_rx_msdu_details *msdu;
298 int i;
299
300 *num_msdus = HAL_NUM_RX_MSDUS_PER_LINK_DESC;
301
302 msdu = &link->msdu_link[0];
303 *rbm = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
304 msdu->buf_addr_info.info1);
305
306 for (i = 0; i < *num_msdus; i++) {
307 msdu = &link->msdu_link[i];
308
309 if (!FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
310 msdu->buf_addr_info.info0)) {
311 *num_msdus = i;
312 break;
313 }
314 *msdu_cookies = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
315 msdu->buf_addr_info.info1);
316 msdu_cookies++;
317 }
318 }
319
ath11k_hal_desc_reo_parse_err(struct ath11k_base * ab,u32 * rx_desc,dma_addr_t * paddr,u32 * desc_bank)320 int ath11k_hal_desc_reo_parse_err(struct ath11k_base *ab, u32 *rx_desc,
321 dma_addr_t *paddr, u32 *desc_bank)
322 {
323 struct hal_reo_dest_ring *desc = (struct hal_reo_dest_ring *)rx_desc;
324 enum hal_reo_dest_ring_push_reason push_reason;
325 enum hal_reo_dest_ring_error_code err_code;
326
327 push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON,
328 desc->info0);
329 err_code = FIELD_GET(HAL_REO_DEST_RING_INFO0_ERROR_CODE,
330 desc->info0);
331 ab->soc_stats.reo_error[err_code]++;
332
333 if (push_reason != HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED &&
334 push_reason != HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) {
335 ath11k_warn(ab, "expected error push reason code, received %d\n",
336 push_reason);
337 return -EINVAL;
338 }
339
340 if (FIELD_GET(HAL_REO_DEST_RING_INFO0_BUFFER_TYPE, desc->info0) !=
341 HAL_REO_DEST_RING_BUFFER_TYPE_LINK_DESC) {
342 ath11k_warn(ab, "expected buffer type link_desc");
343 return -EINVAL;
344 }
345
346 ath11k_hal_rx_reo_ent_paddr_get(ab, rx_desc, paddr, desc_bank);
347
348 return 0;
349 }
350
ath11k_hal_wbm_desc_parse_err(struct ath11k_base * ab,void * desc,struct hal_rx_wbm_rel_info * rel_info)351 int ath11k_hal_wbm_desc_parse_err(struct ath11k_base *ab, void *desc,
352 struct hal_rx_wbm_rel_info *rel_info)
353 {
354 struct hal_wbm_release_ring *wbm_desc = desc;
355 enum hal_wbm_rel_desc_type type;
356 enum hal_wbm_rel_src_module rel_src;
357 enum hal_rx_buf_return_buf_manager ret_buf_mgr;
358
359 type = FIELD_GET(HAL_WBM_RELEASE_INFO0_DESC_TYPE,
360 wbm_desc->info0);
361 /* We expect only WBM_REL buffer type */
362 if (type != HAL_WBM_REL_DESC_TYPE_REL_MSDU) {
363 WARN_ON(1);
364 return -EINVAL;
365 }
366
367 rel_src = FIELD_GET(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE,
368 wbm_desc->info0);
369 if (rel_src != HAL_WBM_REL_SRC_MODULE_RXDMA &&
370 rel_src != HAL_WBM_REL_SRC_MODULE_REO)
371 return -EINVAL;
372
373 ret_buf_mgr = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
374 wbm_desc->buf_addr_info.info1);
375 if (ret_buf_mgr != HAL_RX_BUF_RBM_SW1_BM &&
376 ret_buf_mgr != HAL_RX_BUF_RBM_SW3_BM) {
377 ab->soc_stats.invalid_rbm++;
378 return -EINVAL;
379 }
380
381 rel_info->cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
382 wbm_desc->buf_addr_info.info1);
383 rel_info->err_rel_src = rel_src;
384 if (rel_src == HAL_WBM_REL_SRC_MODULE_REO) {
385 rel_info->push_reason =
386 FIELD_GET(HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON,
387 wbm_desc->info0);
388 rel_info->err_code =
389 FIELD_GET(HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE,
390 wbm_desc->info0);
391 } else {
392 rel_info->push_reason =
393 FIELD_GET(HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON,
394 wbm_desc->info0);
395 rel_info->err_code =
396 FIELD_GET(HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE,
397 wbm_desc->info0);
398 }
399
400 rel_info->first_msdu = FIELD_GET(HAL_WBM_RELEASE_INFO2_FIRST_MSDU,
401 wbm_desc->info2);
402 rel_info->last_msdu = FIELD_GET(HAL_WBM_RELEASE_INFO2_LAST_MSDU,
403 wbm_desc->info2);
404 return 0;
405 }
406
ath11k_hal_rx_reo_ent_paddr_get(struct ath11k_base * ab,void * desc,dma_addr_t * paddr,u32 * desc_bank)407 void ath11k_hal_rx_reo_ent_paddr_get(struct ath11k_base *ab, void *desc,
408 dma_addr_t *paddr, u32 *desc_bank)
409 {
410 struct ath11k_buffer_addr *buff_addr = desc;
411
412 *paddr = ((u64)(FIELD_GET(BUFFER_ADDR_INFO1_ADDR, buff_addr->info1)) << 32) |
413 FIELD_GET(BUFFER_ADDR_INFO0_ADDR, buff_addr->info0);
414
415 *desc_bank = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, buff_addr->info1);
416 }
417
ath11k_hal_rx_msdu_link_desc_set(struct ath11k_base * ab,void * desc,void * link_desc,enum hal_wbm_rel_bm_act action)418 void ath11k_hal_rx_msdu_link_desc_set(struct ath11k_base *ab, void *desc,
419 void *link_desc,
420 enum hal_wbm_rel_bm_act action)
421 {
422 struct hal_wbm_release_ring *dst_desc = desc;
423 struct hal_wbm_release_ring *src_desc = link_desc;
424
425 dst_desc->buf_addr_info = src_desc->buf_addr_info;
426 dst_desc->info0 |= FIELD_PREP(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE,
427 HAL_WBM_REL_SRC_MODULE_SW) |
428 FIELD_PREP(HAL_WBM_RELEASE_INFO0_BM_ACTION, action) |
429 FIELD_PREP(HAL_WBM_RELEASE_INFO0_DESC_TYPE,
430 HAL_WBM_REL_DESC_TYPE_MSDU_LINK);
431 }
432
ath11k_hal_reo_status_queue_stats(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)433 void ath11k_hal_reo_status_queue_stats(struct ath11k_base *ab, u32 *reo_desc,
434 struct hal_reo_status *status)
435 {
436 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
437 struct hal_reo_get_queue_stats_status *desc =
438 (struct hal_reo_get_queue_stats_status *)tlv->value;
439
440 status->uniform_hdr.cmd_num =
441 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
442 desc->hdr.info0);
443 status->uniform_hdr.cmd_status =
444 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
445 desc->hdr.info0);
446
447 ath11k_dbg(ab, ATH11K_DBG_HAL, "Queue stats status:\n");
448 ath11k_dbg(ab, ATH11K_DBG_HAL, "header: cmd_num %d status %d\n",
449 status->uniform_hdr.cmd_num,
450 status->uniform_hdr.cmd_status);
451 ath11k_dbg(ab, ATH11K_DBG_HAL, "ssn %ld cur_idx %ld\n",
452 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN,
453 desc->info0),
454 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX,
455 desc->info0));
456 ath11k_dbg(ab, ATH11K_DBG_HAL, "pn = [%08x, %08x, %08x, %08x]\n",
457 desc->pn[0], desc->pn[1], desc->pn[2], desc->pn[3]);
458 ath11k_dbg(ab, ATH11K_DBG_HAL,
459 "last_rx: enqueue_tstamp %08x dequeue_tstamp %08x\n",
460 desc->last_rx_enqueue_timestamp,
461 desc->last_rx_dequeue_timestamp);
462 ath11k_dbg(ab, ATH11K_DBG_HAL,
463 "rx_bitmap [%08x %08x %08x %08x %08x %08x %08x %08x]\n",
464 desc->rx_bitmap[0], desc->rx_bitmap[1], desc->rx_bitmap[2],
465 desc->rx_bitmap[3], desc->rx_bitmap[4], desc->rx_bitmap[5],
466 desc->rx_bitmap[6], desc->rx_bitmap[7]);
467 ath11k_dbg(ab, ATH11K_DBG_HAL, "count: cur_mpdu %ld cur_msdu %ld\n",
468 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT,
469 desc->info1),
470 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT,
471 desc->info1));
472 ath11k_dbg(ab, ATH11K_DBG_HAL, "fwd_timeout %ld fwd_bar %ld dup_count %ld\n",
473 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT,
474 desc->info2),
475 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT,
476 desc->info2),
477 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT,
478 desc->info2));
479 ath11k_dbg(ab, ATH11K_DBG_HAL, "frames_in_order %ld bar_rcvd %ld\n",
480 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT,
481 desc->info3),
482 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT,
483 desc->info3));
484 ath11k_dbg(ab, ATH11K_DBG_HAL, "num_mpdus %d num_msdus %d total_bytes %d\n",
485 desc->num_mpdu_frames, desc->num_msdu_frames,
486 desc->total_bytes);
487 ath11k_dbg(ab, ATH11K_DBG_HAL, "late_rcvd %ld win_jump_2k %ld hole_cnt %ld\n",
488 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU,
489 desc->info4),
490 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_WINDOW_JMP2K,
491 desc->info4),
492 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT,
493 desc->info4));
494 ath11k_dbg(ab, ATH11K_DBG_HAL, "looping count %ld\n",
495 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT,
496 desc->info5));
497 }
498
ath11k_hal_reo_process_status(u8 * reo_desc,u8 * status)499 int ath11k_hal_reo_process_status(u8 *reo_desc, u8 *status)
500 {
501 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
502 struct hal_reo_status_hdr *hdr;
503
504 hdr = (struct hal_reo_status_hdr *)tlv->value;
505 *status = FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, hdr->info0);
506
507 return FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, hdr->info0);
508 }
509
ath11k_hal_reo_flush_queue_status(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)510 void ath11k_hal_reo_flush_queue_status(struct ath11k_base *ab, u32 *reo_desc,
511 struct hal_reo_status *status)
512 {
513 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
514 struct hal_reo_flush_queue_status *desc =
515 (struct hal_reo_flush_queue_status *)tlv->value;
516
517 status->uniform_hdr.cmd_num =
518 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
519 desc->hdr.info0);
520 status->uniform_hdr.cmd_status =
521 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
522 desc->hdr.info0);
523 status->u.flush_queue.err_detected =
524 FIELD_GET(HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED,
525 desc->info0);
526 }
527
ath11k_hal_reo_flush_cache_status(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)528 void ath11k_hal_reo_flush_cache_status(struct ath11k_base *ab, u32 *reo_desc,
529 struct hal_reo_status *status)
530 {
531 struct ath11k_hal *hal = &ab->hal;
532 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
533 struct hal_reo_flush_cache_status *desc =
534 (struct hal_reo_flush_cache_status *)tlv->value;
535
536 status->uniform_hdr.cmd_num =
537 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
538 desc->hdr.info0);
539 status->uniform_hdr.cmd_status =
540 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
541 desc->hdr.info0);
542
543 status->u.flush_cache.err_detected =
544 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR,
545 desc->info0);
546 status->u.flush_cache.err_code =
547 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE,
548 desc->info0);
549 if (!status->u.flush_cache.err_code)
550 hal->avail_blk_resource |= BIT(hal->current_blk_index);
551
552 status->u.flush_cache.cache_controller_flush_status_hit =
553 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT,
554 desc->info0);
555
556 status->u.flush_cache.cache_controller_flush_status_desc_type =
557 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE,
558 desc->info0);
559 status->u.flush_cache.cache_controller_flush_status_client_id =
560 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID,
561 desc->info0);
562 status->u.flush_cache.cache_controller_flush_status_err =
563 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR,
564 desc->info0);
565 status->u.flush_cache.cache_controller_flush_status_cnt =
566 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT,
567 desc->info0);
568 }
569
ath11k_hal_reo_unblk_cache_status(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)570 void ath11k_hal_reo_unblk_cache_status(struct ath11k_base *ab, u32 *reo_desc,
571 struct hal_reo_status *status)
572 {
573 struct ath11k_hal *hal = &ab->hal;
574 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
575 struct hal_reo_unblock_cache_status *desc =
576 (struct hal_reo_unblock_cache_status *)tlv->value;
577
578 status->uniform_hdr.cmd_num =
579 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
580 desc->hdr.info0);
581 status->uniform_hdr.cmd_status =
582 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
583 desc->hdr.info0);
584
585 status->u.unblock_cache.err_detected =
586 FIELD_GET(HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR,
587 desc->info0);
588 status->u.unblock_cache.unblock_type =
589 FIELD_GET(HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE,
590 desc->info0);
591
592 if (!status->u.unblock_cache.err_detected &&
593 status->u.unblock_cache.unblock_type ==
594 HAL_REO_STATUS_UNBLOCK_BLOCKING_RESOURCE)
595 hal->avail_blk_resource &= ~BIT(hal->current_blk_index);
596 }
597
ath11k_hal_reo_flush_timeout_list_status(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)598 void ath11k_hal_reo_flush_timeout_list_status(struct ath11k_base *ab,
599 u32 *reo_desc,
600 struct hal_reo_status *status)
601 {
602 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
603 struct hal_reo_flush_timeout_list_status *desc =
604 (struct hal_reo_flush_timeout_list_status *)tlv->value;
605
606 status->uniform_hdr.cmd_num =
607 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
608 desc->hdr.info0);
609 status->uniform_hdr.cmd_status =
610 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
611 desc->hdr.info0);
612
613 status->u.timeout_list.err_detected =
614 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR,
615 desc->info0);
616 status->u.timeout_list.list_empty =
617 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY,
618 desc->info0);
619
620 status->u.timeout_list.release_desc_cnt =
621 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT,
622 desc->info1);
623 status->u.timeout_list.fwd_buf_cnt =
624 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT,
625 desc->info1);
626 }
627
ath11k_hal_reo_desc_thresh_reached_status(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)628 void ath11k_hal_reo_desc_thresh_reached_status(struct ath11k_base *ab,
629 u32 *reo_desc,
630 struct hal_reo_status *status)
631 {
632 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
633 struct hal_reo_desc_thresh_reached_status *desc =
634 (struct hal_reo_desc_thresh_reached_status *)tlv->value;
635
636 status->uniform_hdr.cmd_num =
637 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
638 desc->hdr.info0);
639 status->uniform_hdr.cmd_status =
640 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
641 desc->hdr.info0);
642
643 status->u.desc_thresh_reached.threshold_idx =
644 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX,
645 desc->info0);
646
647 status->u.desc_thresh_reached.link_desc_counter0 =
648 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0,
649 desc->info1);
650
651 status->u.desc_thresh_reached.link_desc_counter1 =
652 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1,
653 desc->info2);
654
655 status->u.desc_thresh_reached.link_desc_counter2 =
656 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2,
657 desc->info3);
658
659 status->u.desc_thresh_reached.link_desc_counter_sum =
660 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM,
661 desc->info4);
662 }
663
ath11k_hal_reo_update_rx_reo_queue_status(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)664 void ath11k_hal_reo_update_rx_reo_queue_status(struct ath11k_base *ab,
665 u32 *reo_desc,
666 struct hal_reo_status *status)
667 {
668 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
669 struct hal_reo_status_hdr *desc =
670 (struct hal_reo_status_hdr *)tlv->value;
671
672 status->uniform_hdr.cmd_num =
673 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
674 desc->info0);
675 status->uniform_hdr.cmd_status =
676 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
677 desc->info0);
678 }
679
ath11k_hal_reo_qdesc_size(u32 ba_window_size,u8 tid)680 u32 ath11k_hal_reo_qdesc_size(u32 ba_window_size, u8 tid)
681 {
682 u32 num_ext_desc;
683
684 if (ba_window_size <= 1) {
685 if (tid != HAL_DESC_REO_NON_QOS_TID)
686 num_ext_desc = 1;
687 else
688 num_ext_desc = 0;
689 } else if (ba_window_size <= 105) {
690 num_ext_desc = 1;
691 } else if (ba_window_size <= 210) {
692 num_ext_desc = 2;
693 } else {
694 num_ext_desc = 3;
695 }
696
697 return sizeof(struct hal_rx_reo_queue) +
698 (num_ext_desc * sizeof(struct hal_rx_reo_queue_ext));
699 }
700
ath11k_hal_reo_qdesc_setup(void * vaddr,int tid,u32 ba_window_size,u32 start_seq,enum hal_pn_type type)701 void ath11k_hal_reo_qdesc_setup(void *vaddr, int tid, u32 ba_window_size,
702 u32 start_seq, enum hal_pn_type type)
703 {
704 struct hal_rx_reo_queue *qdesc = (struct hal_rx_reo_queue *)vaddr;
705 struct hal_rx_reo_queue_ext *ext_desc;
706
707 memset(qdesc, 0, sizeof(*qdesc));
708
709 ath11k_hal_reo_set_desc_hdr(&qdesc->desc_hdr, HAL_DESC_REO_OWNED,
710 HAL_DESC_REO_QUEUE_DESC,
711 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0);
712
713 qdesc->rx_queue_num = FIELD_PREP(HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER, tid);
714
715 qdesc->info0 =
716 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_VLD, 1) |
717 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER, 1) |
718 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_AC, ath11k_tid_to_ac(tid));
719
720 if (ba_window_size < 1)
721 ba_window_size = 1;
722
723 if (ba_window_size == 1 && tid != HAL_DESC_REO_NON_QOS_TID)
724 ba_window_size++;
725
726 if (ba_window_size == 1)
727 qdesc->info0 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_RETRY, 1);
728
729 qdesc->info0 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE,
730 ba_window_size - 1);
731 switch (type) {
732 case HAL_PN_TYPE_NONE:
733 case HAL_PN_TYPE_WAPI_EVEN:
734 case HAL_PN_TYPE_WAPI_UNEVEN:
735 break;
736 case HAL_PN_TYPE_WPA:
737 qdesc->info0 |=
738 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_PN_CHECK, 1) |
739 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_PN_SIZE,
740 HAL_RX_REO_QUEUE_PN_SIZE_48);
741 break;
742 }
743
744 /* TODO: Set Ignore ampdu flags based on BA window size and/or
745 * AMPDU capabilities
746 */
747 qdesc->info0 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG, 1);
748
749 qdesc->info1 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO1_SVLD, 0);
750
751 if (start_seq <= 0xfff)
752 qdesc->info1 = FIELD_PREP(HAL_RX_REO_QUEUE_INFO1_SSN,
753 start_seq);
754
755 if (tid == HAL_DESC_REO_NON_QOS_TID)
756 return;
757
758 ext_desc = qdesc->ext_desc;
759
760 /* TODO: HW queue descriptors are currently allocated for max BA
761 * window size for all QOS TIDs so that same descriptor can be used
762 * later when ADDBA request is received. This should be changed to
763 * allocate HW queue descriptors based on BA window size being
764 * negotiated (0 for non BA cases), and reallocate when BA window
765 * size changes and also send WMI message to FW to change the REO
766 * queue descriptor in Rx peer entry as part of dp_rx_tid_update.
767 */
768 memset(ext_desc, 0, sizeof(*ext_desc));
769 ath11k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED,
770 HAL_DESC_REO_QUEUE_EXT_DESC,
771 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1);
772 ext_desc++;
773 memset(ext_desc, 0, sizeof(*ext_desc));
774 ath11k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED,
775 HAL_DESC_REO_QUEUE_EXT_DESC,
776 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2);
777 ext_desc++;
778 memset(ext_desc, 0, sizeof(*ext_desc));
779 ath11k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED,
780 HAL_DESC_REO_QUEUE_EXT_DESC,
781 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3);
782 }
783
ath11k_hal_reo_init_cmd_ring(struct ath11k_base * ab,struct hal_srng * srng)784 void ath11k_hal_reo_init_cmd_ring(struct ath11k_base *ab,
785 struct hal_srng *srng)
786 {
787 struct hal_srng_params params;
788 struct hal_tlv_hdr *tlv;
789 struct hal_reo_get_queue_stats *desc;
790 int i, cmd_num = 1;
791 int entry_size;
792 u8 *entry;
793
794 memset(¶ms, 0, sizeof(params));
795
796 entry_size = ath11k_hal_srng_get_entrysize(ab, HAL_REO_CMD);
797 ath11k_hal_srng_get_params(ab, srng, ¶ms);
798 entry = (u8 *)params.ring_base_vaddr;
799
800 for (i = 0; i < params.num_entries; i++) {
801 tlv = (struct hal_tlv_hdr *)entry;
802 desc = (struct hal_reo_get_queue_stats *)tlv->value;
803 desc->cmd.info0 =
804 FIELD_PREP(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, cmd_num++);
805 entry += entry_size;
806 }
807 }
808
809 #define HAL_MAX_UL_MU_USERS 37
810 static inline void
ath11k_hal_rx_handle_ofdma_info(void * rx_tlv,struct hal_rx_user_status * rx_user_status)811 ath11k_hal_rx_handle_ofdma_info(void *rx_tlv,
812 struct hal_rx_user_status *rx_user_status)
813 {
814 struct hal_rx_ppdu_end_user_stats *ppdu_end_user =
815 (struct hal_rx_ppdu_end_user_stats *)rx_tlv;
816
817 rx_user_status->ul_ofdma_user_v0_word0 = __le32_to_cpu(ppdu_end_user->info6);
818
819 rx_user_status->ul_ofdma_user_v0_word1 = __le32_to_cpu(ppdu_end_user->rsvd2[10]);
820 }
821
822 static inline void
ath11k_hal_rx_populate_byte_count(void * rx_tlv,void * ppduinfo,struct hal_rx_user_status * rx_user_status)823 ath11k_hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo,
824 struct hal_rx_user_status *rx_user_status)
825 {
826 struct hal_rx_ppdu_end_user_stats *ppdu_end_user =
827 (struct hal_rx_ppdu_end_user_stats *)rx_tlv;
828
829 rx_user_status->mpdu_ok_byte_count =
830 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_RSVD2_6_MPDU_OK_BYTE_COUNT,
831 __le32_to_cpu(ppdu_end_user->rsvd2[6]));
832 rx_user_status->mpdu_err_byte_count =
833 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_RSVD2_8_MPDU_ERR_BYTE_COUNT,
834 __le32_to_cpu(ppdu_end_user->rsvd2[8]));
835 }
836
837 static inline void
ath11k_hal_rx_populate_mu_user_info(void * rx_tlv,struct hal_rx_mon_ppdu_info * ppdu_info,struct hal_rx_user_status * rx_user_status)838 ath11k_hal_rx_populate_mu_user_info(void *rx_tlv, struct hal_rx_mon_ppdu_info *ppdu_info,
839 struct hal_rx_user_status *rx_user_status)
840 {
841 rx_user_status->ast_index = ppdu_info->ast_index;
842 rx_user_status->tid = ppdu_info->tid;
843 rx_user_status->tcp_msdu_count =
844 ppdu_info->tcp_msdu_count;
845 rx_user_status->udp_msdu_count =
846 ppdu_info->udp_msdu_count;
847 rx_user_status->other_msdu_count =
848 ppdu_info->other_msdu_count;
849 rx_user_status->frame_control = ppdu_info->frame_control;
850 rx_user_status->frame_control_info_valid =
851 ppdu_info->frame_control_info_valid;
852 rx_user_status->data_sequence_control_info_valid =
853 ppdu_info->data_sequence_control_info_valid;
854 rx_user_status->first_data_seq_ctrl =
855 ppdu_info->first_data_seq_ctrl;
856 rx_user_status->preamble_type = ppdu_info->preamble_type;
857 rx_user_status->ht_flags = ppdu_info->ht_flags;
858 rx_user_status->vht_flags = ppdu_info->vht_flags;
859 rx_user_status->he_flags = ppdu_info->he_flags;
860 rx_user_status->rs_flags = ppdu_info->rs_flags;
861
862 rx_user_status->mpdu_cnt_fcs_ok =
863 ppdu_info->num_mpdu_fcs_ok;
864 rx_user_status->mpdu_cnt_fcs_err =
865 ppdu_info->num_mpdu_fcs_err;
866
867 ath11k_hal_rx_populate_byte_count(rx_tlv, ppdu_info, rx_user_status);
868 }
869
ath11k_hal_rx_mpduinfo_get_peerid(struct ath11k_base * ab,struct hal_rx_mpdu_info * mpdu_info)870 static u16 ath11k_hal_rx_mpduinfo_get_peerid(struct ath11k_base *ab,
871 struct hal_rx_mpdu_info *mpdu_info)
872 {
873 return ab->hw_params.hw_ops->mpdu_info_get_peerid(mpdu_info);
874 }
875
876 static enum hal_rx_mon_status
ath11k_hal_rx_parse_mon_status_tlv(struct ath11k_base * ab,struct hal_rx_mon_ppdu_info * ppdu_info,u32 tlv_tag,u8 * tlv_data,u32 userid)877 ath11k_hal_rx_parse_mon_status_tlv(struct ath11k_base *ab,
878 struct hal_rx_mon_ppdu_info *ppdu_info,
879 u32 tlv_tag, u8 *tlv_data, u32 userid)
880 {
881 u32 info0, info1, value;
882 u8 he_dcm = 0, he_stbc = 0;
883 u16 he_gi = 0, he_ltf = 0;
884
885 switch (tlv_tag) {
886 case HAL_RX_PPDU_START: {
887 struct hal_rx_ppdu_start *ppdu_start =
888 (struct hal_rx_ppdu_start *)tlv_data;
889
890 ppdu_info->ppdu_id =
891 FIELD_GET(HAL_RX_PPDU_START_INFO0_PPDU_ID,
892 __le32_to_cpu(ppdu_start->info0));
893 ppdu_info->chan_num = __le32_to_cpu(ppdu_start->chan_num);
894 ppdu_info->ppdu_ts = __le32_to_cpu(ppdu_start->ppdu_start_ts);
895 break;
896 }
897 case HAL_RX_PPDU_END_USER_STATS: {
898 struct hal_rx_ppdu_end_user_stats *eu_stats =
899 (struct hal_rx_ppdu_end_user_stats *)tlv_data;
900
901 info0 = __le32_to_cpu(eu_stats->info0);
902 info1 = __le32_to_cpu(eu_stats->info1);
903
904 ppdu_info->ast_index =
905 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX,
906 __le32_to_cpu(eu_stats->info2));
907 ppdu_info->tid =
908 ffs(FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP,
909 __le32_to_cpu(eu_stats->info6))) - 1;
910 ppdu_info->tcp_msdu_count =
911 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT,
912 __le32_to_cpu(eu_stats->info4));
913 ppdu_info->udp_msdu_count =
914 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT,
915 __le32_to_cpu(eu_stats->info4));
916 ppdu_info->other_msdu_count =
917 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT,
918 __le32_to_cpu(eu_stats->info5));
919 ppdu_info->tcp_ack_msdu_count =
920 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT,
921 __le32_to_cpu(eu_stats->info5));
922 ppdu_info->preamble_type =
923 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE, info1);
924 ppdu_info->num_mpdu_fcs_ok =
925 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK,
926 info1);
927 ppdu_info->num_mpdu_fcs_err =
928 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR,
929 info0);
930 switch (ppdu_info->preamble_type) {
931 case HAL_RX_PREAMBLE_11N:
932 ppdu_info->ht_flags = 1;
933 break;
934 case HAL_RX_PREAMBLE_11AC:
935 ppdu_info->vht_flags = 1;
936 break;
937 case HAL_RX_PREAMBLE_11AX:
938 ppdu_info->he_flags = 1;
939 break;
940 default:
941 break;
942 }
943
944 if (userid < HAL_MAX_UL_MU_USERS) {
945 struct hal_rx_user_status *rxuser_stats =
946 &ppdu_info->userstats;
947
948 ath11k_hal_rx_handle_ofdma_info(tlv_data, rxuser_stats);
949 ath11k_hal_rx_populate_mu_user_info(tlv_data, ppdu_info,
950 rxuser_stats);
951 }
952 ppdu_info->userstats.mpdu_fcs_ok_bitmap[0] =
953 __le32_to_cpu(eu_stats->rsvd1[0]);
954 ppdu_info->userstats.mpdu_fcs_ok_bitmap[1] =
955 __le32_to_cpu(eu_stats->rsvd1[1]);
956
957 break;
958 }
959 case HAL_RX_PPDU_END_USER_STATS_EXT: {
960 struct hal_rx_ppdu_end_user_stats_ext *eu_stats =
961 (struct hal_rx_ppdu_end_user_stats_ext *)tlv_data;
962 ppdu_info->userstats.mpdu_fcs_ok_bitmap[2] = eu_stats->info1;
963 ppdu_info->userstats.mpdu_fcs_ok_bitmap[3] = eu_stats->info2;
964 ppdu_info->userstats.mpdu_fcs_ok_bitmap[4] = eu_stats->info3;
965 ppdu_info->userstats.mpdu_fcs_ok_bitmap[5] = eu_stats->info4;
966 ppdu_info->userstats.mpdu_fcs_ok_bitmap[6] = eu_stats->info5;
967 ppdu_info->userstats.mpdu_fcs_ok_bitmap[7] = eu_stats->info6;
968 break;
969 }
970 case HAL_PHYRX_HT_SIG: {
971 struct hal_rx_ht_sig_info *ht_sig =
972 (struct hal_rx_ht_sig_info *)tlv_data;
973
974 info0 = __le32_to_cpu(ht_sig->info0);
975 info1 = __le32_to_cpu(ht_sig->info1);
976
977 ppdu_info->mcs = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO0_MCS, info0);
978 ppdu_info->bw = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO0_BW, info0);
979 ppdu_info->is_stbc = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO1_STBC,
980 info1);
981 ppdu_info->ldpc = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING, info1);
982 ppdu_info->gi = info1 & HAL_RX_HT_SIG_INFO_INFO1_GI;
983
984 switch (ppdu_info->mcs) {
985 case 0 ... 7:
986 ppdu_info->nss = 1;
987 break;
988 case 8 ... 15:
989 ppdu_info->nss = 2;
990 break;
991 case 16 ... 23:
992 ppdu_info->nss = 3;
993 break;
994 case 24 ... 31:
995 ppdu_info->nss = 4;
996 break;
997 }
998
999 if (ppdu_info->nss > 1)
1000 ppdu_info->mcs = ppdu_info->mcs % 8;
1001
1002 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
1003 break;
1004 }
1005 case HAL_PHYRX_L_SIG_B: {
1006 struct hal_rx_lsig_b_info *lsigb =
1007 (struct hal_rx_lsig_b_info *)tlv_data;
1008
1009 ppdu_info->rate = FIELD_GET(HAL_RX_LSIG_B_INFO_INFO0_RATE,
1010 __le32_to_cpu(lsigb->info0));
1011 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
1012 break;
1013 }
1014 case HAL_PHYRX_L_SIG_A: {
1015 struct hal_rx_lsig_a_info *lsiga =
1016 (struct hal_rx_lsig_a_info *)tlv_data;
1017
1018 ppdu_info->rate = FIELD_GET(HAL_RX_LSIG_A_INFO_INFO0_RATE,
1019 __le32_to_cpu(lsiga->info0));
1020 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
1021 break;
1022 }
1023 case HAL_PHYRX_VHT_SIG_A: {
1024 struct hal_rx_vht_sig_a_info *vht_sig =
1025 (struct hal_rx_vht_sig_a_info *)tlv_data;
1026 u32 nsts;
1027 u32 group_id;
1028 u8 gi_setting;
1029
1030 info0 = __le32_to_cpu(vht_sig->info0);
1031 info1 = __le32_to_cpu(vht_sig->info1);
1032
1033 ppdu_info->ldpc = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING,
1034 info1);
1035 ppdu_info->mcs = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_MCS,
1036 info1);
1037 gi_setting = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING,
1038 info1);
1039 switch (gi_setting) {
1040 case HAL_RX_VHT_SIG_A_NORMAL_GI:
1041 ppdu_info->gi = HAL_RX_GI_0_8_US;
1042 break;
1043 case HAL_RX_VHT_SIG_A_SHORT_GI:
1044 case HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY:
1045 ppdu_info->gi = HAL_RX_GI_0_4_US;
1046 break;
1047 }
1048
1049 ppdu_info->is_stbc = info0 & HAL_RX_VHT_SIG_A_INFO_INFO0_STBC;
1050 nsts = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS, info0);
1051 if (ppdu_info->is_stbc && nsts > 0)
1052 nsts = ((nsts + 1) >> 1) - 1;
1053
1054 ppdu_info->nss = (nsts & VHT_SIG_SU_NSS_MASK) + 1;
1055 ppdu_info->bw = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO0_BW,
1056 info0);
1057 ppdu_info->beamformed = info1 &
1058 HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED;
1059 group_id = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID,
1060 info0);
1061 if (group_id == 0 || group_id == 63)
1062 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
1063 else
1064 ppdu_info->reception_type =
1065 HAL_RX_RECEPTION_TYPE_MU_MIMO;
1066 ppdu_info->vht_flag_values5 = group_id;
1067 ppdu_info->vht_flag_values3[0] = (((ppdu_info->mcs) << 4) |
1068 ppdu_info->nss);
1069 ppdu_info->vht_flag_values2 = ppdu_info->bw;
1070 ppdu_info->vht_flag_values4 =
1071 FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING, info1);
1072 break;
1073 }
1074 case HAL_PHYRX_HE_SIG_A_SU: {
1075 struct hal_rx_he_sig_a_su_info *he_sig_a =
1076 (struct hal_rx_he_sig_a_su_info *)tlv_data;
1077
1078 ppdu_info->he_flags = 1;
1079 info0 = __le32_to_cpu(he_sig_a->info0);
1080 info1 = __le32_to_cpu(he_sig_a->info1);
1081
1082 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND, info0);
1083
1084 if (value == 0)
1085 ppdu_info->he_data1 = IEEE80211_RADIOTAP_HE_DATA1_FORMAT_TRIG;
1086 else
1087 ppdu_info->he_data1 = IEEE80211_RADIOTAP_HE_DATA1_FORMAT_SU;
1088
1089 ppdu_info->he_data1 |=
1090 IEEE80211_RADIOTAP_HE_DATA1_BSS_COLOR_KNOWN |
1091 IEEE80211_RADIOTAP_HE_DATA1_BEAM_CHANGE_KNOWN |
1092 IEEE80211_RADIOTAP_HE_DATA1_UL_DL_KNOWN |
1093 IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
1094 IEEE80211_RADIOTAP_HE_DATA1_DATA_DCM_KNOWN |
1095 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN |
1096 IEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN |
1097 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN |
1098 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN |
1099 IEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN;
1100
1101 ppdu_info->he_data2 |=
1102 IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN |
1103 IEEE80211_RADIOTAP_HE_DATA2_TXBF_KNOWN |
1104 IEEE80211_RADIOTAP_HE_DATA2_PE_DISAMBIG_KNOWN |
1105 IEEE80211_RADIOTAP_HE_DATA2_TXOP_KNOWN |
1106 IEEE80211_RADIOTAP_HE_DATA2_NUM_LTF_SYMS_KNOWN |
1107 IEEE80211_RADIOTAP_HE_DATA2_PRE_FEC_PAD_KNOWN |
1108 IEEE80211_RADIOTAP_HE_DATA2_MIDAMBLE_KNOWN;
1109
1110 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR, info0);
1111 ppdu_info->he_data3 =
1112 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_BSS_COLOR, value);
1113 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE, info0);
1114 ppdu_info->he_data3 |=
1115 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_BEAM_CHANGE, value);
1116 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG, info0);
1117 ppdu_info->he_data3 |=
1118 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_UL_DL, value);
1119 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS, info0);
1120 ppdu_info->mcs = value;
1121 ppdu_info->he_data3 |=
1122 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_DATA_MCS, value);
1123
1124 he_dcm = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM, info0);
1125 ppdu_info->dcm = he_dcm;
1126 ppdu_info->he_data3 |=
1127 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_DATA_DCM, he_dcm);
1128 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING, info1);
1129 ppdu_info->ldpc = (value == HAL_RX_SU_MU_CODING_LDPC) ? 1 : 0;
1130 ppdu_info->he_data3 |=
1131 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_CODING, value);
1132 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA, info1);
1133 ppdu_info->he_data3 |=
1134 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_LDPC_XSYMSEG, value);
1135 he_stbc = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC, info1);
1136 ppdu_info->is_stbc = he_stbc;
1137 ppdu_info->he_data3 |=
1138 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_STBC, he_stbc);
1139
1140 /* data4 */
1141 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE, info0);
1142 ppdu_info->he_data4 =
1143 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA4_SU_MU_SPTL_REUSE, value);
1144
1145 /* data5 */
1146 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW, info0);
1147 ppdu_info->bw = value;
1148 ppdu_info->he_data5 =
1149 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC, value);
1150 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE, info0);
1151 switch (value) {
1152 case 0:
1153 he_gi = HE_GI_0_8;
1154 he_ltf = HE_LTF_1_X;
1155 break;
1156 case 1:
1157 he_gi = HE_GI_0_8;
1158 he_ltf = HE_LTF_2_X;
1159 break;
1160 case 2:
1161 he_gi = HE_GI_1_6;
1162 he_ltf = HE_LTF_2_X;
1163 break;
1164 case 3:
1165 if (he_dcm && he_stbc) {
1166 he_gi = HE_GI_0_8;
1167 he_ltf = HE_LTF_4_X;
1168 } else {
1169 he_gi = HE_GI_3_2;
1170 he_ltf = HE_LTF_4_X;
1171 }
1172 break;
1173 }
1174 ppdu_info->gi = he_gi;
1175 he_gi = (he_gi != 0) ? he_gi - 1 : 0;
1176 ppdu_info->he_data5 |= FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_GI, he_gi);
1177 ppdu_info->ltf_size = he_ltf;
1178 ppdu_info->he_data5 |=
1179 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE,
1180 (he_ltf == HE_LTF_4_X) ? he_ltf - 1 : he_ltf);
1181
1182 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS, info0);
1183 ppdu_info->he_data5 |=
1184 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_NUM_LTF_SYMS, value);
1185
1186 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR, info1);
1187 ppdu_info->he_data5 |=
1188 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_PRE_FEC_PAD, value);
1189
1190 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF, info1);
1191 ppdu_info->beamformed = value;
1192 ppdu_info->he_data5 |=
1193 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_TXBF, value);
1194 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM, info1);
1195 ppdu_info->he_data5 |=
1196 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_PE_DISAMBIG, value);
1197
1198 /* data6 */
1199 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS, info0);
1200 value++;
1201 ppdu_info->nss = value;
1202 ppdu_info->he_data6 =
1203 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA6_NSTS, value);
1204 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND, info1);
1205 ppdu_info->he_data6 |=
1206 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA6_DOPPLER, value);
1207 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION, info1);
1208 ppdu_info->he_data6 |=
1209 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA6_TXOP, value);
1210
1211 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
1212 break;
1213 }
1214 case HAL_PHYRX_HE_SIG_A_MU_DL: {
1215 struct hal_rx_he_sig_a_mu_dl_info *he_sig_a_mu_dl =
1216 (struct hal_rx_he_sig_a_mu_dl_info *)tlv_data;
1217
1218 info0 = __le32_to_cpu(he_sig_a_mu_dl->info0);
1219 info1 = __le32_to_cpu(he_sig_a_mu_dl->info1);
1220
1221 ppdu_info->he_mu_flags = 1;
1222
1223 ppdu_info->he_data1 = IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MU;
1224 ppdu_info->he_data1 |=
1225 IEEE80211_RADIOTAP_HE_DATA1_BSS_COLOR_KNOWN |
1226 IEEE80211_RADIOTAP_HE_DATA1_UL_DL_KNOWN |
1227 IEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN |
1228 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN |
1229 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN |
1230 IEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN;
1231
1232 ppdu_info->he_data2 =
1233 IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN |
1234 IEEE80211_RADIOTAP_HE_DATA2_NUM_LTF_SYMS_KNOWN |
1235 IEEE80211_RADIOTAP_HE_DATA2_PRE_FEC_PAD_KNOWN |
1236 IEEE80211_RADIOTAP_HE_DATA2_PE_DISAMBIG_KNOWN |
1237 IEEE80211_RADIOTAP_HE_DATA2_TXOP_KNOWN |
1238 IEEE80211_RADIOTAP_HE_DATA2_MIDAMBLE_KNOWN;
1239
1240 /*data3*/
1241 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_BSS_COLOR, info0);
1242 ppdu_info->he_data3 =
1243 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_BSS_COLOR, value);
1244
1245 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_UL_FLAG, info0);
1246 ppdu_info->he_data3 |=
1247 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_UL_DL, value);
1248
1249 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_LDPC_EXTRA, info1);
1250 ppdu_info->he_data3 |=
1251 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_LDPC_XSYMSEG, value);
1252
1253 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_STBC, info1);
1254 he_stbc = value;
1255 ppdu_info->he_data3 |=
1256 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_STBC, value);
1257
1258 /*data4*/
1259 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_SPATIAL_REUSE, info0);
1260 ppdu_info->he_data4 =
1261 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA4_SU_MU_SPTL_REUSE, value);
1262
1263 /*data5*/
1264 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_TRANSMIT_BW, info0);
1265 ppdu_info->bw = value;
1266 ppdu_info->he_data5 =
1267 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC, value);
1268
1269 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_CP_LTF_SIZE, info0);
1270 switch (value) {
1271 case 0:
1272 he_gi = HE_GI_0_8;
1273 he_ltf = HE_LTF_4_X;
1274 break;
1275 case 1:
1276 he_gi = HE_GI_0_8;
1277 he_ltf = HE_LTF_2_X;
1278 break;
1279 case 2:
1280 he_gi = HE_GI_1_6;
1281 he_ltf = HE_LTF_2_X;
1282 break;
1283 case 3:
1284 he_gi = HE_GI_3_2;
1285 he_ltf = HE_LTF_4_X;
1286 break;
1287 }
1288 ppdu_info->gi = he_gi;
1289 he_gi = (he_gi != 0) ? he_gi - 1 : 0;
1290 ppdu_info->he_data5 |= FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_GI, he_gi);
1291 ppdu_info->ltf_size = he_ltf;
1292 ppdu_info->he_data5 |=
1293 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE,
1294 (he_ltf == HE_LTF_4_X) ? he_ltf - 1 : he_ltf);
1295
1296 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_NUM_LTF_SYMB, info1);
1297 ppdu_info->he_data5 |=
1298 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_NUM_LTF_SYMS, value);
1299
1300 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_PKT_EXT_FACTOR,
1301 info1);
1302 ppdu_info->he_data5 |=
1303 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_PRE_FEC_PAD, value);
1304
1305 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_PKT_EXT_PE_DISAM,
1306 info1);
1307 ppdu_info->he_data5 |=
1308 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_PE_DISAMBIG, value);
1309
1310 /*data6*/
1311 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_DOPPLER_INDICATION,
1312 info0);
1313 ppdu_info->he_data6 |=
1314 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA6_DOPPLER, value);
1315
1316 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_TXOP_DURATION, info1);
1317 ppdu_info->he_data6 |=
1318 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA6_TXOP, value);
1319
1320 /* HE-MU Flags */
1321 /* HE-MU-flags1 */
1322 ppdu_info->he_flags1 =
1323 IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS_KNOWN |
1324 IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM_KNOWN |
1325 IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_COMP_KNOWN |
1326 IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_SYMS_USERS_KNOWN |
1327 IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_RU_KNOWN;
1328
1329 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_MCS_OF_SIGB, info0);
1330 ppdu_info->he_flags1 |=
1331 FIELD_PREP(IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS_KNOWN,
1332 value);
1333 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_DCM_OF_SIGB, info0);
1334 ppdu_info->he_flags1 |=
1335 FIELD_PREP(IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM_KNOWN,
1336 value);
1337
1338 /* HE-MU-flags2 */
1339 ppdu_info->he_flags2 =
1340 IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_KNOWN;
1341
1342 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_TRANSMIT_BW, info0);
1343 ppdu_info->he_flags2 |=
1344 FIELD_PREP(IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW,
1345 value);
1346 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_COMP_MODE_SIGB, info0);
1347 ppdu_info->he_flags2 |=
1348 FIELD_PREP(IEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_COMP, value);
1349 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_NUM_SIGB_SYMB, info0);
1350 value = value - 1;
1351 ppdu_info->he_flags2 |=
1352 FIELD_PREP(IEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_SYMS_USERS,
1353 value);
1354
1355 ppdu_info->is_stbc = info1 &
1356 HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_STBC;
1357 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO;
1358 break;
1359 }
1360 case HAL_PHYRX_HE_SIG_B1_MU: {
1361 struct hal_rx_he_sig_b1_mu_info *he_sig_b1_mu =
1362 (struct hal_rx_he_sig_b1_mu_info *)tlv_data;
1363 u16 ru_tones;
1364
1365 info0 = __le32_to_cpu(he_sig_b1_mu->info0);
1366
1367 ru_tones = FIELD_GET(HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION,
1368 info0);
1369 ppdu_info->ru_alloc =
1370 ath11k_mac_phy_he_ru_to_nl80211_he_ru_alloc(ru_tones);
1371 ppdu_info->he_RU[0] = ru_tones;
1372 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO;
1373 break;
1374 }
1375 case HAL_PHYRX_HE_SIG_B2_MU: {
1376 struct hal_rx_he_sig_b2_mu_info *he_sig_b2_mu =
1377 (struct hal_rx_he_sig_b2_mu_info *)tlv_data;
1378
1379 info0 = __le32_to_cpu(he_sig_b2_mu->info0);
1380
1381 ppdu_info->he_data1 |= IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
1382 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN;
1383
1384 ppdu_info->mcs =
1385 FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS, info0);
1386 ppdu_info->he_data3 |=
1387 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_DATA_MCS, ppdu_info->mcs);
1388
1389 value = FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING, info0);
1390 ppdu_info->ldpc = value;
1391 ppdu_info->he_data3 |=
1392 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_CODING, value);
1393
1394 value = FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID, info0);
1395 ppdu_info->he_data4 |=
1396 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA4_MU_STA_ID, value);
1397
1398 ppdu_info->nss =
1399 FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS, info0) + 1;
1400 break;
1401 }
1402 case HAL_PHYRX_HE_SIG_B2_OFDMA: {
1403 struct hal_rx_he_sig_b2_ofdma_info *he_sig_b2_ofdma =
1404 (struct hal_rx_he_sig_b2_ofdma_info *)tlv_data;
1405
1406 info0 = __le32_to_cpu(he_sig_b2_ofdma->info0);
1407
1408 ppdu_info->he_data1 |=
1409 IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
1410 IEEE80211_RADIOTAP_HE_DATA1_DATA_DCM_KNOWN |
1411 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN;
1412
1413 /* HE-data2 */
1414 ppdu_info->he_data2 |= IEEE80211_RADIOTAP_HE_DATA2_TXBF_KNOWN;
1415
1416 ppdu_info->mcs =
1417 FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS,
1418 info0);
1419 ppdu_info->he_data3 |=
1420 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_DATA_MCS, ppdu_info->mcs);
1421
1422 value = FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM, info0);
1423 he_dcm = value;
1424 ppdu_info->he_data3 |=
1425 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_DATA_DCM, value);
1426
1427 value = FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING, info0);
1428 ppdu_info->ldpc = value;
1429 ppdu_info->he_data3 |=
1430 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_CODING, value);
1431
1432 /* HE-data4 */
1433 value = FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID, info0);
1434 ppdu_info->he_data4 |=
1435 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA4_MU_STA_ID, value);
1436
1437 ppdu_info->nss =
1438 FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS,
1439 info0) + 1;
1440 ppdu_info->beamformed =
1441 info0 & HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF;
1442 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA;
1443 break;
1444 }
1445 case HAL_PHYRX_RSSI_LEGACY: {
1446 int i;
1447 bool db2dbm = test_bit(WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT,
1448 ab->wmi_ab.svc_map);
1449 struct hal_rx_phyrx_rssi_legacy_info *rssi =
1450 (struct hal_rx_phyrx_rssi_legacy_info *)tlv_data;
1451
1452 /* TODO: Please note that the combined rssi will not be accurate
1453 * in MU case. Rssi in MU needs to be retrieved from
1454 * PHYRX_OTHER_RECEIVE_INFO TLV.
1455 */
1456 ppdu_info->rssi_comb =
1457 FIELD_GET(HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RSSI_COMB,
1458 __le32_to_cpu(rssi->info0));
1459
1460 if (db2dbm) {
1461 for (i = 0; i < ARRAY_SIZE(rssi->preamble); i++) {
1462 ppdu_info->rssi_chain_pri20[i] =
1463 le32_get_bits(rssi->preamble[i].rssi_2040,
1464 HAL_RX_PHYRX_RSSI_PREAMBLE_PRI20);
1465 }
1466 }
1467 break;
1468 }
1469 case HAL_RX_MPDU_START: {
1470 struct hal_rx_mpdu_info *mpdu_info =
1471 (struct hal_rx_mpdu_info *)tlv_data;
1472 u16 peer_id;
1473
1474 peer_id = ath11k_hal_rx_mpduinfo_get_peerid(ab, mpdu_info);
1475 if (peer_id)
1476 ppdu_info->peer_id = peer_id;
1477 break;
1478 }
1479 case HAL_RXPCU_PPDU_END_INFO: {
1480 struct hal_rx_ppdu_end_duration *ppdu_rx_duration =
1481 (struct hal_rx_ppdu_end_duration *)tlv_data;
1482 ppdu_info->rx_duration =
1483 FIELD_GET(HAL_RX_PPDU_END_DURATION,
1484 __le32_to_cpu(ppdu_rx_duration->info0));
1485 ppdu_info->tsft = __le32_to_cpu(ppdu_rx_duration->rsvd0[1]);
1486 ppdu_info->tsft = (ppdu_info->tsft << 32) |
1487 __le32_to_cpu(ppdu_rx_duration->rsvd0[0]);
1488 break;
1489 }
1490 case HAL_DUMMY:
1491 return HAL_RX_MON_STATUS_BUF_DONE;
1492 case HAL_RX_PPDU_END_STATUS_DONE:
1493 case 0:
1494 return HAL_RX_MON_STATUS_PPDU_DONE;
1495 default:
1496 break;
1497 }
1498
1499 return HAL_RX_MON_STATUS_PPDU_NOT_DONE;
1500 }
1501
1502 enum hal_rx_mon_status
ath11k_hal_rx_parse_mon_status(struct ath11k_base * ab,struct hal_rx_mon_ppdu_info * ppdu_info,struct sk_buff * skb)1503 ath11k_hal_rx_parse_mon_status(struct ath11k_base *ab,
1504 struct hal_rx_mon_ppdu_info *ppdu_info,
1505 struct sk_buff *skb)
1506 {
1507 struct hal_tlv_hdr *tlv;
1508 enum hal_rx_mon_status hal_status = HAL_RX_MON_STATUS_BUF_DONE;
1509 u16 tlv_tag;
1510 u16 tlv_len;
1511 u32 tlv_userid = 0;
1512 u8 *ptr = skb->data;
1513
1514 do {
1515 tlv = (struct hal_tlv_hdr *)ptr;
1516 tlv_tag = FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl);
1517 tlv_len = FIELD_GET(HAL_TLV_HDR_LEN, tlv->tl);
1518 tlv_userid = FIELD_GET(HAL_TLV_USR_ID, tlv->tl);
1519 ptr += sizeof(*tlv);
1520
1521 /* The actual length of PPDU_END is the combined length of many PHY
1522 * TLVs that follow. Skip the TLV header and
1523 * rx_rxpcu_classification_overview that follows the header to get to
1524 * next TLV.
1525 */
1526 if (tlv_tag == HAL_RX_PPDU_END)
1527 tlv_len = sizeof(struct hal_rx_rxpcu_classification_overview);
1528
1529 hal_status = ath11k_hal_rx_parse_mon_status_tlv(ab, ppdu_info,
1530 tlv_tag, ptr, tlv_userid);
1531 ptr += tlv_len;
1532 ptr = PTR_ALIGN(ptr, HAL_TLV_ALIGN);
1533
1534 if ((ptr - skb->data) >= DP_RX_BUFFER_SIZE)
1535 break;
1536 } while (hal_status == HAL_RX_MON_STATUS_PPDU_NOT_DONE);
1537
1538 return hal_status;
1539 }
1540
ath11k_hal_rx_reo_ent_buf_paddr_get(void * rx_desc,dma_addr_t * paddr,u32 * sw_cookie,void ** pp_buf_addr,u8 * rbm,u32 * msdu_cnt)1541 void ath11k_hal_rx_reo_ent_buf_paddr_get(void *rx_desc, dma_addr_t *paddr,
1542 u32 *sw_cookie, void **pp_buf_addr,
1543 u8 *rbm, u32 *msdu_cnt)
1544 {
1545 struct hal_reo_entrance_ring *reo_ent_ring =
1546 (struct hal_reo_entrance_ring *)rx_desc;
1547 struct ath11k_buffer_addr *buf_addr_info;
1548 struct rx_mpdu_desc *rx_mpdu_desc_info_details;
1549
1550 rx_mpdu_desc_info_details =
1551 (struct rx_mpdu_desc *)&reo_ent_ring->rx_mpdu_info;
1552
1553 *msdu_cnt = FIELD_GET(RX_MPDU_DESC_INFO0_MSDU_COUNT,
1554 rx_mpdu_desc_info_details->info0);
1555
1556 buf_addr_info = (struct ath11k_buffer_addr *)&reo_ent_ring->buf_addr_info;
1557
1558 *paddr = (((u64)FIELD_GET(BUFFER_ADDR_INFO1_ADDR,
1559 buf_addr_info->info1)) << 32) |
1560 FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
1561 buf_addr_info->info0);
1562
1563 *sw_cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
1564 buf_addr_info->info1);
1565 *rbm = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
1566 buf_addr_info->info1);
1567
1568 *pp_buf_addr = (void *)buf_addr_info;
1569 }
1570
1571 void
ath11k_hal_rx_sw_mon_ring_buf_paddr_get(void * rx_desc,struct hal_sw_mon_ring_entries * sw_mon_entries)1572 ath11k_hal_rx_sw_mon_ring_buf_paddr_get(void *rx_desc,
1573 struct hal_sw_mon_ring_entries *sw_mon_entries)
1574 {
1575 struct hal_sw_monitor_ring *sw_mon_ring = rx_desc;
1576 struct ath11k_buffer_addr *buf_addr_info;
1577 struct ath11k_buffer_addr *status_buf_addr_info;
1578 struct rx_mpdu_desc *rx_mpdu_desc_info_details;
1579
1580 rx_mpdu_desc_info_details = &sw_mon_ring->rx_mpdu_info;
1581
1582 sw_mon_entries->msdu_cnt = FIELD_GET(RX_MPDU_DESC_INFO0_MSDU_COUNT,
1583 rx_mpdu_desc_info_details->info0);
1584
1585 buf_addr_info = &sw_mon_ring->buf_addr_info;
1586 status_buf_addr_info = &sw_mon_ring->status_buf_addr_info;
1587
1588 sw_mon_entries->mon_dst_paddr = (((u64)FIELD_GET(BUFFER_ADDR_INFO1_ADDR,
1589 buf_addr_info->info1)) << 32) |
1590 FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
1591 buf_addr_info->info0);
1592
1593 sw_mon_entries->mon_status_paddr =
1594 (((u64)FIELD_GET(BUFFER_ADDR_INFO1_ADDR,
1595 status_buf_addr_info->info1)) << 32) |
1596 FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
1597 status_buf_addr_info->info0);
1598
1599 sw_mon_entries->mon_dst_sw_cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
1600 buf_addr_info->info1);
1601
1602 sw_mon_entries->mon_status_sw_cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
1603 status_buf_addr_info->info1);
1604
1605 sw_mon_entries->status_buf_count = FIELD_GET(HAL_SW_MON_RING_INFO0_STATUS_BUF_CNT,
1606 sw_mon_ring->info0);
1607
1608 sw_mon_entries->dst_buf_addr_info = buf_addr_info;
1609 sw_mon_entries->status_buf_addr_info = status_buf_addr_info;
1610
1611 sw_mon_entries->ppdu_id =
1612 FIELD_GET(HAL_SW_MON_RING_INFO1_PHY_PPDU_ID, sw_mon_ring->info1);
1613 }
1614