1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/module.h>
8 #include <linux/slab.h>
9 #include <linux/remoteproc.h>
10 #include <linux/firmware.h>
11 #include <linux/of.h>
12
13 #include "core.h"
14 #include "dp_tx.h"
15 #include "dp_rx.h"
16 #include "debug.h"
17 #include "hif.h"
18 #include "wow.h"
19
20 unsigned int ath11k_debug_mask;
21 EXPORT_SYMBOL(ath11k_debug_mask);
22 module_param_named(debug_mask, ath11k_debug_mask, uint, 0644);
23 MODULE_PARM_DESC(debug_mask, "Debugging mask");
24
25 static unsigned int ath11k_crypto_mode;
26 module_param_named(crypto_mode, ath11k_crypto_mode, uint, 0644);
27 MODULE_PARM_DESC(crypto_mode, "crypto mode: 0-hardware, 1-software");
28
29 /* frame mode values are mapped as per enum ath11k_hw_txrx_mode */
30 unsigned int ath11k_frame_mode = ATH11K_HW_TXRX_NATIVE_WIFI;
31 module_param_named(frame_mode, ath11k_frame_mode, uint, 0644);
32 MODULE_PARM_DESC(frame_mode,
33 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)");
34
35 bool ath11k_ftm_mode;
36 module_param_named(ftm_mode, ath11k_ftm_mode, bool, 0444);
37 MODULE_PARM_DESC(ftm_mode, "Boots up in factory test mode");
38
39 static const struct ath11k_hw_params ath11k_hw_params[] = {
40 {
41 .hw_rev = ATH11K_HW_IPQ8074,
42 .name = "ipq8074 hw2.0",
43 .fw = {
44 .dir = "IPQ8074/hw2.0",
45 .board_size = 256 * 1024,
46 .cal_offset = 128 * 1024,
47 },
48 .max_radios = 3,
49 .bdf_addr = 0x4B0C0000,
50 .hw_ops = &ipq8074_ops,
51 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
52 .internal_sleep_clock = false,
53 .regs = &ipq8074_regs,
54 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
55 .host_ce_config = ath11k_host_ce_config_ipq8074,
56 .ce_count = 12,
57 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074,
58 .target_ce_count = 11,
59 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq8074,
60 .svc_to_ce_map_len = 21,
61 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
62 .single_pdev_only = false,
63 .rxdma1_enable = true,
64 .num_rxmda_per_pdev = 1,
65 .rx_mac_buf_ring = false,
66 .vdev_start_delay = false,
67 .htt_peer_map_v2 = true,
68
69 .spectral = {
70 .fft_sz = 2,
71 /* HW bug, expected BIN size is 2 bytes but HW report as 4 bytes.
72 * so added pad size as 2 bytes to compensate the BIN size
73 */
74 .fft_pad_sz = 2,
75 .summary_pad_sz = 0,
76 .fft_hdr_len = 16,
77 .max_fft_bins = 512,
78 .fragment_160mhz = true,
79 },
80
81 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
82 BIT(NL80211_IFTYPE_AP) |
83 BIT(NL80211_IFTYPE_MESH_POINT),
84 .supports_monitor = true,
85 .full_monitor_mode = false,
86 .supports_shadow_regs = false,
87 .idle_ps = false,
88 .supports_sta_ps = false,
89 .coldboot_cal_mm = true,
90 .coldboot_cal_ftm = true,
91 .cbcal_restart_fw = true,
92 .fw_mem_mode = 0,
93 .num_vdevs = 16 + 1,
94 .num_peers = 512,
95 .supports_suspend = false,
96 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
97 .supports_regdb = false,
98 .fix_l1ss = true,
99 .credit_flow = false,
100 .max_tx_ring = DP_TCL_NUM_RING_MAX,
101 .hal_params = &ath11k_hw_hal_params_ipq8074,
102 .supports_dynamic_smps_6ghz = false,
103 .alloc_cacheable_memory = true,
104 .supports_rssi_stats = false,
105 .fw_wmi_diag_event = false,
106 .current_cc_support = false,
107 .dbr_debug_support = true,
108 .global_reset = false,
109 .bios_sar_capa = NULL,
110 .m3_fw_support = false,
111 .fixed_bdf_addr = true,
112 .fixed_mem_region = true,
113 .static_window_map = false,
114 .hybrid_bus_type = false,
115 .fixed_fw_mem = false,
116 .support_off_channel_tx = false,
117 .supports_multi_bssid = false,
118
119 .sram_dump = {},
120
121 .tcl_ring_retry = true,
122 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
123 .smp2p_wow_exit = false,
124 },
125 {
126 .hw_rev = ATH11K_HW_IPQ6018_HW10,
127 .name = "ipq6018 hw1.0",
128 .fw = {
129 .dir = "IPQ6018/hw1.0",
130 .board_size = 256 * 1024,
131 .cal_offset = 128 * 1024,
132 },
133 .max_radios = 2,
134 .bdf_addr = 0x4ABC0000,
135 .hw_ops = &ipq6018_ops,
136 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
137 .internal_sleep_clock = false,
138 .regs = &ipq8074_regs,
139 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
140 .host_ce_config = ath11k_host_ce_config_ipq8074,
141 .ce_count = 12,
142 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074,
143 .target_ce_count = 11,
144 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq6018,
145 .svc_to_ce_map_len = 19,
146 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
147 .single_pdev_only = false,
148 .rxdma1_enable = true,
149 .num_rxmda_per_pdev = 1,
150 .rx_mac_buf_ring = false,
151 .vdev_start_delay = false,
152 .htt_peer_map_v2 = true,
153
154 .spectral = {
155 .fft_sz = 4,
156 .fft_pad_sz = 0,
157 .summary_pad_sz = 0,
158 .fft_hdr_len = 16,
159 .max_fft_bins = 512,
160 .fragment_160mhz = true,
161 },
162
163 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
164 BIT(NL80211_IFTYPE_AP) |
165 BIT(NL80211_IFTYPE_MESH_POINT),
166 .supports_monitor = true,
167 .full_monitor_mode = false,
168 .supports_shadow_regs = false,
169 .idle_ps = false,
170 .supports_sta_ps = false,
171 .coldboot_cal_mm = true,
172 .coldboot_cal_ftm = true,
173 .cbcal_restart_fw = true,
174 .fw_mem_mode = 0,
175 .num_vdevs = 16 + 1,
176 .num_peers = 512,
177 .supports_suspend = false,
178 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
179 .supports_regdb = false,
180 .fix_l1ss = true,
181 .credit_flow = false,
182 .max_tx_ring = DP_TCL_NUM_RING_MAX,
183 .hal_params = &ath11k_hw_hal_params_ipq8074,
184 .supports_dynamic_smps_6ghz = false,
185 .alloc_cacheable_memory = true,
186 .supports_rssi_stats = false,
187 .fw_wmi_diag_event = false,
188 .current_cc_support = false,
189 .dbr_debug_support = true,
190 .global_reset = false,
191 .bios_sar_capa = NULL,
192 .m3_fw_support = false,
193 .fixed_bdf_addr = true,
194 .fixed_mem_region = true,
195 .static_window_map = false,
196 .hybrid_bus_type = false,
197 .fixed_fw_mem = false,
198 .support_off_channel_tx = false,
199 .supports_multi_bssid = false,
200
201 .sram_dump = {},
202
203 .tcl_ring_retry = true,
204 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
205 .smp2p_wow_exit = false,
206 .support_fw_mac_sequence = false,
207 },
208 {
209 .name = "qca6390 hw2.0",
210 .hw_rev = ATH11K_HW_QCA6390_HW20,
211 .fw = {
212 .dir = "QCA6390/hw2.0",
213 .board_size = 256 * 1024,
214 .cal_offset = 128 * 1024,
215 },
216 .max_radios = 3,
217 .bdf_addr = 0x4B0C0000,
218 .hw_ops = &qca6390_ops,
219 .ring_mask = &ath11k_hw_ring_mask_qca6390,
220 .internal_sleep_clock = true,
221 .regs = &qca6390_regs,
222 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
223 .host_ce_config = ath11k_host_ce_config_qca6390,
224 .ce_count = 9,
225 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
226 .target_ce_count = 9,
227 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
228 .svc_to_ce_map_len = 14,
229 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
230 .single_pdev_only = true,
231 .rxdma1_enable = false,
232 .num_rxmda_per_pdev = 2,
233 .rx_mac_buf_ring = true,
234 .vdev_start_delay = true,
235 .htt_peer_map_v2 = false,
236
237 .spectral = {
238 .fft_sz = 0,
239 .fft_pad_sz = 0,
240 .summary_pad_sz = 0,
241 .fft_hdr_len = 0,
242 .max_fft_bins = 0,
243 .fragment_160mhz = false,
244 },
245
246 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
247 BIT(NL80211_IFTYPE_AP),
248 .supports_monitor = false,
249 .full_monitor_mode = false,
250 .supports_shadow_regs = true,
251 .idle_ps = true,
252 .supports_sta_ps = true,
253 .coldboot_cal_mm = false,
254 .coldboot_cal_ftm = false,
255 .cbcal_restart_fw = false,
256 .fw_mem_mode = 0,
257 .num_vdevs = 16 + 1,
258 .num_peers = 512,
259 .supports_suspend = true,
260 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
261 .supports_regdb = false,
262 .fix_l1ss = true,
263 .credit_flow = true,
264 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
265 .hal_params = &ath11k_hw_hal_params_qca6390,
266 .supports_dynamic_smps_6ghz = false,
267 .alloc_cacheable_memory = false,
268 .supports_rssi_stats = true,
269 .fw_wmi_diag_event = true,
270 .current_cc_support = true,
271 .dbr_debug_support = false,
272 .global_reset = true,
273 .bios_sar_capa = NULL,
274 .m3_fw_support = true,
275 .fixed_bdf_addr = false,
276 .fixed_mem_region = false,
277 .static_window_map = false,
278 .hybrid_bus_type = false,
279 .fixed_fw_mem = false,
280 .support_off_channel_tx = true,
281 .supports_multi_bssid = true,
282
283 .sram_dump = {
284 .start = 0x01400000,
285 .end = 0x0171ffff,
286 },
287
288 .tcl_ring_retry = true,
289 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
290 .smp2p_wow_exit = false,
291 .support_fw_mac_sequence = true,
292 },
293 {
294 .name = "qcn9074 hw1.0",
295 .hw_rev = ATH11K_HW_QCN9074_HW10,
296 .fw = {
297 .dir = "QCN9074/hw1.0",
298 .board_size = 256 * 1024,
299 .cal_offset = 128 * 1024,
300 },
301 .max_radios = 1,
302 .single_pdev_only = false,
303 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074,
304 .hw_ops = &qcn9074_ops,
305 .ring_mask = &ath11k_hw_ring_mask_qcn9074,
306 .internal_sleep_clock = false,
307 .regs = &qcn9074_regs,
308 .host_ce_config = ath11k_host_ce_config_qcn9074,
309 .ce_count = 6,
310 .target_ce_config = ath11k_target_ce_config_wlan_qcn9074,
311 .target_ce_count = 9,
312 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qcn9074,
313 .svc_to_ce_map_len = 18,
314 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
315 .rxdma1_enable = true,
316 .num_rxmda_per_pdev = 1,
317 .rx_mac_buf_ring = false,
318 .vdev_start_delay = false,
319 .htt_peer_map_v2 = true,
320
321 .spectral = {
322 .fft_sz = 2,
323 .fft_pad_sz = 0,
324 .summary_pad_sz = 16,
325 .fft_hdr_len = 24,
326 .max_fft_bins = 1024,
327 .fragment_160mhz = false,
328 },
329
330 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
331 BIT(NL80211_IFTYPE_AP) |
332 BIT(NL80211_IFTYPE_MESH_POINT),
333 .supports_monitor = true,
334 .full_monitor_mode = true,
335 .supports_shadow_regs = false,
336 .idle_ps = false,
337 .supports_sta_ps = false,
338 .coldboot_cal_mm = false,
339 .coldboot_cal_ftm = true,
340 .cbcal_restart_fw = true,
341 .fw_mem_mode = 2,
342 .num_vdevs = 8,
343 .num_peers = 128,
344 .supports_suspend = false,
345 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
346 .supports_regdb = false,
347 .fix_l1ss = true,
348 .credit_flow = false,
349 .max_tx_ring = DP_TCL_NUM_RING_MAX,
350 .hal_params = &ath11k_hw_hal_params_ipq8074,
351 .supports_dynamic_smps_6ghz = true,
352 .alloc_cacheable_memory = true,
353 .supports_rssi_stats = false,
354 .fw_wmi_diag_event = false,
355 .current_cc_support = false,
356 .dbr_debug_support = true,
357 .global_reset = false,
358 .bios_sar_capa = NULL,
359 .m3_fw_support = true,
360 .fixed_bdf_addr = false,
361 .fixed_mem_region = false,
362 .static_window_map = true,
363 .hybrid_bus_type = false,
364 .fixed_fw_mem = false,
365 .support_off_channel_tx = false,
366 .supports_multi_bssid = false,
367
368 .sram_dump = {},
369
370 .tcl_ring_retry = true,
371 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
372 .smp2p_wow_exit = false,
373 .support_fw_mac_sequence = false,
374 },
375 {
376 .name = "wcn6855 hw2.0",
377 .hw_rev = ATH11K_HW_WCN6855_HW20,
378 .fw = {
379 .dir = "WCN6855/hw2.0",
380 .board_size = 256 * 1024,
381 .cal_offset = 128 * 1024,
382 },
383 .max_radios = 3,
384 .bdf_addr = 0x4B0C0000,
385 .hw_ops = &wcn6855_ops,
386 .ring_mask = &ath11k_hw_ring_mask_qca6390,
387 .internal_sleep_clock = true,
388 .regs = &wcn6855_regs,
389 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
390 .host_ce_config = ath11k_host_ce_config_qca6390,
391 .ce_count = 9,
392 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
393 .target_ce_count = 9,
394 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
395 .svc_to_ce_map_len = 14,
396 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
397 .single_pdev_only = true,
398 .rxdma1_enable = false,
399 .num_rxmda_per_pdev = 2,
400 .rx_mac_buf_ring = true,
401 .vdev_start_delay = true,
402 .htt_peer_map_v2 = false,
403
404 .spectral = {
405 .fft_sz = 0,
406 .fft_pad_sz = 0,
407 .summary_pad_sz = 0,
408 .fft_hdr_len = 0,
409 .max_fft_bins = 0,
410 .fragment_160mhz = false,
411 },
412
413 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
414 BIT(NL80211_IFTYPE_AP),
415 .supports_monitor = false,
416 .full_monitor_mode = false,
417 .supports_shadow_regs = true,
418 .idle_ps = true,
419 .supports_sta_ps = true,
420 .coldboot_cal_mm = false,
421 .coldboot_cal_ftm = false,
422 .cbcal_restart_fw = false,
423 .fw_mem_mode = 0,
424 .num_vdevs = 16 + 1,
425 .num_peers = 512,
426 .supports_suspend = true,
427 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
428 .supports_regdb = true,
429 .fix_l1ss = false,
430 .credit_flow = true,
431 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
432 .hal_params = &ath11k_hw_hal_params_qca6390,
433 .supports_dynamic_smps_6ghz = false,
434 .alloc_cacheable_memory = false,
435 .supports_rssi_stats = true,
436 .fw_wmi_diag_event = true,
437 .current_cc_support = true,
438 .dbr_debug_support = false,
439 .global_reset = true,
440 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
441 .m3_fw_support = true,
442 .fixed_bdf_addr = false,
443 .fixed_mem_region = false,
444 .static_window_map = false,
445 .hybrid_bus_type = false,
446 .fixed_fw_mem = false,
447 .support_off_channel_tx = true,
448 .supports_multi_bssid = true,
449
450 .sram_dump = {
451 .start = 0x01400000,
452 .end = 0x0177ffff,
453 },
454
455 .tcl_ring_retry = true,
456 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
457 .smp2p_wow_exit = false,
458 .support_fw_mac_sequence = true,
459 },
460 {
461 .name = "wcn6855 hw2.1",
462 .hw_rev = ATH11K_HW_WCN6855_HW21,
463 .fw = {
464 .dir = "WCN6855/hw2.1",
465 .board_size = 256 * 1024,
466 .cal_offset = 128 * 1024,
467 },
468 .max_radios = 3,
469 .bdf_addr = 0x4B0C0000,
470 .hw_ops = &wcn6855_ops,
471 .ring_mask = &ath11k_hw_ring_mask_qca6390,
472 .internal_sleep_clock = true,
473 .regs = &wcn6855_regs,
474 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
475 .host_ce_config = ath11k_host_ce_config_qca6390,
476 .ce_count = 9,
477 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
478 .target_ce_count = 9,
479 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
480 .svc_to_ce_map_len = 14,
481 .single_pdev_only = true,
482 .rxdma1_enable = false,
483 .num_rxmda_per_pdev = 2,
484 .rx_mac_buf_ring = true,
485 .vdev_start_delay = true,
486 .htt_peer_map_v2 = false,
487
488 .spectral = {
489 .fft_sz = 0,
490 .fft_pad_sz = 0,
491 .summary_pad_sz = 0,
492 .fft_hdr_len = 0,
493 .max_fft_bins = 0,
494 .fragment_160mhz = false,
495 },
496
497 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
498 BIT(NL80211_IFTYPE_AP),
499 .supports_monitor = false,
500 .supports_shadow_regs = true,
501 .idle_ps = true,
502 .supports_sta_ps = true,
503 .coldboot_cal_mm = false,
504 .coldboot_cal_ftm = false,
505 .cbcal_restart_fw = false,
506 .fw_mem_mode = 0,
507 .num_vdevs = 16 + 1,
508 .num_peers = 512,
509 .supports_suspend = true,
510 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
511 .supports_regdb = true,
512 .fix_l1ss = false,
513 .credit_flow = true,
514 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
515 .hal_params = &ath11k_hw_hal_params_qca6390,
516 .supports_dynamic_smps_6ghz = false,
517 .alloc_cacheable_memory = false,
518 .supports_rssi_stats = true,
519 .fw_wmi_diag_event = true,
520 .current_cc_support = true,
521 .dbr_debug_support = false,
522 .global_reset = true,
523 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
524 .m3_fw_support = true,
525 .fixed_bdf_addr = false,
526 .fixed_mem_region = false,
527 .static_window_map = false,
528 .hybrid_bus_type = false,
529 .fixed_fw_mem = false,
530 .support_off_channel_tx = true,
531 .supports_multi_bssid = true,
532
533 .sram_dump = {
534 .start = 0x01400000,
535 .end = 0x0177ffff,
536 },
537
538 .tcl_ring_retry = true,
539 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
540 .smp2p_wow_exit = false,
541 .support_fw_mac_sequence = true,
542 },
543 {
544 .name = "wcn6750 hw1.0",
545 .hw_rev = ATH11K_HW_WCN6750_HW10,
546 .fw = {
547 .dir = "WCN6750/hw1.0",
548 .board_size = 256 * 1024,
549 .cal_offset = 128 * 1024,
550 },
551 .max_radios = 1,
552 .bdf_addr = 0x4B0C0000,
553 .hw_ops = &wcn6750_ops,
554 .ring_mask = &ath11k_hw_ring_mask_wcn6750,
555 .internal_sleep_clock = false,
556 .regs = &wcn6750_regs,
557 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750,
558 .host_ce_config = ath11k_host_ce_config_qca6390,
559 .ce_count = 9,
560 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
561 .target_ce_count = 9,
562 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
563 .svc_to_ce_map_len = 14,
564 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
565 .single_pdev_only = true,
566 .rxdma1_enable = false,
567 .num_rxmda_per_pdev = 1,
568 .rx_mac_buf_ring = true,
569 .vdev_start_delay = true,
570 .htt_peer_map_v2 = false,
571
572 .spectral = {
573 .fft_sz = 0,
574 .fft_pad_sz = 0,
575 .summary_pad_sz = 0,
576 .fft_hdr_len = 0,
577 .max_fft_bins = 0,
578 .fragment_160mhz = false,
579 },
580
581 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
582 BIT(NL80211_IFTYPE_AP),
583 .supports_monitor = false,
584 .supports_shadow_regs = true,
585 .idle_ps = true,
586 .supports_sta_ps = true,
587 .coldboot_cal_mm = true,
588 .coldboot_cal_ftm = true,
589 .cbcal_restart_fw = false,
590 .fw_mem_mode = 0,
591 .num_vdevs = 16 + 1,
592 .num_peers = 512,
593 .supports_suspend = false,
594 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
595 .supports_regdb = true,
596 .fix_l1ss = false,
597 .credit_flow = true,
598 .max_tx_ring = DP_TCL_NUM_RING_MAX,
599 .hal_params = &ath11k_hw_hal_params_wcn6750,
600 .supports_dynamic_smps_6ghz = false,
601 .alloc_cacheable_memory = false,
602 .supports_rssi_stats = true,
603 .fw_wmi_diag_event = false,
604 .current_cc_support = true,
605 .dbr_debug_support = false,
606 .global_reset = false,
607 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
608 .m3_fw_support = false,
609 .fixed_bdf_addr = false,
610 .fixed_mem_region = false,
611 .static_window_map = true,
612 .hybrid_bus_type = true,
613 .fixed_fw_mem = true,
614 .support_off_channel_tx = true,
615 .supports_multi_bssid = true,
616
617 .sram_dump = {},
618
619 .tcl_ring_retry = false,
620 .tx_ring_size = DP_TCL_DATA_RING_SIZE_WCN6750,
621 .smp2p_wow_exit = true,
622 .support_fw_mac_sequence = true,
623 },
624 {
625 .hw_rev = ATH11K_HW_IPQ5018_HW10,
626 .name = "ipq5018 hw1.0",
627 .fw = {
628 .dir = "IPQ5018/hw1.0",
629 .board_size = 256 * 1024,
630 .cal_offset = 128 * 1024,
631 },
632 .max_radios = MAX_RADIOS_5018,
633 .bdf_addr = 0x4BA00000,
634 /* hal_desc_sz and hw ops are similar to qcn9074 */
635 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
636 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
637 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
638 .credit_flow = false,
639 .max_tx_ring = 1,
640 .spectral = {
641 .fft_sz = 2,
642 .fft_pad_sz = 0,
643 .summary_pad_sz = 16,
644 .fft_hdr_len = 24,
645 .max_fft_bins = 1024,
646 },
647 .internal_sleep_clock = false,
648 .regs = &ipq5018_regs,
649 .hw_ops = &ipq5018_ops,
650 .host_ce_config = ath11k_host_ce_config_qcn9074,
651 .ce_count = CE_CNT_5018,
652 .target_ce_config = ath11k_target_ce_config_wlan_ipq5018,
653 .target_ce_count = TARGET_CE_CNT_5018,
654 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq5018,
655 .svc_to_ce_map_len = SVC_CE_MAP_LEN_5018,
656 .ce_ie_addr = &ath11k_ce_ie_addr_ipq5018,
657 .ce_remap = &ath11k_ce_remap_ipq5018,
658 .rxdma1_enable = true,
659 .num_rxmda_per_pdev = RXDMA_PER_PDEV_5018,
660 .rx_mac_buf_ring = false,
661 .vdev_start_delay = false,
662 .htt_peer_map_v2 = true,
663 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
664 BIT(NL80211_IFTYPE_AP) |
665 BIT(NL80211_IFTYPE_MESH_POINT),
666 .supports_monitor = false,
667 .supports_sta_ps = false,
668 .supports_shadow_regs = false,
669 .fw_mem_mode = 0,
670 .num_vdevs = 16 + 1,
671 .num_peers = 512,
672 .supports_regdb = false,
673 .idle_ps = false,
674 .supports_suspend = false,
675 .hal_params = &ath11k_hw_hal_params_ipq8074,
676 .single_pdev_only = false,
677 .coldboot_cal_mm = true,
678 .coldboot_cal_ftm = true,
679 .cbcal_restart_fw = true,
680 .fix_l1ss = true,
681 .supports_dynamic_smps_6ghz = false,
682 .alloc_cacheable_memory = true,
683 .supports_rssi_stats = false,
684 .fw_wmi_diag_event = false,
685 .current_cc_support = false,
686 .dbr_debug_support = true,
687 .global_reset = false,
688 .bios_sar_capa = NULL,
689 .m3_fw_support = false,
690 .fixed_bdf_addr = true,
691 .fixed_mem_region = true,
692 .static_window_map = false,
693 .hybrid_bus_type = false,
694 .fixed_fw_mem = false,
695 .support_off_channel_tx = false,
696 .supports_multi_bssid = false,
697
698 .sram_dump = {},
699
700 .tcl_ring_retry = true,
701 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
702 .smp2p_wow_exit = false,
703 .support_fw_mac_sequence = false,
704 },
705 };
706
707 static const struct dmi_system_id ath11k_pm_quirk_table[] = {
708 {
709 .driver_data = (void *)ATH11K_PM_WOW,
710 .matches = {
711 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
712 DMI_MATCH(DMI_PRODUCT_NAME, "21J4"),
713 },
714 },
715 {
716 .driver_data = (void *)ATH11K_PM_WOW,
717 .matches = {
718 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
719 DMI_MATCH(DMI_PRODUCT_NAME, "21K4"),
720 },
721 },
722 {
723 .driver_data = (void *)ATH11K_PM_WOW,
724 .matches = {
725 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
726 DMI_MATCH(DMI_PRODUCT_NAME, "21K6"),
727 },
728 },
729 {
730 .driver_data = (void *)ATH11K_PM_WOW,
731 .matches = {
732 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
733 DMI_MATCH(DMI_PRODUCT_NAME, "21K8"),
734 },
735 },
736 {
737 .driver_data = (void *)ATH11K_PM_WOW,
738 .matches = {
739 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
740 DMI_MATCH(DMI_PRODUCT_NAME, "21KA"),
741 },
742 },
743 {
744 .driver_data = (void *)ATH11K_PM_WOW,
745 .matches = {
746 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
747 DMI_MATCH(DMI_PRODUCT_NAME, "21F9"),
748 },
749 },
750 {}
751 };
752
ath11k_core_get_single_pdev(struct ath11k_base * ab)753 static inline struct ath11k_pdev *ath11k_core_get_single_pdev(struct ath11k_base *ab)
754 {
755 WARN_ON(!ab->hw_params.single_pdev_only);
756
757 return &ab->pdevs[0];
758 }
759
ath11k_fw_stats_pdevs_free(struct list_head * head)760 void ath11k_fw_stats_pdevs_free(struct list_head *head)
761 {
762 struct ath11k_fw_stats_pdev *i, *tmp;
763
764 list_for_each_entry_safe(i, tmp, head, list) {
765 list_del(&i->list);
766 kfree(i);
767 }
768 }
769
ath11k_fw_stats_vdevs_free(struct list_head * head)770 void ath11k_fw_stats_vdevs_free(struct list_head *head)
771 {
772 struct ath11k_fw_stats_vdev *i, *tmp;
773
774 list_for_each_entry_safe(i, tmp, head, list) {
775 list_del(&i->list);
776 kfree(i);
777 }
778 }
779
ath11k_fw_stats_bcn_free(struct list_head * head)780 void ath11k_fw_stats_bcn_free(struct list_head *head)
781 {
782 struct ath11k_fw_stats_bcn *i, *tmp;
783
784 list_for_each_entry_safe(i, tmp, head, list) {
785 list_del(&i->list);
786 kfree(i);
787 }
788 }
789
ath11k_fw_stats_init(struct ath11k * ar)790 void ath11k_fw_stats_init(struct ath11k *ar)
791 {
792 INIT_LIST_HEAD(&ar->fw_stats.pdevs);
793 INIT_LIST_HEAD(&ar->fw_stats.vdevs);
794 INIT_LIST_HEAD(&ar->fw_stats.bcn);
795
796 init_completion(&ar->fw_stats_complete);
797 init_completion(&ar->fw_stats_done);
798 }
799
ath11k_fw_stats_free(struct ath11k_fw_stats * stats)800 void ath11k_fw_stats_free(struct ath11k_fw_stats *stats)
801 {
802 ath11k_fw_stats_pdevs_free(&stats->pdevs);
803 ath11k_fw_stats_vdevs_free(&stats->vdevs);
804 ath11k_fw_stats_bcn_free(&stats->bcn);
805 }
806
ath11k_core_coldboot_cal_support(struct ath11k_base * ab)807 bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab)
808 {
809 if (!ath11k_cold_boot_cal)
810 return false;
811
812 if (ath11k_ftm_mode)
813 return ab->hw_params.coldboot_cal_ftm;
814
815 else
816 return ab->hw_params.coldboot_cal_mm;
817 }
818
ath11k_core_suspend(struct ath11k_base * ab)819 int ath11k_core_suspend(struct ath11k_base *ab)
820 {
821 int ret;
822 struct ath11k_pdev *pdev;
823 struct ath11k *ar;
824
825 if (!ab->hw_params.supports_suspend)
826 return -EOPNOTSUPP;
827
828 /* so far single_pdev_only chips have supports_suspend as true
829 * and only the first pdev is valid.
830 */
831 pdev = ath11k_core_get_single_pdev(ab);
832 ar = pdev->ar;
833 if (!ar || ar->state != ATH11K_STATE_OFF)
834 return 0;
835
836 ret = ath11k_dp_rx_pktlog_stop(ab, true);
837 if (ret) {
838 ath11k_warn(ab, "failed to stop dp rx (and timer) pktlog during suspend: %d\n",
839 ret);
840 return ret;
841 }
842
843 ret = ath11k_mac_wait_tx_complete(ar);
844 if (ret) {
845 ath11k_warn(ab, "failed to wait tx complete: %d\n", ret);
846 return ret;
847 }
848
849 ret = ath11k_wow_enable(ab);
850 if (ret) {
851 ath11k_warn(ab, "failed to enable wow during suspend: %d\n", ret);
852 return ret;
853 }
854
855 ret = ath11k_dp_rx_pktlog_stop(ab, false);
856 if (ret) {
857 ath11k_warn(ab, "failed to stop dp rx pktlog during suspend: %d\n",
858 ret);
859 return ret;
860 }
861
862 ath11k_ce_stop_shadow_timers(ab);
863 ath11k_dp_stop_shadow_timers(ab);
864
865 ath11k_hif_irq_disable(ab);
866 ath11k_hif_ce_irq_disable(ab);
867
868 ret = ath11k_hif_suspend(ab);
869 if (ret) {
870 ath11k_warn(ab, "failed to suspend hif: %d\n", ret);
871 return ret;
872 }
873
874 return 0;
875 }
876 EXPORT_SYMBOL(ath11k_core_suspend);
877
ath11k_core_resume(struct ath11k_base * ab)878 int ath11k_core_resume(struct ath11k_base *ab)
879 {
880 int ret;
881 struct ath11k_pdev *pdev;
882 struct ath11k *ar;
883
884 if (!ab->hw_params.supports_suspend)
885 return -EOPNOTSUPP;
886
887 /* so far signle_pdev_only chips have supports_suspend as true
888 * and only the first pdev is valid.
889 */
890 pdev = ath11k_core_get_single_pdev(ab);
891 ar = pdev->ar;
892 if (!ar || ar->state != ATH11K_STATE_OFF)
893 return 0;
894
895 ret = ath11k_hif_resume(ab);
896 if (ret) {
897 ath11k_warn(ab, "failed to resume hif during resume: %d\n", ret);
898 return ret;
899 }
900
901 ath11k_hif_ce_irq_enable(ab);
902 ath11k_hif_irq_enable(ab);
903
904 ret = ath11k_dp_rx_pktlog_start(ab);
905 if (ret) {
906 ath11k_warn(ab, "failed to start rx pktlog during resume: %d\n",
907 ret);
908 return ret;
909 }
910
911 ret = ath11k_wow_wakeup(ab);
912 if (ret) {
913 ath11k_warn(ab, "failed to wakeup wow during resume: %d\n", ret);
914 return ret;
915 }
916
917 return 0;
918 }
919 EXPORT_SYMBOL(ath11k_core_resume);
920
ath11k_core_check_cc_code_bdfext(const struct dmi_header * hdr,void * data)921 static void ath11k_core_check_cc_code_bdfext(const struct dmi_header *hdr, void *data)
922 {
923 struct ath11k_base *ab = data;
924 const char *magic = ATH11K_SMBIOS_BDF_EXT_MAGIC;
925 struct ath11k_smbios_bdf *smbios = (struct ath11k_smbios_bdf *)hdr;
926 ssize_t copied;
927 size_t len;
928 int i;
929
930 if (ab->qmi.target.bdf_ext[0] != '\0')
931 return;
932
933 if (hdr->type != ATH11K_SMBIOS_BDF_EXT_TYPE)
934 return;
935
936 if (hdr->length != ATH11K_SMBIOS_BDF_EXT_LENGTH) {
937 ath11k_dbg(ab, ATH11K_DBG_BOOT,
938 "wrong smbios bdf ext type length (%d).\n",
939 hdr->length);
940 return;
941 }
942
943 spin_lock_bh(&ab->base_lock);
944
945 switch (smbios->country_code_flag) {
946 case ATH11K_SMBIOS_CC_ISO:
947 ab->new_alpha2[0] = (smbios->cc_code >> 8) & 0xff;
948 ab->new_alpha2[1] = smbios->cc_code & 0xff;
949 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios cc_code %c%c\n",
950 ab->new_alpha2[0], ab->new_alpha2[1]);
951 break;
952 case ATH11K_SMBIOS_CC_WW:
953 ab->new_alpha2[0] = '0';
954 ab->new_alpha2[1] = '0';
955 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios worldwide regdomain\n");
956 break;
957 default:
958 ath11k_dbg(ab, ATH11K_DBG_BOOT, "ignore smbios country code setting %d\n",
959 smbios->country_code_flag);
960 break;
961 }
962
963 spin_unlock_bh(&ab->base_lock);
964
965 if (!smbios->bdf_enabled) {
966 ath11k_dbg(ab, ATH11K_DBG_BOOT, "bdf variant name not found.\n");
967 return;
968 }
969
970 /* Only one string exists (per spec) */
971 if (memcmp(smbios->bdf_ext, magic, strlen(magic)) != 0) {
972 ath11k_dbg(ab, ATH11K_DBG_BOOT,
973 "bdf variant magic does not match.\n");
974 return;
975 }
976
977 len = min_t(size_t,
978 strlen(smbios->bdf_ext), sizeof(ab->qmi.target.bdf_ext));
979 for (i = 0; i < len; i++) {
980 if (!isascii(smbios->bdf_ext[i]) || !isprint(smbios->bdf_ext[i])) {
981 ath11k_dbg(ab, ATH11K_DBG_BOOT,
982 "bdf variant name contains non ascii chars.\n");
983 return;
984 }
985 }
986
987 /* Copy extension name without magic prefix */
988 copied = strscpy(ab->qmi.target.bdf_ext, smbios->bdf_ext + strlen(magic),
989 sizeof(ab->qmi.target.bdf_ext));
990 if (copied < 0) {
991 ath11k_dbg(ab, ATH11K_DBG_BOOT,
992 "bdf variant string is longer than the buffer can accommodate\n");
993 return;
994 }
995
996 ath11k_dbg(ab, ATH11K_DBG_BOOT,
997 "found and validated bdf variant smbios_type 0x%x bdf %s\n",
998 ATH11K_SMBIOS_BDF_EXT_TYPE, ab->qmi.target.bdf_ext);
999 }
1000
ath11k_core_check_smbios(struct ath11k_base * ab)1001 int ath11k_core_check_smbios(struct ath11k_base *ab)
1002 {
1003 ab->qmi.target.bdf_ext[0] = '\0';
1004 dmi_walk(ath11k_core_check_cc_code_bdfext, ab);
1005
1006 if (ab->qmi.target.bdf_ext[0] == '\0')
1007 return -ENODATA;
1008
1009 return 0;
1010 }
1011
ath11k_core_check_dt(struct ath11k_base * ab)1012 int ath11k_core_check_dt(struct ath11k_base *ab)
1013 {
1014 size_t max_len = sizeof(ab->qmi.target.bdf_ext);
1015 const char *variant = NULL;
1016 struct device_node *node;
1017
1018 node = ab->dev->of_node;
1019 if (!node)
1020 return -ENOENT;
1021
1022 of_property_read_string(node, "qcom,ath11k-calibration-variant",
1023 &variant);
1024 if (!variant)
1025 return -ENODATA;
1026
1027 if (strscpy(ab->qmi.target.bdf_ext, variant, max_len) < 0)
1028 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1029 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n",
1030 variant);
1031
1032 return 0;
1033 }
1034
__ath11k_core_create_board_name(struct ath11k_base * ab,char * name,size_t name_len,bool with_variant,bool bus_type_mode)1035 static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
1036 size_t name_len, bool with_variant,
1037 bool bus_type_mode)
1038 {
1039 /* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */
1040 char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = { 0 };
1041
1042 if (with_variant && ab->qmi.target.bdf_ext[0] != '\0')
1043 scnprintf(variant, sizeof(variant), ",variant=%s",
1044 ab->qmi.target.bdf_ext);
1045
1046 switch (ab->id.bdf_search) {
1047 case ATH11K_BDF_SEARCH_BUS_AND_BOARD:
1048 if (bus_type_mode)
1049 scnprintf(name, name_len,
1050 "bus=%s",
1051 ath11k_bus_str(ab->hif.bus));
1052 else
1053 scnprintf(name, name_len,
1054 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s",
1055 ath11k_bus_str(ab->hif.bus),
1056 ab->id.vendor, ab->id.device,
1057 ab->id.subsystem_vendor,
1058 ab->id.subsystem_device,
1059 ab->qmi.target.chip_id,
1060 ab->qmi.target.board_id,
1061 variant);
1062 break;
1063 default:
1064 scnprintf(name, name_len,
1065 "bus=%s,qmi-chip-id=%d,qmi-board-id=%d%s",
1066 ath11k_bus_str(ab->hif.bus),
1067 ab->qmi.target.chip_id,
1068 ab->qmi.target.board_id, variant);
1069 break;
1070 }
1071
1072 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board name '%s'\n", name);
1073
1074 return 0;
1075 }
1076
ath11k_core_create_board_name(struct ath11k_base * ab,char * name,size_t name_len)1077 static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
1078 size_t name_len)
1079 {
1080 return __ath11k_core_create_board_name(ab, name, name_len, true, false);
1081 }
1082
ath11k_core_create_fallback_board_name(struct ath11k_base * ab,char * name,size_t name_len)1083 static int ath11k_core_create_fallback_board_name(struct ath11k_base *ab, char *name,
1084 size_t name_len)
1085 {
1086 return __ath11k_core_create_board_name(ab, name, name_len, false, false);
1087 }
1088
ath11k_core_create_bus_type_board_name(struct ath11k_base * ab,char * name,size_t name_len)1089 static int ath11k_core_create_bus_type_board_name(struct ath11k_base *ab, char *name,
1090 size_t name_len)
1091 {
1092 return __ath11k_core_create_board_name(ab, name, name_len, false, true);
1093 }
1094
ath11k_core_firmware_request(struct ath11k_base * ab,const char * file)1095 const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab,
1096 const char *file)
1097 {
1098 const struct firmware *fw;
1099 char path[100];
1100 int ret;
1101
1102 if (file == NULL)
1103 return ERR_PTR(-ENOENT);
1104
1105 ath11k_core_create_firmware_path(ab, file, path, sizeof(path));
1106
1107 ret = firmware_request_nowarn(&fw, path, ab->dev);
1108 if (ret)
1109 return ERR_PTR(ret);
1110
1111 ath11k_dbg(ab, ATH11K_DBG_BOOT, "firmware request %s size %zu\n",
1112 path, fw->size);
1113
1114 return fw;
1115 }
1116
ath11k_core_free_bdf(struct ath11k_base * ab,struct ath11k_board_data * bd)1117 void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd)
1118 {
1119 if (!IS_ERR(bd->fw))
1120 release_firmware(bd->fw);
1121
1122 memset(bd, 0, sizeof(*bd));
1123 }
1124
ath11k_core_parse_bd_ie_board(struct ath11k_base * ab,struct ath11k_board_data * bd,const void * buf,size_t buf_len,const char * boardname,int ie_id,int name_id,int data_id)1125 static int ath11k_core_parse_bd_ie_board(struct ath11k_base *ab,
1126 struct ath11k_board_data *bd,
1127 const void *buf, size_t buf_len,
1128 const char *boardname,
1129 int ie_id,
1130 int name_id,
1131 int data_id)
1132 {
1133 const struct ath11k_fw_ie *hdr;
1134 bool name_match_found;
1135 int ret, board_ie_id;
1136 size_t board_ie_len;
1137 const void *board_ie_data;
1138
1139 name_match_found = false;
1140
1141 /* go through ATH11K_BD_IE_BOARD_/ATH11K_BD_IE_REGDB_ elements */
1142 while (buf_len > sizeof(struct ath11k_fw_ie)) {
1143 hdr = buf;
1144 board_ie_id = le32_to_cpu(hdr->id);
1145 board_ie_len = le32_to_cpu(hdr->len);
1146 board_ie_data = hdr->data;
1147
1148 buf_len -= sizeof(*hdr);
1149 buf += sizeof(*hdr);
1150
1151 if (buf_len < ALIGN(board_ie_len, 4)) {
1152 ath11k_err(ab, "invalid %s length: %zu < %zu\n",
1153 ath11k_bd_ie_type_str(ie_id),
1154 buf_len, ALIGN(board_ie_len, 4));
1155 ret = -EINVAL;
1156 goto out;
1157 }
1158
1159 if (board_ie_id == name_id) {
1160 ath11k_dbg_dump(ab, ATH11K_DBG_BOOT, "board name", "",
1161 board_ie_data, board_ie_len);
1162
1163 if (board_ie_len != strlen(boardname))
1164 goto next;
1165
1166 ret = memcmp(board_ie_data, boardname, strlen(boardname));
1167 if (ret)
1168 goto next;
1169
1170 name_match_found = true;
1171 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1172 "found match %s for name '%s'",
1173 ath11k_bd_ie_type_str(ie_id),
1174 boardname);
1175 } else if (board_ie_id == data_id) {
1176 if (!name_match_found)
1177 /* no match found */
1178 goto next;
1179
1180 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1181 "found %s for '%s'",
1182 ath11k_bd_ie_type_str(ie_id),
1183 boardname);
1184
1185 bd->data = board_ie_data;
1186 bd->len = board_ie_len;
1187
1188 ret = 0;
1189 goto out;
1190 } else {
1191 ath11k_warn(ab, "unknown %s id found: %d\n",
1192 ath11k_bd_ie_type_str(ie_id),
1193 board_ie_id);
1194 }
1195 next:
1196 /* jump over the padding */
1197 board_ie_len = ALIGN(board_ie_len, 4);
1198
1199 buf_len -= board_ie_len;
1200 buf += board_ie_len;
1201 }
1202
1203 /* no match found */
1204 ret = -ENOENT;
1205
1206 out:
1207 return ret;
1208 }
1209
ath11k_core_fetch_board_data_api_n(struct ath11k_base * ab,struct ath11k_board_data * bd,const char * boardname,int ie_id_match,int name_id,int data_id)1210 static int ath11k_core_fetch_board_data_api_n(struct ath11k_base *ab,
1211 struct ath11k_board_data *bd,
1212 const char *boardname,
1213 int ie_id_match,
1214 int name_id,
1215 int data_id)
1216 {
1217 size_t len, magic_len;
1218 const u8 *data;
1219 char *filename, filepath[100];
1220 size_t ie_len;
1221 struct ath11k_fw_ie *hdr;
1222 int ret, ie_id;
1223
1224 filename = ATH11K_BOARD_API2_FILE;
1225
1226 if (!bd->fw)
1227 bd->fw = ath11k_core_firmware_request(ab, filename);
1228
1229 if (IS_ERR(bd->fw))
1230 return PTR_ERR(bd->fw);
1231
1232 data = bd->fw->data;
1233 len = bd->fw->size;
1234
1235 ath11k_core_create_firmware_path(ab, filename,
1236 filepath, sizeof(filepath));
1237
1238 /* magic has extra null byte padded */
1239 magic_len = strlen(ATH11K_BOARD_MAGIC) + 1;
1240 if (len < magic_len) {
1241 ath11k_err(ab, "failed to find magic value in %s, file too short: %zu\n",
1242 filepath, len);
1243 ret = -EINVAL;
1244 goto err;
1245 }
1246
1247 if (memcmp(data, ATH11K_BOARD_MAGIC, magic_len)) {
1248 ath11k_err(ab, "found invalid board magic\n");
1249 ret = -EINVAL;
1250 goto err;
1251 }
1252
1253 /* magic is padded to 4 bytes */
1254 magic_len = ALIGN(magic_len, 4);
1255 if (len < magic_len) {
1256 ath11k_err(ab, "failed: %s too small to contain board data, len: %zu\n",
1257 filepath, len);
1258 ret = -EINVAL;
1259 goto err;
1260 }
1261
1262 data += magic_len;
1263 len -= magic_len;
1264
1265 while (len > sizeof(struct ath11k_fw_ie)) {
1266 hdr = (struct ath11k_fw_ie *)data;
1267 ie_id = le32_to_cpu(hdr->id);
1268 ie_len = le32_to_cpu(hdr->len);
1269
1270 len -= sizeof(*hdr);
1271 data = hdr->data;
1272
1273 if (len < ALIGN(ie_len, 4)) {
1274 ath11k_err(ab, "invalid length for board ie_id %d ie_len %zu len %zu\n",
1275 ie_id, ie_len, len);
1276 ret = -EINVAL;
1277 goto err;
1278 }
1279
1280 if (ie_id == ie_id_match) {
1281 ret = ath11k_core_parse_bd_ie_board(ab, bd, data,
1282 ie_len,
1283 boardname,
1284 ie_id_match,
1285 name_id,
1286 data_id);
1287 if (ret == -ENOENT)
1288 /* no match found, continue */
1289 goto next;
1290 else if (ret)
1291 /* there was an error, bail out */
1292 goto err;
1293 /* either found or error, so stop searching */
1294 goto out;
1295 }
1296 next:
1297 /* jump over the padding */
1298 ie_len = ALIGN(ie_len, 4);
1299
1300 len -= ie_len;
1301 data += ie_len;
1302 }
1303
1304 out:
1305 if (!bd->data || !bd->len) {
1306 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1307 "failed to fetch %s for %s from %s\n",
1308 ath11k_bd_ie_type_str(ie_id_match),
1309 boardname, filepath);
1310 ret = -ENODATA;
1311 goto err;
1312 }
1313
1314 return 0;
1315
1316 err:
1317 ath11k_core_free_bdf(ab, bd);
1318 return ret;
1319 }
1320
ath11k_core_fetch_board_data_api_1(struct ath11k_base * ab,struct ath11k_board_data * bd,const char * name)1321 int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab,
1322 struct ath11k_board_data *bd,
1323 const char *name)
1324 {
1325 bd->fw = ath11k_core_firmware_request(ab, name);
1326
1327 if (IS_ERR(bd->fw))
1328 return PTR_ERR(bd->fw);
1329
1330 bd->data = bd->fw->data;
1331 bd->len = bd->fw->size;
1332
1333 return 0;
1334 }
1335
1336 #define BOARD_NAME_SIZE 200
ath11k_core_fetch_bdf(struct ath11k_base * ab,struct ath11k_board_data * bd)1337 int ath11k_core_fetch_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd)
1338 {
1339 char boardname[BOARD_NAME_SIZE], fallback_boardname[BOARD_NAME_SIZE];
1340 char *filename, filepath[100];
1341 int ret;
1342
1343 filename = ATH11K_BOARD_API2_FILE;
1344
1345 ret = ath11k_core_create_board_name(ab, boardname, sizeof(boardname));
1346 if (ret) {
1347 ath11k_err(ab, "failed to create board name: %d", ret);
1348 return ret;
1349 }
1350
1351 ab->bd_api = 2;
1352 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname,
1353 ATH11K_BD_IE_BOARD,
1354 ATH11K_BD_IE_BOARD_NAME,
1355 ATH11K_BD_IE_BOARD_DATA);
1356 if (!ret)
1357 goto success;
1358
1359 ret = ath11k_core_create_fallback_board_name(ab, fallback_boardname,
1360 sizeof(fallback_boardname));
1361 if (ret) {
1362 ath11k_err(ab, "failed to create fallback board name: %d", ret);
1363 return ret;
1364 }
1365
1366 ret = ath11k_core_fetch_board_data_api_n(ab, bd, fallback_boardname,
1367 ATH11K_BD_IE_BOARD,
1368 ATH11K_BD_IE_BOARD_NAME,
1369 ATH11K_BD_IE_BOARD_DATA);
1370 if (!ret)
1371 goto success;
1372
1373 ab->bd_api = 1;
1374 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_DEFAULT_BOARD_FILE);
1375 if (ret) {
1376 ath11k_core_create_firmware_path(ab, filename,
1377 filepath, sizeof(filepath));
1378 ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1379 boardname, filepath);
1380 if (memcmp(boardname, fallback_boardname, strlen(boardname)))
1381 ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1382 fallback_boardname, filepath);
1383
1384 ath11k_err(ab, "failed to fetch board.bin from %s\n",
1385 ab->hw_params.fw.dir);
1386 return ret;
1387 }
1388
1389 success:
1390 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board api %d\n", ab->bd_api);
1391 return 0;
1392 }
1393
ath11k_core_fetch_regdb(struct ath11k_base * ab,struct ath11k_board_data * bd)1394 int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd)
1395 {
1396 char boardname[BOARD_NAME_SIZE], default_boardname[BOARD_NAME_SIZE];
1397 int ret;
1398
1399 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE);
1400 if (ret) {
1401 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1402 "failed to create board name for regdb: %d", ret);
1403 goto exit;
1404 }
1405
1406 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname,
1407 ATH11K_BD_IE_REGDB,
1408 ATH11K_BD_IE_REGDB_NAME,
1409 ATH11K_BD_IE_REGDB_DATA);
1410 if (!ret)
1411 goto exit;
1412
1413 ret = ath11k_core_create_bus_type_board_name(ab, default_boardname,
1414 BOARD_NAME_SIZE);
1415 if (ret) {
1416 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1417 "failed to create default board name for regdb: %d", ret);
1418 goto exit;
1419 }
1420
1421 ret = ath11k_core_fetch_board_data_api_n(ab, bd, default_boardname,
1422 ATH11K_BD_IE_REGDB,
1423 ATH11K_BD_IE_REGDB_NAME,
1424 ATH11K_BD_IE_REGDB_DATA);
1425 if (!ret)
1426 goto exit;
1427
1428 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_REGDB_FILE_NAME);
1429 if (ret)
1430 ath11k_dbg(ab, ATH11K_DBG_BOOT, "failed to fetch %s from %s\n",
1431 ATH11K_REGDB_FILE_NAME, ab->hw_params.fw.dir);
1432
1433 exit:
1434 if (!ret)
1435 ath11k_dbg(ab, ATH11K_DBG_BOOT, "fetched regdb\n");
1436
1437 return ret;
1438 }
1439
ath11k_core_stop(struct ath11k_base * ab)1440 static void ath11k_core_stop(struct ath11k_base *ab)
1441 {
1442 if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags))
1443 ath11k_qmi_firmware_stop(ab);
1444
1445 ath11k_hif_stop(ab);
1446 ath11k_wmi_detach(ab);
1447 ath11k_dp_pdev_reo_cleanup(ab);
1448
1449 /* De-Init of components as needed */
1450 }
1451
ath11k_core_soc_create(struct ath11k_base * ab)1452 static int ath11k_core_soc_create(struct ath11k_base *ab)
1453 {
1454 int ret;
1455
1456 if (ath11k_ftm_mode) {
1457 ab->fw_mode = ATH11K_FIRMWARE_MODE_FTM;
1458 ath11k_info(ab, "Booting in factory test mode\n");
1459 }
1460
1461 ret = ath11k_qmi_init_service(ab);
1462 if (ret) {
1463 ath11k_err(ab, "failed to initialize qmi :%d\n", ret);
1464 return ret;
1465 }
1466
1467 ret = ath11k_debugfs_soc_create(ab);
1468 if (ret) {
1469 ath11k_err(ab, "failed to create ath11k debugfs\n");
1470 goto err_qmi_deinit;
1471 }
1472
1473 ret = ath11k_hif_power_up(ab);
1474 if (ret) {
1475 ath11k_err(ab, "failed to power up :%d\n", ret);
1476 goto err_debugfs_reg;
1477 }
1478
1479 return 0;
1480
1481 err_debugfs_reg:
1482 ath11k_debugfs_soc_destroy(ab);
1483 err_qmi_deinit:
1484 ath11k_qmi_deinit_service(ab);
1485 return ret;
1486 }
1487
ath11k_core_soc_destroy(struct ath11k_base * ab)1488 static void ath11k_core_soc_destroy(struct ath11k_base *ab)
1489 {
1490 ath11k_debugfs_soc_destroy(ab);
1491 ath11k_dp_free(ab);
1492 ath11k_reg_free(ab);
1493 ath11k_qmi_deinit_service(ab);
1494 }
1495
ath11k_core_pdev_create(struct ath11k_base * ab)1496 static int ath11k_core_pdev_create(struct ath11k_base *ab)
1497 {
1498 int ret;
1499
1500 ret = ath11k_debugfs_pdev_create(ab);
1501 if (ret) {
1502 ath11k_err(ab, "failed to create core pdev debugfs: %d\n", ret);
1503 return ret;
1504 }
1505
1506 ret = ath11k_dp_pdev_alloc(ab);
1507 if (ret) {
1508 ath11k_err(ab, "failed to attach DP pdev: %d\n", ret);
1509 goto err_pdev_debug;
1510 }
1511
1512 ret = ath11k_mac_register(ab);
1513 if (ret) {
1514 ath11k_err(ab, "failed register the radio with mac80211: %d\n", ret);
1515 goto err_dp_pdev_free;
1516 }
1517
1518 ret = ath11k_thermal_register(ab);
1519 if (ret) {
1520 ath11k_err(ab, "could not register thermal device: %d\n",
1521 ret);
1522 goto err_mac_unregister;
1523 }
1524
1525 ret = ath11k_spectral_init(ab);
1526 if (ret) {
1527 ath11k_err(ab, "failed to init spectral %d\n", ret);
1528 goto err_thermal_unregister;
1529 }
1530
1531 return 0;
1532
1533 err_thermal_unregister:
1534 ath11k_thermal_unregister(ab);
1535 err_mac_unregister:
1536 ath11k_mac_unregister(ab);
1537 err_dp_pdev_free:
1538 ath11k_dp_pdev_free(ab);
1539 err_pdev_debug:
1540 ath11k_debugfs_pdev_destroy(ab);
1541
1542 return ret;
1543 }
1544
ath11k_core_pdev_destroy(struct ath11k_base * ab)1545 static void ath11k_core_pdev_destroy(struct ath11k_base *ab)
1546 {
1547 ath11k_spectral_deinit(ab);
1548 ath11k_thermal_unregister(ab);
1549 ath11k_mac_unregister(ab);
1550 ath11k_hif_irq_disable(ab);
1551 ath11k_dp_pdev_free(ab);
1552 ath11k_debugfs_pdev_destroy(ab);
1553 }
1554
ath11k_core_start(struct ath11k_base * ab)1555 static int ath11k_core_start(struct ath11k_base *ab)
1556 {
1557 int ret;
1558
1559 ret = ath11k_wmi_attach(ab);
1560 if (ret) {
1561 ath11k_err(ab, "failed to attach wmi: %d\n", ret);
1562 return ret;
1563 }
1564
1565 ret = ath11k_htc_init(ab);
1566 if (ret) {
1567 ath11k_err(ab, "failed to init htc: %d\n", ret);
1568 goto err_wmi_detach;
1569 }
1570
1571 ret = ath11k_hif_start(ab);
1572 if (ret) {
1573 ath11k_err(ab, "failed to start HIF: %d\n", ret);
1574 goto err_wmi_detach;
1575 }
1576
1577 ret = ath11k_htc_wait_target(&ab->htc);
1578 if (ret) {
1579 ath11k_err(ab, "failed to connect to HTC: %d\n", ret);
1580 goto err_hif_stop;
1581 }
1582
1583 ret = ath11k_dp_htt_connect(&ab->dp);
1584 if (ret) {
1585 ath11k_err(ab, "failed to connect to HTT: %d\n", ret);
1586 goto err_hif_stop;
1587 }
1588
1589 ret = ath11k_wmi_connect(ab);
1590 if (ret) {
1591 ath11k_err(ab, "failed to connect wmi: %d\n", ret);
1592 goto err_hif_stop;
1593 }
1594
1595 ret = ath11k_htc_start(&ab->htc);
1596 if (ret) {
1597 ath11k_err(ab, "failed to start HTC: %d\n", ret);
1598 goto err_hif_stop;
1599 }
1600
1601 ret = ath11k_wmi_wait_for_service_ready(ab);
1602 if (ret) {
1603 ath11k_err(ab, "failed to receive wmi service ready event: %d\n",
1604 ret);
1605 goto err_hif_stop;
1606 }
1607
1608 ret = ath11k_mac_allocate(ab);
1609 if (ret) {
1610 ath11k_err(ab, "failed to create new hw device with mac80211 :%d\n",
1611 ret);
1612 goto err_hif_stop;
1613 }
1614
1615 ath11k_dp_pdev_pre_alloc(ab);
1616
1617 ret = ath11k_dp_pdev_reo_setup(ab);
1618 if (ret) {
1619 ath11k_err(ab, "failed to initialize reo destination rings: %d\n", ret);
1620 goto err_mac_destroy;
1621 }
1622
1623 ret = ath11k_wmi_cmd_init(ab);
1624 if (ret) {
1625 ath11k_err(ab, "failed to send wmi init cmd: %d\n", ret);
1626 goto err_reo_cleanup;
1627 }
1628
1629 ret = ath11k_wmi_wait_for_unified_ready(ab);
1630 if (ret) {
1631 ath11k_err(ab, "failed to receive wmi unified ready event: %d\n",
1632 ret);
1633 goto err_reo_cleanup;
1634 }
1635
1636 /* put hardware to DBS mode */
1637 if (ab->hw_params.single_pdev_only && ab->hw_params.num_rxmda_per_pdev > 1) {
1638 ret = ath11k_wmi_set_hw_mode(ab, WMI_HOST_HW_MODE_DBS);
1639 if (ret) {
1640 ath11k_err(ab, "failed to send dbs mode: %d\n", ret);
1641 goto err_hif_stop;
1642 }
1643 }
1644
1645 ret = ath11k_dp_tx_htt_h2t_ver_req_msg(ab);
1646 if (ret) {
1647 ath11k_err(ab, "failed to send htt version request message: %d\n",
1648 ret);
1649 goto err_reo_cleanup;
1650 }
1651
1652 return 0;
1653
1654 err_reo_cleanup:
1655 ath11k_dp_pdev_reo_cleanup(ab);
1656 err_mac_destroy:
1657 ath11k_mac_destroy(ab);
1658 err_hif_stop:
1659 ath11k_hif_stop(ab);
1660 err_wmi_detach:
1661 ath11k_wmi_detach(ab);
1662
1663 return ret;
1664 }
1665
ath11k_core_start_firmware(struct ath11k_base * ab,enum ath11k_firmware_mode mode)1666 static int ath11k_core_start_firmware(struct ath11k_base *ab,
1667 enum ath11k_firmware_mode mode)
1668 {
1669 int ret;
1670
1671 ath11k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v2,
1672 &ab->qmi.ce_cfg.shadow_reg_v2_len);
1673
1674 ret = ath11k_qmi_firmware_start(ab, mode);
1675 if (ret) {
1676 ath11k_err(ab, "failed to send firmware start: %d\n", ret);
1677 return ret;
1678 }
1679
1680 return ret;
1681 }
1682
ath11k_core_qmi_firmware_ready(struct ath11k_base * ab)1683 int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab)
1684 {
1685 int ret;
1686
1687 switch (ath11k_crypto_mode) {
1688 case ATH11K_CRYPT_MODE_SW:
1689 set_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags);
1690 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
1691 break;
1692 case ATH11K_CRYPT_MODE_HW:
1693 clear_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags);
1694 clear_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
1695 break;
1696 default:
1697 ath11k_info(ab, "invalid crypto_mode: %d\n", ath11k_crypto_mode);
1698 return -EINVAL;
1699 }
1700
1701 ret = ath11k_core_start_firmware(ab, ab->fw_mode);
1702 if (ret) {
1703 ath11k_err(ab, "failed to start firmware: %d\n", ret);
1704 return ret;
1705 }
1706
1707 ret = ath11k_ce_init_pipes(ab);
1708 if (ret) {
1709 ath11k_err(ab, "failed to initialize CE: %d\n", ret);
1710 goto err_firmware_stop;
1711 }
1712
1713 ret = ath11k_dp_alloc(ab);
1714 if (ret) {
1715 ath11k_err(ab, "failed to init DP: %d\n", ret);
1716 goto err_firmware_stop;
1717 }
1718
1719 if (ath11k_frame_mode == ATH11K_HW_TXRX_RAW)
1720 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
1721
1722 mutex_lock(&ab->core_lock);
1723 ret = ath11k_core_start(ab);
1724 if (ret) {
1725 ath11k_err(ab, "failed to start core: %d\n", ret);
1726 goto err_dp_free;
1727 }
1728
1729 ret = ath11k_core_pdev_create(ab);
1730 if (ret) {
1731 ath11k_err(ab, "failed to create pdev core: %d\n", ret);
1732 goto err_core_stop;
1733 }
1734 ath11k_hif_irq_enable(ab);
1735 mutex_unlock(&ab->core_lock);
1736
1737 return 0;
1738
1739 err_core_stop:
1740 ath11k_core_stop(ab);
1741 ath11k_mac_destroy(ab);
1742 err_dp_free:
1743 ath11k_dp_free(ab);
1744 mutex_unlock(&ab->core_lock);
1745 err_firmware_stop:
1746 ath11k_qmi_firmware_stop(ab);
1747
1748 return ret;
1749 }
1750
ath11k_core_reconfigure_on_crash(struct ath11k_base * ab)1751 static int ath11k_core_reconfigure_on_crash(struct ath11k_base *ab)
1752 {
1753 int ret;
1754
1755 mutex_lock(&ab->core_lock);
1756 ath11k_thermal_unregister(ab);
1757 ath11k_hif_irq_disable(ab);
1758 ath11k_dp_pdev_free(ab);
1759 ath11k_spectral_deinit(ab);
1760 ath11k_hif_stop(ab);
1761 ath11k_wmi_detach(ab);
1762 ath11k_dp_pdev_reo_cleanup(ab);
1763 mutex_unlock(&ab->core_lock);
1764
1765 ath11k_dp_free(ab);
1766 ath11k_hal_srng_deinit(ab);
1767
1768 ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS(ab))) - 1;
1769
1770 ret = ath11k_hal_srng_init(ab);
1771 if (ret)
1772 return ret;
1773
1774 clear_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags);
1775
1776 ret = ath11k_core_qmi_firmware_ready(ab);
1777 if (ret)
1778 goto err_hal_srng_deinit;
1779
1780 clear_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags);
1781
1782 return 0;
1783
1784 err_hal_srng_deinit:
1785 ath11k_hal_srng_deinit(ab);
1786 return ret;
1787 }
1788
ath11k_core_halt(struct ath11k * ar)1789 void ath11k_core_halt(struct ath11k *ar)
1790 {
1791 struct ath11k_base *ab = ar->ab;
1792 struct list_head *pos, *n;
1793
1794 lockdep_assert_held(&ar->conf_mutex);
1795
1796 ar->num_created_vdevs = 0;
1797 ar->allocated_vdev_map = 0;
1798
1799 ath11k_mac_scan_finish(ar);
1800 ath11k_mac_peer_cleanup_all(ar);
1801 cancel_delayed_work_sync(&ar->scan.timeout);
1802 cancel_work_sync(&ar->regd_update_work);
1803 cancel_work_sync(&ab->update_11d_work);
1804
1805 rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL);
1806 synchronize_rcu();
1807
1808 spin_lock_bh(&ar->data_lock);
1809 list_for_each_safe(pos, n, &ar->arvifs)
1810 list_del_init(pos);
1811 spin_unlock_bh(&ar->data_lock);
1812
1813 idr_init(&ar->txmgmt_idr);
1814 }
1815
ath11k_update_11d(struct work_struct * work)1816 static void ath11k_update_11d(struct work_struct *work)
1817 {
1818 struct ath11k_base *ab = container_of(work, struct ath11k_base, update_11d_work);
1819 struct ath11k *ar;
1820 struct ath11k_pdev *pdev;
1821 struct wmi_set_current_country_params set_current_param = {};
1822 int ret, i;
1823
1824 spin_lock_bh(&ab->base_lock);
1825 memcpy(&set_current_param.alpha2, &ab->new_alpha2, 2);
1826 spin_unlock_bh(&ab->base_lock);
1827
1828 ath11k_dbg(ab, ATH11K_DBG_WMI, "update 11d new cc %c%c\n",
1829 set_current_param.alpha2[0],
1830 set_current_param.alpha2[1]);
1831
1832 for (i = 0; i < ab->num_radios; i++) {
1833 pdev = &ab->pdevs[i];
1834 ar = pdev->ar;
1835
1836 memcpy(&ar->alpha2, &set_current_param.alpha2, 2);
1837 ret = ath11k_wmi_send_set_current_country_cmd(ar, &set_current_param);
1838 if (ret)
1839 ath11k_warn(ar->ab,
1840 "pdev id %d failed set current country code: %d\n",
1841 i, ret);
1842 }
1843 }
1844
ath11k_core_pre_reconfigure_recovery(struct ath11k_base * ab)1845 void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab)
1846 {
1847 struct ath11k *ar;
1848 struct ath11k_pdev *pdev;
1849 int i;
1850
1851 spin_lock_bh(&ab->base_lock);
1852 ab->stats.fw_crash_counter++;
1853 spin_unlock_bh(&ab->base_lock);
1854
1855 for (i = 0; i < ab->num_radios; i++) {
1856 pdev = &ab->pdevs[i];
1857 ar = pdev->ar;
1858 if (!ar || ar->state == ATH11K_STATE_OFF ||
1859 ar->state == ATH11K_STATE_FTM)
1860 continue;
1861
1862 ieee80211_stop_queues(ar->hw);
1863 ath11k_mac_drain_tx(ar);
1864 ar->state_11d = ATH11K_11D_IDLE;
1865 complete(&ar->completed_11d_scan);
1866 complete(&ar->scan.started);
1867 complete_all(&ar->scan.completed);
1868 complete(&ar->scan.on_channel);
1869 complete(&ar->peer_assoc_done);
1870 complete(&ar->peer_delete_done);
1871 complete(&ar->install_key_done);
1872 complete(&ar->vdev_setup_done);
1873 complete(&ar->vdev_delete_done);
1874 complete(&ar->bss_survey_done);
1875 complete(&ar->thermal.wmi_sync);
1876
1877 wake_up(&ar->dp.tx_empty_waitq);
1878 idr_for_each(&ar->txmgmt_idr,
1879 ath11k_mac_tx_mgmt_pending_free, ar);
1880 idr_destroy(&ar->txmgmt_idr);
1881 wake_up(&ar->txmgmt_empty_waitq);
1882
1883 ar->monitor_vdev_id = -1;
1884 clear_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags);
1885 clear_bit(ATH11K_FLAG_MONITOR_VDEV_CREATED, &ar->monitor_flags);
1886 }
1887
1888 wake_up(&ab->wmi_ab.tx_credits_wq);
1889 wake_up(&ab->peer_mapping_wq);
1890
1891 reinit_completion(&ab->driver_recovery);
1892 }
1893
ath11k_core_post_reconfigure_recovery(struct ath11k_base * ab)1894 static void ath11k_core_post_reconfigure_recovery(struct ath11k_base *ab)
1895 {
1896 struct ath11k *ar;
1897 struct ath11k_pdev *pdev;
1898 int i;
1899
1900 for (i = 0; i < ab->num_radios; i++) {
1901 pdev = &ab->pdevs[i];
1902 ar = pdev->ar;
1903 if (!ar || ar->state == ATH11K_STATE_OFF)
1904 continue;
1905
1906 mutex_lock(&ar->conf_mutex);
1907
1908 switch (ar->state) {
1909 case ATH11K_STATE_ON:
1910 ar->state = ATH11K_STATE_RESTARTING;
1911 ath11k_core_halt(ar);
1912 ieee80211_restart_hw(ar->hw);
1913 break;
1914 case ATH11K_STATE_OFF:
1915 ath11k_warn(ab,
1916 "cannot restart radio %d that hasn't been started\n",
1917 i);
1918 break;
1919 case ATH11K_STATE_RESTARTING:
1920 break;
1921 case ATH11K_STATE_RESTARTED:
1922 ar->state = ATH11K_STATE_WEDGED;
1923 fallthrough;
1924 case ATH11K_STATE_WEDGED:
1925 ath11k_warn(ab,
1926 "device is wedged, will not restart radio %d\n", i);
1927 break;
1928 case ATH11K_STATE_FTM:
1929 ath11k_dbg(ab, ATH11K_DBG_TESTMODE,
1930 "fw mode reset done radio %d\n", i);
1931 break;
1932 }
1933
1934 mutex_unlock(&ar->conf_mutex);
1935 }
1936 complete(&ab->driver_recovery);
1937 }
1938
ath11k_core_restart(struct work_struct * work)1939 static void ath11k_core_restart(struct work_struct *work)
1940 {
1941 struct ath11k_base *ab = container_of(work, struct ath11k_base, restart_work);
1942 int ret;
1943
1944 ret = ath11k_core_reconfigure_on_crash(ab);
1945 if (ret) {
1946 ath11k_err(ab, "failed to reconfigure driver on crash recovery\n");
1947 return;
1948 }
1949
1950 if (ab->is_reset)
1951 complete_all(&ab->reconfigure_complete);
1952
1953 if (!ab->is_reset)
1954 ath11k_core_post_reconfigure_recovery(ab);
1955 }
1956
ath11k_core_reset(struct work_struct * work)1957 static void ath11k_core_reset(struct work_struct *work)
1958 {
1959 struct ath11k_base *ab = container_of(work, struct ath11k_base, reset_work);
1960 int reset_count, fail_cont_count;
1961 long time_left;
1962
1963 if (!(test_bit(ATH11K_FLAG_REGISTERED, &ab->dev_flags))) {
1964 ath11k_warn(ab, "ignore reset dev flags 0x%lx\n", ab->dev_flags);
1965 return;
1966 }
1967
1968 /* Sometimes the recovery will fail and then the next all recovery fail,
1969 * this is to avoid infinite recovery since it can not recovery success.
1970 */
1971 fail_cont_count = atomic_read(&ab->fail_cont_count);
1972
1973 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FINAL)
1974 return;
1975
1976 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FIRST &&
1977 time_before(jiffies, ab->reset_fail_timeout))
1978 return;
1979
1980 reset_count = atomic_inc_return(&ab->reset_count);
1981
1982 if (reset_count > 1) {
1983 /* Sometimes it happened another reset worker before the previous one
1984 * completed, then the second reset worker will destroy the previous one,
1985 * thus below is to avoid that.
1986 */
1987 ath11k_warn(ab, "already resetting count %d\n", reset_count);
1988
1989 reinit_completion(&ab->reset_complete);
1990 time_left = wait_for_completion_timeout(&ab->reset_complete,
1991 ATH11K_RESET_TIMEOUT_HZ);
1992
1993 if (time_left) {
1994 ath11k_dbg(ab, ATH11K_DBG_BOOT, "to skip reset\n");
1995 atomic_dec(&ab->reset_count);
1996 return;
1997 }
1998
1999 ab->reset_fail_timeout = jiffies + ATH11K_RESET_FAIL_TIMEOUT_HZ;
2000 /* Record the continuous recovery fail count when recovery failed*/
2001 atomic_inc(&ab->fail_cont_count);
2002 }
2003
2004 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset starting\n");
2005
2006 ab->is_reset = true;
2007 atomic_set(&ab->recovery_count, 0);
2008 reinit_completion(&ab->recovery_start);
2009 atomic_set(&ab->recovery_start_count, 0);
2010
2011 ath11k_core_pre_reconfigure_recovery(ab);
2012
2013 reinit_completion(&ab->reconfigure_complete);
2014 ath11k_core_post_reconfigure_recovery(ab);
2015
2016 ath11k_dbg(ab, ATH11K_DBG_BOOT, "waiting recovery start...\n");
2017
2018 time_left = wait_for_completion_timeout(&ab->recovery_start,
2019 ATH11K_RECOVER_START_TIMEOUT_HZ);
2020
2021 ath11k_hif_power_down(ab);
2022 ath11k_hif_power_up(ab);
2023
2024 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset started\n");
2025 }
2026
ath11k_init_hw_params(struct ath11k_base * ab)2027 static int ath11k_init_hw_params(struct ath11k_base *ab)
2028 {
2029 const struct ath11k_hw_params *hw_params = NULL;
2030 int i;
2031
2032 for (i = 0; i < ARRAY_SIZE(ath11k_hw_params); i++) {
2033 hw_params = &ath11k_hw_params[i];
2034
2035 if (hw_params->hw_rev == ab->hw_rev)
2036 break;
2037 }
2038
2039 if (i == ARRAY_SIZE(ath11k_hw_params)) {
2040 ath11k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev);
2041 return -EINVAL;
2042 }
2043
2044 ab->hw_params = *hw_params;
2045
2046 ath11k_info(ab, "%s\n", ab->hw_params.name);
2047
2048 return 0;
2049 }
2050
ath11k_core_pre_init(struct ath11k_base * ab)2051 int ath11k_core_pre_init(struct ath11k_base *ab)
2052 {
2053 int ret;
2054
2055 ret = ath11k_init_hw_params(ab);
2056 if (ret) {
2057 ath11k_err(ab, "failed to get hw params: %d\n", ret);
2058 return ret;
2059 }
2060
2061 return 0;
2062 }
2063 EXPORT_SYMBOL(ath11k_core_pre_init);
2064
ath11k_core_init(struct ath11k_base * ab)2065 int ath11k_core_init(struct ath11k_base *ab)
2066 {
2067 const struct dmi_system_id *dmi_id;
2068 int ret;
2069
2070 dmi_id = dmi_first_match(ath11k_pm_quirk_table);
2071 if (dmi_id)
2072 ab->pm_policy = (kernel_ulong_t)dmi_id->driver_data;
2073 else
2074 ab->pm_policy = ATH11K_PM_DEFAULT;
2075
2076 ath11k_dbg(ab, ATH11K_DBG_BOOT, "pm policy %u\n", ab->pm_policy);
2077
2078 ret = ath11k_core_soc_create(ab);
2079 if (ret) {
2080 ath11k_err(ab, "failed to create soc core: %d\n", ret);
2081 return ret;
2082 }
2083
2084 return 0;
2085 }
2086 EXPORT_SYMBOL(ath11k_core_init);
2087
ath11k_core_deinit(struct ath11k_base * ab)2088 void ath11k_core_deinit(struct ath11k_base *ab)
2089 {
2090 mutex_lock(&ab->core_lock);
2091
2092 ath11k_core_pdev_destroy(ab);
2093 ath11k_core_stop(ab);
2094
2095 mutex_unlock(&ab->core_lock);
2096
2097 ath11k_hif_power_down(ab);
2098 ath11k_mac_destroy(ab);
2099 ath11k_core_soc_destroy(ab);
2100 }
2101 EXPORT_SYMBOL(ath11k_core_deinit);
2102
ath11k_core_free(struct ath11k_base * ab)2103 void ath11k_core_free(struct ath11k_base *ab)
2104 {
2105 destroy_workqueue(ab->workqueue_aux);
2106 destroy_workqueue(ab->workqueue);
2107
2108 kfree(ab);
2109 }
2110 EXPORT_SYMBOL(ath11k_core_free);
2111
ath11k_core_alloc(struct device * dev,size_t priv_size,enum ath11k_bus bus)2112 struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size,
2113 enum ath11k_bus bus)
2114 {
2115 struct ath11k_base *ab;
2116
2117 ab = kzalloc(sizeof(*ab) + priv_size, GFP_KERNEL);
2118 if (!ab)
2119 return NULL;
2120
2121 init_completion(&ab->driver_recovery);
2122
2123 ab->workqueue = create_singlethread_workqueue("ath11k_wq");
2124 if (!ab->workqueue)
2125 goto err_sc_free;
2126
2127 ab->workqueue_aux = create_singlethread_workqueue("ath11k_aux_wq");
2128 if (!ab->workqueue_aux)
2129 goto err_free_wq;
2130
2131 mutex_init(&ab->core_lock);
2132 mutex_init(&ab->tbl_mtx_lock);
2133 spin_lock_init(&ab->base_lock);
2134 mutex_init(&ab->vdev_id_11d_lock);
2135 init_completion(&ab->reset_complete);
2136 init_completion(&ab->reconfigure_complete);
2137 init_completion(&ab->recovery_start);
2138
2139 INIT_LIST_HEAD(&ab->peers);
2140 init_waitqueue_head(&ab->peer_mapping_wq);
2141 init_waitqueue_head(&ab->wmi_ab.tx_credits_wq);
2142 init_waitqueue_head(&ab->qmi.cold_boot_waitq);
2143 INIT_WORK(&ab->restart_work, ath11k_core_restart);
2144 INIT_WORK(&ab->update_11d_work, ath11k_update_11d);
2145 INIT_WORK(&ab->reset_work, ath11k_core_reset);
2146 timer_setup(&ab->rx_replenish_retry, ath11k_ce_rx_replenish_retry, 0);
2147 init_completion(&ab->htc_suspend);
2148 init_completion(&ab->wow.wakeup_completed);
2149
2150 ab->dev = dev;
2151 ab->hif.bus = bus;
2152
2153 return ab;
2154
2155 err_free_wq:
2156 destroy_workqueue(ab->workqueue);
2157 err_sc_free:
2158 kfree(ab);
2159 return NULL;
2160 }
2161 EXPORT_SYMBOL(ath11k_core_alloc);
2162
2163 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ax wireless LAN cards.");
2164 MODULE_LICENSE("Dual BSD/GPL");
2165