1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/module.h>
8 #include <linux/slab.h>
9 #include <linux/remoteproc.h>
10 #include <linux/firmware.h>
11 #include <linux/of.h>
12
13 #include "core.h"
14 #include "dp_tx.h"
15 #include "dp_rx.h"
16 #include "debug.h"
17 #include "hif.h"
18 #include "wow.h"
19
20 unsigned int ath11k_debug_mask;
21 EXPORT_SYMBOL(ath11k_debug_mask);
22 module_param_named(debug_mask, ath11k_debug_mask, uint, 0644);
23 MODULE_PARM_DESC(debug_mask, "Debugging mask");
24
25 static unsigned int ath11k_crypto_mode;
26 module_param_named(crypto_mode, ath11k_crypto_mode, uint, 0644);
27 MODULE_PARM_DESC(crypto_mode, "crypto mode: 0-hardware, 1-software");
28
29 /* frame mode values are mapped as per enum ath11k_hw_txrx_mode */
30 unsigned int ath11k_frame_mode = ATH11K_HW_TXRX_NATIVE_WIFI;
31 module_param_named(frame_mode, ath11k_frame_mode, uint, 0644);
32 MODULE_PARM_DESC(frame_mode,
33 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)");
34
35 bool ath11k_ftm_mode;
36 module_param_named(ftm_mode, ath11k_ftm_mode, bool, 0444);
37 MODULE_PARM_DESC(ftm_mode, "Boots up in factory test mode");
38
39 static const struct ath11k_hw_params ath11k_hw_params[] = {
40 {
41 .hw_rev = ATH11K_HW_IPQ8074,
42 .name = "ipq8074 hw2.0",
43 .fw = {
44 .dir = "IPQ8074/hw2.0",
45 .board_size = 256 * 1024,
46 .cal_offset = 128 * 1024,
47 },
48 .max_radios = 3,
49 .bdf_addr = 0x4B0C0000,
50 .hw_ops = &ipq8074_ops,
51 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
52 .internal_sleep_clock = false,
53 .regs = &ipq8074_regs,
54 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
55 .host_ce_config = ath11k_host_ce_config_ipq8074,
56 .ce_count = 12,
57 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074,
58 .target_ce_count = 11,
59 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq8074,
60 .svc_to_ce_map_len = 21,
61 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
62 .single_pdev_only = false,
63 .rxdma1_enable = true,
64 .num_rxmda_per_pdev = 1,
65 .rx_mac_buf_ring = false,
66 .vdev_start_delay = false,
67 .htt_peer_map_v2 = true,
68
69 .spectral = {
70 .fft_sz = 2,
71 /* HW bug, expected BIN size is 2 bytes but HW report as 4 bytes.
72 * so added pad size as 2 bytes to compensate the BIN size
73 */
74 .fft_pad_sz = 2,
75 .summary_pad_sz = 0,
76 .fft_hdr_len = 16,
77 .max_fft_bins = 512,
78 .fragment_160mhz = true,
79 },
80
81 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
82 BIT(NL80211_IFTYPE_AP) |
83 BIT(NL80211_IFTYPE_MESH_POINT),
84 .supports_monitor = true,
85 .full_monitor_mode = false,
86 .supports_shadow_regs = false,
87 .idle_ps = false,
88 .supports_sta_ps = false,
89 .coldboot_cal_mm = true,
90 .coldboot_cal_ftm = true,
91 .cbcal_restart_fw = true,
92 .fw_mem_mode = 0,
93 .num_vdevs = 16 + 1,
94 .num_peers = 512,
95 .supports_suspend = false,
96 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
97 .supports_regdb = false,
98 .fix_l1ss = true,
99 .credit_flow = false,
100 .max_tx_ring = DP_TCL_NUM_RING_MAX,
101 .hal_params = &ath11k_hw_hal_params_ipq8074,
102 .supports_dynamic_smps_6ghz = false,
103 .alloc_cacheable_memory = true,
104 .supports_rssi_stats = false,
105 .fw_wmi_diag_event = false,
106 .current_cc_support = false,
107 .dbr_debug_support = true,
108 .global_reset = false,
109 .bios_sar_capa = NULL,
110 .m3_fw_support = false,
111 .fixed_bdf_addr = true,
112 .fixed_mem_region = true,
113 .static_window_map = false,
114 .hybrid_bus_type = false,
115 .fixed_fw_mem = false,
116 .support_off_channel_tx = false,
117 .supports_multi_bssid = false,
118
119 .sram_dump = {},
120
121 .tcl_ring_retry = true,
122 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
123 .smp2p_wow_exit = false,
124 },
125 {
126 .hw_rev = ATH11K_HW_IPQ6018_HW10,
127 .name = "ipq6018 hw1.0",
128 .fw = {
129 .dir = "IPQ6018/hw1.0",
130 .board_size = 256 * 1024,
131 .cal_offset = 128 * 1024,
132 },
133 .max_radios = 2,
134 .bdf_addr = 0x4ABC0000,
135 .hw_ops = &ipq6018_ops,
136 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
137 .internal_sleep_clock = false,
138 .regs = &ipq8074_regs,
139 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
140 .host_ce_config = ath11k_host_ce_config_ipq8074,
141 .ce_count = 12,
142 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074,
143 .target_ce_count = 11,
144 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq6018,
145 .svc_to_ce_map_len = 19,
146 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
147 .single_pdev_only = false,
148 .rxdma1_enable = true,
149 .num_rxmda_per_pdev = 1,
150 .rx_mac_buf_ring = false,
151 .vdev_start_delay = false,
152 .htt_peer_map_v2 = true,
153
154 .spectral = {
155 .fft_sz = 4,
156 .fft_pad_sz = 0,
157 .summary_pad_sz = 0,
158 .fft_hdr_len = 16,
159 .max_fft_bins = 512,
160 .fragment_160mhz = true,
161 },
162
163 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
164 BIT(NL80211_IFTYPE_AP) |
165 BIT(NL80211_IFTYPE_MESH_POINT),
166 .supports_monitor = true,
167 .full_monitor_mode = false,
168 .supports_shadow_regs = false,
169 .idle_ps = false,
170 .supports_sta_ps = false,
171 .coldboot_cal_mm = true,
172 .coldboot_cal_ftm = true,
173 .cbcal_restart_fw = true,
174 .fw_mem_mode = 0,
175 .num_vdevs = 16 + 1,
176 .num_peers = 512,
177 .supports_suspend = false,
178 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
179 .supports_regdb = false,
180 .fix_l1ss = true,
181 .credit_flow = false,
182 .max_tx_ring = DP_TCL_NUM_RING_MAX,
183 .hal_params = &ath11k_hw_hal_params_ipq8074,
184 .supports_dynamic_smps_6ghz = false,
185 .alloc_cacheable_memory = true,
186 .supports_rssi_stats = false,
187 .fw_wmi_diag_event = false,
188 .current_cc_support = false,
189 .dbr_debug_support = true,
190 .global_reset = false,
191 .bios_sar_capa = NULL,
192 .m3_fw_support = false,
193 .fixed_bdf_addr = true,
194 .fixed_mem_region = true,
195 .static_window_map = false,
196 .hybrid_bus_type = false,
197 .fixed_fw_mem = false,
198 .support_off_channel_tx = false,
199 .supports_multi_bssid = false,
200
201 .sram_dump = {},
202
203 .tcl_ring_retry = true,
204 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
205 .smp2p_wow_exit = false,
206 .support_fw_mac_sequence = false,
207 },
208 {
209 .name = "qca6390 hw2.0",
210 .hw_rev = ATH11K_HW_QCA6390_HW20,
211 .fw = {
212 .dir = "QCA6390/hw2.0",
213 .board_size = 256 * 1024,
214 .cal_offset = 128 * 1024,
215 },
216 .max_radios = 3,
217 .bdf_addr = 0x4B0C0000,
218 .hw_ops = &qca6390_ops,
219 .ring_mask = &ath11k_hw_ring_mask_qca6390,
220 .internal_sleep_clock = true,
221 .regs = &qca6390_regs,
222 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
223 .host_ce_config = ath11k_host_ce_config_qca6390,
224 .ce_count = 9,
225 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
226 .target_ce_count = 9,
227 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
228 .svc_to_ce_map_len = 14,
229 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
230 .single_pdev_only = true,
231 .rxdma1_enable = false,
232 .num_rxmda_per_pdev = 2,
233 .rx_mac_buf_ring = true,
234 .vdev_start_delay = true,
235 .htt_peer_map_v2 = false,
236
237 .spectral = {
238 .fft_sz = 0,
239 .fft_pad_sz = 0,
240 .summary_pad_sz = 0,
241 .fft_hdr_len = 0,
242 .max_fft_bins = 0,
243 .fragment_160mhz = false,
244 },
245
246 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
247 BIT(NL80211_IFTYPE_AP),
248 .supports_monitor = false,
249 .full_monitor_mode = false,
250 .supports_shadow_regs = true,
251 .idle_ps = true,
252 .supports_sta_ps = true,
253 .coldboot_cal_mm = false,
254 .coldboot_cal_ftm = false,
255 .cbcal_restart_fw = false,
256 .fw_mem_mode = 0,
257 .num_vdevs = 16 + 1,
258 .num_peers = 512,
259 .supports_suspend = true,
260 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
261 .supports_regdb = false,
262 .fix_l1ss = true,
263 .credit_flow = true,
264 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
265 .hal_params = &ath11k_hw_hal_params_qca6390,
266 .supports_dynamic_smps_6ghz = false,
267 .alloc_cacheable_memory = false,
268 .supports_rssi_stats = true,
269 .fw_wmi_diag_event = true,
270 .current_cc_support = true,
271 .dbr_debug_support = false,
272 .global_reset = true,
273 .bios_sar_capa = NULL,
274 .m3_fw_support = true,
275 .fixed_bdf_addr = false,
276 .fixed_mem_region = false,
277 .static_window_map = false,
278 .hybrid_bus_type = false,
279 .fixed_fw_mem = false,
280 .support_off_channel_tx = true,
281 .supports_multi_bssid = true,
282
283 .sram_dump = {
284 .start = 0x01400000,
285 .end = 0x0171ffff,
286 },
287
288 .tcl_ring_retry = true,
289 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
290 .smp2p_wow_exit = false,
291 .support_fw_mac_sequence = true,
292 },
293 {
294 .name = "qcn9074 hw1.0",
295 .hw_rev = ATH11K_HW_QCN9074_HW10,
296 .fw = {
297 .dir = "QCN9074/hw1.0",
298 .board_size = 256 * 1024,
299 .cal_offset = 128 * 1024,
300 },
301 .max_radios = 1,
302 .single_pdev_only = false,
303 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074,
304 .hw_ops = &qcn9074_ops,
305 .ring_mask = &ath11k_hw_ring_mask_qcn9074,
306 .internal_sleep_clock = false,
307 .regs = &qcn9074_regs,
308 .host_ce_config = ath11k_host_ce_config_qcn9074,
309 .ce_count = 6,
310 .target_ce_config = ath11k_target_ce_config_wlan_qcn9074,
311 .target_ce_count = 9,
312 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qcn9074,
313 .svc_to_ce_map_len = 18,
314 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
315 .rxdma1_enable = true,
316 .num_rxmda_per_pdev = 1,
317 .rx_mac_buf_ring = false,
318 .vdev_start_delay = false,
319 .htt_peer_map_v2 = true,
320
321 .spectral = {
322 .fft_sz = 2,
323 .fft_pad_sz = 0,
324 .summary_pad_sz = 16,
325 .fft_hdr_len = 24,
326 .max_fft_bins = 1024,
327 .fragment_160mhz = false,
328 },
329
330 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
331 BIT(NL80211_IFTYPE_AP) |
332 BIT(NL80211_IFTYPE_MESH_POINT),
333 .supports_monitor = true,
334 .full_monitor_mode = true,
335 .supports_shadow_regs = false,
336 .idle_ps = false,
337 .supports_sta_ps = false,
338 .coldboot_cal_mm = false,
339 .coldboot_cal_ftm = true,
340 .cbcal_restart_fw = true,
341 .fw_mem_mode = 2,
342 .num_vdevs = 8,
343 .num_peers = 128,
344 .supports_suspend = false,
345 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
346 .supports_regdb = false,
347 .fix_l1ss = true,
348 .credit_flow = false,
349 .max_tx_ring = DP_TCL_NUM_RING_MAX,
350 .hal_params = &ath11k_hw_hal_params_ipq8074,
351 .supports_dynamic_smps_6ghz = true,
352 .alloc_cacheable_memory = true,
353 .supports_rssi_stats = false,
354 .fw_wmi_diag_event = false,
355 .current_cc_support = false,
356 .dbr_debug_support = true,
357 .global_reset = false,
358 .bios_sar_capa = NULL,
359 .m3_fw_support = true,
360 .fixed_bdf_addr = false,
361 .fixed_mem_region = false,
362 .static_window_map = true,
363 .hybrid_bus_type = false,
364 .fixed_fw_mem = false,
365 .support_off_channel_tx = false,
366 .supports_multi_bssid = false,
367
368 .sram_dump = {},
369
370 .tcl_ring_retry = true,
371 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
372 .smp2p_wow_exit = false,
373 .support_fw_mac_sequence = false,
374 },
375 {
376 .name = "wcn6855 hw2.0",
377 .hw_rev = ATH11K_HW_WCN6855_HW20,
378 .fw = {
379 .dir = "WCN6855/hw2.0",
380 .board_size = 256 * 1024,
381 .cal_offset = 128 * 1024,
382 },
383 .max_radios = 3,
384 .bdf_addr = 0x4B0C0000,
385 .hw_ops = &wcn6855_ops,
386 .ring_mask = &ath11k_hw_ring_mask_qca6390,
387 .internal_sleep_clock = true,
388 .regs = &wcn6855_regs,
389 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
390 .host_ce_config = ath11k_host_ce_config_qca6390,
391 .ce_count = 9,
392 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
393 .target_ce_count = 9,
394 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
395 .svc_to_ce_map_len = 14,
396 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
397 .single_pdev_only = true,
398 .rxdma1_enable = false,
399 .num_rxmda_per_pdev = 2,
400 .rx_mac_buf_ring = true,
401 .vdev_start_delay = true,
402 .htt_peer_map_v2 = false,
403
404 .spectral = {
405 .fft_sz = 0,
406 .fft_pad_sz = 0,
407 .summary_pad_sz = 0,
408 .fft_hdr_len = 0,
409 .max_fft_bins = 0,
410 .fragment_160mhz = false,
411 },
412
413 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
414 BIT(NL80211_IFTYPE_AP),
415 .supports_monitor = false,
416 .full_monitor_mode = false,
417 .supports_shadow_regs = true,
418 .idle_ps = true,
419 .supports_sta_ps = true,
420 .coldboot_cal_mm = false,
421 .coldboot_cal_ftm = false,
422 .cbcal_restart_fw = false,
423 .fw_mem_mode = 0,
424 .num_vdevs = 16 + 1,
425 .num_peers = 512,
426 .supports_suspend = true,
427 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
428 .supports_regdb = true,
429 .fix_l1ss = false,
430 .credit_flow = true,
431 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
432 .hal_params = &ath11k_hw_hal_params_qca6390,
433 .supports_dynamic_smps_6ghz = false,
434 .alloc_cacheable_memory = false,
435 .supports_rssi_stats = true,
436 .fw_wmi_diag_event = true,
437 .current_cc_support = true,
438 .dbr_debug_support = false,
439 .global_reset = true,
440 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
441 .m3_fw_support = true,
442 .fixed_bdf_addr = false,
443 .fixed_mem_region = false,
444 .static_window_map = false,
445 .hybrid_bus_type = false,
446 .fixed_fw_mem = false,
447 .support_off_channel_tx = true,
448 .supports_multi_bssid = true,
449
450 .sram_dump = {
451 .start = 0x01400000,
452 .end = 0x0177ffff,
453 },
454
455 .tcl_ring_retry = true,
456 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
457 .smp2p_wow_exit = false,
458 .support_fw_mac_sequence = true,
459 },
460 {
461 .name = "wcn6855 hw2.1",
462 .hw_rev = ATH11K_HW_WCN6855_HW21,
463 .fw = {
464 .dir = "WCN6855/hw2.1",
465 .board_size = 256 * 1024,
466 .cal_offset = 128 * 1024,
467 },
468 .max_radios = 3,
469 .bdf_addr = 0x4B0C0000,
470 .hw_ops = &wcn6855_ops,
471 .ring_mask = &ath11k_hw_ring_mask_qca6390,
472 .internal_sleep_clock = true,
473 .regs = &wcn6855_regs,
474 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
475 .host_ce_config = ath11k_host_ce_config_qca6390,
476 .ce_count = 9,
477 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
478 .target_ce_count = 9,
479 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
480 .svc_to_ce_map_len = 14,
481 .single_pdev_only = true,
482 .rxdma1_enable = false,
483 .num_rxmda_per_pdev = 2,
484 .rx_mac_buf_ring = true,
485 .vdev_start_delay = true,
486 .htt_peer_map_v2 = false,
487
488 .spectral = {
489 .fft_sz = 0,
490 .fft_pad_sz = 0,
491 .summary_pad_sz = 0,
492 .fft_hdr_len = 0,
493 .max_fft_bins = 0,
494 .fragment_160mhz = false,
495 },
496
497 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
498 BIT(NL80211_IFTYPE_AP),
499 .supports_monitor = false,
500 .supports_shadow_regs = true,
501 .idle_ps = true,
502 .supports_sta_ps = true,
503 .coldboot_cal_mm = false,
504 .coldboot_cal_ftm = false,
505 .cbcal_restart_fw = false,
506 .fw_mem_mode = 0,
507 .num_vdevs = 16 + 1,
508 .num_peers = 512,
509 .supports_suspend = true,
510 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
511 .supports_regdb = true,
512 .fix_l1ss = false,
513 .credit_flow = true,
514 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
515 .hal_params = &ath11k_hw_hal_params_qca6390,
516 .supports_dynamic_smps_6ghz = false,
517 .alloc_cacheable_memory = false,
518 .supports_rssi_stats = true,
519 .fw_wmi_diag_event = true,
520 .current_cc_support = true,
521 .dbr_debug_support = false,
522 .global_reset = true,
523 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
524 .m3_fw_support = true,
525 .fixed_bdf_addr = false,
526 .fixed_mem_region = false,
527 .static_window_map = false,
528 .hybrid_bus_type = false,
529 .fixed_fw_mem = false,
530 .support_off_channel_tx = true,
531 .supports_multi_bssid = true,
532
533 .sram_dump = {
534 .start = 0x01400000,
535 .end = 0x0177ffff,
536 },
537
538 .tcl_ring_retry = true,
539 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
540 .smp2p_wow_exit = false,
541 .support_fw_mac_sequence = true,
542 },
543 {
544 .name = "wcn6750 hw1.0",
545 .hw_rev = ATH11K_HW_WCN6750_HW10,
546 .fw = {
547 .dir = "WCN6750/hw1.0",
548 .board_size = 256 * 1024,
549 .cal_offset = 128 * 1024,
550 },
551 .max_radios = 1,
552 .bdf_addr = 0x4B0C0000,
553 .hw_ops = &wcn6750_ops,
554 .ring_mask = &ath11k_hw_ring_mask_wcn6750,
555 .internal_sleep_clock = false,
556 .regs = &wcn6750_regs,
557 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750,
558 .host_ce_config = ath11k_host_ce_config_qca6390,
559 .ce_count = 9,
560 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
561 .target_ce_count = 9,
562 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
563 .svc_to_ce_map_len = 14,
564 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
565 .single_pdev_only = true,
566 .rxdma1_enable = false,
567 .num_rxmda_per_pdev = 1,
568 .rx_mac_buf_ring = true,
569 .vdev_start_delay = true,
570 .htt_peer_map_v2 = false,
571
572 .spectral = {
573 .fft_sz = 0,
574 .fft_pad_sz = 0,
575 .summary_pad_sz = 0,
576 .fft_hdr_len = 0,
577 .max_fft_bins = 0,
578 .fragment_160mhz = false,
579 },
580
581 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
582 BIT(NL80211_IFTYPE_AP),
583 .supports_monitor = false,
584 .supports_shadow_regs = true,
585 .idle_ps = true,
586 .supports_sta_ps = true,
587 .coldboot_cal_mm = true,
588 .coldboot_cal_ftm = true,
589 .cbcal_restart_fw = false,
590 .fw_mem_mode = 0,
591 .num_vdevs = 16 + 1,
592 .num_peers = 512,
593 .supports_suspend = false,
594 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
595 .supports_regdb = true,
596 .fix_l1ss = false,
597 .credit_flow = true,
598 .max_tx_ring = DP_TCL_NUM_RING_MAX,
599 .hal_params = &ath11k_hw_hal_params_wcn6750,
600 .supports_dynamic_smps_6ghz = false,
601 .alloc_cacheable_memory = false,
602 .supports_rssi_stats = true,
603 .fw_wmi_diag_event = false,
604 .current_cc_support = true,
605 .dbr_debug_support = false,
606 .global_reset = false,
607 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
608 .m3_fw_support = false,
609 .fixed_bdf_addr = false,
610 .fixed_mem_region = false,
611 .static_window_map = true,
612 .hybrid_bus_type = true,
613 .fixed_fw_mem = true,
614 .support_off_channel_tx = true,
615 .supports_multi_bssid = true,
616
617 .sram_dump = {},
618
619 .tcl_ring_retry = false,
620 .tx_ring_size = DP_TCL_DATA_RING_SIZE_WCN6750,
621 .smp2p_wow_exit = true,
622 .support_fw_mac_sequence = true,
623 },
624 {
625 .hw_rev = ATH11K_HW_IPQ5018_HW10,
626 .name = "ipq5018 hw1.0",
627 .fw = {
628 .dir = "IPQ5018/hw1.0",
629 .board_size = 256 * 1024,
630 .cal_offset = 128 * 1024,
631 },
632 .max_radios = MAX_RADIOS_5018,
633 .bdf_addr = 0x4BA00000,
634 /* hal_desc_sz and hw ops are similar to qcn9074 */
635 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
636 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
637 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
638 .credit_flow = false,
639 .max_tx_ring = 1,
640 .spectral = {
641 .fft_sz = 2,
642 .fft_pad_sz = 0,
643 .summary_pad_sz = 16,
644 .fft_hdr_len = 24,
645 .max_fft_bins = 1024,
646 },
647 .internal_sleep_clock = false,
648 .regs = &ipq5018_regs,
649 .hw_ops = &ipq5018_ops,
650 .host_ce_config = ath11k_host_ce_config_qcn9074,
651 .ce_count = CE_CNT_5018,
652 .target_ce_config = ath11k_target_ce_config_wlan_ipq5018,
653 .target_ce_count = TARGET_CE_CNT_5018,
654 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq5018,
655 .svc_to_ce_map_len = SVC_CE_MAP_LEN_5018,
656 .ce_ie_addr = &ath11k_ce_ie_addr_ipq5018,
657 .ce_remap = &ath11k_ce_remap_ipq5018,
658 .rxdma1_enable = true,
659 .num_rxmda_per_pdev = RXDMA_PER_PDEV_5018,
660 .rx_mac_buf_ring = false,
661 .vdev_start_delay = false,
662 .htt_peer_map_v2 = true,
663 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
664 BIT(NL80211_IFTYPE_AP) |
665 BIT(NL80211_IFTYPE_MESH_POINT),
666 .supports_monitor = false,
667 .supports_sta_ps = false,
668 .supports_shadow_regs = false,
669 .fw_mem_mode = 0,
670 .num_vdevs = 16 + 1,
671 .num_peers = 512,
672 .supports_regdb = false,
673 .idle_ps = false,
674 .supports_suspend = false,
675 .hal_params = &ath11k_hw_hal_params_ipq8074,
676 .single_pdev_only = false,
677 .coldboot_cal_mm = true,
678 .coldboot_cal_ftm = true,
679 .cbcal_restart_fw = true,
680 .fix_l1ss = true,
681 .supports_dynamic_smps_6ghz = false,
682 .alloc_cacheable_memory = true,
683 .supports_rssi_stats = false,
684 .fw_wmi_diag_event = false,
685 .current_cc_support = false,
686 .dbr_debug_support = true,
687 .global_reset = false,
688 .bios_sar_capa = NULL,
689 .m3_fw_support = false,
690 .fixed_bdf_addr = true,
691 .fixed_mem_region = true,
692 .static_window_map = false,
693 .hybrid_bus_type = false,
694 .fixed_fw_mem = false,
695 .support_off_channel_tx = false,
696 .supports_multi_bssid = false,
697
698 .sram_dump = {},
699
700 .tcl_ring_retry = true,
701 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
702 .smp2p_wow_exit = false,
703 .support_fw_mac_sequence = false,
704 },
705 };
706
ath11k_core_get_single_pdev(struct ath11k_base * ab)707 static inline struct ath11k_pdev *ath11k_core_get_single_pdev(struct ath11k_base *ab)
708 {
709 WARN_ON(!ab->hw_params.single_pdev_only);
710
711 return &ab->pdevs[0];
712 }
713
ath11k_fw_stats_pdevs_free(struct list_head * head)714 void ath11k_fw_stats_pdevs_free(struct list_head *head)
715 {
716 struct ath11k_fw_stats_pdev *i, *tmp;
717
718 list_for_each_entry_safe(i, tmp, head, list) {
719 list_del(&i->list);
720 kfree(i);
721 }
722 }
723
ath11k_fw_stats_vdevs_free(struct list_head * head)724 void ath11k_fw_stats_vdevs_free(struct list_head *head)
725 {
726 struct ath11k_fw_stats_vdev *i, *tmp;
727
728 list_for_each_entry_safe(i, tmp, head, list) {
729 list_del(&i->list);
730 kfree(i);
731 }
732 }
733
ath11k_fw_stats_bcn_free(struct list_head * head)734 void ath11k_fw_stats_bcn_free(struct list_head *head)
735 {
736 struct ath11k_fw_stats_bcn *i, *tmp;
737
738 list_for_each_entry_safe(i, tmp, head, list) {
739 list_del(&i->list);
740 kfree(i);
741 }
742 }
743
ath11k_fw_stats_init(struct ath11k * ar)744 void ath11k_fw_stats_init(struct ath11k *ar)
745 {
746 INIT_LIST_HEAD(&ar->fw_stats.pdevs);
747 INIT_LIST_HEAD(&ar->fw_stats.vdevs);
748 INIT_LIST_HEAD(&ar->fw_stats.bcn);
749
750 init_completion(&ar->fw_stats_complete);
751 init_completion(&ar->fw_stats_done);
752 }
753
ath11k_fw_stats_free(struct ath11k_fw_stats * stats)754 void ath11k_fw_stats_free(struct ath11k_fw_stats *stats)
755 {
756 ath11k_fw_stats_pdevs_free(&stats->pdevs);
757 ath11k_fw_stats_vdevs_free(&stats->vdevs);
758 ath11k_fw_stats_bcn_free(&stats->bcn);
759 }
760
ath11k_core_coldboot_cal_support(struct ath11k_base * ab)761 bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab)
762 {
763 if (!ath11k_cold_boot_cal)
764 return false;
765
766 if (ath11k_ftm_mode)
767 return ab->hw_params.coldboot_cal_ftm;
768
769 else
770 return ab->hw_params.coldboot_cal_mm;
771 }
772
ath11k_core_suspend(struct ath11k_base * ab)773 int ath11k_core_suspend(struct ath11k_base *ab)
774 {
775 int ret;
776 struct ath11k_pdev *pdev;
777 struct ath11k *ar;
778
779 if (!ab->hw_params.supports_suspend)
780 return -EOPNOTSUPP;
781
782 /* so far single_pdev_only chips have supports_suspend as true
783 * and only the first pdev is valid.
784 */
785 pdev = ath11k_core_get_single_pdev(ab);
786 ar = pdev->ar;
787 if (!ar || ar->state != ATH11K_STATE_OFF)
788 return 0;
789
790 ret = ath11k_dp_rx_pktlog_stop(ab, true);
791 if (ret) {
792 ath11k_warn(ab, "failed to stop dp rx (and timer) pktlog during suspend: %d\n",
793 ret);
794 return ret;
795 }
796
797 ret = ath11k_mac_wait_tx_complete(ar);
798 if (ret) {
799 ath11k_warn(ab, "failed to wait tx complete: %d\n", ret);
800 return ret;
801 }
802
803 ret = ath11k_wow_enable(ab);
804 if (ret) {
805 ath11k_warn(ab, "failed to enable wow during suspend: %d\n", ret);
806 return ret;
807 }
808
809 ret = ath11k_dp_rx_pktlog_stop(ab, false);
810 if (ret) {
811 ath11k_warn(ab, "failed to stop dp rx pktlog during suspend: %d\n",
812 ret);
813 return ret;
814 }
815
816 ath11k_ce_stop_shadow_timers(ab);
817 ath11k_dp_stop_shadow_timers(ab);
818
819 ath11k_hif_irq_disable(ab);
820 ath11k_hif_ce_irq_disable(ab);
821
822 ret = ath11k_hif_suspend(ab);
823 if (ret) {
824 ath11k_warn(ab, "failed to suspend hif: %d\n", ret);
825 return ret;
826 }
827
828 return 0;
829 }
830 EXPORT_SYMBOL(ath11k_core_suspend);
831
ath11k_core_resume(struct ath11k_base * ab)832 int ath11k_core_resume(struct ath11k_base *ab)
833 {
834 int ret;
835 struct ath11k_pdev *pdev;
836 struct ath11k *ar;
837
838 if (!ab->hw_params.supports_suspend)
839 return -EOPNOTSUPP;
840
841 /* so far signle_pdev_only chips have supports_suspend as true
842 * and only the first pdev is valid.
843 */
844 pdev = ath11k_core_get_single_pdev(ab);
845 ar = pdev->ar;
846 if (!ar || ar->state != ATH11K_STATE_OFF)
847 return 0;
848
849 ret = ath11k_hif_resume(ab);
850 if (ret) {
851 ath11k_warn(ab, "failed to resume hif during resume: %d\n", ret);
852 return ret;
853 }
854
855 ath11k_hif_ce_irq_enable(ab);
856 ath11k_hif_irq_enable(ab);
857
858 ret = ath11k_dp_rx_pktlog_start(ab);
859 if (ret) {
860 ath11k_warn(ab, "failed to start rx pktlog during resume: %d\n",
861 ret);
862 return ret;
863 }
864
865 ret = ath11k_wow_wakeup(ab);
866 if (ret) {
867 ath11k_warn(ab, "failed to wakeup wow during resume: %d\n", ret);
868 return ret;
869 }
870
871 return 0;
872 }
873 EXPORT_SYMBOL(ath11k_core_resume);
874
ath11k_core_check_cc_code_bdfext(const struct dmi_header * hdr,void * data)875 static void ath11k_core_check_cc_code_bdfext(const struct dmi_header *hdr, void *data)
876 {
877 struct ath11k_base *ab = data;
878 const char *magic = ATH11K_SMBIOS_BDF_EXT_MAGIC;
879 struct ath11k_smbios_bdf *smbios = (struct ath11k_smbios_bdf *)hdr;
880 ssize_t copied;
881 size_t len;
882 int i;
883
884 if (ab->qmi.target.bdf_ext[0] != '\0')
885 return;
886
887 if (hdr->type != ATH11K_SMBIOS_BDF_EXT_TYPE)
888 return;
889
890 if (hdr->length != ATH11K_SMBIOS_BDF_EXT_LENGTH) {
891 ath11k_dbg(ab, ATH11K_DBG_BOOT,
892 "wrong smbios bdf ext type length (%d).\n",
893 hdr->length);
894 return;
895 }
896
897 spin_lock_bh(&ab->base_lock);
898
899 switch (smbios->country_code_flag) {
900 case ATH11K_SMBIOS_CC_ISO:
901 ab->new_alpha2[0] = (smbios->cc_code >> 8) & 0xff;
902 ab->new_alpha2[1] = smbios->cc_code & 0xff;
903 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios cc_code %c%c\n",
904 ab->new_alpha2[0], ab->new_alpha2[1]);
905 break;
906 case ATH11K_SMBIOS_CC_WW:
907 ab->new_alpha2[0] = '0';
908 ab->new_alpha2[1] = '0';
909 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios worldwide regdomain\n");
910 break;
911 default:
912 ath11k_dbg(ab, ATH11K_DBG_BOOT, "ignore smbios country code setting %d\n",
913 smbios->country_code_flag);
914 break;
915 }
916
917 spin_unlock_bh(&ab->base_lock);
918
919 if (!smbios->bdf_enabled) {
920 ath11k_dbg(ab, ATH11K_DBG_BOOT, "bdf variant name not found.\n");
921 return;
922 }
923
924 /* Only one string exists (per spec) */
925 if (memcmp(smbios->bdf_ext, magic, strlen(magic)) != 0) {
926 ath11k_dbg(ab, ATH11K_DBG_BOOT,
927 "bdf variant magic does not match.\n");
928 return;
929 }
930
931 len = min_t(size_t,
932 strlen(smbios->bdf_ext), sizeof(ab->qmi.target.bdf_ext));
933 for (i = 0; i < len; i++) {
934 if (!isascii(smbios->bdf_ext[i]) || !isprint(smbios->bdf_ext[i])) {
935 ath11k_dbg(ab, ATH11K_DBG_BOOT,
936 "bdf variant name contains non ascii chars.\n");
937 return;
938 }
939 }
940
941 /* Copy extension name without magic prefix */
942 copied = strscpy(ab->qmi.target.bdf_ext, smbios->bdf_ext + strlen(magic),
943 sizeof(ab->qmi.target.bdf_ext));
944 if (copied < 0) {
945 ath11k_dbg(ab, ATH11K_DBG_BOOT,
946 "bdf variant string is longer than the buffer can accommodate\n");
947 return;
948 }
949
950 ath11k_dbg(ab, ATH11K_DBG_BOOT,
951 "found and validated bdf variant smbios_type 0x%x bdf %s\n",
952 ATH11K_SMBIOS_BDF_EXT_TYPE, ab->qmi.target.bdf_ext);
953 }
954
ath11k_core_check_smbios(struct ath11k_base * ab)955 int ath11k_core_check_smbios(struct ath11k_base *ab)
956 {
957 ab->qmi.target.bdf_ext[0] = '\0';
958 dmi_walk(ath11k_core_check_cc_code_bdfext, ab);
959
960 if (ab->qmi.target.bdf_ext[0] == '\0')
961 return -ENODATA;
962
963 return 0;
964 }
965
ath11k_core_check_dt(struct ath11k_base * ab)966 int ath11k_core_check_dt(struct ath11k_base *ab)
967 {
968 size_t max_len = sizeof(ab->qmi.target.bdf_ext);
969 const char *variant = NULL;
970 struct device_node *node;
971
972 node = ab->dev->of_node;
973 if (!node)
974 return -ENOENT;
975
976 of_property_read_string(node, "qcom,ath11k-calibration-variant",
977 &variant);
978 if (!variant)
979 return -ENODATA;
980
981 if (strscpy(ab->qmi.target.bdf_ext, variant, max_len) < 0)
982 ath11k_dbg(ab, ATH11K_DBG_BOOT,
983 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n",
984 variant);
985
986 return 0;
987 }
988
__ath11k_core_create_board_name(struct ath11k_base * ab,char * name,size_t name_len,bool with_variant,bool bus_type_mode)989 static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
990 size_t name_len, bool with_variant,
991 bool bus_type_mode)
992 {
993 /* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */
994 char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = { 0 };
995
996 if (with_variant && ab->qmi.target.bdf_ext[0] != '\0')
997 scnprintf(variant, sizeof(variant), ",variant=%s",
998 ab->qmi.target.bdf_ext);
999
1000 switch (ab->id.bdf_search) {
1001 case ATH11K_BDF_SEARCH_BUS_AND_BOARD:
1002 if (bus_type_mode)
1003 scnprintf(name, name_len,
1004 "bus=%s",
1005 ath11k_bus_str(ab->hif.bus));
1006 else
1007 scnprintf(name, name_len,
1008 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s",
1009 ath11k_bus_str(ab->hif.bus),
1010 ab->id.vendor, ab->id.device,
1011 ab->id.subsystem_vendor,
1012 ab->id.subsystem_device,
1013 ab->qmi.target.chip_id,
1014 ab->qmi.target.board_id,
1015 variant);
1016 break;
1017 default:
1018 scnprintf(name, name_len,
1019 "bus=%s,qmi-chip-id=%d,qmi-board-id=%d%s",
1020 ath11k_bus_str(ab->hif.bus),
1021 ab->qmi.target.chip_id,
1022 ab->qmi.target.board_id, variant);
1023 break;
1024 }
1025
1026 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board name '%s'\n", name);
1027
1028 return 0;
1029 }
1030
ath11k_core_create_board_name(struct ath11k_base * ab,char * name,size_t name_len)1031 static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
1032 size_t name_len)
1033 {
1034 return __ath11k_core_create_board_name(ab, name, name_len, true, false);
1035 }
1036
ath11k_core_create_fallback_board_name(struct ath11k_base * ab,char * name,size_t name_len)1037 static int ath11k_core_create_fallback_board_name(struct ath11k_base *ab, char *name,
1038 size_t name_len)
1039 {
1040 return __ath11k_core_create_board_name(ab, name, name_len, false, false);
1041 }
1042
ath11k_core_create_bus_type_board_name(struct ath11k_base * ab,char * name,size_t name_len)1043 static int ath11k_core_create_bus_type_board_name(struct ath11k_base *ab, char *name,
1044 size_t name_len)
1045 {
1046 return __ath11k_core_create_board_name(ab, name, name_len, false, true);
1047 }
1048
ath11k_core_firmware_request(struct ath11k_base * ab,const char * file)1049 const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab,
1050 const char *file)
1051 {
1052 const struct firmware *fw;
1053 char path[100];
1054 int ret;
1055
1056 if (file == NULL)
1057 return ERR_PTR(-ENOENT);
1058
1059 ath11k_core_create_firmware_path(ab, file, path, sizeof(path));
1060
1061 ret = firmware_request_nowarn(&fw, path, ab->dev);
1062 if (ret)
1063 return ERR_PTR(ret);
1064
1065 ath11k_dbg(ab, ATH11K_DBG_BOOT, "firmware request %s size %zu\n",
1066 path, fw->size);
1067
1068 return fw;
1069 }
1070
ath11k_core_free_bdf(struct ath11k_base * ab,struct ath11k_board_data * bd)1071 void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd)
1072 {
1073 if (!IS_ERR(bd->fw))
1074 release_firmware(bd->fw);
1075
1076 memset(bd, 0, sizeof(*bd));
1077 }
1078
ath11k_core_parse_bd_ie_board(struct ath11k_base * ab,struct ath11k_board_data * bd,const void * buf,size_t buf_len,const char * boardname,int ie_id,int name_id,int data_id)1079 static int ath11k_core_parse_bd_ie_board(struct ath11k_base *ab,
1080 struct ath11k_board_data *bd,
1081 const void *buf, size_t buf_len,
1082 const char *boardname,
1083 int ie_id,
1084 int name_id,
1085 int data_id)
1086 {
1087 const struct ath11k_fw_ie *hdr;
1088 bool name_match_found;
1089 int ret, board_ie_id;
1090 size_t board_ie_len;
1091 const void *board_ie_data;
1092
1093 name_match_found = false;
1094
1095 /* go through ATH11K_BD_IE_BOARD_/ATH11K_BD_IE_REGDB_ elements */
1096 while (buf_len > sizeof(struct ath11k_fw_ie)) {
1097 hdr = buf;
1098 board_ie_id = le32_to_cpu(hdr->id);
1099 board_ie_len = le32_to_cpu(hdr->len);
1100 board_ie_data = hdr->data;
1101
1102 buf_len -= sizeof(*hdr);
1103 buf += sizeof(*hdr);
1104
1105 if (buf_len < ALIGN(board_ie_len, 4)) {
1106 ath11k_err(ab, "invalid %s length: %zu < %zu\n",
1107 ath11k_bd_ie_type_str(ie_id),
1108 buf_len, ALIGN(board_ie_len, 4));
1109 ret = -EINVAL;
1110 goto out;
1111 }
1112
1113 if (board_ie_id == name_id) {
1114 ath11k_dbg_dump(ab, ATH11K_DBG_BOOT, "board name", "",
1115 board_ie_data, board_ie_len);
1116
1117 if (board_ie_len != strlen(boardname))
1118 goto next;
1119
1120 ret = memcmp(board_ie_data, boardname, strlen(boardname));
1121 if (ret)
1122 goto next;
1123
1124 name_match_found = true;
1125 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1126 "found match %s for name '%s'",
1127 ath11k_bd_ie_type_str(ie_id),
1128 boardname);
1129 } else if (board_ie_id == data_id) {
1130 if (!name_match_found)
1131 /* no match found */
1132 goto next;
1133
1134 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1135 "found %s for '%s'",
1136 ath11k_bd_ie_type_str(ie_id),
1137 boardname);
1138
1139 bd->data = board_ie_data;
1140 bd->len = board_ie_len;
1141
1142 ret = 0;
1143 goto out;
1144 } else {
1145 ath11k_warn(ab, "unknown %s id found: %d\n",
1146 ath11k_bd_ie_type_str(ie_id),
1147 board_ie_id);
1148 }
1149 next:
1150 /* jump over the padding */
1151 board_ie_len = ALIGN(board_ie_len, 4);
1152
1153 buf_len -= board_ie_len;
1154 buf += board_ie_len;
1155 }
1156
1157 /* no match found */
1158 ret = -ENOENT;
1159
1160 out:
1161 return ret;
1162 }
1163
ath11k_core_fetch_board_data_api_n(struct ath11k_base * ab,struct ath11k_board_data * bd,const char * boardname,int ie_id_match,int name_id,int data_id)1164 static int ath11k_core_fetch_board_data_api_n(struct ath11k_base *ab,
1165 struct ath11k_board_data *bd,
1166 const char *boardname,
1167 int ie_id_match,
1168 int name_id,
1169 int data_id)
1170 {
1171 size_t len, magic_len;
1172 const u8 *data;
1173 char *filename, filepath[100];
1174 size_t ie_len;
1175 struct ath11k_fw_ie *hdr;
1176 int ret, ie_id;
1177
1178 filename = ATH11K_BOARD_API2_FILE;
1179
1180 if (!bd->fw)
1181 bd->fw = ath11k_core_firmware_request(ab, filename);
1182
1183 if (IS_ERR(bd->fw))
1184 return PTR_ERR(bd->fw);
1185
1186 data = bd->fw->data;
1187 len = bd->fw->size;
1188
1189 ath11k_core_create_firmware_path(ab, filename,
1190 filepath, sizeof(filepath));
1191
1192 /* magic has extra null byte padded */
1193 magic_len = strlen(ATH11K_BOARD_MAGIC) + 1;
1194 if (len < magic_len) {
1195 ath11k_err(ab, "failed to find magic value in %s, file too short: %zu\n",
1196 filepath, len);
1197 ret = -EINVAL;
1198 goto err;
1199 }
1200
1201 if (memcmp(data, ATH11K_BOARD_MAGIC, magic_len)) {
1202 ath11k_err(ab, "found invalid board magic\n");
1203 ret = -EINVAL;
1204 goto err;
1205 }
1206
1207 /* magic is padded to 4 bytes */
1208 magic_len = ALIGN(magic_len, 4);
1209 if (len < magic_len) {
1210 ath11k_err(ab, "failed: %s too small to contain board data, len: %zu\n",
1211 filepath, len);
1212 ret = -EINVAL;
1213 goto err;
1214 }
1215
1216 data += magic_len;
1217 len -= magic_len;
1218
1219 while (len > sizeof(struct ath11k_fw_ie)) {
1220 hdr = (struct ath11k_fw_ie *)data;
1221 ie_id = le32_to_cpu(hdr->id);
1222 ie_len = le32_to_cpu(hdr->len);
1223
1224 len -= sizeof(*hdr);
1225 data = hdr->data;
1226
1227 if (len < ALIGN(ie_len, 4)) {
1228 ath11k_err(ab, "invalid length for board ie_id %d ie_len %zu len %zu\n",
1229 ie_id, ie_len, len);
1230 ret = -EINVAL;
1231 goto err;
1232 }
1233
1234 if (ie_id == ie_id_match) {
1235 ret = ath11k_core_parse_bd_ie_board(ab, bd, data,
1236 ie_len,
1237 boardname,
1238 ie_id_match,
1239 name_id,
1240 data_id);
1241 if (ret == -ENOENT)
1242 /* no match found, continue */
1243 goto next;
1244 else if (ret)
1245 /* there was an error, bail out */
1246 goto err;
1247 /* either found or error, so stop searching */
1248 goto out;
1249 }
1250 next:
1251 /* jump over the padding */
1252 ie_len = ALIGN(ie_len, 4);
1253
1254 len -= ie_len;
1255 data += ie_len;
1256 }
1257
1258 out:
1259 if (!bd->data || !bd->len) {
1260 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1261 "failed to fetch %s for %s from %s\n",
1262 ath11k_bd_ie_type_str(ie_id_match),
1263 boardname, filepath);
1264 ret = -ENODATA;
1265 goto err;
1266 }
1267
1268 return 0;
1269
1270 err:
1271 ath11k_core_free_bdf(ab, bd);
1272 return ret;
1273 }
1274
ath11k_core_fetch_board_data_api_1(struct ath11k_base * ab,struct ath11k_board_data * bd,const char * name)1275 int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab,
1276 struct ath11k_board_data *bd,
1277 const char *name)
1278 {
1279 bd->fw = ath11k_core_firmware_request(ab, name);
1280
1281 if (IS_ERR(bd->fw))
1282 return PTR_ERR(bd->fw);
1283
1284 bd->data = bd->fw->data;
1285 bd->len = bd->fw->size;
1286
1287 return 0;
1288 }
1289
1290 #define BOARD_NAME_SIZE 200
ath11k_core_fetch_bdf(struct ath11k_base * ab,struct ath11k_board_data * bd)1291 int ath11k_core_fetch_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd)
1292 {
1293 char boardname[BOARD_NAME_SIZE], fallback_boardname[BOARD_NAME_SIZE];
1294 char *filename, filepath[100];
1295 int ret;
1296
1297 filename = ATH11K_BOARD_API2_FILE;
1298
1299 ret = ath11k_core_create_board_name(ab, boardname, sizeof(boardname));
1300 if (ret) {
1301 ath11k_err(ab, "failed to create board name: %d", ret);
1302 return ret;
1303 }
1304
1305 ab->bd_api = 2;
1306 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname,
1307 ATH11K_BD_IE_BOARD,
1308 ATH11K_BD_IE_BOARD_NAME,
1309 ATH11K_BD_IE_BOARD_DATA);
1310 if (!ret)
1311 goto success;
1312
1313 ret = ath11k_core_create_fallback_board_name(ab, fallback_boardname,
1314 sizeof(fallback_boardname));
1315 if (ret) {
1316 ath11k_err(ab, "failed to create fallback board name: %d", ret);
1317 return ret;
1318 }
1319
1320 ret = ath11k_core_fetch_board_data_api_n(ab, bd, fallback_boardname,
1321 ATH11K_BD_IE_BOARD,
1322 ATH11K_BD_IE_BOARD_NAME,
1323 ATH11K_BD_IE_BOARD_DATA);
1324 if (!ret)
1325 goto success;
1326
1327 ab->bd_api = 1;
1328 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_DEFAULT_BOARD_FILE);
1329 if (ret) {
1330 ath11k_core_create_firmware_path(ab, filename,
1331 filepath, sizeof(filepath));
1332 ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1333 boardname, filepath);
1334 if (memcmp(boardname, fallback_boardname, strlen(boardname)))
1335 ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1336 fallback_boardname, filepath);
1337
1338 ath11k_err(ab, "failed to fetch board.bin from %s\n",
1339 ab->hw_params.fw.dir);
1340 return ret;
1341 }
1342
1343 success:
1344 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board api %d\n", ab->bd_api);
1345 return 0;
1346 }
1347
ath11k_core_fetch_regdb(struct ath11k_base * ab,struct ath11k_board_data * bd)1348 int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd)
1349 {
1350 char boardname[BOARD_NAME_SIZE], default_boardname[BOARD_NAME_SIZE];
1351 int ret;
1352
1353 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE);
1354 if (ret) {
1355 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1356 "failed to create board name for regdb: %d", ret);
1357 goto exit;
1358 }
1359
1360 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname,
1361 ATH11K_BD_IE_REGDB,
1362 ATH11K_BD_IE_REGDB_NAME,
1363 ATH11K_BD_IE_REGDB_DATA);
1364 if (!ret)
1365 goto exit;
1366
1367 ret = ath11k_core_create_bus_type_board_name(ab, default_boardname,
1368 BOARD_NAME_SIZE);
1369 if (ret) {
1370 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1371 "failed to create default board name for regdb: %d", ret);
1372 goto exit;
1373 }
1374
1375 ret = ath11k_core_fetch_board_data_api_n(ab, bd, default_boardname,
1376 ATH11K_BD_IE_REGDB,
1377 ATH11K_BD_IE_REGDB_NAME,
1378 ATH11K_BD_IE_REGDB_DATA);
1379 if (!ret)
1380 goto exit;
1381
1382 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_REGDB_FILE_NAME);
1383 if (ret)
1384 ath11k_dbg(ab, ATH11K_DBG_BOOT, "failed to fetch %s from %s\n",
1385 ATH11K_REGDB_FILE_NAME, ab->hw_params.fw.dir);
1386
1387 exit:
1388 if (!ret)
1389 ath11k_dbg(ab, ATH11K_DBG_BOOT, "fetched regdb\n");
1390
1391 return ret;
1392 }
1393
ath11k_core_stop(struct ath11k_base * ab)1394 static void ath11k_core_stop(struct ath11k_base *ab)
1395 {
1396 if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags))
1397 ath11k_qmi_firmware_stop(ab);
1398
1399 ath11k_hif_stop(ab);
1400 ath11k_wmi_detach(ab);
1401 ath11k_dp_pdev_reo_cleanup(ab);
1402
1403 /* De-Init of components as needed */
1404 }
1405
ath11k_core_soc_create(struct ath11k_base * ab)1406 static int ath11k_core_soc_create(struct ath11k_base *ab)
1407 {
1408 int ret;
1409
1410 if (ath11k_ftm_mode) {
1411 ab->fw_mode = ATH11K_FIRMWARE_MODE_FTM;
1412 ath11k_info(ab, "Booting in factory test mode\n");
1413 }
1414
1415 ret = ath11k_qmi_init_service(ab);
1416 if (ret) {
1417 ath11k_err(ab, "failed to initialize qmi :%d\n", ret);
1418 return ret;
1419 }
1420
1421 ret = ath11k_debugfs_soc_create(ab);
1422 if (ret) {
1423 ath11k_err(ab, "failed to create ath11k debugfs\n");
1424 goto err_qmi_deinit;
1425 }
1426
1427 ret = ath11k_hif_power_up(ab);
1428 if (ret) {
1429 ath11k_err(ab, "failed to power up :%d\n", ret);
1430 goto err_debugfs_reg;
1431 }
1432
1433 return 0;
1434
1435 err_debugfs_reg:
1436 ath11k_debugfs_soc_destroy(ab);
1437 err_qmi_deinit:
1438 ath11k_qmi_deinit_service(ab);
1439 return ret;
1440 }
1441
ath11k_core_soc_destroy(struct ath11k_base * ab)1442 static void ath11k_core_soc_destroy(struct ath11k_base *ab)
1443 {
1444 ath11k_debugfs_soc_destroy(ab);
1445 ath11k_dp_free(ab);
1446 ath11k_reg_free(ab);
1447 ath11k_qmi_deinit_service(ab);
1448 }
1449
ath11k_core_pdev_create(struct ath11k_base * ab)1450 static int ath11k_core_pdev_create(struct ath11k_base *ab)
1451 {
1452 int ret;
1453
1454 ret = ath11k_debugfs_pdev_create(ab);
1455 if (ret) {
1456 ath11k_err(ab, "failed to create core pdev debugfs: %d\n", ret);
1457 return ret;
1458 }
1459
1460 ret = ath11k_dp_pdev_alloc(ab);
1461 if (ret) {
1462 ath11k_err(ab, "failed to attach DP pdev: %d\n", ret);
1463 goto err_pdev_debug;
1464 }
1465
1466 ret = ath11k_mac_register(ab);
1467 if (ret) {
1468 ath11k_err(ab, "failed register the radio with mac80211: %d\n", ret);
1469 goto err_dp_pdev_free;
1470 }
1471
1472 ret = ath11k_thermal_register(ab);
1473 if (ret) {
1474 ath11k_err(ab, "could not register thermal device: %d\n",
1475 ret);
1476 goto err_mac_unregister;
1477 }
1478
1479 ret = ath11k_spectral_init(ab);
1480 if (ret) {
1481 ath11k_err(ab, "failed to init spectral %d\n", ret);
1482 goto err_thermal_unregister;
1483 }
1484
1485 return 0;
1486
1487 err_thermal_unregister:
1488 ath11k_thermal_unregister(ab);
1489 err_mac_unregister:
1490 ath11k_mac_unregister(ab);
1491 err_dp_pdev_free:
1492 ath11k_dp_pdev_free(ab);
1493 err_pdev_debug:
1494 ath11k_debugfs_pdev_destroy(ab);
1495
1496 return ret;
1497 }
1498
ath11k_core_pdev_destroy(struct ath11k_base * ab)1499 static void ath11k_core_pdev_destroy(struct ath11k_base *ab)
1500 {
1501 ath11k_spectral_deinit(ab);
1502 ath11k_thermal_unregister(ab);
1503 ath11k_mac_unregister(ab);
1504 ath11k_hif_irq_disable(ab);
1505 ath11k_dp_pdev_free(ab);
1506 ath11k_debugfs_pdev_destroy(ab);
1507 }
1508
ath11k_core_start(struct ath11k_base * ab)1509 static int ath11k_core_start(struct ath11k_base *ab)
1510 {
1511 int ret;
1512
1513 ret = ath11k_wmi_attach(ab);
1514 if (ret) {
1515 ath11k_err(ab, "failed to attach wmi: %d\n", ret);
1516 return ret;
1517 }
1518
1519 ret = ath11k_htc_init(ab);
1520 if (ret) {
1521 ath11k_err(ab, "failed to init htc: %d\n", ret);
1522 goto err_wmi_detach;
1523 }
1524
1525 ret = ath11k_hif_start(ab);
1526 if (ret) {
1527 ath11k_err(ab, "failed to start HIF: %d\n", ret);
1528 goto err_wmi_detach;
1529 }
1530
1531 ret = ath11k_htc_wait_target(&ab->htc);
1532 if (ret) {
1533 ath11k_err(ab, "failed to connect to HTC: %d\n", ret);
1534 goto err_hif_stop;
1535 }
1536
1537 ret = ath11k_dp_htt_connect(&ab->dp);
1538 if (ret) {
1539 ath11k_err(ab, "failed to connect to HTT: %d\n", ret);
1540 goto err_hif_stop;
1541 }
1542
1543 ret = ath11k_wmi_connect(ab);
1544 if (ret) {
1545 ath11k_err(ab, "failed to connect wmi: %d\n", ret);
1546 goto err_hif_stop;
1547 }
1548
1549 ret = ath11k_htc_start(&ab->htc);
1550 if (ret) {
1551 ath11k_err(ab, "failed to start HTC: %d\n", ret);
1552 goto err_hif_stop;
1553 }
1554
1555 ret = ath11k_wmi_wait_for_service_ready(ab);
1556 if (ret) {
1557 ath11k_err(ab, "failed to receive wmi service ready event: %d\n",
1558 ret);
1559 goto err_hif_stop;
1560 }
1561
1562 ret = ath11k_mac_allocate(ab);
1563 if (ret) {
1564 ath11k_err(ab, "failed to create new hw device with mac80211 :%d\n",
1565 ret);
1566 goto err_hif_stop;
1567 }
1568
1569 ath11k_dp_pdev_pre_alloc(ab);
1570
1571 ret = ath11k_dp_pdev_reo_setup(ab);
1572 if (ret) {
1573 ath11k_err(ab, "failed to initialize reo destination rings: %d\n", ret);
1574 goto err_mac_destroy;
1575 }
1576
1577 ret = ath11k_wmi_cmd_init(ab);
1578 if (ret) {
1579 ath11k_err(ab, "failed to send wmi init cmd: %d\n", ret);
1580 goto err_reo_cleanup;
1581 }
1582
1583 ret = ath11k_wmi_wait_for_unified_ready(ab);
1584 if (ret) {
1585 ath11k_err(ab, "failed to receive wmi unified ready event: %d\n",
1586 ret);
1587 goto err_reo_cleanup;
1588 }
1589
1590 /* put hardware to DBS mode */
1591 if (ab->hw_params.single_pdev_only && ab->hw_params.num_rxmda_per_pdev > 1) {
1592 ret = ath11k_wmi_set_hw_mode(ab, WMI_HOST_HW_MODE_DBS);
1593 if (ret) {
1594 ath11k_err(ab, "failed to send dbs mode: %d\n", ret);
1595 goto err_hif_stop;
1596 }
1597 }
1598
1599 ret = ath11k_dp_tx_htt_h2t_ver_req_msg(ab);
1600 if (ret) {
1601 ath11k_err(ab, "failed to send htt version request message: %d\n",
1602 ret);
1603 goto err_reo_cleanup;
1604 }
1605
1606 return 0;
1607
1608 err_reo_cleanup:
1609 ath11k_dp_pdev_reo_cleanup(ab);
1610 err_mac_destroy:
1611 ath11k_mac_destroy(ab);
1612 err_hif_stop:
1613 ath11k_hif_stop(ab);
1614 err_wmi_detach:
1615 ath11k_wmi_detach(ab);
1616
1617 return ret;
1618 }
1619
ath11k_core_start_firmware(struct ath11k_base * ab,enum ath11k_firmware_mode mode)1620 static int ath11k_core_start_firmware(struct ath11k_base *ab,
1621 enum ath11k_firmware_mode mode)
1622 {
1623 int ret;
1624
1625 ath11k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v2,
1626 &ab->qmi.ce_cfg.shadow_reg_v2_len);
1627
1628 ret = ath11k_qmi_firmware_start(ab, mode);
1629 if (ret) {
1630 ath11k_err(ab, "failed to send firmware start: %d\n", ret);
1631 return ret;
1632 }
1633
1634 return ret;
1635 }
1636
ath11k_core_qmi_firmware_ready(struct ath11k_base * ab)1637 int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab)
1638 {
1639 int ret;
1640
1641 switch (ath11k_crypto_mode) {
1642 case ATH11K_CRYPT_MODE_SW:
1643 set_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags);
1644 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
1645 break;
1646 case ATH11K_CRYPT_MODE_HW:
1647 clear_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags);
1648 clear_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
1649 break;
1650 default:
1651 ath11k_info(ab, "invalid crypto_mode: %d\n", ath11k_crypto_mode);
1652 return -EINVAL;
1653 }
1654
1655 ret = ath11k_core_start_firmware(ab, ab->fw_mode);
1656 if (ret) {
1657 ath11k_err(ab, "failed to start firmware: %d\n", ret);
1658 return ret;
1659 }
1660
1661 ret = ath11k_ce_init_pipes(ab);
1662 if (ret) {
1663 ath11k_err(ab, "failed to initialize CE: %d\n", ret);
1664 goto err_firmware_stop;
1665 }
1666
1667 ret = ath11k_dp_alloc(ab);
1668 if (ret) {
1669 ath11k_err(ab, "failed to init DP: %d\n", ret);
1670 goto err_firmware_stop;
1671 }
1672
1673 if (ath11k_frame_mode == ATH11K_HW_TXRX_RAW)
1674 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
1675
1676 mutex_lock(&ab->core_lock);
1677 ret = ath11k_core_start(ab);
1678 if (ret) {
1679 ath11k_err(ab, "failed to start core: %d\n", ret);
1680 goto err_dp_free;
1681 }
1682
1683 ret = ath11k_core_pdev_create(ab);
1684 if (ret) {
1685 ath11k_err(ab, "failed to create pdev core: %d\n", ret);
1686 goto err_core_stop;
1687 }
1688 ath11k_hif_irq_enable(ab);
1689 mutex_unlock(&ab->core_lock);
1690
1691 return 0;
1692
1693 err_core_stop:
1694 ath11k_core_stop(ab);
1695 ath11k_mac_destroy(ab);
1696 err_dp_free:
1697 ath11k_dp_free(ab);
1698 mutex_unlock(&ab->core_lock);
1699 err_firmware_stop:
1700 ath11k_qmi_firmware_stop(ab);
1701
1702 return ret;
1703 }
1704
ath11k_core_reconfigure_on_crash(struct ath11k_base * ab)1705 static int ath11k_core_reconfigure_on_crash(struct ath11k_base *ab)
1706 {
1707 int ret;
1708
1709 mutex_lock(&ab->core_lock);
1710 ath11k_thermal_unregister(ab);
1711 ath11k_hif_irq_disable(ab);
1712 ath11k_dp_pdev_free(ab);
1713 ath11k_spectral_deinit(ab);
1714 ath11k_hif_stop(ab);
1715 ath11k_wmi_detach(ab);
1716 ath11k_dp_pdev_reo_cleanup(ab);
1717 mutex_unlock(&ab->core_lock);
1718
1719 ath11k_dp_free(ab);
1720 ath11k_hal_srng_deinit(ab);
1721
1722 ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS(ab))) - 1;
1723
1724 ret = ath11k_hal_srng_init(ab);
1725 if (ret)
1726 return ret;
1727
1728 clear_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags);
1729
1730 ret = ath11k_core_qmi_firmware_ready(ab);
1731 if (ret)
1732 goto err_hal_srng_deinit;
1733
1734 clear_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags);
1735
1736 return 0;
1737
1738 err_hal_srng_deinit:
1739 ath11k_hal_srng_deinit(ab);
1740 return ret;
1741 }
1742
ath11k_core_halt(struct ath11k * ar)1743 void ath11k_core_halt(struct ath11k *ar)
1744 {
1745 struct ath11k_base *ab = ar->ab;
1746 struct list_head *pos, *n;
1747
1748 lockdep_assert_held(&ar->conf_mutex);
1749
1750 ar->num_created_vdevs = 0;
1751 ar->allocated_vdev_map = 0;
1752
1753 ath11k_mac_scan_finish(ar);
1754 ath11k_mac_peer_cleanup_all(ar);
1755 cancel_delayed_work_sync(&ar->scan.timeout);
1756 cancel_work_sync(&ar->regd_update_work);
1757 cancel_work_sync(&ab->update_11d_work);
1758
1759 rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL);
1760 synchronize_rcu();
1761
1762 spin_lock_bh(&ar->data_lock);
1763 list_for_each_safe(pos, n, &ar->arvifs)
1764 list_del_init(pos);
1765 spin_unlock_bh(&ar->data_lock);
1766
1767 idr_init(&ar->txmgmt_idr);
1768 }
1769
ath11k_update_11d(struct work_struct * work)1770 static void ath11k_update_11d(struct work_struct *work)
1771 {
1772 struct ath11k_base *ab = container_of(work, struct ath11k_base, update_11d_work);
1773 struct ath11k *ar;
1774 struct ath11k_pdev *pdev;
1775 struct wmi_set_current_country_params set_current_param = {};
1776 int ret, i;
1777
1778 spin_lock_bh(&ab->base_lock);
1779 memcpy(&set_current_param.alpha2, &ab->new_alpha2, 2);
1780 spin_unlock_bh(&ab->base_lock);
1781
1782 ath11k_dbg(ab, ATH11K_DBG_WMI, "update 11d new cc %c%c\n",
1783 set_current_param.alpha2[0],
1784 set_current_param.alpha2[1]);
1785
1786 for (i = 0; i < ab->num_radios; i++) {
1787 pdev = &ab->pdevs[i];
1788 ar = pdev->ar;
1789
1790 memcpy(&ar->alpha2, &set_current_param.alpha2, 2);
1791 ret = ath11k_wmi_send_set_current_country_cmd(ar, &set_current_param);
1792 if (ret)
1793 ath11k_warn(ar->ab,
1794 "pdev id %d failed set current country code: %d\n",
1795 i, ret);
1796 }
1797 }
1798
ath11k_core_pre_reconfigure_recovery(struct ath11k_base * ab)1799 void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab)
1800 {
1801 struct ath11k *ar;
1802 struct ath11k_pdev *pdev;
1803 int i;
1804
1805 spin_lock_bh(&ab->base_lock);
1806 ab->stats.fw_crash_counter++;
1807 spin_unlock_bh(&ab->base_lock);
1808
1809 for (i = 0; i < ab->num_radios; i++) {
1810 pdev = &ab->pdevs[i];
1811 ar = pdev->ar;
1812 if (!ar || ar->state == ATH11K_STATE_OFF ||
1813 ar->state == ATH11K_STATE_FTM)
1814 continue;
1815
1816 ieee80211_stop_queues(ar->hw);
1817 ath11k_mac_drain_tx(ar);
1818 ar->state_11d = ATH11K_11D_IDLE;
1819 complete(&ar->completed_11d_scan);
1820 complete(&ar->scan.started);
1821 complete_all(&ar->scan.completed);
1822 complete(&ar->scan.on_channel);
1823 complete(&ar->peer_assoc_done);
1824 complete(&ar->peer_delete_done);
1825 complete(&ar->install_key_done);
1826 complete(&ar->vdev_setup_done);
1827 complete(&ar->vdev_delete_done);
1828 complete(&ar->bss_survey_done);
1829 complete(&ar->thermal.wmi_sync);
1830
1831 wake_up(&ar->dp.tx_empty_waitq);
1832 idr_for_each(&ar->txmgmt_idr,
1833 ath11k_mac_tx_mgmt_pending_free, ar);
1834 idr_destroy(&ar->txmgmt_idr);
1835 wake_up(&ar->txmgmt_empty_waitq);
1836
1837 ar->monitor_vdev_id = -1;
1838 clear_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags);
1839 clear_bit(ATH11K_FLAG_MONITOR_VDEV_CREATED, &ar->monitor_flags);
1840 }
1841
1842 wake_up(&ab->wmi_ab.tx_credits_wq);
1843 wake_up(&ab->peer_mapping_wq);
1844
1845 reinit_completion(&ab->driver_recovery);
1846 }
1847
ath11k_core_post_reconfigure_recovery(struct ath11k_base * ab)1848 static void ath11k_core_post_reconfigure_recovery(struct ath11k_base *ab)
1849 {
1850 struct ath11k *ar;
1851 struct ath11k_pdev *pdev;
1852 int i;
1853
1854 for (i = 0; i < ab->num_radios; i++) {
1855 pdev = &ab->pdevs[i];
1856 ar = pdev->ar;
1857 if (!ar || ar->state == ATH11K_STATE_OFF)
1858 continue;
1859
1860 mutex_lock(&ar->conf_mutex);
1861
1862 switch (ar->state) {
1863 case ATH11K_STATE_ON:
1864 ar->state = ATH11K_STATE_RESTARTING;
1865 ath11k_core_halt(ar);
1866 ieee80211_restart_hw(ar->hw);
1867 break;
1868 case ATH11K_STATE_OFF:
1869 ath11k_warn(ab,
1870 "cannot restart radio %d that hasn't been started\n",
1871 i);
1872 break;
1873 case ATH11K_STATE_RESTARTING:
1874 break;
1875 case ATH11K_STATE_RESTARTED:
1876 ar->state = ATH11K_STATE_WEDGED;
1877 fallthrough;
1878 case ATH11K_STATE_WEDGED:
1879 ath11k_warn(ab,
1880 "device is wedged, will not restart radio %d\n", i);
1881 break;
1882 case ATH11K_STATE_FTM:
1883 ath11k_dbg(ab, ATH11K_DBG_TESTMODE,
1884 "fw mode reset done radio %d\n", i);
1885 break;
1886 }
1887
1888 mutex_unlock(&ar->conf_mutex);
1889 }
1890 complete(&ab->driver_recovery);
1891 }
1892
ath11k_core_restart(struct work_struct * work)1893 static void ath11k_core_restart(struct work_struct *work)
1894 {
1895 struct ath11k_base *ab = container_of(work, struct ath11k_base, restart_work);
1896 int ret;
1897
1898 ret = ath11k_core_reconfigure_on_crash(ab);
1899 if (ret) {
1900 ath11k_err(ab, "failed to reconfigure driver on crash recovery\n");
1901 return;
1902 }
1903
1904 if (ab->is_reset)
1905 complete_all(&ab->reconfigure_complete);
1906
1907 if (!ab->is_reset)
1908 ath11k_core_post_reconfigure_recovery(ab);
1909 }
1910
ath11k_core_reset(struct work_struct * work)1911 static void ath11k_core_reset(struct work_struct *work)
1912 {
1913 struct ath11k_base *ab = container_of(work, struct ath11k_base, reset_work);
1914 int reset_count, fail_cont_count;
1915 long time_left;
1916
1917 if (!(test_bit(ATH11K_FLAG_REGISTERED, &ab->dev_flags))) {
1918 ath11k_warn(ab, "ignore reset dev flags 0x%lx\n", ab->dev_flags);
1919 return;
1920 }
1921
1922 /* Sometimes the recovery will fail and then the next all recovery fail,
1923 * this is to avoid infinite recovery since it can not recovery success.
1924 */
1925 fail_cont_count = atomic_read(&ab->fail_cont_count);
1926
1927 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FINAL)
1928 return;
1929
1930 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FIRST &&
1931 time_before(jiffies, ab->reset_fail_timeout))
1932 return;
1933
1934 reset_count = atomic_inc_return(&ab->reset_count);
1935
1936 if (reset_count > 1) {
1937 /* Sometimes it happened another reset worker before the previous one
1938 * completed, then the second reset worker will destroy the previous one,
1939 * thus below is to avoid that.
1940 */
1941 ath11k_warn(ab, "already resetting count %d\n", reset_count);
1942
1943 reinit_completion(&ab->reset_complete);
1944 time_left = wait_for_completion_timeout(&ab->reset_complete,
1945 ATH11K_RESET_TIMEOUT_HZ);
1946
1947 if (time_left) {
1948 ath11k_dbg(ab, ATH11K_DBG_BOOT, "to skip reset\n");
1949 atomic_dec(&ab->reset_count);
1950 return;
1951 }
1952
1953 ab->reset_fail_timeout = jiffies + ATH11K_RESET_FAIL_TIMEOUT_HZ;
1954 /* Record the continuous recovery fail count when recovery failed*/
1955 atomic_inc(&ab->fail_cont_count);
1956 }
1957
1958 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset starting\n");
1959
1960 ab->is_reset = true;
1961 atomic_set(&ab->recovery_count, 0);
1962 reinit_completion(&ab->recovery_start);
1963 atomic_set(&ab->recovery_start_count, 0);
1964
1965 ath11k_core_pre_reconfigure_recovery(ab);
1966
1967 reinit_completion(&ab->reconfigure_complete);
1968 ath11k_core_post_reconfigure_recovery(ab);
1969
1970 ath11k_dbg(ab, ATH11K_DBG_BOOT, "waiting recovery start...\n");
1971
1972 time_left = wait_for_completion_timeout(&ab->recovery_start,
1973 ATH11K_RECOVER_START_TIMEOUT_HZ);
1974
1975 ath11k_hif_power_down(ab);
1976 ath11k_hif_power_up(ab);
1977
1978 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset started\n");
1979 }
1980
ath11k_init_hw_params(struct ath11k_base * ab)1981 static int ath11k_init_hw_params(struct ath11k_base *ab)
1982 {
1983 const struct ath11k_hw_params *hw_params = NULL;
1984 int i;
1985
1986 for (i = 0; i < ARRAY_SIZE(ath11k_hw_params); i++) {
1987 hw_params = &ath11k_hw_params[i];
1988
1989 if (hw_params->hw_rev == ab->hw_rev)
1990 break;
1991 }
1992
1993 if (i == ARRAY_SIZE(ath11k_hw_params)) {
1994 ath11k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev);
1995 return -EINVAL;
1996 }
1997
1998 ab->hw_params = *hw_params;
1999
2000 ath11k_info(ab, "%s\n", ab->hw_params.name);
2001
2002 return 0;
2003 }
2004
ath11k_core_pre_init(struct ath11k_base * ab)2005 int ath11k_core_pre_init(struct ath11k_base *ab)
2006 {
2007 int ret;
2008
2009 ret = ath11k_init_hw_params(ab);
2010 if (ret) {
2011 ath11k_err(ab, "failed to get hw params: %d\n", ret);
2012 return ret;
2013 }
2014
2015 return 0;
2016 }
2017 EXPORT_SYMBOL(ath11k_core_pre_init);
2018
ath11k_core_init(struct ath11k_base * ab)2019 int ath11k_core_init(struct ath11k_base *ab)
2020 {
2021 int ret;
2022
2023 ret = ath11k_core_soc_create(ab);
2024 if (ret) {
2025 ath11k_err(ab, "failed to create soc core: %d\n", ret);
2026 return ret;
2027 }
2028
2029 return 0;
2030 }
2031 EXPORT_SYMBOL(ath11k_core_init);
2032
ath11k_core_deinit(struct ath11k_base * ab)2033 void ath11k_core_deinit(struct ath11k_base *ab)
2034 {
2035 mutex_lock(&ab->core_lock);
2036
2037 ath11k_core_pdev_destroy(ab);
2038 ath11k_core_stop(ab);
2039
2040 mutex_unlock(&ab->core_lock);
2041
2042 ath11k_hif_power_down(ab);
2043 ath11k_mac_destroy(ab);
2044 ath11k_core_soc_destroy(ab);
2045 }
2046 EXPORT_SYMBOL(ath11k_core_deinit);
2047
ath11k_core_free(struct ath11k_base * ab)2048 void ath11k_core_free(struct ath11k_base *ab)
2049 {
2050 destroy_workqueue(ab->workqueue_aux);
2051 destroy_workqueue(ab->workqueue);
2052
2053 kfree(ab);
2054 }
2055 EXPORT_SYMBOL(ath11k_core_free);
2056
ath11k_core_alloc(struct device * dev,size_t priv_size,enum ath11k_bus bus)2057 struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size,
2058 enum ath11k_bus bus)
2059 {
2060 struct ath11k_base *ab;
2061
2062 ab = kzalloc(sizeof(*ab) + priv_size, GFP_KERNEL);
2063 if (!ab)
2064 return NULL;
2065
2066 init_completion(&ab->driver_recovery);
2067
2068 ab->workqueue = create_singlethread_workqueue("ath11k_wq");
2069 if (!ab->workqueue)
2070 goto err_sc_free;
2071
2072 ab->workqueue_aux = create_singlethread_workqueue("ath11k_aux_wq");
2073 if (!ab->workqueue_aux)
2074 goto err_free_wq;
2075
2076 mutex_init(&ab->core_lock);
2077 mutex_init(&ab->tbl_mtx_lock);
2078 spin_lock_init(&ab->base_lock);
2079 mutex_init(&ab->vdev_id_11d_lock);
2080 init_completion(&ab->reset_complete);
2081 init_completion(&ab->reconfigure_complete);
2082 init_completion(&ab->recovery_start);
2083
2084 INIT_LIST_HEAD(&ab->peers);
2085 init_waitqueue_head(&ab->peer_mapping_wq);
2086 init_waitqueue_head(&ab->wmi_ab.tx_credits_wq);
2087 init_waitqueue_head(&ab->qmi.cold_boot_waitq);
2088 INIT_WORK(&ab->restart_work, ath11k_core_restart);
2089 INIT_WORK(&ab->update_11d_work, ath11k_update_11d);
2090 INIT_WORK(&ab->reset_work, ath11k_core_reset);
2091 timer_setup(&ab->rx_replenish_retry, ath11k_ce_rx_replenish_retry, 0);
2092 init_completion(&ab->htc_suspend);
2093 init_completion(&ab->wow.wakeup_completed);
2094
2095 ab->dev = dev;
2096 ab->hif.bus = bus;
2097
2098 return ab;
2099
2100 err_free_wq:
2101 destroy_workqueue(ab->workqueue);
2102 err_sc_free:
2103 kfree(ab);
2104 return NULL;
2105 }
2106 EXPORT_SYMBOL(ath11k_core_alloc);
2107
2108 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ax wireless LAN cards.");
2109 MODULE_LICENSE("Dual BSD/GPL");
2110