1 // SPDX-License-Identifier: ISC
2 /*
3  * Copyright (c) 2005-2011 Atheros Communications Inc.
4  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5  * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
6  */
7 
8 #include <linux/module.h>
9 #include <linux/firmware.h>
10 #include <linux/of.h>
11 #include <linux/property.h>
12 #include <linux/dmi.h>
13 #include <linux/ctype.h>
14 #include <linux/pm_qos.h>
15 #include <linux/nvmem-consumer.h>
16 #include <asm/byteorder.h>
17 
18 #include "core.h"
19 #include "mac.h"
20 #include "htc.h"
21 #include "hif.h"
22 #include "wmi.h"
23 #include "bmi.h"
24 #include "debug.h"
25 #include "htt.h"
26 #include "testmode.h"
27 #include "wmi-ops.h"
28 #include "coredump.h"
29 
30 unsigned int ath10k_debug_mask;
31 EXPORT_SYMBOL(ath10k_debug_mask);
32 
33 static unsigned int ath10k_cryptmode_param;
34 static bool uart_print;
35 static bool skip_otp;
36 static bool fw_diag_log;
37 
38 /* frame mode values are mapped as per enum ath10k_hw_txrx_mode */
39 unsigned int ath10k_frame_mode = ATH10K_HW_TXRX_NATIVE_WIFI;
40 
41 unsigned long ath10k_coredump_mask = BIT(ATH10K_FW_CRASH_DUMP_REGISTERS) |
42 				     BIT(ATH10K_FW_CRASH_DUMP_CE_DATA);
43 
44 /* FIXME: most of these should be readonly */
45 module_param_named(debug_mask, ath10k_debug_mask, uint, 0644);
46 module_param_named(cryptmode, ath10k_cryptmode_param, uint, 0644);
47 module_param(uart_print, bool, 0644);
48 module_param(skip_otp, bool, 0644);
49 module_param(fw_diag_log, bool, 0644);
50 module_param_named(frame_mode, ath10k_frame_mode, uint, 0644);
51 module_param_named(coredump_mask, ath10k_coredump_mask, ulong, 0444);
52 
53 MODULE_PARM_DESC(debug_mask, "Debugging mask");
54 MODULE_PARM_DESC(uart_print, "Uart target debugging");
55 MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode");
56 MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software");
57 MODULE_PARM_DESC(frame_mode,
58 		 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)");
59 MODULE_PARM_DESC(coredump_mask, "Bitfield of what to include in firmware crash file");
60 MODULE_PARM_DESC(fw_diag_log, "Diag based fw log debugging");
61 
62 static const struct ath10k_hw_params ath10k_hw_params_list[] = {
63 	{
64 		.id = QCA988X_HW_2_0_VERSION,
65 		.dev_id = QCA988X_2_0_DEVICE_ID,
66 		.bus = ATH10K_BUS_PCI,
67 		.name = "qca988x hw2.0",
68 		.patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
69 		.uart_pin = 7,
70 		.cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
71 		.otp_exe_param = 0,
72 		.channel_counters_freq_hz = 88000,
73 		.max_probe_resp_desc_thres = 0,
74 		.cal_data_len = 2116,
75 		.fw = {
76 			.dir = QCA988X_HW_2_0_FW_DIR,
77 			.board = QCA988X_HW_2_0_BOARD_DATA_FILE,
78 			.board_size = QCA988X_BOARD_DATA_SZ,
79 			.board_ext_size = QCA988X_BOARD_EXT_DATA_SZ,
80 		},
81 		.rx_desc_ops = &qca988x_rx_desc_ops,
82 		.hw_ops = &qca988x_ops,
83 		.decap_align_bytes = 4,
84 		.spectral_bin_discard = 0,
85 		.spectral_bin_offset = 0,
86 		.vht160_mcs_rx_highest = 0,
87 		.vht160_mcs_tx_highest = 0,
88 		.n_cipher_suites = 8,
89 		.ast_skid_limit = 0x10,
90 		.num_wds_entries = 0x20,
91 		.target_64bit = false,
92 		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
93 		.shadow_reg_support = false,
94 		.rri_on_ddr = false,
95 		.hw_filter_reset_required = true,
96 		.fw_diag_ce_download = false,
97 		.credit_size_workaround = false,
98 		.tx_stats_over_pktlog = true,
99 		.dynamic_sar_support = false,
100 		.hw_restart_disconnect = false,
101 		.use_fw_tx_credits = true,
102 		.delay_unmap_buffer = false,
103 	},
104 	{
105 		.id = QCA988X_HW_2_0_VERSION,
106 		.dev_id = QCA988X_2_0_DEVICE_ID_UBNT,
107 		.name = "qca988x hw2.0 ubiquiti",
108 		.patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
109 		.uart_pin = 7,
110 		.cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
111 		.otp_exe_param = 0,
112 		.channel_counters_freq_hz = 88000,
113 		.max_probe_resp_desc_thres = 0,
114 		.cal_data_len = 2116,
115 		.fw = {
116 			.dir = QCA988X_HW_2_0_FW_DIR,
117 			.board = QCA988X_HW_2_0_BOARD_DATA_FILE,
118 			.board_size = QCA988X_BOARD_DATA_SZ,
119 			.board_ext_size = QCA988X_BOARD_EXT_DATA_SZ,
120 		},
121 		.rx_desc_ops = &qca988x_rx_desc_ops,
122 		.hw_ops = &qca988x_ops,
123 		.decap_align_bytes = 4,
124 		.spectral_bin_discard = 0,
125 		.spectral_bin_offset = 0,
126 		.vht160_mcs_rx_highest = 0,
127 		.vht160_mcs_tx_highest = 0,
128 		.n_cipher_suites = 8,
129 		.ast_skid_limit = 0x10,
130 		.num_wds_entries = 0x20,
131 		.target_64bit = false,
132 		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
133 		.shadow_reg_support = false,
134 		.rri_on_ddr = false,
135 		.hw_filter_reset_required = true,
136 		.fw_diag_ce_download = false,
137 		.credit_size_workaround = false,
138 		.tx_stats_over_pktlog = true,
139 		.dynamic_sar_support = false,
140 		.hw_restart_disconnect = false,
141 		.use_fw_tx_credits = true,
142 		.delay_unmap_buffer = false,
143 	},
144 	{
145 		.id = QCA9887_HW_1_0_VERSION,
146 		.dev_id = QCA9887_1_0_DEVICE_ID,
147 		.bus = ATH10K_BUS_PCI,
148 		.name = "qca9887 hw1.0",
149 		.patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR,
150 		.uart_pin = 7,
151 		.cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
152 		.otp_exe_param = 0,
153 		.channel_counters_freq_hz = 88000,
154 		.max_probe_resp_desc_thres = 0,
155 		.cal_data_len = 2116,
156 		.fw = {
157 			.dir = QCA9887_HW_1_0_FW_DIR,
158 			.board = QCA9887_HW_1_0_BOARD_DATA_FILE,
159 			.board_size = QCA9887_BOARD_DATA_SZ,
160 			.board_ext_size = QCA9887_BOARD_EXT_DATA_SZ,
161 		},
162 		.rx_desc_ops = &qca988x_rx_desc_ops,
163 		.hw_ops = &qca988x_ops,
164 		.decap_align_bytes = 4,
165 		.spectral_bin_discard = 0,
166 		.spectral_bin_offset = 0,
167 		.vht160_mcs_rx_highest = 0,
168 		.vht160_mcs_tx_highest = 0,
169 		.n_cipher_suites = 8,
170 		.ast_skid_limit = 0x10,
171 		.num_wds_entries = 0x20,
172 		.target_64bit = false,
173 		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
174 		.shadow_reg_support = false,
175 		.rri_on_ddr = false,
176 		.hw_filter_reset_required = true,
177 		.fw_diag_ce_download = false,
178 		.credit_size_workaround = false,
179 		.tx_stats_over_pktlog = false,
180 		.dynamic_sar_support = false,
181 		.hw_restart_disconnect = false,
182 		.use_fw_tx_credits = true,
183 		.delay_unmap_buffer = false,
184 	},
185 	{
186 		.id = QCA6174_HW_3_2_VERSION,
187 		.dev_id = QCA6174_3_2_DEVICE_ID,
188 		.bus = ATH10K_BUS_SDIO,
189 		.name = "qca6174 hw3.2 sdio",
190 		.patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
191 		.uart_pin = 19,
192 		.otp_exe_param = 0,
193 		.channel_counters_freq_hz = 88000,
194 		.max_probe_resp_desc_thres = 0,
195 		.cal_data_len = 0,
196 		.fw = {
197 			.dir = QCA6174_HW_3_0_FW_DIR,
198 			.board = QCA6174_HW_3_0_BOARD_DATA_FILE,
199 			.board_size = QCA6174_BOARD_DATA_SZ,
200 			.board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
201 		},
202 		.rx_desc_ops = &qca988x_rx_desc_ops,
203 		.hw_ops = &qca6174_sdio_ops,
204 		.hw_clk = qca6174_clk,
205 		.target_cpu_freq = 176000000,
206 		.decap_align_bytes = 4,
207 		.n_cipher_suites = 8,
208 		.num_peers = 10,
209 		.ast_skid_limit = 0x10,
210 		.num_wds_entries = 0x20,
211 		.uart_pin_workaround = true,
212 		.tx_stats_over_pktlog = false,
213 		.credit_size_workaround = false,
214 		.bmi_large_size_download = true,
215 		.supports_peer_stats_info = true,
216 		.dynamic_sar_support = true,
217 		.hw_restart_disconnect = false,
218 		.use_fw_tx_credits = true,
219 		.delay_unmap_buffer = false,
220 	},
221 	{
222 		.id = QCA6174_HW_2_1_VERSION,
223 		.dev_id = QCA6164_2_1_DEVICE_ID,
224 		.bus = ATH10K_BUS_PCI,
225 		.name = "qca6164 hw2.1",
226 		.patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
227 		.uart_pin = 6,
228 		.otp_exe_param = 0,
229 		.channel_counters_freq_hz = 88000,
230 		.max_probe_resp_desc_thres = 0,
231 		.cal_data_len = 8124,
232 		.fw = {
233 			.dir = QCA6174_HW_2_1_FW_DIR,
234 			.board = QCA6174_HW_2_1_BOARD_DATA_FILE,
235 			.board_size = QCA6174_BOARD_DATA_SZ,
236 			.board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
237 		},
238 		.rx_desc_ops = &qca988x_rx_desc_ops,
239 		.hw_ops = &qca988x_ops,
240 		.decap_align_bytes = 4,
241 		.spectral_bin_discard = 0,
242 		.spectral_bin_offset = 0,
243 		.vht160_mcs_rx_highest = 0,
244 		.vht160_mcs_tx_highest = 0,
245 		.n_cipher_suites = 8,
246 		.ast_skid_limit = 0x10,
247 		.num_wds_entries = 0x20,
248 		.target_64bit = false,
249 		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
250 		.shadow_reg_support = false,
251 		.rri_on_ddr = false,
252 		.hw_filter_reset_required = true,
253 		.fw_diag_ce_download = false,
254 		.credit_size_workaround = false,
255 		.tx_stats_over_pktlog = false,
256 		.dynamic_sar_support = false,
257 		.hw_restart_disconnect = false,
258 		.use_fw_tx_credits = true,
259 		.delay_unmap_buffer = false,
260 	},
261 	{
262 		.id = QCA6174_HW_2_1_VERSION,
263 		.dev_id = QCA6174_2_1_DEVICE_ID,
264 		.bus = ATH10K_BUS_PCI,
265 		.name = "qca6174 hw2.1",
266 		.patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
267 		.uart_pin = 6,
268 		.otp_exe_param = 0,
269 		.channel_counters_freq_hz = 88000,
270 		.max_probe_resp_desc_thres = 0,
271 		.cal_data_len = 8124,
272 		.fw = {
273 			.dir = QCA6174_HW_2_1_FW_DIR,
274 			.board = QCA6174_HW_2_1_BOARD_DATA_FILE,
275 			.board_size = QCA6174_BOARD_DATA_SZ,
276 			.board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
277 		},
278 		.rx_desc_ops = &qca988x_rx_desc_ops,
279 		.hw_ops = &qca988x_ops,
280 		.decap_align_bytes = 4,
281 		.spectral_bin_discard = 0,
282 		.spectral_bin_offset = 0,
283 		.vht160_mcs_rx_highest = 0,
284 		.vht160_mcs_tx_highest = 0,
285 		.n_cipher_suites = 8,
286 		.ast_skid_limit = 0x10,
287 		.num_wds_entries = 0x20,
288 		.target_64bit = false,
289 		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
290 		.shadow_reg_support = false,
291 		.rri_on_ddr = false,
292 		.hw_filter_reset_required = true,
293 		.fw_diag_ce_download = false,
294 		.credit_size_workaround = false,
295 		.tx_stats_over_pktlog = false,
296 		.dynamic_sar_support = false,
297 		.hw_restart_disconnect = false,
298 		.use_fw_tx_credits = true,
299 		.delay_unmap_buffer = false,
300 	},
301 	{
302 		.id = QCA6174_HW_3_0_VERSION,
303 		.dev_id = QCA6174_2_1_DEVICE_ID,
304 		.bus = ATH10K_BUS_PCI,
305 		.name = "qca6174 hw3.0",
306 		.patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
307 		.uart_pin = 6,
308 		.otp_exe_param = 0,
309 		.channel_counters_freq_hz = 88000,
310 		.max_probe_resp_desc_thres = 0,
311 		.cal_data_len = 8124,
312 		.fw = {
313 			.dir = QCA6174_HW_3_0_FW_DIR,
314 			.board = QCA6174_HW_3_0_BOARD_DATA_FILE,
315 			.board_size = QCA6174_BOARD_DATA_SZ,
316 			.board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
317 		},
318 		.rx_desc_ops = &qca988x_rx_desc_ops,
319 		.hw_ops = &qca988x_ops,
320 		.decap_align_bytes = 4,
321 		.spectral_bin_discard = 0,
322 		.spectral_bin_offset = 0,
323 		.vht160_mcs_rx_highest = 0,
324 		.vht160_mcs_tx_highest = 0,
325 		.n_cipher_suites = 8,
326 		.ast_skid_limit = 0x10,
327 		.num_wds_entries = 0x20,
328 		.target_64bit = false,
329 		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
330 		.shadow_reg_support = false,
331 		.rri_on_ddr = false,
332 		.hw_filter_reset_required = true,
333 		.fw_diag_ce_download = false,
334 		.credit_size_workaround = false,
335 		.tx_stats_over_pktlog = false,
336 		.dynamic_sar_support = false,
337 		.hw_restart_disconnect = false,
338 		.use_fw_tx_credits = true,
339 		.delay_unmap_buffer = false,
340 	},
341 	{
342 		.id = QCA6174_HW_3_2_VERSION,
343 		.dev_id = QCA6174_2_1_DEVICE_ID,
344 		.bus = ATH10K_BUS_PCI,
345 		.name = "qca6174 hw3.2",
346 		.patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
347 		.uart_pin = 6,
348 		.otp_exe_param = 0,
349 		.channel_counters_freq_hz = 88000,
350 		.max_probe_resp_desc_thres = 0,
351 		.cal_data_len = 8124,
352 		.fw = {
353 			/* uses same binaries as hw3.0 */
354 			.dir = QCA6174_HW_3_0_FW_DIR,
355 			.board = QCA6174_HW_3_0_BOARD_DATA_FILE,
356 			.board_size = QCA6174_BOARD_DATA_SZ,
357 			.board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
358 		},
359 		.rx_desc_ops = &qca988x_rx_desc_ops,
360 		.hw_ops = &qca6174_ops,
361 		.hw_clk = qca6174_clk,
362 		.target_cpu_freq = 176000000,
363 		.decap_align_bytes = 4,
364 		.spectral_bin_discard = 0,
365 		.spectral_bin_offset = 0,
366 		.vht160_mcs_rx_highest = 0,
367 		.vht160_mcs_tx_highest = 0,
368 		.n_cipher_suites = 8,
369 		.ast_skid_limit = 0x10,
370 		.num_wds_entries = 0x20,
371 		.target_64bit = false,
372 		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
373 		.shadow_reg_support = false,
374 		.rri_on_ddr = false,
375 		.hw_filter_reset_required = true,
376 		.fw_diag_ce_download = true,
377 		.credit_size_workaround = false,
378 		.tx_stats_over_pktlog = false,
379 		.supports_peer_stats_info = true,
380 		.dynamic_sar_support = true,
381 		.hw_restart_disconnect = false,
382 		.use_fw_tx_credits = true,
383 		.delay_unmap_buffer = false,
384 	},
385 	{
386 		.id = QCA99X0_HW_2_0_DEV_VERSION,
387 		.dev_id = QCA99X0_2_0_DEVICE_ID,
388 		.bus = ATH10K_BUS_PCI,
389 		.name = "qca99x0 hw2.0",
390 		.patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR,
391 		.uart_pin = 7,
392 		.otp_exe_param = 0x00000700,
393 		.continuous_frag_desc = true,
394 		.cck_rate_map_rev2 = true,
395 		.channel_counters_freq_hz = 150000,
396 		.max_probe_resp_desc_thres = 24,
397 		.tx_chain_mask = 0xf,
398 		.rx_chain_mask = 0xf,
399 		.max_spatial_stream = 4,
400 		.cal_data_len = 12064,
401 		.fw = {
402 			.dir = QCA99X0_HW_2_0_FW_DIR,
403 			.board = QCA99X0_HW_2_0_BOARD_DATA_FILE,
404 			.board_size = QCA99X0_BOARD_DATA_SZ,
405 			.board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
406 		},
407 		.sw_decrypt_mcast_mgmt = true,
408 		.rx_desc_ops = &qca99x0_rx_desc_ops,
409 		.hw_ops = &qca99x0_ops,
410 		.decap_align_bytes = 1,
411 		.spectral_bin_discard = 4,
412 		.spectral_bin_offset = 0,
413 		.vht160_mcs_rx_highest = 0,
414 		.vht160_mcs_tx_highest = 0,
415 		.n_cipher_suites = 11,
416 		.ast_skid_limit = 0x10,
417 		.num_wds_entries = 0x20,
418 		.target_64bit = false,
419 		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
420 		.shadow_reg_support = false,
421 		.rri_on_ddr = false,
422 		.hw_filter_reset_required = true,
423 		.fw_diag_ce_download = false,
424 		.credit_size_workaround = false,
425 		.tx_stats_over_pktlog = false,
426 		.dynamic_sar_support = false,
427 		.hw_restart_disconnect = false,
428 		.use_fw_tx_credits = true,
429 		.delay_unmap_buffer = false,
430 	},
431 	{
432 		.id = QCA9984_HW_1_0_DEV_VERSION,
433 		.dev_id = QCA9984_1_0_DEVICE_ID,
434 		.bus = ATH10K_BUS_PCI,
435 		.name = "qca9984/qca9994 hw1.0",
436 		.patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR,
437 		.uart_pin = 7,
438 		.cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
439 		.otp_exe_param = 0x00000700,
440 		.continuous_frag_desc = true,
441 		.cck_rate_map_rev2 = true,
442 		.channel_counters_freq_hz = 150000,
443 		.max_probe_resp_desc_thres = 24,
444 		.tx_chain_mask = 0xf,
445 		.rx_chain_mask = 0xf,
446 		.max_spatial_stream = 4,
447 		.cal_data_len = 12064,
448 		.fw = {
449 			.dir = QCA9984_HW_1_0_FW_DIR,
450 			.board = QCA9984_HW_1_0_BOARD_DATA_FILE,
451 			.eboard = QCA9984_HW_1_0_EBOARD_DATA_FILE,
452 			.board_size = QCA99X0_BOARD_DATA_SZ,
453 			.board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
454 			.ext_board_size = QCA99X0_EXT_BOARD_DATA_SZ,
455 		},
456 		.sw_decrypt_mcast_mgmt = true,
457 		.rx_desc_ops = &qca99x0_rx_desc_ops,
458 		.hw_ops = &qca99x0_ops,
459 		.decap_align_bytes = 1,
460 		.spectral_bin_discard = 12,
461 		.spectral_bin_offset = 8,
462 
463 		/* Can do only 2x2 VHT160 or 80+80. 1560Mbps is 4x4 80Mhz
464 		 * or 2x2 160Mhz, long-guard-interval.
465 		 */
466 		.vht160_mcs_rx_highest = 1560,
467 		.vht160_mcs_tx_highest = 1560,
468 		.n_cipher_suites = 11,
469 		.ast_skid_limit = 0x10,
470 		.num_wds_entries = 0x20,
471 		.target_64bit = false,
472 		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
473 		.shadow_reg_support = false,
474 		.rri_on_ddr = false,
475 		.hw_filter_reset_required = true,
476 		.fw_diag_ce_download = false,
477 		.credit_size_workaround = false,
478 		.tx_stats_over_pktlog = false,
479 		.dynamic_sar_support = false,
480 		.hw_restart_disconnect = false,
481 		.use_fw_tx_credits = true,
482 		.delay_unmap_buffer = false,
483 	},
484 	{
485 		.id = QCA9888_HW_2_0_DEV_VERSION,
486 		.dev_id = QCA9888_2_0_DEVICE_ID,
487 		.bus = ATH10K_BUS_PCI,
488 		.name = "qca9888 hw2.0",
489 		.patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR,
490 		.uart_pin = 7,
491 		.cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
492 		.otp_exe_param = 0x00000700,
493 		.continuous_frag_desc = true,
494 		.channel_counters_freq_hz = 150000,
495 		.max_probe_resp_desc_thres = 24,
496 		.tx_chain_mask = 3,
497 		.rx_chain_mask = 3,
498 		.max_spatial_stream = 2,
499 		.cal_data_len = 12064,
500 		.fw = {
501 			.dir = QCA9888_HW_2_0_FW_DIR,
502 			.board = QCA9888_HW_2_0_BOARD_DATA_FILE,
503 			.board_size = QCA99X0_BOARD_DATA_SZ,
504 			.board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
505 		},
506 		.sw_decrypt_mcast_mgmt = true,
507 		.rx_desc_ops = &qca99x0_rx_desc_ops,
508 		.hw_ops = &qca99x0_ops,
509 		.decap_align_bytes = 1,
510 		.spectral_bin_discard = 12,
511 		.spectral_bin_offset = 8,
512 
513 		/* Can do only 1x1 VHT160 or 80+80. 780Mbps is 2x2 80Mhz or
514 		 * 1x1 160Mhz, long-guard-interval.
515 		 */
516 		.vht160_mcs_rx_highest = 780,
517 		.vht160_mcs_tx_highest = 780,
518 		.n_cipher_suites = 11,
519 		.ast_skid_limit = 0x10,
520 		.num_wds_entries = 0x20,
521 		.target_64bit = false,
522 		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
523 		.shadow_reg_support = false,
524 		.rri_on_ddr = false,
525 		.hw_filter_reset_required = true,
526 		.fw_diag_ce_download = false,
527 		.credit_size_workaround = false,
528 		.tx_stats_over_pktlog = false,
529 		.dynamic_sar_support = false,
530 		.hw_restart_disconnect = false,
531 		.use_fw_tx_credits = true,
532 		.delay_unmap_buffer = false,
533 	},
534 	{
535 		.id = QCA9377_HW_1_0_DEV_VERSION,
536 		.dev_id = QCA9377_1_0_DEVICE_ID,
537 		.bus = ATH10K_BUS_PCI,
538 		.name = "qca9377 hw1.0",
539 		.patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
540 		.uart_pin = 6,
541 		.otp_exe_param = 0,
542 		.channel_counters_freq_hz = 88000,
543 		.max_probe_resp_desc_thres = 0,
544 		.cal_data_len = 8124,
545 		.fw = {
546 			.dir = QCA9377_HW_1_0_FW_DIR,
547 			.board = QCA9377_HW_1_0_BOARD_DATA_FILE,
548 			.board_size = QCA9377_BOARD_DATA_SZ,
549 			.board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
550 		},
551 		.rx_desc_ops = &qca988x_rx_desc_ops,
552 		.hw_ops = &qca988x_ops,
553 		.decap_align_bytes = 4,
554 		.spectral_bin_discard = 0,
555 		.spectral_bin_offset = 0,
556 		.vht160_mcs_rx_highest = 0,
557 		.vht160_mcs_tx_highest = 0,
558 		.n_cipher_suites = 8,
559 		.ast_skid_limit = 0x10,
560 		.num_wds_entries = 0x20,
561 		.target_64bit = false,
562 		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
563 		.shadow_reg_support = false,
564 		.rri_on_ddr = false,
565 		.hw_filter_reset_required = true,
566 		.fw_diag_ce_download = false,
567 		.credit_size_workaround = false,
568 		.tx_stats_over_pktlog = false,
569 		.dynamic_sar_support = false,
570 		.hw_restart_disconnect = false,
571 		.use_fw_tx_credits = true,
572 		.delay_unmap_buffer = false,
573 	},
574 	{
575 		.id = QCA9377_HW_1_1_DEV_VERSION,
576 		.dev_id = QCA9377_1_0_DEVICE_ID,
577 		.bus = ATH10K_BUS_PCI,
578 		.name = "qca9377 hw1.1",
579 		.patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
580 		.uart_pin = 6,
581 		.otp_exe_param = 0,
582 		.channel_counters_freq_hz = 88000,
583 		.max_probe_resp_desc_thres = 0,
584 		.cal_data_len = 8124,
585 		.fw = {
586 			.dir = QCA9377_HW_1_0_FW_DIR,
587 			.board = QCA9377_HW_1_0_BOARD_DATA_FILE,
588 			.board_size = QCA9377_BOARD_DATA_SZ,
589 			.board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
590 		},
591 		.rx_desc_ops = &qca988x_rx_desc_ops,
592 		.hw_ops = &qca6174_ops,
593 		.hw_clk = qca6174_clk,
594 		.target_cpu_freq = 176000000,
595 		.decap_align_bytes = 4,
596 		.spectral_bin_discard = 0,
597 		.spectral_bin_offset = 0,
598 		.vht160_mcs_rx_highest = 0,
599 		.vht160_mcs_tx_highest = 0,
600 		.n_cipher_suites = 8,
601 		.ast_skid_limit = 0x10,
602 		.num_wds_entries = 0x20,
603 		.target_64bit = false,
604 		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
605 		.shadow_reg_support = false,
606 		.rri_on_ddr = false,
607 		.hw_filter_reset_required = true,
608 		.fw_diag_ce_download = true,
609 		.credit_size_workaround = false,
610 		.tx_stats_over_pktlog = false,
611 		.dynamic_sar_support = false,
612 		.hw_restart_disconnect = false,
613 		.use_fw_tx_credits = true,
614 		.delay_unmap_buffer = false,
615 	},
616 	{
617 		.id = QCA9377_HW_1_1_DEV_VERSION,
618 		.dev_id = QCA9377_1_0_DEVICE_ID,
619 		.bus = ATH10K_BUS_SDIO,
620 		.name = "qca9377 hw1.1 sdio",
621 		.patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
622 		.uart_pin = 19,
623 		.otp_exe_param = 0,
624 		.channel_counters_freq_hz = 88000,
625 		.max_probe_resp_desc_thres = 0,
626 		.cal_data_len = 8124,
627 		.fw = {
628 			.dir = QCA9377_HW_1_0_FW_DIR,
629 			.board = QCA9377_HW_1_0_BOARD_DATA_FILE,
630 			.board_size = QCA9377_BOARD_DATA_SZ,
631 			.board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
632 		},
633 		.rx_desc_ops = &qca988x_rx_desc_ops,
634 		.hw_ops = &qca6174_ops,
635 		.hw_clk = qca6174_clk,
636 		.target_cpu_freq = 176000000,
637 		.decap_align_bytes = 4,
638 		.n_cipher_suites = 8,
639 		.num_peers = TARGET_QCA9377_HL_NUM_PEERS,
640 		.ast_skid_limit = 0x10,
641 		.num_wds_entries = 0x20,
642 		.uart_pin_workaround = true,
643 		.credit_size_workaround = true,
644 		.dynamic_sar_support = false,
645 		.hw_restart_disconnect = false,
646 		.use_fw_tx_credits = true,
647 		.delay_unmap_buffer = false,
648 	},
649 	{
650 		.id = QCA4019_HW_1_0_DEV_VERSION,
651 		.dev_id = 0,
652 		.bus = ATH10K_BUS_AHB,
653 		.name = "qca4019 hw1.0",
654 		.patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR,
655 		.uart_pin = 7,
656 		.cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
657 		.otp_exe_param = 0x0010000,
658 		.continuous_frag_desc = true,
659 		.cck_rate_map_rev2 = true,
660 		.channel_counters_freq_hz = 125000,
661 		.max_probe_resp_desc_thres = 24,
662 		.tx_chain_mask = 0x3,
663 		.rx_chain_mask = 0x3,
664 		.max_spatial_stream = 2,
665 		.cal_data_len = 12064,
666 		.fw = {
667 			.dir = QCA4019_HW_1_0_FW_DIR,
668 			.board = QCA4019_HW_1_0_BOARD_DATA_FILE,
669 			.board_size = QCA4019_BOARD_DATA_SZ,
670 			.board_ext_size = QCA4019_BOARD_EXT_DATA_SZ,
671 		},
672 		.sw_decrypt_mcast_mgmt = true,
673 		.rx_desc_ops = &qca99x0_rx_desc_ops,
674 		.hw_ops = &qca99x0_ops,
675 		.decap_align_bytes = 1,
676 		.spectral_bin_discard = 4,
677 		.spectral_bin_offset = 0,
678 		.vht160_mcs_rx_highest = 0,
679 		.vht160_mcs_tx_highest = 0,
680 		.n_cipher_suites = 11,
681 		.ast_skid_limit = 0x10,
682 		.num_wds_entries = 0x20,
683 		.target_64bit = false,
684 		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
685 		.shadow_reg_support = false,
686 		.rri_on_ddr = false,
687 		.hw_filter_reset_required = true,
688 		.fw_diag_ce_download = false,
689 		.credit_size_workaround = false,
690 		.tx_stats_over_pktlog = false,
691 		.dynamic_sar_support = false,
692 		.hw_restart_disconnect = false,
693 		.use_fw_tx_credits = true,
694 		.delay_unmap_buffer = false,
695 	},
696 	{
697 		.id = WCN3990_HW_1_0_DEV_VERSION,
698 		.dev_id = 0,
699 		.bus = ATH10K_BUS_SNOC,
700 		.name = "wcn3990 hw1.0",
701 		.continuous_frag_desc = true,
702 		.tx_chain_mask = 0x7,
703 		.rx_chain_mask = 0x7,
704 		.max_spatial_stream = 4,
705 		.fw = {
706 			.dir = WCN3990_HW_1_0_FW_DIR,
707 			.board = WCN3990_HW_1_0_BOARD_DATA_FILE,
708 			.board_size = WCN3990_BOARD_DATA_SZ,
709 			.board_ext_size = WCN3990_BOARD_EXT_DATA_SZ,
710 		},
711 		.sw_decrypt_mcast_mgmt = true,
712 		.rx_desc_ops = &wcn3990_rx_desc_ops,
713 		.hw_ops = &wcn3990_ops,
714 		.decap_align_bytes = 1,
715 		.num_peers = TARGET_HL_TLV_NUM_PEERS,
716 		.n_cipher_suites = 11,
717 		.ast_skid_limit = TARGET_HL_TLV_AST_SKID_LIMIT,
718 		.num_wds_entries = TARGET_HL_TLV_NUM_WDS_ENTRIES,
719 		.target_64bit = true,
720 		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC,
721 		.shadow_reg_support = true,
722 		.rri_on_ddr = true,
723 		.hw_filter_reset_required = false,
724 		.fw_diag_ce_download = false,
725 		.credit_size_workaround = false,
726 		.tx_stats_over_pktlog = false,
727 		.dynamic_sar_support = true,
728 		.hw_restart_disconnect = true,
729 		.use_fw_tx_credits = false,
730 		.delay_unmap_buffer = true,
731 	},
732 };
733 
734 static const char *const ath10k_core_fw_feature_str[] = {
735 	[ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx",
736 	[ATH10K_FW_FEATURE_WMI_10X] = "wmi-10.x",
737 	[ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX] = "has-wmi-mgmt-tx",
738 	[ATH10K_FW_FEATURE_NO_P2P] = "no-p2p",
739 	[ATH10K_FW_FEATURE_WMI_10_2] = "wmi-10.2",
740 	[ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT] = "multi-vif-ps",
741 	[ATH10K_FW_FEATURE_WOWLAN_SUPPORT] = "wowlan",
742 	[ATH10K_FW_FEATURE_IGNORE_OTP_RESULT] = "ignore-otp",
743 	[ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING] = "no-4addr-pad",
744 	[ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init",
745 	[ATH10K_FW_FEATURE_RAW_MODE_SUPPORT] = "raw-mode",
746 	[ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA] = "adaptive-cca",
747 	[ATH10K_FW_FEATURE_MFP_SUPPORT] = "mfp",
748 	[ATH10K_FW_FEATURE_PEER_FLOW_CONTROL] = "peer-flow-ctrl",
749 	[ATH10K_FW_FEATURE_BTCOEX_PARAM] = "btcoex-param",
750 	[ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR] = "skip-null-func-war",
751 	[ATH10K_FW_FEATURE_ALLOWS_MESH_BCAST] = "allows-mesh-bcast",
752 	[ATH10K_FW_FEATURE_NO_PS] = "no-ps",
753 	[ATH10K_FW_FEATURE_MGMT_TX_BY_REF] = "mgmt-tx-by-reference",
754 	[ATH10K_FW_FEATURE_NON_BMI] = "non-bmi",
755 	[ATH10K_FW_FEATURE_SINGLE_CHAN_INFO_PER_CHANNEL] = "single-chan-info-per-channel",
756 	[ATH10K_FW_FEATURE_PEER_FIXED_RATE] = "peer-fixed-rate",
757 	[ATH10K_FW_FEATURE_IRAM_RECOVERY] = "iram-recovery",
758 };
759 
ath10k_core_get_fw_feature_str(char * buf,size_t buf_len,enum ath10k_fw_features feat)760 static unsigned int ath10k_core_get_fw_feature_str(char *buf,
761 						   size_t buf_len,
762 						   enum ath10k_fw_features feat)
763 {
764 	/* make sure that ath10k_core_fw_feature_str[] gets updated */
765 	BUILD_BUG_ON(ARRAY_SIZE(ath10k_core_fw_feature_str) !=
766 		     ATH10K_FW_FEATURE_COUNT);
767 
768 	if (feat >= ARRAY_SIZE(ath10k_core_fw_feature_str) ||
769 	    WARN_ON(!ath10k_core_fw_feature_str[feat])) {
770 		return scnprintf(buf, buf_len, "bit%d", feat);
771 	}
772 
773 	return scnprintf(buf, buf_len, "%s", ath10k_core_fw_feature_str[feat]);
774 }
775 
ath10k_core_get_fw_features_str(struct ath10k * ar,char * buf,size_t buf_len)776 void ath10k_core_get_fw_features_str(struct ath10k *ar,
777 				     char *buf,
778 				     size_t buf_len)
779 {
780 	size_t len = 0;
781 	int i;
782 
783 	for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
784 		if (test_bit(i, ar->normal_mode_fw.fw_file.fw_features)) {
785 			if (len > 0)
786 				len += scnprintf(buf + len, buf_len - len, ",");
787 
788 			len += ath10k_core_get_fw_feature_str(buf + len,
789 							      buf_len - len,
790 							      i);
791 		}
792 	}
793 }
794 
ath10k_send_suspend_complete(struct ath10k * ar)795 static void ath10k_send_suspend_complete(struct ath10k *ar)
796 {
797 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n");
798 
799 	complete(&ar->target_suspend);
800 }
801 
ath10k_init_sdio(struct ath10k * ar,enum ath10k_firmware_mode mode)802 static int ath10k_init_sdio(struct ath10k *ar, enum ath10k_firmware_mode mode)
803 {
804 	bool mtu_workaround = ar->hw_params.credit_size_workaround;
805 	int ret;
806 	u32 param = 0;
807 
808 	ret = ath10k_bmi_write32(ar, hi_mbox_io_block_sz, 256);
809 	if (ret)
810 		return ret;
811 
812 	ret = ath10k_bmi_write32(ar, hi_mbox_isr_yield_limit, 99);
813 	if (ret)
814 		return ret;
815 
816 	ret = ath10k_bmi_read32(ar, hi_acs_flags, &param);
817 	if (ret)
818 		return ret;
819 
820 	param |= HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET;
821 
822 	if (mode == ATH10K_FIRMWARE_MODE_NORMAL && !mtu_workaround)
823 		param |= HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE;
824 	else
825 		param &= ~HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE;
826 
827 	if (mode == ATH10K_FIRMWARE_MODE_UTF)
828 		param &= ~HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET;
829 	else
830 		param |= HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET;
831 
832 	ret = ath10k_bmi_write32(ar, hi_acs_flags, param);
833 	if (ret)
834 		return ret;
835 
836 	ret = ath10k_bmi_read32(ar, hi_option_flag2, &param);
837 	if (ret)
838 		return ret;
839 
840 	param |= HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_HOST;
841 
842 	ret = ath10k_bmi_write32(ar, hi_option_flag2, param);
843 	if (ret)
844 		return ret;
845 
846 	return 0;
847 }
848 
ath10k_init_configure_target(struct ath10k * ar)849 static int ath10k_init_configure_target(struct ath10k *ar)
850 {
851 	u32 param_host;
852 	int ret;
853 
854 	/* tell target which HTC version it is used*/
855 	ret = ath10k_bmi_write32(ar, hi_app_host_interest,
856 				 HTC_PROTOCOL_VERSION);
857 	if (ret) {
858 		ath10k_err(ar, "settings HTC version failed\n");
859 		return ret;
860 	}
861 
862 	/* set the firmware mode to STA/IBSS/AP */
863 	ret = ath10k_bmi_read32(ar, hi_option_flag, &param_host);
864 	if (ret) {
865 		ath10k_err(ar, "setting firmware mode (1/2) failed\n");
866 		return ret;
867 	}
868 
869 	/* TODO following parameters need to be re-visited. */
870 	/* num_device */
871 	param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT);
872 	/* Firmware mode */
873 	/* FIXME: Why FW_MODE_AP ??.*/
874 	param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT);
875 	/* mac_addr_method */
876 	param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
877 	/* firmware_bridge */
878 	param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
879 	/* fwsubmode */
880 	param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT);
881 
882 	ret = ath10k_bmi_write32(ar, hi_option_flag, param_host);
883 	if (ret) {
884 		ath10k_err(ar, "setting firmware mode (2/2) failed\n");
885 		return ret;
886 	}
887 
888 	/* We do all byte-swapping on the host */
889 	ret = ath10k_bmi_write32(ar, hi_be, 0);
890 	if (ret) {
891 		ath10k_err(ar, "setting host CPU BE mode failed\n");
892 		return ret;
893 	}
894 
895 	/* FW descriptor/Data swap flags */
896 	ret = ath10k_bmi_write32(ar, hi_fw_swap, 0);
897 
898 	if (ret) {
899 		ath10k_err(ar, "setting FW data/desc swap flags failed\n");
900 		return ret;
901 	}
902 
903 	/* Some devices have a special sanity check that verifies the PCI
904 	 * Device ID is written to this host interest var. It is known to be
905 	 * required to boot QCA6164.
906 	 */
907 	ret = ath10k_bmi_write32(ar, hi_hci_uart_pwr_mgmt_params_ext,
908 				 ar->dev_id);
909 	if (ret) {
910 		ath10k_err(ar, "failed to set pwr_mgmt_params: %d\n", ret);
911 		return ret;
912 	}
913 
914 	return 0;
915 }
916 
ath10k_fetch_fw_file(struct ath10k * ar,const char * dir,const char * file)917 static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar,
918 						   const char *dir,
919 						   const char *file)
920 {
921 	char filename[100];
922 	const struct firmware *fw;
923 	int ret;
924 
925 	if (file == NULL)
926 		return ERR_PTR(-ENOENT);
927 
928 	if (dir == NULL)
929 		dir = ".";
930 
931 	snprintf(filename, sizeof(filename), "%s/%s", dir, file);
932 	ret = firmware_request_nowarn(&fw, filename, ar->dev);
933 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot fw request '%s': %d\n",
934 		   filename, ret);
935 
936 	if (ret)
937 		return ERR_PTR(ret);
938 
939 	return fw;
940 }
941 
ath10k_push_board_ext_data(struct ath10k * ar,const void * data,size_t data_len)942 static int ath10k_push_board_ext_data(struct ath10k *ar, const void *data,
943 				      size_t data_len)
944 {
945 	u32 board_data_size = ar->hw_params.fw.board_size;
946 	u32 board_ext_data_size = ar->hw_params.fw.board_ext_size;
947 	u32 board_ext_data_addr;
948 	int ret;
949 
950 	ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr);
951 	if (ret) {
952 		ath10k_err(ar, "could not read board ext data addr (%d)\n",
953 			   ret);
954 		return ret;
955 	}
956 
957 	ath10k_dbg(ar, ATH10K_DBG_BOOT,
958 		   "boot push board extended data addr 0x%x\n",
959 		   board_ext_data_addr);
960 
961 	if (board_ext_data_addr == 0)
962 		return 0;
963 
964 	if (data_len != (board_data_size + board_ext_data_size)) {
965 		ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n",
966 			   data_len, board_data_size, board_ext_data_size);
967 		return -EINVAL;
968 	}
969 
970 	ret = ath10k_bmi_write_memory(ar, board_ext_data_addr,
971 				      data + board_data_size,
972 				      board_ext_data_size);
973 	if (ret) {
974 		ath10k_err(ar, "could not write board ext data (%d)\n", ret);
975 		return ret;
976 	}
977 
978 	ret = ath10k_bmi_write32(ar, hi_board_ext_data_config,
979 				 (board_ext_data_size << 16) | 1);
980 	if (ret) {
981 		ath10k_err(ar, "could not write board ext data bit (%d)\n",
982 			   ret);
983 		return ret;
984 	}
985 
986 	return 0;
987 }
988 
ath10k_core_get_board_id_from_otp(struct ath10k * ar)989 static int ath10k_core_get_board_id_from_otp(struct ath10k *ar)
990 {
991 	u32 result, address;
992 	u8 board_id, chip_id;
993 	bool ext_bid_support;
994 	int ret, bmi_board_id_param;
995 
996 	address = ar->hw_params.patch_load_addr;
997 
998 	if (!ar->normal_mode_fw.fw_file.otp_data ||
999 	    !ar->normal_mode_fw.fw_file.otp_len) {
1000 		ath10k_warn(ar,
1001 			    "failed to retrieve board id because of invalid otp\n");
1002 		return -ENODATA;
1003 	}
1004 
1005 	if (ar->id.bmi_ids_valid) {
1006 		ath10k_dbg(ar, ATH10K_DBG_BOOT,
1007 			   "boot already acquired valid otp board id,skip download, board_id %d chip_id %d\n",
1008 			   ar->id.bmi_board_id, ar->id.bmi_chip_id);
1009 		goto skip_otp_download;
1010 	}
1011 
1012 	ath10k_dbg(ar, ATH10K_DBG_BOOT,
1013 		   "boot upload otp to 0x%x len %zd for board id\n",
1014 		   address, ar->normal_mode_fw.fw_file.otp_len);
1015 
1016 	ret = ath10k_bmi_fast_download(ar, address,
1017 				       ar->normal_mode_fw.fw_file.otp_data,
1018 				       ar->normal_mode_fw.fw_file.otp_len);
1019 	if (ret) {
1020 		ath10k_err(ar, "could not write otp for board id check: %d\n",
1021 			   ret);
1022 		return ret;
1023 	}
1024 
1025 	if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT ||
1026 	    ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE ||
1027 	    ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM)
1028 		bmi_board_id_param = BMI_PARAM_GET_FLASH_BOARD_ID;
1029 	else
1030 		bmi_board_id_param = BMI_PARAM_GET_EEPROM_BOARD_ID;
1031 
1032 	ret = ath10k_bmi_execute(ar, address, bmi_board_id_param, &result);
1033 	if (ret) {
1034 		ath10k_err(ar, "could not execute otp for board id check: %d\n",
1035 			   ret);
1036 		return ret;
1037 	}
1038 
1039 	board_id = MS(result, ATH10K_BMI_BOARD_ID_FROM_OTP);
1040 	chip_id = MS(result, ATH10K_BMI_CHIP_ID_FROM_OTP);
1041 	ext_bid_support = (result & ATH10K_BMI_EXT_BOARD_ID_SUPPORT);
1042 
1043 	ath10k_dbg(ar, ATH10K_DBG_BOOT,
1044 		   "boot get otp board id result 0x%08x board_id %d chip_id %d ext_bid_support %d\n",
1045 		   result, board_id, chip_id, ext_bid_support);
1046 
1047 	ar->id.ext_bid_supported = ext_bid_support;
1048 
1049 	if ((result & ATH10K_BMI_BOARD_ID_STATUS_MASK) != 0 ||
1050 	    (board_id == 0)) {
1051 		ath10k_dbg(ar, ATH10K_DBG_BOOT,
1052 			   "board id does not exist in otp, ignore it\n");
1053 		return -EOPNOTSUPP;
1054 	}
1055 
1056 	ar->id.bmi_ids_valid = true;
1057 	ar->id.bmi_board_id = board_id;
1058 	ar->id.bmi_chip_id = chip_id;
1059 
1060 skip_otp_download:
1061 
1062 	return 0;
1063 }
1064 
ath10k_core_check_bdfext(const struct dmi_header * hdr,void * data)1065 static void ath10k_core_check_bdfext(const struct dmi_header *hdr, void *data)
1066 {
1067 	struct ath10k *ar = data;
1068 	const char *bdf_ext;
1069 	const char *magic = ATH10K_SMBIOS_BDF_EXT_MAGIC;
1070 	u8 bdf_enabled;
1071 	int i;
1072 
1073 	if (hdr->type != ATH10K_SMBIOS_BDF_EXT_TYPE)
1074 		return;
1075 
1076 	if (hdr->length != ATH10K_SMBIOS_BDF_EXT_LENGTH) {
1077 		ath10k_dbg(ar, ATH10K_DBG_BOOT,
1078 			   "wrong smbios bdf ext type length (%d).\n",
1079 			   hdr->length);
1080 		return;
1081 	}
1082 
1083 	bdf_enabled = *((u8 *)hdr + ATH10K_SMBIOS_BDF_EXT_OFFSET);
1084 	if (!bdf_enabled) {
1085 		ath10k_dbg(ar, ATH10K_DBG_BOOT, "bdf variant name not found.\n");
1086 		return;
1087 	}
1088 
1089 	/* Only one string exists (per spec) */
1090 	bdf_ext = (char *)hdr + hdr->length;
1091 
1092 	if (memcmp(bdf_ext, magic, strlen(magic)) != 0) {
1093 		ath10k_dbg(ar, ATH10K_DBG_BOOT,
1094 			   "bdf variant magic does not match.\n");
1095 		return;
1096 	}
1097 
1098 	for (i = 0; i < strlen(bdf_ext); i++) {
1099 		if (!isascii(bdf_ext[i]) || !isprint(bdf_ext[i])) {
1100 			ath10k_dbg(ar, ATH10K_DBG_BOOT,
1101 				   "bdf variant name contains non ascii chars.\n");
1102 			return;
1103 		}
1104 	}
1105 
1106 	/* Copy extension name without magic suffix */
1107 	if (strscpy(ar->id.bdf_ext, bdf_ext + strlen(magic),
1108 		    sizeof(ar->id.bdf_ext)) < 0) {
1109 		ath10k_dbg(ar, ATH10K_DBG_BOOT,
1110 			   "bdf variant string is longer than the buffer can accommodate (variant: %s)\n",
1111 			    bdf_ext);
1112 		return;
1113 	}
1114 
1115 	ath10k_dbg(ar, ATH10K_DBG_BOOT,
1116 		   "found and validated bdf variant smbios_type 0x%x bdf %s\n",
1117 		   ATH10K_SMBIOS_BDF_EXT_TYPE, bdf_ext);
1118 }
1119 
ath10k_core_check_smbios(struct ath10k * ar)1120 static int ath10k_core_check_smbios(struct ath10k *ar)
1121 {
1122 	ar->id.bdf_ext[0] = '\0';
1123 	dmi_walk(ath10k_core_check_bdfext, ar);
1124 
1125 	if (ar->id.bdf_ext[0] == '\0')
1126 		return -ENODATA;
1127 
1128 	return 0;
1129 }
1130 
ath10k_core_check_dt(struct ath10k * ar)1131 int ath10k_core_check_dt(struct ath10k *ar)
1132 {
1133 	struct device_node *node;
1134 	const char *variant = NULL;
1135 
1136 	node = ar->dev->of_node;
1137 	if (!node)
1138 		return -ENOENT;
1139 
1140 	of_property_read_string(node, "qcom,ath10k-calibration-variant",
1141 				&variant);
1142 	if (!variant)
1143 		return -ENODATA;
1144 
1145 	if (strscpy(ar->id.bdf_ext, variant, sizeof(ar->id.bdf_ext)) < 0)
1146 		ath10k_dbg(ar, ATH10K_DBG_BOOT,
1147 			   "bdf variant string is longer than the buffer can accommodate (variant: %s)\n",
1148 			    variant);
1149 
1150 	return 0;
1151 }
1152 EXPORT_SYMBOL(ath10k_core_check_dt);
1153 
ath10k_download_fw(struct ath10k * ar)1154 static int ath10k_download_fw(struct ath10k *ar)
1155 {
1156 	u32 address, data_len;
1157 	const void *data;
1158 	int ret;
1159 	struct pm_qos_request latency_qos;
1160 
1161 	address = ar->hw_params.patch_load_addr;
1162 
1163 	data = ar->running_fw->fw_file.firmware_data;
1164 	data_len = ar->running_fw->fw_file.firmware_len;
1165 
1166 	ret = ath10k_swap_code_seg_configure(ar, &ar->running_fw->fw_file);
1167 	if (ret) {
1168 		ath10k_err(ar, "failed to configure fw code swap: %d\n",
1169 			   ret);
1170 		return ret;
1171 	}
1172 
1173 	ath10k_dbg(ar, ATH10K_DBG_BOOT,
1174 		   "boot uploading firmware image %pK len %d\n",
1175 		   data, data_len);
1176 
1177 	/* Check if device supports to download firmware via
1178 	 * diag copy engine. Downloading firmware via diag CE
1179 	 * greatly reduces the time to download firmware.
1180 	 */
1181 	if (ar->hw_params.fw_diag_ce_download) {
1182 		ret = ath10k_hw_diag_fast_download(ar, address,
1183 						   data, data_len);
1184 		if (ret == 0)
1185 			/* firmware upload via diag ce was successful */
1186 			return 0;
1187 
1188 		ath10k_warn(ar,
1189 			    "failed to upload firmware via diag ce, trying BMI: %d",
1190 			    ret);
1191 	}
1192 
1193 	memset(&latency_qos, 0, sizeof(latency_qos));
1194 	cpu_latency_qos_add_request(&latency_qos, 0);
1195 
1196 	ret = ath10k_bmi_fast_download(ar, address, data, data_len);
1197 
1198 	cpu_latency_qos_remove_request(&latency_qos);
1199 
1200 	return ret;
1201 }
1202 
ath10k_core_free_board_files(struct ath10k * ar)1203 void ath10k_core_free_board_files(struct ath10k *ar)
1204 {
1205 	if (!IS_ERR(ar->normal_mode_fw.board))
1206 		release_firmware(ar->normal_mode_fw.board);
1207 
1208 	if (!IS_ERR(ar->normal_mode_fw.ext_board))
1209 		release_firmware(ar->normal_mode_fw.ext_board);
1210 
1211 	ar->normal_mode_fw.board = NULL;
1212 	ar->normal_mode_fw.board_data = NULL;
1213 	ar->normal_mode_fw.board_len = 0;
1214 	ar->normal_mode_fw.ext_board = NULL;
1215 	ar->normal_mode_fw.ext_board_data = NULL;
1216 	ar->normal_mode_fw.ext_board_len = 0;
1217 }
1218 EXPORT_SYMBOL(ath10k_core_free_board_files);
1219 
ath10k_core_free_firmware_files(struct ath10k * ar)1220 static void ath10k_core_free_firmware_files(struct ath10k *ar)
1221 {
1222 	if (!IS_ERR(ar->normal_mode_fw.fw_file.firmware))
1223 		release_firmware(ar->normal_mode_fw.fw_file.firmware);
1224 
1225 	if (!IS_ERR(ar->cal_file))
1226 		release_firmware(ar->cal_file);
1227 
1228 	if (!IS_ERR(ar->pre_cal_file))
1229 		release_firmware(ar->pre_cal_file);
1230 
1231 	ath10k_swap_code_seg_release(ar, &ar->normal_mode_fw.fw_file);
1232 
1233 	ar->normal_mode_fw.fw_file.otp_data = NULL;
1234 	ar->normal_mode_fw.fw_file.otp_len = 0;
1235 
1236 	ar->normal_mode_fw.fw_file.firmware = NULL;
1237 	ar->normal_mode_fw.fw_file.firmware_data = NULL;
1238 	ar->normal_mode_fw.fw_file.firmware_len = 0;
1239 
1240 	ar->cal_file = NULL;
1241 	ar->pre_cal_file = NULL;
1242 }
1243 
ath10k_fetch_cal_file(struct ath10k * ar)1244 static int ath10k_fetch_cal_file(struct ath10k *ar)
1245 {
1246 	char filename[100];
1247 
1248 	/* pre-cal-<bus>-<id>.bin */
1249 	scnprintf(filename, sizeof(filename), "pre-cal-%s-%s.bin",
1250 		  ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
1251 
1252 	ar->pre_cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename);
1253 	if (!IS_ERR(ar->pre_cal_file))
1254 		goto success;
1255 
1256 	/* cal-<bus>-<id>.bin */
1257 	scnprintf(filename, sizeof(filename), "cal-%s-%s.bin",
1258 		  ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
1259 
1260 	ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename);
1261 	if (IS_ERR(ar->cal_file))
1262 		/* calibration file is optional, don't print any warnings */
1263 		return PTR_ERR(ar->cal_file);
1264 success:
1265 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n",
1266 		   ATH10K_FW_DIR, filename);
1267 
1268 	return 0;
1269 }
1270 
ath10k_core_fetch_board_data_api_1(struct ath10k * ar,int bd_ie_type)1271 static int ath10k_core_fetch_board_data_api_1(struct ath10k *ar, int bd_ie_type)
1272 {
1273 	const struct firmware *fw;
1274 	char boardname[100];
1275 
1276 	if (bd_ie_type == ATH10K_BD_IE_BOARD) {
1277 		if (!ar->hw_params.fw.board) {
1278 			ath10k_err(ar, "failed to find board file fw entry\n");
1279 			return -EINVAL;
1280 		}
1281 
1282 		scnprintf(boardname, sizeof(boardname), "board-%s-%s.bin",
1283 			  ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
1284 
1285 		ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar,
1286 								ar->hw_params.fw.dir,
1287 								boardname);
1288 		if (IS_ERR(ar->normal_mode_fw.board)) {
1289 			fw = ath10k_fetch_fw_file(ar,
1290 						  ar->hw_params.fw.dir,
1291 						  ar->hw_params.fw.board);
1292 			ar->normal_mode_fw.board = fw;
1293 		}
1294 
1295 		if (IS_ERR(ar->normal_mode_fw.board))
1296 			return PTR_ERR(ar->normal_mode_fw.board);
1297 
1298 		ar->normal_mode_fw.board_data = ar->normal_mode_fw.board->data;
1299 		ar->normal_mode_fw.board_len = ar->normal_mode_fw.board->size;
1300 	} else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) {
1301 		if (!ar->hw_params.fw.eboard) {
1302 			ath10k_err(ar, "failed to find eboard file fw entry\n");
1303 			return -EINVAL;
1304 		}
1305 
1306 		fw = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir,
1307 					  ar->hw_params.fw.eboard);
1308 		ar->normal_mode_fw.ext_board = fw;
1309 		if (IS_ERR(ar->normal_mode_fw.ext_board))
1310 			return PTR_ERR(ar->normal_mode_fw.ext_board);
1311 
1312 		ar->normal_mode_fw.ext_board_data = ar->normal_mode_fw.ext_board->data;
1313 		ar->normal_mode_fw.ext_board_len = ar->normal_mode_fw.ext_board->size;
1314 	}
1315 
1316 	return 0;
1317 }
1318 
ath10k_core_parse_bd_ie_board(struct ath10k * ar,const void * buf,size_t buf_len,const char * boardname,int bd_ie_type)1319 static int ath10k_core_parse_bd_ie_board(struct ath10k *ar,
1320 					 const void *buf, size_t buf_len,
1321 					 const char *boardname,
1322 					 int bd_ie_type)
1323 {
1324 	const struct ath10k_fw_ie *hdr;
1325 	bool name_match_found;
1326 	int ret, board_ie_id;
1327 	size_t board_ie_len;
1328 	const void *board_ie_data;
1329 
1330 	name_match_found = false;
1331 
1332 	/* go through ATH10K_BD_IE_BOARD_ elements */
1333 	while (buf_len > sizeof(struct ath10k_fw_ie)) {
1334 		hdr = buf;
1335 		board_ie_id = le32_to_cpu(hdr->id);
1336 		board_ie_len = le32_to_cpu(hdr->len);
1337 		board_ie_data = hdr->data;
1338 
1339 		buf_len -= sizeof(*hdr);
1340 		buf += sizeof(*hdr);
1341 
1342 		if (buf_len < ALIGN(board_ie_len, 4)) {
1343 			ath10k_err(ar, "invalid ATH10K_BD_IE_BOARD length: %zu < %zu\n",
1344 				   buf_len, ALIGN(board_ie_len, 4));
1345 			ret = -EINVAL;
1346 			goto out;
1347 		}
1348 
1349 		switch (board_ie_id) {
1350 		case ATH10K_BD_IE_BOARD_NAME:
1351 			ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "board name", "",
1352 					board_ie_data, board_ie_len);
1353 
1354 			if (board_ie_len != strlen(boardname))
1355 				break;
1356 
1357 			ret = memcmp(board_ie_data, boardname, strlen(boardname));
1358 			if (ret)
1359 				break;
1360 
1361 			name_match_found = true;
1362 			ath10k_dbg(ar, ATH10K_DBG_BOOT,
1363 				   "boot found match for name '%s'",
1364 				   boardname);
1365 			break;
1366 		case ATH10K_BD_IE_BOARD_DATA:
1367 			if (!name_match_found)
1368 				/* no match found */
1369 				break;
1370 
1371 			if (bd_ie_type == ATH10K_BD_IE_BOARD) {
1372 				ath10k_dbg(ar, ATH10K_DBG_BOOT,
1373 					   "boot found board data for '%s'",
1374 						boardname);
1375 
1376 				ar->normal_mode_fw.board_data = board_ie_data;
1377 				ar->normal_mode_fw.board_len = board_ie_len;
1378 			} else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) {
1379 				ath10k_dbg(ar, ATH10K_DBG_BOOT,
1380 					   "boot found eboard data for '%s'",
1381 						boardname);
1382 
1383 				ar->normal_mode_fw.ext_board_data = board_ie_data;
1384 				ar->normal_mode_fw.ext_board_len = board_ie_len;
1385 			}
1386 
1387 			ret = 0;
1388 			goto out;
1389 		default:
1390 			ath10k_warn(ar, "unknown ATH10K_BD_IE_BOARD found: %d\n",
1391 				    board_ie_id);
1392 			break;
1393 		}
1394 
1395 		/* jump over the padding */
1396 		board_ie_len = ALIGN(board_ie_len, 4);
1397 
1398 		buf_len -= board_ie_len;
1399 		buf += board_ie_len;
1400 	}
1401 
1402 	/* no match found */
1403 	ret = -ENOENT;
1404 
1405 out:
1406 	return ret;
1407 }
1408 
ath10k_core_search_bd(struct ath10k * ar,const char * boardname,const u8 * data,size_t len)1409 static int ath10k_core_search_bd(struct ath10k *ar,
1410 				 const char *boardname,
1411 				 const u8 *data,
1412 				 size_t len)
1413 {
1414 	size_t ie_len;
1415 	struct ath10k_fw_ie *hdr;
1416 	int ret = -ENOENT, ie_id;
1417 
1418 	while (len > sizeof(struct ath10k_fw_ie)) {
1419 		hdr = (struct ath10k_fw_ie *)data;
1420 		ie_id = le32_to_cpu(hdr->id);
1421 		ie_len = le32_to_cpu(hdr->len);
1422 
1423 		len -= sizeof(*hdr);
1424 		data = hdr->data;
1425 
1426 		if (len < ALIGN(ie_len, 4)) {
1427 			ath10k_err(ar, "invalid length for board ie_id %d ie_len %zu len %zu\n",
1428 				   ie_id, ie_len, len);
1429 			return -EINVAL;
1430 		}
1431 
1432 		switch (ie_id) {
1433 		case ATH10K_BD_IE_BOARD:
1434 			ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len,
1435 							    boardname,
1436 							    ATH10K_BD_IE_BOARD);
1437 			if (ret == -ENOENT)
1438 				/* no match found, continue */
1439 				break;
1440 
1441 			/* either found or error, so stop searching */
1442 			goto out;
1443 		case ATH10K_BD_IE_BOARD_EXT:
1444 			ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len,
1445 							    boardname,
1446 							    ATH10K_BD_IE_BOARD_EXT);
1447 			if (ret == -ENOENT)
1448 				/* no match found, continue */
1449 				break;
1450 
1451 			/* either found or error, so stop searching */
1452 			goto out;
1453 		}
1454 
1455 		/* jump over the padding */
1456 		ie_len = ALIGN(ie_len, 4);
1457 
1458 		len -= ie_len;
1459 		data += ie_len;
1460 	}
1461 
1462 out:
1463 	/* return result of parse_bd_ie_board() or -ENOENT */
1464 	return ret;
1465 }
1466 
ath10k_core_fetch_board_data_api_n(struct ath10k * ar,const char * boardname,const char * fallback_boardname1,const char * fallback_boardname2,const char * filename)1467 static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar,
1468 					      const char *boardname,
1469 					      const char *fallback_boardname1,
1470 					      const char *fallback_boardname2,
1471 					      const char *filename)
1472 {
1473 	size_t len, magic_len;
1474 	const u8 *data;
1475 	int ret;
1476 
1477 	/* Skip if already fetched during board data download */
1478 	if (!ar->normal_mode_fw.board)
1479 		ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar,
1480 								ar->hw_params.fw.dir,
1481 								filename);
1482 	if (IS_ERR(ar->normal_mode_fw.board))
1483 		return PTR_ERR(ar->normal_mode_fw.board);
1484 
1485 	data = ar->normal_mode_fw.board->data;
1486 	len = ar->normal_mode_fw.board->size;
1487 
1488 	/* magic has extra null byte padded */
1489 	magic_len = strlen(ATH10K_BOARD_MAGIC) + 1;
1490 	if (len < magic_len) {
1491 		ath10k_err(ar, "failed to find magic value in %s/%s, file too short: %zu\n",
1492 			   ar->hw_params.fw.dir, filename, len);
1493 		ret = -EINVAL;
1494 		goto err;
1495 	}
1496 
1497 	if (memcmp(data, ATH10K_BOARD_MAGIC, magic_len)) {
1498 		ath10k_err(ar, "found invalid board magic\n");
1499 		ret = -EINVAL;
1500 		goto err;
1501 	}
1502 
1503 	/* magic is padded to 4 bytes */
1504 	magic_len = ALIGN(magic_len, 4);
1505 	if (len < magic_len) {
1506 		ath10k_err(ar, "failed: %s/%s too small to contain board data, len: %zu\n",
1507 			   ar->hw_params.fw.dir, filename, len);
1508 		ret = -EINVAL;
1509 		goto err;
1510 	}
1511 
1512 	data += magic_len;
1513 	len -= magic_len;
1514 
1515 	/* attempt to find boardname in the IE list */
1516 	ret = ath10k_core_search_bd(ar, boardname, data, len);
1517 
1518 	/* if we didn't find it and have a fallback name, try that */
1519 	if (ret == -ENOENT && fallback_boardname1)
1520 		ret = ath10k_core_search_bd(ar, fallback_boardname1, data, len);
1521 
1522 	if (ret == -ENOENT && fallback_boardname2)
1523 		ret = ath10k_core_search_bd(ar, fallback_boardname2, data, len);
1524 
1525 	if (ret == -ENOENT) {
1526 		ath10k_err(ar,
1527 			   "failed to fetch board data for %s from %s/%s\n",
1528 			   boardname, ar->hw_params.fw.dir, filename);
1529 		ret = -ENODATA;
1530 	}
1531 
1532 	if (ret)
1533 		goto err;
1534 
1535 	return 0;
1536 
1537 err:
1538 	ath10k_core_free_board_files(ar);
1539 	return ret;
1540 }
1541 
ath10k_core_create_board_name(struct ath10k * ar,char * name,size_t name_len,bool with_variant,bool with_chip_id)1542 static int ath10k_core_create_board_name(struct ath10k *ar, char *name,
1543 					 size_t name_len, bool with_variant,
1544 					 bool with_chip_id)
1545 {
1546 	/* strlen(',variant=') + strlen(ar->id.bdf_ext) */
1547 	char variant[9 + ATH10K_SMBIOS_BDF_EXT_STR_LENGTH] = { 0 };
1548 
1549 	if (with_variant && ar->id.bdf_ext[0] != '\0')
1550 		scnprintf(variant, sizeof(variant), ",variant=%s",
1551 			  ar->id.bdf_ext);
1552 
1553 	if (ar->id.bmi_ids_valid) {
1554 		scnprintf(name, name_len,
1555 			  "bus=%s,bmi-chip-id=%d,bmi-board-id=%d%s",
1556 			  ath10k_bus_str(ar->hif.bus),
1557 			  ar->id.bmi_chip_id,
1558 			  ar->id.bmi_board_id, variant);
1559 		goto out;
1560 	}
1561 
1562 	if (ar->id.qmi_ids_valid) {
1563 		if (with_chip_id)
1564 			scnprintf(name, name_len,
1565 				  "bus=%s,qmi-board-id=%x,qmi-chip-id=%x%s",
1566 				  ath10k_bus_str(ar->hif.bus),
1567 				  ar->id.qmi_board_id, ar->id.qmi_chip_id,
1568 				  variant);
1569 		else
1570 			scnprintf(name, name_len,
1571 				  "bus=%s,qmi-board-id=%x",
1572 				  ath10k_bus_str(ar->hif.bus),
1573 				  ar->id.qmi_board_id);
1574 		goto out;
1575 	}
1576 
1577 	scnprintf(name, name_len,
1578 		  "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x%s",
1579 		  ath10k_bus_str(ar->hif.bus),
1580 		  ar->id.vendor, ar->id.device,
1581 		  ar->id.subsystem_vendor, ar->id.subsystem_device, variant);
1582 out:
1583 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using board name '%s'\n", name);
1584 
1585 	return 0;
1586 }
1587 
ath10k_core_create_eboard_name(struct ath10k * ar,char * name,size_t name_len)1588 static int ath10k_core_create_eboard_name(struct ath10k *ar, char *name,
1589 					  size_t name_len)
1590 {
1591 	if (ar->id.bmi_ids_valid) {
1592 		scnprintf(name, name_len,
1593 			  "bus=%s,bmi-chip-id=%d,bmi-eboard-id=%d",
1594 			  ath10k_bus_str(ar->hif.bus),
1595 			  ar->id.bmi_chip_id,
1596 			  ar->id.bmi_eboard_id);
1597 
1598 		ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using eboard name '%s'\n", name);
1599 		return 0;
1600 	}
1601 	/* Fallback if returned board id is zero */
1602 	return -1;
1603 }
1604 
ath10k_core_fetch_board_file(struct ath10k * ar,int bd_ie_type)1605 int ath10k_core_fetch_board_file(struct ath10k *ar, int bd_ie_type)
1606 {
1607 	char boardname[100], fallback_boardname1[100], fallback_boardname2[100];
1608 	int ret;
1609 
1610 	if (bd_ie_type == ATH10K_BD_IE_BOARD) {
1611 		/* With variant and chip id */
1612 		ret = ath10k_core_create_board_name(ar, boardname,
1613 						    sizeof(boardname), true,
1614 						    true);
1615 		if (ret) {
1616 			ath10k_err(ar, "failed to create board name: %d", ret);
1617 			return ret;
1618 		}
1619 
1620 		/* Without variant and only chip-id */
1621 		ret = ath10k_core_create_board_name(ar, fallback_boardname1,
1622 						    sizeof(boardname), false,
1623 						    true);
1624 		if (ret) {
1625 			ath10k_err(ar, "failed to create 1st fallback board name: %d",
1626 				   ret);
1627 			return ret;
1628 		}
1629 
1630 		/* Without variant and without chip-id */
1631 		ret = ath10k_core_create_board_name(ar, fallback_boardname2,
1632 						    sizeof(boardname), false,
1633 						    false);
1634 		if (ret) {
1635 			ath10k_err(ar, "failed to create 2nd fallback board name: %d",
1636 				   ret);
1637 			return ret;
1638 		}
1639 	} else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) {
1640 		ret = ath10k_core_create_eboard_name(ar, boardname,
1641 						     sizeof(boardname));
1642 		if (ret) {
1643 			ath10k_err(ar, "fallback to eboard.bin since board id 0");
1644 			goto fallback;
1645 		}
1646 	}
1647 
1648 	ar->bd_api = 2;
1649 	ret = ath10k_core_fetch_board_data_api_n(ar, boardname,
1650 						 fallback_boardname1,
1651 						 fallback_boardname2,
1652 						 ATH10K_BOARD_API2_FILE);
1653 	if (!ret)
1654 		goto success;
1655 
1656 fallback:
1657 	ar->bd_api = 1;
1658 	ret = ath10k_core_fetch_board_data_api_1(ar, bd_ie_type);
1659 	if (ret) {
1660 		ath10k_err(ar, "failed to fetch board-2.bin or board.bin from %s\n",
1661 			   ar->hw_params.fw.dir);
1662 		return ret;
1663 	}
1664 
1665 success:
1666 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "using board api %d\n", ar->bd_api);
1667 	return 0;
1668 }
1669 EXPORT_SYMBOL(ath10k_core_fetch_board_file);
1670 
ath10k_core_get_ext_board_id_from_otp(struct ath10k * ar)1671 static int ath10k_core_get_ext_board_id_from_otp(struct ath10k *ar)
1672 {
1673 	u32 result, address;
1674 	u8 ext_board_id;
1675 	int ret;
1676 
1677 	address = ar->hw_params.patch_load_addr;
1678 
1679 	if (!ar->normal_mode_fw.fw_file.otp_data ||
1680 	    !ar->normal_mode_fw.fw_file.otp_len) {
1681 		ath10k_warn(ar,
1682 			    "failed to retrieve extended board id due to otp binary missing\n");
1683 		return -ENODATA;
1684 	}
1685 
1686 	ath10k_dbg(ar, ATH10K_DBG_BOOT,
1687 		   "boot upload otp to 0x%x len %zd for ext board id\n",
1688 		   address, ar->normal_mode_fw.fw_file.otp_len);
1689 
1690 	ret = ath10k_bmi_fast_download(ar, address,
1691 				       ar->normal_mode_fw.fw_file.otp_data,
1692 				       ar->normal_mode_fw.fw_file.otp_len);
1693 	if (ret) {
1694 		ath10k_err(ar, "could not write otp for ext board id check: %d\n",
1695 			   ret);
1696 		return ret;
1697 	}
1698 
1699 	ret = ath10k_bmi_execute(ar, address, BMI_PARAM_GET_EXT_BOARD_ID, &result);
1700 	if (ret) {
1701 		ath10k_err(ar, "could not execute otp for ext board id check: %d\n",
1702 			   ret);
1703 		return ret;
1704 	}
1705 
1706 	if (!result) {
1707 		ath10k_dbg(ar, ATH10K_DBG_BOOT,
1708 			   "ext board id does not exist in otp, ignore it\n");
1709 		return -EOPNOTSUPP;
1710 	}
1711 
1712 	ext_board_id = result & ATH10K_BMI_EBOARD_ID_STATUS_MASK;
1713 
1714 	ath10k_dbg(ar, ATH10K_DBG_BOOT,
1715 		   "boot get otp ext board id result 0x%08x ext_board_id %d\n",
1716 		   result, ext_board_id);
1717 
1718 	ar->id.bmi_eboard_id = ext_board_id;
1719 
1720 	return 0;
1721 }
1722 
ath10k_download_board_data(struct ath10k * ar,const void * data,size_t data_len)1723 static int ath10k_download_board_data(struct ath10k *ar, const void *data,
1724 				      size_t data_len)
1725 {
1726 	u32 board_data_size = ar->hw_params.fw.board_size;
1727 	u32 eboard_data_size = ar->hw_params.fw.ext_board_size;
1728 	u32 board_address;
1729 	u32 ext_board_address;
1730 	int ret;
1731 
1732 	ret = ath10k_push_board_ext_data(ar, data, data_len);
1733 	if (ret) {
1734 		ath10k_err(ar, "could not push board ext data (%d)\n", ret);
1735 		goto exit;
1736 	}
1737 
1738 	ret = ath10k_bmi_read32(ar, hi_board_data, &board_address);
1739 	if (ret) {
1740 		ath10k_err(ar, "could not read board data addr (%d)\n", ret);
1741 		goto exit;
1742 	}
1743 
1744 	ret = ath10k_bmi_write_memory(ar, board_address, data,
1745 				      min_t(u32, board_data_size,
1746 					    data_len));
1747 	if (ret) {
1748 		ath10k_err(ar, "could not write board data (%d)\n", ret);
1749 		goto exit;
1750 	}
1751 
1752 	ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1);
1753 	if (ret) {
1754 		ath10k_err(ar, "could not write board data bit (%d)\n", ret);
1755 		goto exit;
1756 	}
1757 
1758 	if (!ar->id.ext_bid_supported)
1759 		goto exit;
1760 
1761 	/* Extended board data download */
1762 	ret = ath10k_core_get_ext_board_id_from_otp(ar);
1763 	if (ret == -EOPNOTSUPP) {
1764 		/* Not fetching ext_board_data if ext board id is 0 */
1765 		ath10k_dbg(ar, ATH10K_DBG_BOOT, "otp returned ext board id 0\n");
1766 		return 0;
1767 	} else if (ret) {
1768 		ath10k_err(ar, "failed to get extended board id: %d\n", ret);
1769 		goto exit;
1770 	}
1771 
1772 	ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD_EXT);
1773 	if (ret)
1774 		goto exit;
1775 
1776 	if (ar->normal_mode_fw.ext_board_data) {
1777 		ext_board_address = board_address + EXT_BOARD_ADDRESS_OFFSET;
1778 		ath10k_dbg(ar, ATH10K_DBG_BOOT,
1779 			   "boot writing ext board data to addr 0x%x",
1780 			   ext_board_address);
1781 		ret = ath10k_bmi_write_memory(ar, ext_board_address,
1782 					      ar->normal_mode_fw.ext_board_data,
1783 					      min_t(u32, eboard_data_size, data_len));
1784 		if (ret)
1785 			ath10k_err(ar, "failed to write ext board data: %d\n", ret);
1786 	}
1787 
1788 exit:
1789 	return ret;
1790 }
1791 
ath10k_download_and_run_otp(struct ath10k * ar)1792 static int ath10k_download_and_run_otp(struct ath10k *ar)
1793 {
1794 	u32 result, address = ar->hw_params.patch_load_addr;
1795 	u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param;
1796 	int ret;
1797 
1798 	ret = ath10k_download_board_data(ar,
1799 					 ar->running_fw->board_data,
1800 					 ar->running_fw->board_len);
1801 	if (ret) {
1802 		ath10k_err(ar, "failed to download board data: %d\n", ret);
1803 		return ret;
1804 	}
1805 
1806 	/* OTP is optional */
1807 
1808 	if (!ar->running_fw->fw_file.otp_data ||
1809 	    !ar->running_fw->fw_file.otp_len) {
1810 		ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %pK otp_len %zd)!\n",
1811 			    ar->running_fw->fw_file.otp_data,
1812 			    ar->running_fw->fw_file.otp_len);
1813 		return 0;
1814 	}
1815 
1816 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n",
1817 		   address, ar->running_fw->fw_file.otp_len);
1818 
1819 	ret = ath10k_bmi_fast_download(ar, address,
1820 				       ar->running_fw->fw_file.otp_data,
1821 				       ar->running_fw->fw_file.otp_len);
1822 	if (ret) {
1823 		ath10k_err(ar, "could not write otp (%d)\n", ret);
1824 		return ret;
1825 	}
1826 
1827 	/* As of now pre-cal is valid for 10_4 variants */
1828 	if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT ||
1829 	    ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE ||
1830 	    ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM)
1831 		bmi_otp_exe_param = BMI_PARAM_FLASH_SECTION_ALL;
1832 
1833 	ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result);
1834 	if (ret) {
1835 		ath10k_err(ar, "could not execute otp (%d)\n", ret);
1836 		return ret;
1837 	}
1838 
1839 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result);
1840 
1841 	if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT,
1842 				   ar->running_fw->fw_file.fw_features)) &&
1843 	    result != 0) {
1844 		ath10k_err(ar, "otp calibration failed: %d", result);
1845 		return -EINVAL;
1846 	}
1847 
1848 	return 0;
1849 }
1850 
ath10k_download_cal_file(struct ath10k * ar,const struct firmware * file)1851 static int ath10k_download_cal_file(struct ath10k *ar,
1852 				    const struct firmware *file)
1853 {
1854 	int ret;
1855 
1856 	if (!file)
1857 		return -ENOENT;
1858 
1859 	if (IS_ERR(file))
1860 		return PTR_ERR(file);
1861 
1862 	ret = ath10k_download_board_data(ar, file->data, file->size);
1863 	if (ret) {
1864 		ath10k_err(ar, "failed to download cal_file data: %d\n", ret);
1865 		return ret;
1866 	}
1867 
1868 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cal file downloaded\n");
1869 
1870 	return 0;
1871 }
1872 
ath10k_download_cal_dt(struct ath10k * ar,const char * dt_name)1873 static int ath10k_download_cal_dt(struct ath10k *ar, const char *dt_name)
1874 {
1875 	struct device_node *node;
1876 	int data_len;
1877 	void *data;
1878 	int ret;
1879 
1880 	node = ar->dev->of_node;
1881 	if (!node)
1882 		/* Device Tree is optional, don't print any warnings if
1883 		 * there's no node for ath10k.
1884 		 */
1885 		return -ENOENT;
1886 
1887 	if (!of_get_property(node, dt_name, &data_len)) {
1888 		/* The calibration data node is optional */
1889 		return -ENOENT;
1890 	}
1891 
1892 	if (data_len != ar->hw_params.cal_data_len) {
1893 		ath10k_warn(ar, "invalid calibration data length in DT: %d\n",
1894 			    data_len);
1895 		ret = -EMSGSIZE;
1896 		goto out;
1897 	}
1898 
1899 	data = kmalloc(data_len, GFP_KERNEL);
1900 	if (!data) {
1901 		ret = -ENOMEM;
1902 		goto out;
1903 	}
1904 
1905 	ret = of_property_read_u8_array(node, dt_name, data, data_len);
1906 	if (ret) {
1907 		ath10k_warn(ar, "failed to read calibration data from DT: %d\n",
1908 			    ret);
1909 		goto out_free;
1910 	}
1911 
1912 	ret = ath10k_download_board_data(ar, data, data_len);
1913 	if (ret) {
1914 		ath10k_warn(ar, "failed to download calibration data from Device Tree: %d\n",
1915 			    ret);
1916 		goto out_free;
1917 	}
1918 
1919 	ret = 0;
1920 
1921 out_free:
1922 	kfree(data);
1923 
1924 out:
1925 	return ret;
1926 }
1927 
ath10k_download_cal_eeprom(struct ath10k * ar)1928 static int ath10k_download_cal_eeprom(struct ath10k *ar)
1929 {
1930 	size_t data_len;
1931 	void *data = NULL;
1932 	int ret;
1933 
1934 	ret = ath10k_hif_fetch_cal_eeprom(ar, &data, &data_len);
1935 	if (ret) {
1936 		if (ret != -EOPNOTSUPP)
1937 			ath10k_warn(ar, "failed to read calibration data from EEPROM: %d\n",
1938 				    ret);
1939 		goto out_free;
1940 	}
1941 
1942 	ret = ath10k_download_board_data(ar, data, data_len);
1943 	if (ret) {
1944 		ath10k_warn(ar, "failed to download calibration data from EEPROM: %d\n",
1945 			    ret);
1946 		goto out_free;
1947 	}
1948 
1949 	ret = 0;
1950 
1951 out_free:
1952 	kfree(data);
1953 
1954 	return ret;
1955 }
1956 
ath10k_download_cal_nvmem(struct ath10k * ar,const char * cell_name)1957 static int ath10k_download_cal_nvmem(struct ath10k *ar, const char *cell_name)
1958 {
1959 	struct nvmem_cell *cell;
1960 	void *buf;
1961 	size_t len;
1962 	int ret;
1963 
1964 	cell = devm_nvmem_cell_get(ar->dev, cell_name);
1965 	if (IS_ERR(cell)) {
1966 		ret = PTR_ERR(cell);
1967 		return ret;
1968 	}
1969 
1970 	buf = nvmem_cell_read(cell, &len);
1971 	if (IS_ERR(buf))
1972 		return PTR_ERR(buf);
1973 
1974 	if (ar->hw_params.cal_data_len != len) {
1975 		kfree(buf);
1976 		ath10k_warn(ar, "invalid calibration data length in nvmem-cell '%s': %zu != %u\n",
1977 			    cell_name, len, ar->hw_params.cal_data_len);
1978 		return -EMSGSIZE;
1979 	}
1980 
1981 	ret = ath10k_download_board_data(ar, buf, len);
1982 	kfree(buf);
1983 	if (ret)
1984 		ath10k_warn(ar, "failed to download calibration data from nvmem-cell '%s': %d\n",
1985 			    cell_name, ret);
1986 
1987 	return ret;
1988 }
1989 
ath10k_core_fetch_firmware_api_n(struct ath10k * ar,const char * name,struct ath10k_fw_file * fw_file)1990 int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name,
1991 				     struct ath10k_fw_file *fw_file)
1992 {
1993 	size_t magic_len, len, ie_len;
1994 	int ie_id, i, index, bit, ret;
1995 	struct ath10k_fw_ie *hdr;
1996 	const u8 *data;
1997 	__le32 *timestamp, *version;
1998 
1999 	/* first fetch the firmware file (firmware-*.bin) */
2000 	fw_file->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir,
2001 						 name);
2002 	if (IS_ERR(fw_file->firmware))
2003 		return PTR_ERR(fw_file->firmware);
2004 
2005 	data = fw_file->firmware->data;
2006 	len = fw_file->firmware->size;
2007 
2008 	/* magic also includes the null byte, check that as well */
2009 	magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1;
2010 
2011 	if (len < magic_len) {
2012 		ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n",
2013 			   ar->hw_params.fw.dir, name, len);
2014 		ret = -EINVAL;
2015 		goto err;
2016 	}
2017 
2018 	if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) {
2019 		ath10k_err(ar, "invalid firmware magic\n");
2020 		ret = -EINVAL;
2021 		goto err;
2022 	}
2023 
2024 	/* jump over the padding */
2025 	magic_len = ALIGN(magic_len, 4);
2026 
2027 	len -= magic_len;
2028 	data += magic_len;
2029 
2030 	/* loop elements */
2031 	while (len > sizeof(struct ath10k_fw_ie)) {
2032 		hdr = (struct ath10k_fw_ie *)data;
2033 
2034 		ie_id = le32_to_cpu(hdr->id);
2035 		ie_len = le32_to_cpu(hdr->len);
2036 
2037 		len -= sizeof(*hdr);
2038 		data += sizeof(*hdr);
2039 
2040 		if (len < ie_len) {
2041 			ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n",
2042 				   ie_id, len, ie_len);
2043 			ret = -EINVAL;
2044 			goto err;
2045 		}
2046 
2047 		switch (ie_id) {
2048 		case ATH10K_FW_IE_FW_VERSION:
2049 			if (ie_len > sizeof(fw_file->fw_version) - 1)
2050 				break;
2051 
2052 			memcpy(fw_file->fw_version, data, ie_len);
2053 			fw_file->fw_version[ie_len] = '\0';
2054 
2055 			ath10k_dbg(ar, ATH10K_DBG_BOOT,
2056 				   "found fw version %s\n",
2057 				    fw_file->fw_version);
2058 			break;
2059 		case ATH10K_FW_IE_TIMESTAMP:
2060 			if (ie_len != sizeof(u32))
2061 				break;
2062 
2063 			timestamp = (__le32 *)data;
2064 
2065 			ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n",
2066 				   le32_to_cpup(timestamp));
2067 			break;
2068 		case ATH10K_FW_IE_FEATURES:
2069 			ath10k_dbg(ar, ATH10K_DBG_BOOT,
2070 				   "found firmware features ie (%zd B)\n",
2071 				   ie_len);
2072 
2073 			for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
2074 				index = i / 8;
2075 				bit = i % 8;
2076 
2077 				if (index == ie_len)
2078 					break;
2079 
2080 				if (data[index] & (1 << bit)) {
2081 					ath10k_dbg(ar, ATH10K_DBG_BOOT,
2082 						   "Enabling feature bit: %i\n",
2083 						   i);
2084 					__set_bit(i, fw_file->fw_features);
2085 				}
2086 			}
2087 
2088 			ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "",
2089 					fw_file->fw_features,
2090 					sizeof(fw_file->fw_features));
2091 			break;
2092 		case ATH10K_FW_IE_FW_IMAGE:
2093 			ath10k_dbg(ar, ATH10K_DBG_BOOT,
2094 				   "found fw image ie (%zd B)\n",
2095 				   ie_len);
2096 
2097 			fw_file->firmware_data = data;
2098 			fw_file->firmware_len = ie_len;
2099 
2100 			break;
2101 		case ATH10K_FW_IE_OTP_IMAGE:
2102 			ath10k_dbg(ar, ATH10K_DBG_BOOT,
2103 				   "found otp image ie (%zd B)\n",
2104 				   ie_len);
2105 
2106 			fw_file->otp_data = data;
2107 			fw_file->otp_len = ie_len;
2108 
2109 			break;
2110 		case ATH10K_FW_IE_WMI_OP_VERSION:
2111 			if (ie_len != sizeof(u32))
2112 				break;
2113 
2114 			version = (__le32 *)data;
2115 
2116 			fw_file->wmi_op_version = le32_to_cpup(version);
2117 
2118 			ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n",
2119 				   fw_file->wmi_op_version);
2120 			break;
2121 		case ATH10K_FW_IE_HTT_OP_VERSION:
2122 			if (ie_len != sizeof(u32))
2123 				break;
2124 
2125 			version = (__le32 *)data;
2126 
2127 			fw_file->htt_op_version = le32_to_cpup(version);
2128 
2129 			ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n",
2130 				   fw_file->htt_op_version);
2131 			break;
2132 		case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE:
2133 			ath10k_dbg(ar, ATH10K_DBG_BOOT,
2134 				   "found fw code swap image ie (%zd B)\n",
2135 				   ie_len);
2136 			fw_file->codeswap_data = data;
2137 			fw_file->codeswap_len = ie_len;
2138 			break;
2139 		default:
2140 			ath10k_warn(ar, "Unknown FW IE: %u\n",
2141 				    le32_to_cpu(hdr->id));
2142 			break;
2143 		}
2144 
2145 		/* jump over the padding */
2146 		ie_len = ALIGN(ie_len, 4);
2147 
2148 		len -= ie_len;
2149 		data += ie_len;
2150 	}
2151 
2152 	if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, fw_file->fw_features) &&
2153 	    (!fw_file->firmware_data || !fw_file->firmware_len)) {
2154 		ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n",
2155 			    ar->hw_params.fw.dir, name);
2156 		ret = -ENOMEDIUM;
2157 		goto err;
2158 	}
2159 
2160 	return 0;
2161 
2162 err:
2163 	ath10k_core_free_firmware_files(ar);
2164 	return ret;
2165 }
2166 
ath10k_core_get_fw_name(struct ath10k * ar,char * fw_name,size_t fw_name_len,int fw_api)2167 static void ath10k_core_get_fw_name(struct ath10k *ar, char *fw_name,
2168 				    size_t fw_name_len, int fw_api)
2169 {
2170 	switch (ar->hif.bus) {
2171 	case ATH10K_BUS_SDIO:
2172 	case ATH10K_BUS_USB:
2173 		scnprintf(fw_name, fw_name_len, "%s-%s-%d.bin",
2174 			  ATH10K_FW_FILE_BASE, ath10k_bus_str(ar->hif.bus),
2175 			  fw_api);
2176 		break;
2177 	case ATH10K_BUS_PCI:
2178 	case ATH10K_BUS_AHB:
2179 	case ATH10K_BUS_SNOC:
2180 		scnprintf(fw_name, fw_name_len, "%s-%d.bin",
2181 			  ATH10K_FW_FILE_BASE, fw_api);
2182 		break;
2183 	}
2184 }
2185 
ath10k_core_fetch_firmware_files(struct ath10k * ar)2186 static int ath10k_core_fetch_firmware_files(struct ath10k *ar)
2187 {
2188 	int ret, i;
2189 	char fw_name[100];
2190 
2191 	/* calibration file is optional, don't check for any errors */
2192 	ath10k_fetch_cal_file(ar);
2193 
2194 	for (i = ATH10K_FW_API_MAX; i >= ATH10K_FW_API_MIN; i--) {
2195 		ar->fw_api = i;
2196 		ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n",
2197 			   ar->fw_api);
2198 
2199 		ath10k_core_get_fw_name(ar, fw_name, sizeof(fw_name), ar->fw_api);
2200 		ret = ath10k_core_fetch_firmware_api_n(ar, fw_name,
2201 						       &ar->normal_mode_fw.fw_file);
2202 		if (!ret)
2203 			goto success;
2204 	}
2205 
2206 	/* we end up here if we couldn't fetch any firmware */
2207 
2208 	ath10k_err(ar, "Failed to find firmware-N.bin (N between %d and %d) from %s: %d",
2209 		   ATH10K_FW_API_MIN, ATH10K_FW_API_MAX, ar->hw_params.fw.dir,
2210 		   ret);
2211 
2212 	return ret;
2213 
2214 success:
2215 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api);
2216 
2217 	return 0;
2218 }
2219 
ath10k_core_pre_cal_download(struct ath10k * ar)2220 static int ath10k_core_pre_cal_download(struct ath10k *ar)
2221 {
2222 	int ret;
2223 
2224 	ret = ath10k_download_cal_nvmem(ar, "pre-calibration");
2225 	if (ret == 0) {
2226 		ar->cal_mode = ATH10K_PRE_CAL_MODE_NVMEM;
2227 		goto success;
2228 	} else if (ret == -EPROBE_DEFER) {
2229 		return ret;
2230 	}
2231 
2232 	ath10k_dbg(ar, ATH10K_DBG_BOOT,
2233 		   "boot did not find a pre-calibration nvmem-cell, try file next: %d\n",
2234 		   ret);
2235 
2236 	ret = ath10k_download_cal_file(ar, ar->pre_cal_file);
2237 	if (ret == 0) {
2238 		ar->cal_mode = ATH10K_PRE_CAL_MODE_FILE;
2239 		goto success;
2240 	}
2241 
2242 	ath10k_dbg(ar, ATH10K_DBG_BOOT,
2243 		   "boot did not find a pre calibration file, try DT next: %d\n",
2244 		   ret);
2245 
2246 	ret = ath10k_download_cal_dt(ar, "qcom,ath10k-pre-calibration-data");
2247 	if (ret) {
2248 		ath10k_dbg(ar, ATH10K_DBG_BOOT,
2249 			   "unable to load pre cal data from DT: %d\n", ret);
2250 		return ret;
2251 	}
2252 	ar->cal_mode = ATH10K_PRE_CAL_MODE_DT;
2253 
2254 success:
2255 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
2256 		   ath10k_cal_mode_str(ar->cal_mode));
2257 
2258 	return 0;
2259 }
2260 
ath10k_core_pre_cal_config(struct ath10k * ar)2261 static int ath10k_core_pre_cal_config(struct ath10k *ar)
2262 {
2263 	int ret;
2264 
2265 	ret = ath10k_core_pre_cal_download(ar);
2266 	if (ret) {
2267 		ath10k_dbg(ar, ATH10K_DBG_BOOT,
2268 			   "failed to load pre cal data: %d\n", ret);
2269 		return ret;
2270 	}
2271 
2272 	ret = ath10k_core_get_board_id_from_otp(ar);
2273 	if (ret) {
2274 		ath10k_err(ar, "failed to get board id: %d\n", ret);
2275 		return ret;
2276 	}
2277 
2278 	ret = ath10k_download_and_run_otp(ar);
2279 	if (ret) {
2280 		ath10k_err(ar, "failed to run otp: %d\n", ret);
2281 		return ret;
2282 	}
2283 
2284 	ath10k_dbg(ar, ATH10K_DBG_BOOT,
2285 		   "pre cal configuration done successfully\n");
2286 
2287 	return 0;
2288 }
2289 
ath10k_download_cal_data(struct ath10k * ar)2290 static int ath10k_download_cal_data(struct ath10k *ar)
2291 {
2292 	int ret;
2293 
2294 	ret = ath10k_core_pre_cal_config(ar);
2295 	if (ret == 0)
2296 		return 0;
2297 
2298 	ath10k_dbg(ar, ATH10K_DBG_BOOT,
2299 		   "pre cal download procedure failed, try cal file: %d\n",
2300 		   ret);
2301 
2302 	ret = ath10k_download_cal_nvmem(ar, "calibration");
2303 	if (ret == 0) {
2304 		ar->cal_mode = ATH10K_CAL_MODE_NVMEM;
2305 		goto done;
2306 	} else if (ret == -EPROBE_DEFER) {
2307 		return ret;
2308 	}
2309 
2310 	ath10k_dbg(ar, ATH10K_DBG_BOOT,
2311 		   "boot did not find a calibration nvmem-cell, try file next: %d\n",
2312 		   ret);
2313 
2314 	ret = ath10k_download_cal_file(ar, ar->cal_file);
2315 	if (ret == 0) {
2316 		ar->cal_mode = ATH10K_CAL_MODE_FILE;
2317 		goto done;
2318 	}
2319 
2320 	ath10k_dbg(ar, ATH10K_DBG_BOOT,
2321 		   "boot did not find a calibration file, try DT next: %d\n",
2322 		   ret);
2323 
2324 	ret = ath10k_download_cal_dt(ar, "qcom,ath10k-calibration-data");
2325 	if (ret == 0) {
2326 		ar->cal_mode = ATH10K_CAL_MODE_DT;
2327 		goto done;
2328 	}
2329 
2330 	ath10k_dbg(ar, ATH10K_DBG_BOOT,
2331 		   "boot did not find DT entry, try target EEPROM next: %d\n",
2332 		   ret);
2333 
2334 	ret = ath10k_download_cal_eeprom(ar);
2335 	if (ret == 0) {
2336 		ar->cal_mode = ATH10K_CAL_MODE_EEPROM;
2337 		goto done;
2338 	}
2339 
2340 	ath10k_dbg(ar, ATH10K_DBG_BOOT,
2341 		   "boot did not find target EEPROM entry, try OTP next: %d\n",
2342 		   ret);
2343 
2344 	ret = ath10k_download_and_run_otp(ar);
2345 	if (ret) {
2346 		ath10k_err(ar, "failed to run otp: %d\n", ret);
2347 		return ret;
2348 	}
2349 
2350 	ar->cal_mode = ATH10K_CAL_MODE_OTP;
2351 
2352 done:
2353 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
2354 		   ath10k_cal_mode_str(ar->cal_mode));
2355 	return 0;
2356 }
2357 
ath10k_core_fetch_btcoex_dt(struct ath10k * ar)2358 static void ath10k_core_fetch_btcoex_dt(struct ath10k *ar)
2359 {
2360 	struct device_node *node;
2361 	u8 coex_support = 0;
2362 	int ret;
2363 
2364 	node = ar->dev->of_node;
2365 	if (!node)
2366 		goto out;
2367 
2368 	ret = of_property_read_u8(node, "qcom,coexist-support", &coex_support);
2369 	if (ret) {
2370 		ar->coex_support = true;
2371 		goto out;
2372 	}
2373 
2374 	if (coex_support) {
2375 		ar->coex_support = true;
2376 	} else {
2377 		ar->coex_support = false;
2378 		ar->coex_gpio_pin = -1;
2379 		goto out;
2380 	}
2381 
2382 	ret = of_property_read_u32(node, "qcom,coexist-gpio-pin",
2383 				   &ar->coex_gpio_pin);
2384 	if (ret)
2385 		ar->coex_gpio_pin = -1;
2386 
2387 out:
2388 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot coex_support %d coex_gpio_pin %d\n",
2389 		   ar->coex_support, ar->coex_gpio_pin);
2390 }
2391 
ath10k_init_uart(struct ath10k * ar)2392 static int ath10k_init_uart(struct ath10k *ar)
2393 {
2394 	int ret;
2395 
2396 	/*
2397 	 * Explicitly setting UART prints to zero as target turns it on
2398 	 * based on scratch registers.
2399 	 */
2400 	ret = ath10k_bmi_write32(ar, hi_serial_enable, 0);
2401 	if (ret) {
2402 		ath10k_warn(ar, "could not disable UART prints (%d)\n", ret);
2403 		return ret;
2404 	}
2405 
2406 	if (!uart_print) {
2407 		if (ar->hw_params.uart_pin_workaround) {
2408 			ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin,
2409 						 ar->hw_params.uart_pin);
2410 			if (ret) {
2411 				ath10k_warn(ar, "failed to set UART TX pin: %d",
2412 					    ret);
2413 				return ret;
2414 			}
2415 		}
2416 
2417 		return 0;
2418 	}
2419 
2420 	ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, ar->hw_params.uart_pin);
2421 	if (ret) {
2422 		ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
2423 		return ret;
2424 	}
2425 
2426 	ret = ath10k_bmi_write32(ar, hi_serial_enable, 1);
2427 	if (ret) {
2428 		ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
2429 		return ret;
2430 	}
2431 
2432 	/* Set the UART baud rate to 19200. */
2433 	ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200);
2434 	if (ret) {
2435 		ath10k_warn(ar, "could not set the baud rate (%d)\n", ret);
2436 		return ret;
2437 	}
2438 
2439 	ath10k_info(ar, "UART prints enabled\n");
2440 	return 0;
2441 }
2442 
ath10k_init_hw_params(struct ath10k * ar)2443 static int ath10k_init_hw_params(struct ath10k *ar)
2444 {
2445 	const struct ath10k_hw_params *hw_params;
2446 	int i;
2447 
2448 	for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) {
2449 		hw_params = &ath10k_hw_params_list[i];
2450 
2451 		if (hw_params->bus == ar->hif.bus &&
2452 		    hw_params->id == ar->target_version &&
2453 		    hw_params->dev_id == ar->dev_id)
2454 			break;
2455 	}
2456 
2457 	if (i == ARRAY_SIZE(ath10k_hw_params_list)) {
2458 		ath10k_err(ar, "Unsupported hardware version: 0x%x\n",
2459 			   ar->target_version);
2460 		return -EINVAL;
2461 	}
2462 
2463 	ar->hw_params = *hw_params;
2464 
2465 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n",
2466 		   ar->hw_params.name, ar->target_version);
2467 
2468 	return 0;
2469 }
2470 
ath10k_core_start_recovery(struct ath10k * ar)2471 void ath10k_core_start_recovery(struct ath10k *ar)
2472 {
2473 	if (test_and_set_bit(ATH10K_FLAG_RESTARTING, &ar->dev_flags)) {
2474 		ath10k_warn(ar, "already restarting\n");
2475 		return;
2476 	}
2477 
2478 	queue_work(ar->workqueue, &ar->restart_work);
2479 }
2480 EXPORT_SYMBOL(ath10k_core_start_recovery);
2481 
ath10k_core_napi_enable(struct ath10k * ar)2482 void ath10k_core_napi_enable(struct ath10k *ar)
2483 {
2484 	lockdep_assert_held(&ar->conf_mutex);
2485 
2486 	if (test_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags))
2487 		return;
2488 
2489 	napi_enable(&ar->napi);
2490 	set_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags);
2491 }
2492 EXPORT_SYMBOL(ath10k_core_napi_enable);
2493 
ath10k_core_napi_sync_disable(struct ath10k * ar)2494 void ath10k_core_napi_sync_disable(struct ath10k *ar)
2495 {
2496 	lockdep_assert_held(&ar->conf_mutex);
2497 
2498 	if (!test_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags))
2499 		return;
2500 
2501 	napi_synchronize(&ar->napi);
2502 	napi_disable(&ar->napi);
2503 	clear_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags);
2504 }
2505 EXPORT_SYMBOL(ath10k_core_napi_sync_disable);
2506 
ath10k_core_restart(struct work_struct * work)2507 static void ath10k_core_restart(struct work_struct *work)
2508 {
2509 	struct ath10k *ar = container_of(work, struct ath10k, restart_work);
2510 	int ret;
2511 
2512 	set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
2513 
2514 	/* Place a barrier to make sure the compiler doesn't reorder
2515 	 * CRASH_FLUSH and calling other functions.
2516 	 */
2517 	barrier();
2518 
2519 	ieee80211_stop_queues(ar->hw);
2520 	ath10k_drain_tx(ar);
2521 	complete(&ar->scan.started);
2522 	complete(&ar->scan.completed);
2523 	complete(&ar->scan.on_channel);
2524 	complete(&ar->offchan_tx_completed);
2525 	complete(&ar->install_key_done);
2526 	complete(&ar->vdev_setup_done);
2527 	complete(&ar->vdev_delete_done);
2528 	complete(&ar->thermal.wmi_sync);
2529 	complete(&ar->bss_survey_done);
2530 	wake_up(&ar->htt.empty_tx_wq);
2531 	wake_up(&ar->wmi.tx_credits_wq);
2532 	wake_up(&ar->peer_mapping_wq);
2533 
2534 	/* TODO: We can have one instance of cancelling coverage_class_work by
2535 	 * moving it to ath10k_halt(), so that both stop() and restart() would
2536 	 * call that but it takes conf_mutex() and if we call cancel_work_sync()
2537 	 * with conf_mutex it will deadlock.
2538 	 */
2539 	cancel_work_sync(&ar->set_coverage_class_work);
2540 
2541 	mutex_lock(&ar->conf_mutex);
2542 
2543 	switch (ar->state) {
2544 	case ATH10K_STATE_ON:
2545 		ar->state = ATH10K_STATE_RESTARTING;
2546 		ath10k_halt(ar);
2547 		ath10k_scan_finish(ar);
2548 		ieee80211_restart_hw(ar->hw);
2549 		break;
2550 	case ATH10K_STATE_OFF:
2551 		/* this can happen if driver is being unloaded
2552 		 * or if the crash happens during FW probing
2553 		 */
2554 		ath10k_warn(ar, "cannot restart a device that hasn't been started\n");
2555 		break;
2556 	case ATH10K_STATE_RESTARTING:
2557 		/* hw restart might be requested from multiple places */
2558 		break;
2559 	case ATH10K_STATE_RESTARTED:
2560 		ar->state = ATH10K_STATE_WEDGED;
2561 		fallthrough;
2562 	case ATH10K_STATE_WEDGED:
2563 		ath10k_warn(ar, "device is wedged, will not restart\n");
2564 		break;
2565 	case ATH10K_STATE_UTF:
2566 		ath10k_warn(ar, "firmware restart in UTF mode not supported\n");
2567 		break;
2568 	}
2569 
2570 	mutex_unlock(&ar->conf_mutex);
2571 
2572 	ret = ath10k_coredump_submit(ar);
2573 	if (ret)
2574 		ath10k_warn(ar, "failed to send firmware crash dump via devcoredump: %d",
2575 			    ret);
2576 
2577 	complete(&ar->driver_recovery);
2578 }
2579 
ath10k_core_set_coverage_class_work(struct work_struct * work)2580 static void ath10k_core_set_coverage_class_work(struct work_struct *work)
2581 {
2582 	struct ath10k *ar = container_of(work, struct ath10k,
2583 					 set_coverage_class_work);
2584 
2585 	if (ar->hw_params.hw_ops->set_coverage_class)
2586 		ar->hw_params.hw_ops->set_coverage_class(ar, -1);
2587 }
2588 
ath10k_core_init_firmware_features(struct ath10k * ar)2589 static int ath10k_core_init_firmware_features(struct ath10k *ar)
2590 {
2591 	struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file;
2592 	int max_num_peers;
2593 
2594 	if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, fw_file->fw_features) &&
2595 	    !test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) {
2596 		ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well");
2597 		return -EINVAL;
2598 	}
2599 
2600 	if (fw_file->wmi_op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) {
2601 		ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n",
2602 			   ATH10K_FW_WMI_OP_VERSION_MAX, fw_file->wmi_op_version);
2603 		return -EINVAL;
2604 	}
2605 
2606 	ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_NATIVE_WIFI;
2607 	switch (ath10k_cryptmode_param) {
2608 	case ATH10K_CRYPT_MODE_HW:
2609 		clear_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
2610 		clear_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
2611 		break;
2612 	case ATH10K_CRYPT_MODE_SW:
2613 		if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
2614 			      fw_file->fw_features)) {
2615 			ath10k_err(ar, "cryptmode > 0 requires raw mode support from firmware");
2616 			return -EINVAL;
2617 		}
2618 
2619 		set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
2620 		set_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
2621 		break;
2622 	default:
2623 		ath10k_info(ar, "invalid cryptmode: %d\n",
2624 			    ath10k_cryptmode_param);
2625 		return -EINVAL;
2626 	}
2627 
2628 	ar->htt.max_num_amsdu = ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT;
2629 	ar->htt.max_num_ampdu = ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT;
2630 
2631 	if (ath10k_frame_mode == ATH10K_HW_TXRX_RAW) {
2632 		if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
2633 			      fw_file->fw_features)) {
2634 			ath10k_err(ar, "rawmode = 1 requires support from firmware");
2635 			return -EINVAL;
2636 		}
2637 		set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
2638 	}
2639 
2640 	if (test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) {
2641 		ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_RAW;
2642 
2643 		/* Workaround:
2644 		 *
2645 		 * Firmware A-MSDU aggregation breaks with RAW Tx encap mode
2646 		 * and causes enormous performance issues (malformed frames,
2647 		 * etc).
2648 		 *
2649 		 * Disabling A-MSDU makes RAW mode stable with heavy traffic
2650 		 * albeit a bit slower compared to regular operation.
2651 		 */
2652 		ar->htt.max_num_amsdu = 1;
2653 	}
2654 
2655 	/* Backwards compatibility for firmwares without
2656 	 * ATH10K_FW_IE_WMI_OP_VERSION.
2657 	 */
2658 	if (fw_file->wmi_op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) {
2659 		if (test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) {
2660 			if (test_bit(ATH10K_FW_FEATURE_WMI_10_2,
2661 				     fw_file->fw_features))
2662 				fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_2;
2663 			else
2664 				fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_1;
2665 		} else {
2666 			fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_MAIN;
2667 		}
2668 	}
2669 
2670 	switch (fw_file->wmi_op_version) {
2671 	case ATH10K_FW_WMI_OP_VERSION_MAIN:
2672 		max_num_peers = TARGET_NUM_PEERS;
2673 		ar->max_num_stations = TARGET_NUM_STATIONS;
2674 		ar->max_num_vdevs = TARGET_NUM_VDEVS;
2675 		ar->htt.max_num_pending_tx = TARGET_NUM_MSDU_DESC;
2676 		ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV |
2677 			WMI_STAT_PEER;
2678 		ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
2679 		break;
2680 	case ATH10K_FW_WMI_OP_VERSION_10_1:
2681 	case ATH10K_FW_WMI_OP_VERSION_10_2:
2682 	case ATH10K_FW_WMI_OP_VERSION_10_2_4:
2683 		if (ath10k_peer_stats_enabled(ar)) {
2684 			max_num_peers = TARGET_10X_TX_STATS_NUM_PEERS;
2685 			ar->max_num_stations = TARGET_10X_TX_STATS_NUM_STATIONS;
2686 		} else {
2687 			max_num_peers = TARGET_10X_NUM_PEERS;
2688 			ar->max_num_stations = TARGET_10X_NUM_STATIONS;
2689 		}
2690 		ar->max_num_vdevs = TARGET_10X_NUM_VDEVS;
2691 		ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC;
2692 		ar->fw_stats_req_mask = WMI_STAT_PEER;
2693 		ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
2694 		break;
2695 	case ATH10K_FW_WMI_OP_VERSION_TLV:
2696 		max_num_peers = TARGET_TLV_NUM_PEERS;
2697 		ar->max_num_stations = TARGET_TLV_NUM_STATIONS;
2698 		ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS;
2699 		ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS;
2700 		if (ar->hif.bus == ATH10K_BUS_SDIO)
2701 			ar->htt.max_num_pending_tx =
2702 				TARGET_TLV_NUM_MSDU_DESC_HL;
2703 		else
2704 			ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC;
2705 		ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS;
2706 		ar->fw_stats_req_mask = WMI_TLV_STAT_PDEV | WMI_TLV_STAT_VDEV |
2707 			WMI_TLV_STAT_PEER | WMI_TLV_STAT_PEER_EXTD;
2708 		ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
2709 		ar->wmi.mgmt_max_num_pending_tx = TARGET_TLV_MGMT_NUM_MSDU_DESC;
2710 		break;
2711 	case ATH10K_FW_WMI_OP_VERSION_10_4:
2712 		max_num_peers = TARGET_10_4_NUM_PEERS;
2713 		ar->max_num_stations = TARGET_10_4_NUM_STATIONS;
2714 		ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS;
2715 		ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS;
2716 		ar->num_tids = TARGET_10_4_TGT_NUM_TIDS;
2717 		ar->fw_stats_req_mask = WMI_10_4_STAT_PEER |
2718 					WMI_10_4_STAT_PEER_EXTD |
2719 					WMI_10_4_STAT_VDEV_EXTD;
2720 		ar->max_spatial_stream = ar->hw_params.max_spatial_stream;
2721 		ar->max_num_tdls_vdevs = TARGET_10_4_NUM_TDLS_VDEVS;
2722 
2723 		if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL,
2724 			     fw_file->fw_features))
2725 			ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC_PFC;
2726 		else
2727 			ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC;
2728 		break;
2729 	case ATH10K_FW_WMI_OP_VERSION_UNSET:
2730 	case ATH10K_FW_WMI_OP_VERSION_MAX:
2731 	default:
2732 		WARN_ON(1);
2733 		return -EINVAL;
2734 	}
2735 
2736 	if (ar->hw_params.num_peers)
2737 		ar->max_num_peers = ar->hw_params.num_peers;
2738 	else
2739 		ar->max_num_peers = max_num_peers;
2740 
2741 	/* Backwards compatibility for firmwares without
2742 	 * ATH10K_FW_IE_HTT_OP_VERSION.
2743 	 */
2744 	if (fw_file->htt_op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) {
2745 		switch (fw_file->wmi_op_version) {
2746 		case ATH10K_FW_WMI_OP_VERSION_MAIN:
2747 			fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_MAIN;
2748 			break;
2749 		case ATH10K_FW_WMI_OP_VERSION_10_1:
2750 		case ATH10K_FW_WMI_OP_VERSION_10_2:
2751 		case ATH10K_FW_WMI_OP_VERSION_10_2_4:
2752 			fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_10_1;
2753 			break;
2754 		case ATH10K_FW_WMI_OP_VERSION_TLV:
2755 			fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_TLV;
2756 			break;
2757 		case ATH10K_FW_WMI_OP_VERSION_10_4:
2758 		case ATH10K_FW_WMI_OP_VERSION_UNSET:
2759 		case ATH10K_FW_WMI_OP_VERSION_MAX:
2760 			ath10k_err(ar, "htt op version not found from fw meta data");
2761 			return -EINVAL;
2762 		}
2763 	}
2764 
2765 	return 0;
2766 }
2767 
ath10k_core_reset_rx_filter(struct ath10k * ar)2768 static int ath10k_core_reset_rx_filter(struct ath10k *ar)
2769 {
2770 	int ret;
2771 	int vdev_id;
2772 	int vdev_type;
2773 	int vdev_subtype;
2774 	const u8 *vdev_addr;
2775 
2776 	vdev_id = 0;
2777 	vdev_type = WMI_VDEV_TYPE_STA;
2778 	vdev_subtype = ath10k_wmi_get_vdev_subtype(ar, WMI_VDEV_SUBTYPE_NONE);
2779 	vdev_addr = ar->mac_addr;
2780 
2781 	ret = ath10k_wmi_vdev_create(ar, vdev_id, vdev_type, vdev_subtype,
2782 				     vdev_addr);
2783 	if (ret) {
2784 		ath10k_err(ar, "failed to create dummy vdev: %d\n", ret);
2785 		return ret;
2786 	}
2787 
2788 	ret = ath10k_wmi_vdev_delete(ar, vdev_id);
2789 	if (ret) {
2790 		ath10k_err(ar, "failed to delete dummy vdev: %d\n", ret);
2791 		return ret;
2792 	}
2793 
2794 	/* WMI and HTT may use separate HIF pipes and are not guaranteed to be
2795 	 * serialized properly implicitly.
2796 	 *
2797 	 * Moreover (most) WMI commands have no explicit acknowledges. It is
2798 	 * possible to infer it implicitly by poking firmware with echo
2799 	 * command - getting a reply means all preceding comments have been
2800 	 * (mostly) processed.
2801 	 *
2802 	 * In case of vdev create/delete this is sufficient.
2803 	 *
2804 	 * Without this it's possible to end up with a race when HTT Rx ring is
2805 	 * started before vdev create/delete hack is complete allowing a short
2806 	 * window of opportunity to receive (and Tx ACK) a bunch of frames.
2807 	 */
2808 	ret = ath10k_wmi_barrier(ar);
2809 	if (ret) {
2810 		ath10k_err(ar, "failed to ping firmware: %d\n", ret);
2811 		return ret;
2812 	}
2813 
2814 	return 0;
2815 }
2816 
ath10k_core_compat_services(struct ath10k * ar)2817 static int ath10k_core_compat_services(struct ath10k *ar)
2818 {
2819 	struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file;
2820 
2821 	/* all 10.x firmware versions support thermal throttling but don't
2822 	 * advertise the support via service flags so we have to hardcode
2823 	 * it here
2824 	 */
2825 	switch (fw_file->wmi_op_version) {
2826 	case ATH10K_FW_WMI_OP_VERSION_10_1:
2827 	case ATH10K_FW_WMI_OP_VERSION_10_2:
2828 	case ATH10K_FW_WMI_OP_VERSION_10_2_4:
2829 	case ATH10K_FW_WMI_OP_VERSION_10_4:
2830 		set_bit(WMI_SERVICE_THERM_THROT, ar->wmi.svc_map);
2831 		break;
2832 	default:
2833 		break;
2834 	}
2835 
2836 	return 0;
2837 }
2838 
2839 #define TGT_IRAM_READ_PER_ITR (8 * 1024)
2840 
ath10k_core_copy_target_iram(struct ath10k * ar)2841 static int ath10k_core_copy_target_iram(struct ath10k *ar)
2842 {
2843 	const struct ath10k_hw_mem_layout *hw_mem;
2844 	const struct ath10k_mem_region *tmp, *mem_region = NULL;
2845 	dma_addr_t paddr;
2846 	void *vaddr = NULL;
2847 	u8 num_read_itr;
2848 	int i, ret;
2849 	u32 len, remaining_len;
2850 
2851 	/* copy target iram feature must work also when
2852 	 * ATH10K_FW_CRASH_DUMP_RAM_DATA is disabled, so
2853 	 * _ath10k_coredump_get_mem_layout() to accomplist that
2854 	 */
2855 	hw_mem = _ath10k_coredump_get_mem_layout(ar);
2856 	if (!hw_mem)
2857 		/* if CONFIG_DEV_COREDUMP is disabled we get NULL, then
2858 		 * just silently disable the feature by doing nothing
2859 		 */
2860 		return 0;
2861 
2862 	for (i = 0; i < hw_mem->region_table.size; i++) {
2863 		tmp = &hw_mem->region_table.regions[i];
2864 		if (tmp->type == ATH10K_MEM_REGION_TYPE_REG) {
2865 			mem_region = tmp;
2866 			break;
2867 		}
2868 	}
2869 
2870 	if (!mem_region)
2871 		return -ENOMEM;
2872 
2873 	for (i = 0; i < ar->wmi.num_mem_chunks; i++) {
2874 		if (ar->wmi.mem_chunks[i].req_id ==
2875 		    WMI_IRAM_RECOVERY_HOST_MEM_REQ_ID) {
2876 			vaddr = ar->wmi.mem_chunks[i].vaddr;
2877 			len = ar->wmi.mem_chunks[i].len;
2878 			break;
2879 		}
2880 	}
2881 
2882 	if (!vaddr || !len) {
2883 		ath10k_warn(ar, "No allocated memory for IRAM back up");
2884 		return -ENOMEM;
2885 	}
2886 
2887 	len = (len < mem_region->len) ? len : mem_region->len;
2888 	paddr = mem_region->start;
2889 	num_read_itr = len / TGT_IRAM_READ_PER_ITR;
2890 	remaining_len = len % TGT_IRAM_READ_PER_ITR;
2891 	for (i = 0; i < num_read_itr; i++) {
2892 		ret = ath10k_hif_diag_read(ar, paddr, vaddr,
2893 					   TGT_IRAM_READ_PER_ITR);
2894 		if (ret) {
2895 			ath10k_warn(ar, "failed to copy firmware IRAM contents: %d",
2896 				    ret);
2897 			return ret;
2898 		}
2899 
2900 		paddr += TGT_IRAM_READ_PER_ITR;
2901 		vaddr += TGT_IRAM_READ_PER_ITR;
2902 	}
2903 
2904 	if (remaining_len) {
2905 		ret = ath10k_hif_diag_read(ar, paddr, vaddr, remaining_len);
2906 		if (ret) {
2907 			ath10k_warn(ar, "failed to copy firmware IRAM contents: %d",
2908 				    ret);
2909 			return ret;
2910 		}
2911 	}
2912 
2913 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "target IRAM back up completed\n");
2914 
2915 	return 0;
2916 }
2917 
ath10k_core_start(struct ath10k * ar,enum ath10k_firmware_mode mode,const struct ath10k_fw_components * fw)2918 int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode,
2919 		      const struct ath10k_fw_components *fw)
2920 {
2921 	int status;
2922 	u32 val;
2923 
2924 	lockdep_assert_held(&ar->conf_mutex);
2925 
2926 	clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
2927 
2928 	ar->running_fw = fw;
2929 
2930 	if (!test_bit(ATH10K_FW_FEATURE_NON_BMI,
2931 		      ar->running_fw->fw_file.fw_features)) {
2932 		ath10k_bmi_start(ar);
2933 
2934 		/* Enable hardware clock to speed up firmware download */
2935 		if (ar->hw_params.hw_ops->enable_pll_clk) {
2936 			status = ar->hw_params.hw_ops->enable_pll_clk(ar);
2937 			ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot enable pll ret %d\n",
2938 				   status);
2939 		}
2940 
2941 		if (ath10k_init_configure_target(ar)) {
2942 			status = -EINVAL;
2943 			goto err;
2944 		}
2945 
2946 		status = ath10k_download_cal_data(ar);
2947 		if (status)
2948 			goto err;
2949 
2950 		/* Some of qca988x solutions are having global reset issue
2951 		 * during target initialization. Bypassing PLL setting before
2952 		 * downloading firmware and letting the SoC run on REF_CLK is
2953 		 * fixing the problem. Corresponding firmware change is also
2954 		 * needed to set the clock source once the target is
2955 		 * initialized.
2956 		 */
2957 		if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT,
2958 			     ar->running_fw->fw_file.fw_features)) {
2959 			status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1);
2960 			if (status) {
2961 				ath10k_err(ar, "could not write to skip_clock_init: %d\n",
2962 					   status);
2963 				goto err;
2964 			}
2965 		}
2966 
2967 		status = ath10k_download_fw(ar);
2968 		if (status)
2969 			goto err;
2970 
2971 		status = ath10k_init_uart(ar);
2972 		if (status)
2973 			goto err;
2974 
2975 		if (ar->hif.bus == ATH10K_BUS_SDIO) {
2976 			status = ath10k_init_sdio(ar, mode);
2977 			if (status) {
2978 				ath10k_err(ar, "failed to init SDIO: %d\n", status);
2979 				goto err;
2980 			}
2981 		}
2982 	}
2983 
2984 	ar->htc.htc_ops.target_send_suspend_complete =
2985 		ath10k_send_suspend_complete;
2986 
2987 	status = ath10k_htc_init(ar);
2988 	if (status) {
2989 		ath10k_err(ar, "could not init HTC (%d)\n", status);
2990 		goto err;
2991 	}
2992 
2993 	if (!test_bit(ATH10K_FW_FEATURE_NON_BMI,
2994 		      ar->running_fw->fw_file.fw_features)) {
2995 		status = ath10k_bmi_done(ar);
2996 		if (status)
2997 			goto err;
2998 	}
2999 
3000 	status = ath10k_wmi_attach(ar);
3001 	if (status) {
3002 		ath10k_err(ar, "WMI attach failed: %d\n", status);
3003 		goto err;
3004 	}
3005 
3006 	status = ath10k_htt_init(ar);
3007 	if (status) {
3008 		ath10k_err(ar, "failed to init htt: %d\n", status);
3009 		goto err_wmi_detach;
3010 	}
3011 
3012 	status = ath10k_htt_tx_start(&ar->htt);
3013 	if (status) {
3014 		ath10k_err(ar, "failed to alloc htt tx: %d\n", status);
3015 		goto err_wmi_detach;
3016 	}
3017 
3018 	/* If firmware indicates Full Rx Reorder support it must be used in a
3019 	 * slightly different manner. Let HTT code know.
3020 	 */
3021 	ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER,
3022 						ar->wmi.svc_map));
3023 
3024 	status = ath10k_htt_rx_alloc(&ar->htt);
3025 	if (status) {
3026 		ath10k_err(ar, "failed to alloc htt rx: %d\n", status);
3027 		goto err_htt_tx_detach;
3028 	}
3029 
3030 	status = ath10k_hif_start(ar);
3031 	if (status) {
3032 		ath10k_err(ar, "could not start HIF: %d\n", status);
3033 		goto err_htt_rx_detach;
3034 	}
3035 
3036 	status = ath10k_htc_wait_target(&ar->htc);
3037 	if (status) {
3038 		ath10k_err(ar, "failed to connect to HTC: %d\n", status);
3039 		goto err_hif_stop;
3040 	}
3041 
3042 	status = ath10k_hif_start_post(ar);
3043 	if (status) {
3044 		ath10k_err(ar, "failed to swap mailbox: %d\n", status);
3045 		goto err_hif_stop;
3046 	}
3047 
3048 	if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
3049 		status = ath10k_htt_connect(&ar->htt);
3050 		if (status) {
3051 			ath10k_err(ar, "failed to connect htt (%d)\n", status);
3052 			goto err_hif_stop;
3053 		}
3054 	}
3055 
3056 	status = ath10k_wmi_connect(ar);
3057 	if (status) {
3058 		ath10k_err(ar, "could not connect wmi: %d\n", status);
3059 		goto err_hif_stop;
3060 	}
3061 
3062 	status = ath10k_htc_start(&ar->htc);
3063 	if (status) {
3064 		ath10k_err(ar, "failed to start htc: %d\n", status);
3065 		goto err_hif_stop;
3066 	}
3067 
3068 	if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
3069 		status = ath10k_wmi_wait_for_service_ready(ar);
3070 		if (status) {
3071 			ath10k_warn(ar, "wmi service ready event not received");
3072 			goto err_hif_stop;
3073 		}
3074 	}
3075 
3076 	ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n",
3077 		   ar->hw->wiphy->fw_version);
3078 
3079 	if (test_bit(ATH10K_FW_FEATURE_IRAM_RECOVERY,
3080 		     ar->running_fw->fw_file.fw_features)) {
3081 		status = ath10k_core_copy_target_iram(ar);
3082 		if (status) {
3083 			ath10k_warn(ar, "failed to copy target iram contents: %d",
3084 				    status);
3085 			goto err_hif_stop;
3086 		}
3087 	}
3088 
3089 	if (test_bit(WMI_SERVICE_EXT_RES_CFG_SUPPORT, ar->wmi.svc_map) &&
3090 	    mode == ATH10K_FIRMWARE_MODE_NORMAL) {
3091 		val = 0;
3092 		if (ath10k_peer_stats_enabled(ar))
3093 			val = WMI_10_4_PEER_STATS;
3094 
3095 		/* Enable vdev stats by default */
3096 		val |= WMI_10_4_VDEV_STATS;
3097 
3098 		if (test_bit(WMI_SERVICE_BSS_CHANNEL_INFO_64, ar->wmi.svc_map))
3099 			val |= WMI_10_4_BSS_CHANNEL_INFO_64;
3100 
3101 		ath10k_core_fetch_btcoex_dt(ar);
3102 
3103 		/* 10.4 firmware supports BT-Coex without reloading firmware
3104 		 * via pdev param. To support Bluetooth coexistence pdev param,
3105 		 * WMI_COEX_GPIO_SUPPORT of extended resource config should be
3106 		 * enabled always.
3107 		 *
3108 		 * We can still enable BTCOEX if firmware has the support
3109 		 * even though btceox_support value is
3110 		 * ATH10K_DT_BTCOEX_NOT_FOUND
3111 		 */
3112 
3113 		if (test_bit(WMI_SERVICE_COEX_GPIO, ar->wmi.svc_map) &&
3114 		    test_bit(ATH10K_FW_FEATURE_BTCOEX_PARAM,
3115 			     ar->running_fw->fw_file.fw_features) &&
3116 		    ar->coex_support)
3117 			val |= WMI_10_4_COEX_GPIO_SUPPORT;
3118 
3119 		if (test_bit(WMI_SERVICE_TDLS_EXPLICIT_MODE_ONLY,
3120 			     ar->wmi.svc_map))
3121 			val |= WMI_10_4_TDLS_EXPLICIT_MODE_ONLY;
3122 
3123 		if (test_bit(WMI_SERVICE_TDLS_UAPSD_BUFFER_STA,
3124 			     ar->wmi.svc_map))
3125 			val |= WMI_10_4_TDLS_UAPSD_BUFFER_STA;
3126 
3127 		if (test_bit(WMI_SERVICE_TX_DATA_ACK_RSSI,
3128 			     ar->wmi.svc_map))
3129 			val |= WMI_10_4_TX_DATA_ACK_RSSI;
3130 
3131 		if (test_bit(WMI_SERVICE_REPORT_AIRTIME, ar->wmi.svc_map))
3132 			val |= WMI_10_4_REPORT_AIRTIME;
3133 
3134 		if (test_bit(WMI_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT,
3135 			     ar->wmi.svc_map))
3136 			val |= WMI_10_4_EXT_PEER_TID_CONFIGS_SUPPORT;
3137 
3138 		status = ath10k_mac_ext_resource_config(ar, val);
3139 		if (status) {
3140 			ath10k_err(ar,
3141 				   "failed to send ext resource cfg command : %d\n",
3142 				   status);
3143 			goto err_hif_stop;
3144 		}
3145 	}
3146 
3147 	status = ath10k_wmi_cmd_init(ar);
3148 	if (status) {
3149 		ath10k_err(ar, "could not send WMI init command (%d)\n",
3150 			   status);
3151 		goto err_hif_stop;
3152 	}
3153 
3154 	status = ath10k_wmi_wait_for_unified_ready(ar);
3155 	if (status) {
3156 		ath10k_err(ar, "wmi unified ready event not received\n");
3157 		goto err_hif_stop;
3158 	}
3159 
3160 	status = ath10k_core_compat_services(ar);
3161 	if (status) {
3162 		ath10k_err(ar, "compat services failed: %d\n", status);
3163 		goto err_hif_stop;
3164 	}
3165 
3166 	status = ath10k_wmi_pdev_set_base_macaddr(ar, ar->mac_addr);
3167 	if (status && status != -EOPNOTSUPP) {
3168 		ath10k_err(ar,
3169 			   "failed to set base mac address: %d\n", status);
3170 		goto err_hif_stop;
3171 	}
3172 
3173 	/* Some firmware revisions do not properly set up hardware rx filter
3174 	 * registers.
3175 	 *
3176 	 * A known example from QCA9880 and 10.2.4 is that MAC_PCU_ADDR1_MASK
3177 	 * is filled with 0s instead of 1s allowing HW to respond with ACKs to
3178 	 * any frames that matches MAC_PCU_RX_FILTER which is also
3179 	 * misconfigured to accept anything.
3180 	 *
3181 	 * The ADDR1 is programmed using internal firmware structure field and
3182 	 * can't be (easily/sanely) reached from the driver explicitly. It is
3183 	 * possible to implicitly make it correct by creating a dummy vdev and
3184 	 * then deleting it.
3185 	 */
3186 	if (ar->hw_params.hw_filter_reset_required &&
3187 	    mode == ATH10K_FIRMWARE_MODE_NORMAL) {
3188 		status = ath10k_core_reset_rx_filter(ar);
3189 		if (status) {
3190 			ath10k_err(ar,
3191 				   "failed to reset rx filter: %d\n", status);
3192 			goto err_hif_stop;
3193 		}
3194 	}
3195 
3196 	status = ath10k_htt_rx_ring_refill(ar);
3197 	if (status) {
3198 		ath10k_err(ar, "failed to refill htt rx ring: %d\n", status);
3199 		goto err_hif_stop;
3200 	}
3201 
3202 	if (ar->max_num_vdevs >= 64)
3203 		ar->free_vdev_map = 0xFFFFFFFFFFFFFFFFLL;
3204 	else
3205 		ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1;
3206 
3207 	INIT_LIST_HEAD(&ar->arvifs);
3208 
3209 	/* we don't care about HTT in UTF mode */
3210 	if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
3211 		status = ath10k_htt_setup(&ar->htt);
3212 		if (status) {
3213 			ath10k_err(ar, "failed to setup htt: %d\n", status);
3214 			goto err_hif_stop;
3215 		}
3216 	}
3217 
3218 	status = ath10k_debug_start(ar);
3219 	if (status)
3220 		goto err_hif_stop;
3221 
3222 	status = ath10k_hif_set_target_log_mode(ar, fw_diag_log);
3223 	if (status && status != -EOPNOTSUPP) {
3224 		ath10k_warn(ar, "set target log mode failed: %d\n", status);
3225 		goto err_hif_stop;
3226 	}
3227 
3228 	return 0;
3229 
3230 err_hif_stop:
3231 	ath10k_hif_stop(ar);
3232 err_htt_rx_detach:
3233 	ath10k_htt_rx_free(&ar->htt);
3234 err_htt_tx_detach:
3235 	ath10k_htt_tx_free(&ar->htt);
3236 err_wmi_detach:
3237 	ath10k_wmi_detach(ar);
3238 err:
3239 	return status;
3240 }
3241 EXPORT_SYMBOL(ath10k_core_start);
3242 
ath10k_wait_for_suspend(struct ath10k * ar,u32 suspend_opt)3243 int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt)
3244 {
3245 	int ret;
3246 	unsigned long time_left;
3247 
3248 	reinit_completion(&ar->target_suspend);
3249 
3250 	ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt);
3251 	if (ret) {
3252 		ath10k_warn(ar, "could not suspend target (%d)\n", ret);
3253 		return ret;
3254 	}
3255 
3256 	time_left = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ);
3257 
3258 	if (!time_left) {
3259 		ath10k_warn(ar, "suspend timed out - target pause event never came\n");
3260 		return -ETIMEDOUT;
3261 	}
3262 
3263 	return 0;
3264 }
3265 
ath10k_core_stop(struct ath10k * ar)3266 void ath10k_core_stop(struct ath10k *ar)
3267 {
3268 	lockdep_assert_held(&ar->conf_mutex);
3269 	ath10k_debug_stop(ar);
3270 
3271 	/* try to suspend target */
3272 	if (ar->state != ATH10K_STATE_RESTARTING &&
3273 	    ar->state != ATH10K_STATE_UTF)
3274 		ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR);
3275 
3276 	ath10k_hif_stop(ar);
3277 	ath10k_htt_tx_stop(&ar->htt);
3278 	ath10k_htt_rx_free(&ar->htt);
3279 	ath10k_wmi_detach(ar);
3280 
3281 	ar->id.bmi_ids_valid = false;
3282 }
3283 EXPORT_SYMBOL(ath10k_core_stop);
3284 
3285 /* mac80211 manages fw/hw initialization through start/stop hooks. However in
3286  * order to know what hw capabilities should be advertised to mac80211 it is
3287  * necessary to load the firmware (and tear it down immediately since start
3288  * hook will try to init it again) before registering
3289  */
ath10k_core_probe_fw(struct ath10k * ar)3290 static int ath10k_core_probe_fw(struct ath10k *ar)
3291 {
3292 	struct bmi_target_info target_info;
3293 	int ret = 0;
3294 
3295 	ret = ath10k_hif_power_up(ar, ATH10K_FIRMWARE_MODE_NORMAL);
3296 	if (ret) {
3297 		ath10k_err(ar, "could not power on hif bus (%d)\n", ret);
3298 		return ret;
3299 	}
3300 
3301 	switch (ar->hif.bus) {
3302 	case ATH10K_BUS_SDIO:
3303 		memset(&target_info, 0, sizeof(target_info));
3304 		ret = ath10k_bmi_get_target_info_sdio(ar, &target_info);
3305 		if (ret) {
3306 			ath10k_err(ar, "could not get target info (%d)\n", ret);
3307 			goto err_power_down;
3308 		}
3309 		ar->target_version = target_info.version;
3310 		ar->hw->wiphy->hw_version = target_info.version;
3311 		break;
3312 	case ATH10K_BUS_PCI:
3313 	case ATH10K_BUS_AHB:
3314 	case ATH10K_BUS_USB:
3315 		memset(&target_info, 0, sizeof(target_info));
3316 		ret = ath10k_bmi_get_target_info(ar, &target_info);
3317 		if (ret) {
3318 			ath10k_err(ar, "could not get target info (%d)\n", ret);
3319 			goto err_power_down;
3320 		}
3321 		ar->target_version = target_info.version;
3322 		ar->hw->wiphy->hw_version = target_info.version;
3323 		break;
3324 	case ATH10K_BUS_SNOC:
3325 		memset(&target_info, 0, sizeof(target_info));
3326 		ret = ath10k_hif_get_target_info(ar, &target_info);
3327 		if (ret) {
3328 			ath10k_err(ar, "could not get target info (%d)\n", ret);
3329 			goto err_power_down;
3330 		}
3331 		ar->target_version = target_info.version;
3332 		ar->hw->wiphy->hw_version = target_info.version;
3333 		break;
3334 	default:
3335 		ath10k_err(ar, "incorrect hif bus type: %d\n", ar->hif.bus);
3336 	}
3337 
3338 	ret = ath10k_init_hw_params(ar);
3339 	if (ret) {
3340 		ath10k_err(ar, "could not get hw params (%d)\n", ret);
3341 		goto err_power_down;
3342 	}
3343 
3344 	ret = ath10k_core_fetch_firmware_files(ar);
3345 	if (ret) {
3346 		ath10k_err(ar, "could not fetch firmware files (%d)\n", ret);
3347 		goto err_power_down;
3348 	}
3349 
3350 	BUILD_BUG_ON(sizeof(ar->hw->wiphy->fw_version) !=
3351 		     sizeof(ar->normal_mode_fw.fw_file.fw_version));
3352 	memcpy(ar->hw->wiphy->fw_version, ar->normal_mode_fw.fw_file.fw_version,
3353 	       sizeof(ar->hw->wiphy->fw_version));
3354 
3355 	ath10k_debug_print_hwfw_info(ar);
3356 
3357 	if (!test_bit(ATH10K_FW_FEATURE_NON_BMI,
3358 		      ar->normal_mode_fw.fw_file.fw_features)) {
3359 		ret = ath10k_core_pre_cal_download(ar);
3360 		if (ret) {
3361 			/* pre calibration data download is not necessary
3362 			 * for all the chipsets. Ignore failures and continue.
3363 			 */
3364 			ath10k_dbg(ar, ATH10K_DBG_BOOT,
3365 				   "could not load pre cal data: %d\n", ret);
3366 		}
3367 
3368 		ret = ath10k_core_get_board_id_from_otp(ar);
3369 		if (ret && ret != -EOPNOTSUPP) {
3370 			ath10k_err(ar, "failed to get board id from otp: %d\n",
3371 				   ret);
3372 			goto err_free_firmware_files;
3373 		}
3374 
3375 		ret = ath10k_core_check_smbios(ar);
3376 		if (ret)
3377 			ath10k_dbg(ar, ATH10K_DBG_BOOT, "SMBIOS bdf variant name not set.\n");
3378 
3379 		ret = ath10k_core_check_dt(ar);
3380 		if (ret)
3381 			ath10k_dbg(ar, ATH10K_DBG_BOOT, "DT bdf variant name not set.\n");
3382 
3383 		ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD);
3384 		if (ret) {
3385 			ath10k_err(ar, "failed to fetch board file: %d\n", ret);
3386 			goto err_free_firmware_files;
3387 		}
3388 
3389 		ath10k_debug_print_board_info(ar);
3390 	}
3391 
3392 	device_get_mac_address(ar->dev, ar->mac_addr);
3393 
3394 	ret = ath10k_core_init_firmware_features(ar);
3395 	if (ret) {
3396 		ath10k_err(ar, "fatal problem with firmware features: %d\n",
3397 			   ret);
3398 		goto err_free_firmware_files;
3399 	}
3400 
3401 	if (!test_bit(ATH10K_FW_FEATURE_NON_BMI,
3402 		      ar->normal_mode_fw.fw_file.fw_features)) {
3403 		ret = ath10k_swap_code_seg_init(ar,
3404 						&ar->normal_mode_fw.fw_file);
3405 		if (ret) {
3406 			ath10k_err(ar, "failed to initialize code swap segment: %d\n",
3407 				   ret);
3408 			goto err_free_firmware_files;
3409 		}
3410 	}
3411 
3412 	mutex_lock(&ar->conf_mutex);
3413 
3414 	ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL,
3415 				&ar->normal_mode_fw);
3416 	if (ret) {
3417 		ath10k_err(ar, "could not init core (%d)\n", ret);
3418 		goto err_unlock;
3419 	}
3420 
3421 	ath10k_debug_print_boot_info(ar);
3422 	ath10k_core_stop(ar);
3423 
3424 	mutex_unlock(&ar->conf_mutex);
3425 
3426 	ath10k_hif_power_down(ar);
3427 	return 0;
3428 
3429 err_unlock:
3430 	mutex_unlock(&ar->conf_mutex);
3431 
3432 err_free_firmware_files:
3433 	ath10k_core_free_firmware_files(ar);
3434 
3435 err_power_down:
3436 	ath10k_hif_power_down(ar);
3437 
3438 	return ret;
3439 }
3440 
ath10k_core_register_work(struct work_struct * work)3441 static void ath10k_core_register_work(struct work_struct *work)
3442 {
3443 	struct ath10k *ar = container_of(work, struct ath10k, register_work);
3444 	int status;
3445 
3446 	/* peer stats are enabled by default */
3447 	set_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags);
3448 
3449 	status = ath10k_core_probe_fw(ar);
3450 	if (status) {
3451 		ath10k_err(ar, "could not probe fw (%d)\n", status);
3452 		goto err;
3453 	}
3454 
3455 	status = ath10k_mac_register(ar);
3456 	if (status) {
3457 		ath10k_err(ar, "could not register to mac80211 (%d)\n", status);
3458 		goto err_release_fw;
3459 	}
3460 
3461 	status = ath10k_coredump_register(ar);
3462 	if (status) {
3463 		ath10k_err(ar, "unable to register coredump\n");
3464 		goto err_unregister_mac;
3465 	}
3466 
3467 	status = ath10k_debug_register(ar);
3468 	if (status) {
3469 		ath10k_err(ar, "unable to initialize debugfs\n");
3470 		goto err_unregister_coredump;
3471 	}
3472 
3473 	status = ath10k_spectral_create(ar);
3474 	if (status) {
3475 		ath10k_err(ar, "failed to initialize spectral\n");
3476 		goto err_debug_destroy;
3477 	}
3478 
3479 	status = ath10k_thermal_register(ar);
3480 	if (status) {
3481 		ath10k_err(ar, "could not register thermal device: %d\n",
3482 			   status);
3483 		goto err_spectral_destroy;
3484 	}
3485 
3486 	set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags);
3487 	return;
3488 
3489 err_spectral_destroy:
3490 	ath10k_spectral_destroy(ar);
3491 err_debug_destroy:
3492 	ath10k_debug_destroy(ar);
3493 err_unregister_coredump:
3494 	ath10k_coredump_unregister(ar);
3495 err_unregister_mac:
3496 	ath10k_mac_unregister(ar);
3497 err_release_fw:
3498 	ath10k_core_free_firmware_files(ar);
3499 err:
3500 	/* TODO: It's probably a good idea to release device from the driver
3501 	 * but calling device_release_driver() here will cause a deadlock.
3502 	 */
3503 	return;
3504 }
3505 
ath10k_core_register(struct ath10k * ar,const struct ath10k_bus_params * bus_params)3506 int ath10k_core_register(struct ath10k *ar,
3507 			 const struct ath10k_bus_params *bus_params)
3508 {
3509 	ar->bus_param = *bus_params;
3510 
3511 	queue_work(ar->workqueue, &ar->register_work);
3512 
3513 	return 0;
3514 }
3515 EXPORT_SYMBOL(ath10k_core_register);
3516 
ath10k_core_unregister(struct ath10k * ar)3517 void ath10k_core_unregister(struct ath10k *ar)
3518 {
3519 	cancel_work_sync(&ar->register_work);
3520 
3521 	if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags))
3522 		return;
3523 
3524 	ath10k_thermal_unregister(ar);
3525 	/* Stop spectral before unregistering from mac80211 to remove the
3526 	 * relayfs debugfs file cleanly. Otherwise the parent debugfs tree
3527 	 * would be already be free'd recursively, leading to a double free.
3528 	 */
3529 	ath10k_spectral_destroy(ar);
3530 
3531 	/* We must unregister from mac80211 before we stop HTC and HIF.
3532 	 * Otherwise we will fail to submit commands to FW and mac80211 will be
3533 	 * unhappy about callback failures.
3534 	 */
3535 	ath10k_mac_unregister(ar);
3536 
3537 	ath10k_testmode_destroy(ar);
3538 
3539 	ath10k_core_free_firmware_files(ar);
3540 	ath10k_core_free_board_files(ar);
3541 
3542 	ath10k_debug_unregister(ar);
3543 }
3544 EXPORT_SYMBOL(ath10k_core_unregister);
3545 
ath10k_core_create(size_t priv_size,struct device * dev,enum ath10k_bus bus,enum ath10k_hw_rev hw_rev,const struct ath10k_hif_ops * hif_ops)3546 struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
3547 				  enum ath10k_bus bus,
3548 				  enum ath10k_hw_rev hw_rev,
3549 				  const struct ath10k_hif_ops *hif_ops)
3550 {
3551 	struct ath10k *ar;
3552 	int ret;
3553 
3554 	ar = ath10k_mac_create(priv_size);
3555 	if (!ar)
3556 		return NULL;
3557 
3558 	ar->ath_common.priv = ar;
3559 	ar->ath_common.hw = ar->hw;
3560 	ar->dev = dev;
3561 	ar->hw_rev = hw_rev;
3562 	ar->hif.ops = hif_ops;
3563 	ar->hif.bus = bus;
3564 
3565 	switch (hw_rev) {
3566 	case ATH10K_HW_QCA988X:
3567 	case ATH10K_HW_QCA9887:
3568 		ar->regs = &qca988x_regs;
3569 		ar->hw_ce_regs = &qcax_ce_regs;
3570 		ar->hw_values = &qca988x_values;
3571 		break;
3572 	case ATH10K_HW_QCA6174:
3573 	case ATH10K_HW_QCA9377:
3574 		ar->regs = &qca6174_regs;
3575 		ar->hw_ce_regs = &qcax_ce_regs;
3576 		ar->hw_values = &qca6174_values;
3577 		break;
3578 	case ATH10K_HW_QCA99X0:
3579 	case ATH10K_HW_QCA9984:
3580 		ar->regs = &qca99x0_regs;
3581 		ar->hw_ce_regs = &qcax_ce_regs;
3582 		ar->hw_values = &qca99x0_values;
3583 		break;
3584 	case ATH10K_HW_QCA9888:
3585 		ar->regs = &qca99x0_regs;
3586 		ar->hw_ce_regs = &qcax_ce_regs;
3587 		ar->hw_values = &qca9888_values;
3588 		break;
3589 	case ATH10K_HW_QCA4019:
3590 		ar->regs = &qca4019_regs;
3591 		ar->hw_ce_regs = &qcax_ce_regs;
3592 		ar->hw_values = &qca4019_values;
3593 		break;
3594 	case ATH10K_HW_WCN3990:
3595 		ar->regs = &wcn3990_regs;
3596 		ar->hw_ce_regs = &wcn3990_ce_regs;
3597 		ar->hw_values = &wcn3990_values;
3598 		break;
3599 	default:
3600 		ath10k_err(ar, "unsupported core hardware revision %d\n",
3601 			   hw_rev);
3602 		ret = -ENOTSUPP;
3603 		goto err_free_mac;
3604 	}
3605 
3606 	init_completion(&ar->scan.started);
3607 	init_completion(&ar->scan.completed);
3608 	init_completion(&ar->scan.on_channel);
3609 	init_completion(&ar->target_suspend);
3610 	init_completion(&ar->driver_recovery);
3611 	init_completion(&ar->wow.wakeup_completed);
3612 
3613 	init_completion(&ar->install_key_done);
3614 	init_completion(&ar->vdev_setup_done);
3615 	init_completion(&ar->vdev_delete_done);
3616 	init_completion(&ar->thermal.wmi_sync);
3617 	init_completion(&ar->bss_survey_done);
3618 	init_completion(&ar->peer_delete_done);
3619 	init_completion(&ar->peer_stats_info_complete);
3620 
3621 	INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work);
3622 
3623 	ar->workqueue = create_singlethread_workqueue("ath10k_wq");
3624 	if (!ar->workqueue)
3625 		goto err_free_mac;
3626 
3627 	ar->workqueue_aux = create_singlethread_workqueue("ath10k_aux_wq");
3628 	if (!ar->workqueue_aux)
3629 		goto err_free_wq;
3630 
3631 	ar->workqueue_tx_complete =
3632 		create_singlethread_workqueue("ath10k_tx_complete_wq");
3633 	if (!ar->workqueue_tx_complete)
3634 		goto err_free_aux_wq;
3635 
3636 	mutex_init(&ar->conf_mutex);
3637 	mutex_init(&ar->dump_mutex);
3638 	spin_lock_init(&ar->data_lock);
3639 
3640 	for (int ac = 0; ac < IEEE80211_NUM_ACS; ac++)
3641 		spin_lock_init(&ar->queue_lock[ac]);
3642 
3643 	INIT_LIST_HEAD(&ar->peers);
3644 	init_waitqueue_head(&ar->peer_mapping_wq);
3645 	init_waitqueue_head(&ar->htt.empty_tx_wq);
3646 	init_waitqueue_head(&ar->wmi.tx_credits_wq);
3647 
3648 	skb_queue_head_init(&ar->htt.rx_indication_head);
3649 
3650 	init_completion(&ar->offchan_tx_completed);
3651 	INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work);
3652 	skb_queue_head_init(&ar->offchan_tx_queue);
3653 
3654 	INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work);
3655 	skb_queue_head_init(&ar->wmi_mgmt_tx_queue);
3656 
3657 	INIT_WORK(&ar->register_work, ath10k_core_register_work);
3658 	INIT_WORK(&ar->restart_work, ath10k_core_restart);
3659 	INIT_WORK(&ar->set_coverage_class_work,
3660 		  ath10k_core_set_coverage_class_work);
3661 
3662 	init_dummy_netdev(&ar->napi_dev);
3663 
3664 	ret = ath10k_coredump_create(ar);
3665 	if (ret)
3666 		goto err_free_tx_complete;
3667 
3668 	ret = ath10k_debug_create(ar);
3669 	if (ret)
3670 		goto err_free_coredump;
3671 
3672 	return ar;
3673 
3674 err_free_coredump:
3675 	ath10k_coredump_destroy(ar);
3676 err_free_tx_complete:
3677 	destroy_workqueue(ar->workqueue_tx_complete);
3678 err_free_aux_wq:
3679 	destroy_workqueue(ar->workqueue_aux);
3680 err_free_wq:
3681 	destroy_workqueue(ar->workqueue);
3682 err_free_mac:
3683 	ath10k_mac_destroy(ar);
3684 
3685 	return NULL;
3686 }
3687 EXPORT_SYMBOL(ath10k_core_create);
3688 
ath10k_core_destroy(struct ath10k * ar)3689 void ath10k_core_destroy(struct ath10k *ar)
3690 {
3691 	destroy_workqueue(ar->workqueue);
3692 
3693 	destroy_workqueue(ar->workqueue_aux);
3694 
3695 	destroy_workqueue(ar->workqueue_tx_complete);
3696 
3697 	ath10k_debug_destroy(ar);
3698 	ath10k_coredump_destroy(ar);
3699 	ath10k_htt_tx_destroy(&ar->htt);
3700 	ath10k_wmi_free_host_mem(ar);
3701 	ath10k_mac_destroy(ar);
3702 }
3703 EXPORT_SYMBOL(ath10k_core_destroy);
3704 
3705 MODULE_AUTHOR("Qualcomm Atheros");
3706 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ac wireless LAN cards.");
3707 MODULE_LICENSE("Dual BSD/GPL");
3708