xref: /openbmc/linux/drivers/ata/libata-sff.c (revision 360823a09426347ea8f232b0b0b5156d0aed0302)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *  libata-sff.c - helper library for PCI IDE BMDMA
4  *
5  *  Copyright 2003-2006 Red Hat, Inc.  All rights reserved.
6  *  Copyright 2003-2006 Jeff Garzik
7  *
8  *  libata documentation is available via 'make {ps|pdf}docs',
9  *  as Documentation/driver-api/libata.rst
10  *
11  *  Hardware documentation available from http://www.t13.org/ and
12  *  http://www.sata-io.org/
13  */
14 
15 #include <linux/kernel.h>
16 #include <linux/gfp.h>
17 #include <linux/pci.h>
18 #include <linux/module.h>
19 #include <linux/libata.h>
20 #include <linux/highmem.h>
21 #include <trace/events/libata.h>
22 #include "libata.h"
23 
24 static struct workqueue_struct *ata_sff_wq;
25 
26 const struct ata_port_operations ata_sff_port_ops = {
27 	.inherits		= &ata_base_port_ops,
28 
29 	.qc_prep		= ata_noop_qc_prep,
30 	.qc_issue		= ata_sff_qc_issue,
31 	.qc_fill_rtf		= ata_sff_qc_fill_rtf,
32 
33 	.freeze			= ata_sff_freeze,
34 	.thaw			= ata_sff_thaw,
35 	.prereset		= ata_sff_prereset,
36 	.softreset		= ata_sff_softreset,
37 	.hardreset		= sata_sff_hardreset,
38 	.postreset		= ata_sff_postreset,
39 	.error_handler		= ata_sff_error_handler,
40 
41 	.sff_dev_select		= ata_sff_dev_select,
42 	.sff_check_status	= ata_sff_check_status,
43 	.sff_tf_load		= ata_sff_tf_load,
44 	.sff_tf_read		= ata_sff_tf_read,
45 	.sff_exec_command	= ata_sff_exec_command,
46 	.sff_data_xfer		= ata_sff_data_xfer,
47 	.sff_drain_fifo		= ata_sff_drain_fifo,
48 
49 	.lost_interrupt		= ata_sff_lost_interrupt,
50 };
51 EXPORT_SYMBOL_GPL(ata_sff_port_ops);
52 
53 /**
54  *	ata_sff_check_status - Read device status reg & clear interrupt
55  *	@ap: port where the device is
56  *
57  *	Reads ATA taskfile status register for currently-selected device
58  *	and return its value. This also clears pending interrupts
59  *      from this device
60  *
61  *	LOCKING:
62  *	Inherited from caller.
63  */
ata_sff_check_status(struct ata_port * ap)64 u8 ata_sff_check_status(struct ata_port *ap)
65 {
66 	return ioread8(ap->ioaddr.status_addr);
67 }
68 EXPORT_SYMBOL_GPL(ata_sff_check_status);
69 
70 /**
71  *	ata_sff_altstatus - Read device alternate status reg
72  *	@ap: port where the device is
73  *	@status: pointer to a status value
74  *
75  *	Reads ATA alternate status register for currently-selected device
76  *	and return its value.
77  *
78  *	RETURN:
79  *	true if the register exists, false if not.
80  *
81  *	LOCKING:
82  *	Inherited from caller.
83  */
ata_sff_altstatus(struct ata_port * ap,u8 * status)84 static bool ata_sff_altstatus(struct ata_port *ap, u8 *status)
85 {
86 	u8 tmp;
87 
88 	if (ap->ops->sff_check_altstatus) {
89 		tmp = ap->ops->sff_check_altstatus(ap);
90 		goto read;
91 	}
92 	if (ap->ioaddr.altstatus_addr) {
93 		tmp = ioread8(ap->ioaddr.altstatus_addr);
94 		goto read;
95 	}
96 	return false;
97 
98 read:
99 	if (status)
100 		*status = tmp;
101 	return true;
102 }
103 
104 /**
105  *	ata_sff_irq_status - Check if the device is busy
106  *	@ap: port where the device is
107  *
108  *	Determine if the port is currently busy. Uses altstatus
109  *	if available in order to avoid clearing shared IRQ status
110  *	when finding an IRQ source. Non ctl capable devices don't
111  *	share interrupt lines fortunately for us.
112  *
113  *	LOCKING:
114  *	Inherited from caller.
115  */
ata_sff_irq_status(struct ata_port * ap)116 static u8 ata_sff_irq_status(struct ata_port *ap)
117 {
118 	u8 status;
119 
120 	/* Not us: We are busy */
121 	if (ata_sff_altstatus(ap, &status) && (status & ATA_BUSY))
122 		return status;
123 	/* Clear INTRQ latch */
124 	status = ap->ops->sff_check_status(ap);
125 	return status;
126 }
127 
128 /**
129  *	ata_sff_sync - Flush writes
130  *	@ap: Port to wait for.
131  *
132  *	CAUTION:
133  *	If we have an mmio device with no ctl and no altstatus
134  *	method this will fail. No such devices are known to exist.
135  *
136  *	LOCKING:
137  *	Inherited from caller.
138  */
139 
ata_sff_sync(struct ata_port * ap)140 static void ata_sff_sync(struct ata_port *ap)
141 {
142 	ata_sff_altstatus(ap, NULL);
143 }
144 
145 /**
146  *	ata_sff_pause		-	Flush writes and wait 400nS
147  *	@ap: Port to pause for.
148  *
149  *	CAUTION:
150  *	If we have an mmio device with no ctl and no altstatus
151  *	method this will fail. No such devices are known to exist.
152  *
153  *	LOCKING:
154  *	Inherited from caller.
155  */
156 
ata_sff_pause(struct ata_port * ap)157 void ata_sff_pause(struct ata_port *ap)
158 {
159 	ata_sff_sync(ap);
160 	ndelay(400);
161 }
162 EXPORT_SYMBOL_GPL(ata_sff_pause);
163 
164 /**
165  *	ata_sff_dma_pause	-	Pause before commencing DMA
166  *	@ap: Port to pause for.
167  *
168  *	Perform I/O fencing and ensure sufficient cycle delays occur
169  *	for the HDMA1:0 transition
170  */
171 
ata_sff_dma_pause(struct ata_port * ap)172 void ata_sff_dma_pause(struct ata_port *ap)
173 {
174 	/*
175 	 * An altstatus read will cause the needed delay without
176 	 * messing up the IRQ status
177 	 */
178 	if (ata_sff_altstatus(ap, NULL))
179 		return;
180 	/* There are no DMA controllers without ctl. BUG here to ensure
181 	   we never violate the HDMA1:0 transition timing and risk
182 	   corruption. */
183 	BUG();
184 }
185 EXPORT_SYMBOL_GPL(ata_sff_dma_pause);
186 
ata_sff_check_ready(struct ata_link * link)187 static int ata_sff_check_ready(struct ata_link *link)
188 {
189 	u8 status = link->ap->ops->sff_check_status(link->ap);
190 
191 	return ata_check_ready(status);
192 }
193 
194 /**
195  *	ata_sff_wait_ready - sleep until BSY clears, or timeout
196  *	@link: SFF link to wait ready status for
197  *	@deadline: deadline jiffies for the operation
198  *
199  *	Sleep until ATA Status register bit BSY clears, or timeout
200  *	occurs.
201  *
202  *	LOCKING:
203  *	Kernel thread context (may sleep).
204  *
205  *	RETURNS:
206  *	0 on success, -errno otherwise.
207  */
ata_sff_wait_ready(struct ata_link * link,unsigned long deadline)208 int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline)
209 {
210 	return ata_wait_ready(link, deadline, ata_sff_check_ready);
211 }
212 EXPORT_SYMBOL_GPL(ata_sff_wait_ready);
213 
214 /**
215  *	ata_sff_set_devctl - Write device control reg
216  *	@ap: port where the device is
217  *	@ctl: value to write
218  *
219  *	Writes ATA device control register.
220  *
221  *	RETURN:
222  *	true if the register exists, false if not.
223  *
224  *	LOCKING:
225  *	Inherited from caller.
226  */
ata_sff_set_devctl(struct ata_port * ap,u8 ctl)227 static bool ata_sff_set_devctl(struct ata_port *ap, u8 ctl)
228 {
229 	if (ap->ops->sff_set_devctl) {
230 		ap->ops->sff_set_devctl(ap, ctl);
231 		return true;
232 	}
233 	if (ap->ioaddr.ctl_addr) {
234 		iowrite8(ctl, ap->ioaddr.ctl_addr);
235 		return true;
236 	}
237 
238 	return false;
239 }
240 
241 /**
242  *	ata_sff_dev_select - Select device 0/1 on ATA bus
243  *	@ap: ATA channel to manipulate
244  *	@device: ATA device (numbered from zero) to select
245  *
246  *	Use the method defined in the ATA specification to
247  *	make either device 0, or device 1, active on the
248  *	ATA channel.  Works with both PIO and MMIO.
249  *
250  *	May be used as the dev_select() entry in ata_port_operations.
251  *
252  *	LOCKING:
253  *	caller.
254  */
ata_sff_dev_select(struct ata_port * ap,unsigned int device)255 void ata_sff_dev_select(struct ata_port *ap, unsigned int device)
256 {
257 	u8 tmp;
258 
259 	if (device == 0)
260 		tmp = ATA_DEVICE_OBS;
261 	else
262 		tmp = ATA_DEVICE_OBS | ATA_DEV1;
263 
264 	iowrite8(tmp, ap->ioaddr.device_addr);
265 	ata_sff_pause(ap);	/* needed; also flushes, for mmio */
266 }
267 EXPORT_SYMBOL_GPL(ata_sff_dev_select);
268 
269 /**
270  *	ata_dev_select - Select device 0/1 on ATA bus
271  *	@ap: ATA channel to manipulate
272  *	@device: ATA device (numbered from zero) to select
273  *	@wait: non-zero to wait for Status register BSY bit to clear
274  *	@can_sleep: non-zero if context allows sleeping
275  *
276  *	Use the method defined in the ATA specification to
277  *	make either device 0, or device 1, active on the
278  *	ATA channel.
279  *
280  *	This is a high-level version of ata_sff_dev_select(), which
281  *	additionally provides the services of inserting the proper
282  *	pauses and status polling, where needed.
283  *
284  *	LOCKING:
285  *	caller.
286  */
ata_dev_select(struct ata_port * ap,unsigned int device,unsigned int wait,unsigned int can_sleep)287 static void ata_dev_select(struct ata_port *ap, unsigned int device,
288 			   unsigned int wait, unsigned int can_sleep)
289 {
290 	if (wait)
291 		ata_wait_idle(ap);
292 
293 	ap->ops->sff_dev_select(ap, device);
294 
295 	if (wait) {
296 		if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
297 			ata_msleep(ap, 150);
298 		ata_wait_idle(ap);
299 	}
300 }
301 
302 /**
303  *	ata_sff_irq_on - Enable interrupts on a port.
304  *	@ap: Port on which interrupts are enabled.
305  *
306  *	Enable interrupts on a legacy IDE device using MMIO or PIO,
307  *	wait for idle, clear any pending interrupts.
308  *
309  *	Note: may NOT be used as the sff_irq_on() entry in
310  *	ata_port_operations.
311  *
312  *	LOCKING:
313  *	Inherited from caller.
314  */
ata_sff_irq_on(struct ata_port * ap)315 void ata_sff_irq_on(struct ata_port *ap)
316 {
317 	if (ap->ops->sff_irq_on) {
318 		ap->ops->sff_irq_on(ap);
319 		return;
320 	}
321 
322 	ap->ctl &= ~ATA_NIEN;
323 	ap->last_ctl = ap->ctl;
324 
325 	ata_sff_set_devctl(ap, ap->ctl);
326 	ata_wait_idle(ap);
327 
328 	if (ap->ops->sff_irq_clear)
329 		ap->ops->sff_irq_clear(ap);
330 }
331 EXPORT_SYMBOL_GPL(ata_sff_irq_on);
332 
333 /**
334  *	ata_sff_tf_load - send taskfile registers to host controller
335  *	@ap: Port to which output is sent
336  *	@tf: ATA taskfile register set
337  *
338  *	Outputs ATA taskfile to standard ATA host controller.
339  *
340  *	LOCKING:
341  *	Inherited from caller.
342  */
ata_sff_tf_load(struct ata_port * ap,const struct ata_taskfile * tf)343 void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
344 {
345 	struct ata_ioports *ioaddr = &ap->ioaddr;
346 	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
347 
348 	if (tf->ctl != ap->last_ctl) {
349 		if (ioaddr->ctl_addr)
350 			iowrite8(tf->ctl, ioaddr->ctl_addr);
351 		ap->last_ctl = tf->ctl;
352 		ata_wait_idle(ap);
353 	}
354 
355 	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
356 		WARN_ON_ONCE(!ioaddr->ctl_addr);
357 		iowrite8(tf->hob_feature, ioaddr->feature_addr);
358 		iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
359 		iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
360 		iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
361 		iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
362 	}
363 
364 	if (is_addr) {
365 		iowrite8(tf->feature, ioaddr->feature_addr);
366 		iowrite8(tf->nsect, ioaddr->nsect_addr);
367 		iowrite8(tf->lbal, ioaddr->lbal_addr);
368 		iowrite8(tf->lbam, ioaddr->lbam_addr);
369 		iowrite8(tf->lbah, ioaddr->lbah_addr);
370 	}
371 
372 	if (tf->flags & ATA_TFLAG_DEVICE)
373 		iowrite8(tf->device, ioaddr->device_addr);
374 
375 	ata_wait_idle(ap);
376 }
377 EXPORT_SYMBOL_GPL(ata_sff_tf_load);
378 
379 /**
380  *	ata_sff_tf_read - input device's ATA taskfile shadow registers
381  *	@ap: Port from which input is read
382  *	@tf: ATA taskfile register set for storing input
383  *
384  *	Reads ATA taskfile registers for currently-selected device
385  *	into @tf. Assumes the device has a fully SFF compliant task file
386  *	layout and behaviour. If you device does not (eg has a different
387  *	status method) then you will need to provide a replacement tf_read
388  *
389  *	LOCKING:
390  *	Inherited from caller.
391  */
ata_sff_tf_read(struct ata_port * ap,struct ata_taskfile * tf)392 void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
393 {
394 	struct ata_ioports *ioaddr = &ap->ioaddr;
395 
396 	tf->status = ata_sff_check_status(ap);
397 	tf->error = ioread8(ioaddr->error_addr);
398 	tf->nsect = ioread8(ioaddr->nsect_addr);
399 	tf->lbal = ioread8(ioaddr->lbal_addr);
400 	tf->lbam = ioread8(ioaddr->lbam_addr);
401 	tf->lbah = ioread8(ioaddr->lbah_addr);
402 	tf->device = ioread8(ioaddr->device_addr);
403 
404 	if (tf->flags & ATA_TFLAG_LBA48) {
405 		if (likely(ioaddr->ctl_addr)) {
406 			iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
407 			tf->hob_feature = ioread8(ioaddr->error_addr);
408 			tf->hob_nsect = ioread8(ioaddr->nsect_addr);
409 			tf->hob_lbal = ioread8(ioaddr->lbal_addr);
410 			tf->hob_lbam = ioread8(ioaddr->lbam_addr);
411 			tf->hob_lbah = ioread8(ioaddr->lbah_addr);
412 			iowrite8(tf->ctl, ioaddr->ctl_addr);
413 			ap->last_ctl = tf->ctl;
414 		} else
415 			WARN_ON_ONCE(1);
416 	}
417 }
418 EXPORT_SYMBOL_GPL(ata_sff_tf_read);
419 
420 /**
421  *	ata_sff_exec_command - issue ATA command to host controller
422  *	@ap: port to which command is being issued
423  *	@tf: ATA taskfile register set
424  *
425  *	Issues ATA command, with proper synchronization with interrupt
426  *	handler / other threads.
427  *
428  *	LOCKING:
429  *	spin_lock_irqsave(host lock)
430  */
ata_sff_exec_command(struct ata_port * ap,const struct ata_taskfile * tf)431 void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
432 {
433 	iowrite8(tf->command, ap->ioaddr.command_addr);
434 	ata_sff_pause(ap);
435 }
436 EXPORT_SYMBOL_GPL(ata_sff_exec_command);
437 
438 /**
439  *	ata_tf_to_host - issue ATA taskfile to host controller
440  *	@ap: port to which command is being issued
441  *	@tf: ATA taskfile register set
442  *	@tag: tag of the associated command
443  *
444  *	Issues ATA taskfile register set to ATA host controller,
445  *	with proper synchronization with interrupt handler and
446  *	other threads.
447  *
448  *	LOCKING:
449  *	spin_lock_irqsave(host lock)
450  */
ata_tf_to_host(struct ata_port * ap,const struct ata_taskfile * tf,unsigned int tag)451 static inline void ata_tf_to_host(struct ata_port *ap,
452 				  const struct ata_taskfile *tf,
453 				  unsigned int tag)
454 {
455 	trace_ata_tf_load(ap, tf);
456 	ap->ops->sff_tf_load(ap, tf);
457 	trace_ata_exec_command(ap, tf, tag);
458 	ap->ops->sff_exec_command(ap, tf);
459 }
460 
461 /**
462  *	ata_sff_data_xfer - Transfer data by PIO
463  *	@qc: queued command
464  *	@buf: data buffer
465  *	@buflen: buffer length
466  *	@rw: read/write
467  *
468  *	Transfer data from/to the device data register by PIO.
469  *
470  *	LOCKING:
471  *	Inherited from caller.
472  *
473  *	RETURNS:
474  *	Bytes consumed.
475  */
ata_sff_data_xfer(struct ata_queued_cmd * qc,unsigned char * buf,unsigned int buflen,int rw)476 unsigned int ata_sff_data_xfer(struct ata_queued_cmd *qc, unsigned char *buf,
477 			       unsigned int buflen, int rw)
478 {
479 	struct ata_port *ap = qc->dev->link->ap;
480 	void __iomem *data_addr = ap->ioaddr.data_addr;
481 	unsigned int words = buflen >> 1;
482 
483 	/* Transfer multiple of 2 bytes */
484 	if (rw == READ)
485 		ioread16_rep(data_addr, buf, words);
486 	else
487 		iowrite16_rep(data_addr, buf, words);
488 
489 	/* Transfer trailing byte, if any. */
490 	if (unlikely(buflen & 0x01)) {
491 		unsigned char pad[2] = { };
492 
493 		/* Point buf to the tail of buffer */
494 		buf += buflen - 1;
495 
496 		/*
497 		 * Use io*16_rep() accessors here as well to avoid pointlessly
498 		 * swapping bytes to and from on the big endian machines...
499 		 */
500 		if (rw == READ) {
501 			ioread16_rep(data_addr, pad, 1);
502 			*buf = pad[0];
503 		} else {
504 			pad[0] = *buf;
505 			iowrite16_rep(data_addr, pad, 1);
506 		}
507 		words++;
508 	}
509 
510 	return words << 1;
511 }
512 EXPORT_SYMBOL_GPL(ata_sff_data_xfer);
513 
514 /**
515  *	ata_sff_data_xfer32 - Transfer data by PIO
516  *	@qc: queued command
517  *	@buf: data buffer
518  *	@buflen: buffer length
519  *	@rw: read/write
520  *
521  *	Transfer data from/to the device data register by PIO using 32bit
522  *	I/O operations.
523  *
524  *	LOCKING:
525  *	Inherited from caller.
526  *
527  *	RETURNS:
528  *	Bytes consumed.
529  */
530 
ata_sff_data_xfer32(struct ata_queued_cmd * qc,unsigned char * buf,unsigned int buflen,int rw)531 unsigned int ata_sff_data_xfer32(struct ata_queued_cmd *qc, unsigned char *buf,
532 			       unsigned int buflen, int rw)
533 {
534 	struct ata_device *dev = qc->dev;
535 	struct ata_port *ap = dev->link->ap;
536 	void __iomem *data_addr = ap->ioaddr.data_addr;
537 	unsigned int words = buflen >> 2;
538 	int slop = buflen & 3;
539 
540 	if (!(ap->pflags & ATA_PFLAG_PIO32))
541 		return ata_sff_data_xfer(qc, buf, buflen, rw);
542 
543 	/* Transfer multiple of 4 bytes */
544 	if (rw == READ)
545 		ioread32_rep(data_addr, buf, words);
546 	else
547 		iowrite32_rep(data_addr, buf, words);
548 
549 	/* Transfer trailing bytes, if any */
550 	if (unlikely(slop)) {
551 		unsigned char pad[4] = { };
552 
553 		/* Point buf to the tail of buffer */
554 		buf += buflen - slop;
555 
556 		/*
557 		 * Use io*_rep() accessors here as well to avoid pointlessly
558 		 * swapping bytes to and from on the big endian machines...
559 		 */
560 		if (rw == READ) {
561 			if (slop < 3)
562 				ioread16_rep(data_addr, pad, 1);
563 			else
564 				ioread32_rep(data_addr, pad, 1);
565 			memcpy(buf, pad, slop);
566 		} else {
567 			memcpy(pad, buf, slop);
568 			if (slop < 3)
569 				iowrite16_rep(data_addr, pad, 1);
570 			else
571 				iowrite32_rep(data_addr, pad, 1);
572 		}
573 	}
574 	return (buflen + 1) & ~1;
575 }
576 EXPORT_SYMBOL_GPL(ata_sff_data_xfer32);
577 
ata_pio_xfer(struct ata_queued_cmd * qc,struct page * page,unsigned int offset,size_t xfer_size)578 static void ata_pio_xfer(struct ata_queued_cmd *qc, struct page *page,
579 		unsigned int offset, size_t xfer_size)
580 {
581 	bool do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
582 	unsigned char *buf;
583 
584 	buf = kmap_atomic(page);
585 	qc->ap->ops->sff_data_xfer(qc, buf + offset, xfer_size, do_write);
586 	kunmap_atomic(buf);
587 
588 	if (!do_write && !PageSlab(page))
589 		flush_dcache_page(page);
590 }
591 
592 /**
593  *	ata_pio_sector - Transfer a sector of data.
594  *	@qc: Command on going
595  *
596  *	Transfer qc->sect_size bytes of data from/to the ATA device.
597  *
598  *	LOCKING:
599  *	Inherited from caller.
600  */
ata_pio_sector(struct ata_queued_cmd * qc)601 static void ata_pio_sector(struct ata_queued_cmd *qc)
602 {
603 	struct ata_port *ap = qc->ap;
604 	struct page *page;
605 	unsigned int offset, count;
606 
607 	if (!qc->cursg) {
608 		qc->curbytes = qc->nbytes;
609 		return;
610 	}
611 	if (qc->curbytes == qc->nbytes - qc->sect_size)
612 		ap->hsm_task_state = HSM_ST_LAST;
613 
614 	page = sg_page(qc->cursg);
615 	offset = qc->cursg->offset + qc->cursg_ofs;
616 
617 	/* get the current page and offset */
618 	page = nth_page(page, (offset >> PAGE_SHIFT));
619 	offset %= PAGE_SIZE;
620 
621 	/* don't overrun current sg */
622 	count = min(qc->cursg->length - qc->cursg_ofs, qc->sect_size);
623 
624 	trace_ata_sff_pio_transfer_data(qc, offset, count);
625 
626 	/*
627 	 * Split the transfer when it splits a page boundary.  Note that the
628 	 * split still has to be dword aligned like all ATA data transfers.
629 	 */
630 	WARN_ON_ONCE(offset % 4);
631 	if (offset + count > PAGE_SIZE) {
632 		unsigned int split_len = PAGE_SIZE - offset;
633 
634 		ata_pio_xfer(qc, page, offset, split_len);
635 		ata_pio_xfer(qc, nth_page(page, 1), 0, count - split_len);
636 	} else {
637 		ata_pio_xfer(qc, page, offset, count);
638 	}
639 
640 	qc->curbytes += count;
641 	qc->cursg_ofs += count;
642 
643 	if (qc->cursg_ofs == qc->cursg->length) {
644 		qc->cursg = sg_next(qc->cursg);
645 		if (!qc->cursg)
646 			ap->hsm_task_state = HSM_ST_LAST;
647 		qc->cursg_ofs = 0;
648 	}
649 }
650 
651 /**
652  *	ata_pio_sectors - Transfer one or many sectors.
653  *	@qc: Command on going
654  *
655  *	Transfer one or many sectors of data from/to the
656  *	ATA device for the DRQ request.
657  *
658  *	LOCKING:
659  *	Inherited from caller.
660  */
ata_pio_sectors(struct ata_queued_cmd * qc)661 static void ata_pio_sectors(struct ata_queued_cmd *qc)
662 {
663 	if (is_multi_taskfile(&qc->tf)) {
664 		/* READ/WRITE MULTIPLE */
665 		unsigned int nsect;
666 
667 		WARN_ON_ONCE(qc->dev->multi_count == 0);
668 
669 		nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
670 			    qc->dev->multi_count);
671 		while (nsect--)
672 			ata_pio_sector(qc);
673 	} else
674 		ata_pio_sector(qc);
675 
676 	ata_sff_sync(qc->ap); /* flush */
677 }
678 
679 /**
680  *	atapi_send_cdb - Write CDB bytes to hardware
681  *	@ap: Port to which ATAPI device is attached.
682  *	@qc: Taskfile currently active
683  *
684  *	When device has indicated its readiness to accept
685  *	a CDB, this function is called.  Send the CDB.
686  *
687  *	LOCKING:
688  *	caller.
689  */
atapi_send_cdb(struct ata_port * ap,struct ata_queued_cmd * qc)690 static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
691 {
692 	/* send SCSI cdb */
693 	trace_atapi_send_cdb(qc, 0, qc->dev->cdb_len);
694 	WARN_ON_ONCE(qc->dev->cdb_len < 12);
695 
696 	ap->ops->sff_data_xfer(qc, qc->cdb, qc->dev->cdb_len, 1);
697 	ata_sff_sync(ap);
698 	/* FIXME: If the CDB is for DMA do we need to do the transition delay
699 	   or is bmdma_start guaranteed to do it ? */
700 	switch (qc->tf.protocol) {
701 	case ATAPI_PROT_PIO:
702 		ap->hsm_task_state = HSM_ST;
703 		break;
704 	case ATAPI_PROT_NODATA:
705 		ap->hsm_task_state = HSM_ST_LAST;
706 		break;
707 #ifdef CONFIG_ATA_BMDMA
708 	case ATAPI_PROT_DMA:
709 		ap->hsm_task_state = HSM_ST_LAST;
710 		/* initiate bmdma */
711 		trace_ata_bmdma_start(ap, &qc->tf, qc->tag);
712 		ap->ops->bmdma_start(qc);
713 		break;
714 #endif /* CONFIG_ATA_BMDMA */
715 	default:
716 		BUG();
717 	}
718 }
719 
720 /**
721  *	__atapi_pio_bytes - Transfer data from/to the ATAPI device.
722  *	@qc: Command on going
723  *	@bytes: number of bytes
724  *
725  *	Transfer data from/to the ATAPI device.
726  *
727  *	LOCKING:
728  *	Inherited from caller.
729  *
730  */
__atapi_pio_bytes(struct ata_queued_cmd * qc,unsigned int bytes)731 static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
732 {
733 	int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
734 	struct ata_port *ap = qc->ap;
735 	struct ata_device *dev = qc->dev;
736 	struct ata_eh_info *ehi = &dev->link->eh_info;
737 	struct scatterlist *sg;
738 	struct page *page;
739 	unsigned char *buf;
740 	unsigned int offset, count, consumed;
741 
742 next_sg:
743 	sg = qc->cursg;
744 	if (unlikely(!sg)) {
745 		ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
746 				  "buf=%u cur=%u bytes=%u",
747 				  qc->nbytes, qc->curbytes, bytes);
748 		return -1;
749 	}
750 
751 	page = sg_page(sg);
752 	offset = sg->offset + qc->cursg_ofs;
753 
754 	/* get the current page and offset */
755 	page = nth_page(page, (offset >> PAGE_SHIFT));
756 	offset %= PAGE_SIZE;
757 
758 	/* don't overrun current sg */
759 	count = min(sg->length - qc->cursg_ofs, bytes);
760 
761 	/* don't cross page boundaries */
762 	count = min(count, (unsigned int)PAGE_SIZE - offset);
763 
764 	trace_atapi_pio_transfer_data(qc, offset, count);
765 
766 	/* do the actual data transfer */
767 	buf = kmap_atomic(page);
768 	consumed = ap->ops->sff_data_xfer(qc, buf + offset, count, rw);
769 	kunmap_atomic(buf);
770 
771 	bytes -= min(bytes, consumed);
772 	qc->curbytes += count;
773 	qc->cursg_ofs += count;
774 
775 	if (qc->cursg_ofs == sg->length) {
776 		qc->cursg = sg_next(qc->cursg);
777 		qc->cursg_ofs = 0;
778 	}
779 
780 	/*
781 	 * There used to be a  WARN_ON_ONCE(qc->cursg && count != consumed);
782 	 * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN
783 	 * check correctly as it doesn't know if it is the last request being
784 	 * made. Somebody should implement a proper sanity check.
785 	 */
786 	if (bytes)
787 		goto next_sg;
788 	return 0;
789 }
790 
791 /**
792  *	atapi_pio_bytes - Transfer data from/to the ATAPI device.
793  *	@qc: Command on going
794  *
795  *	Transfer Transfer data from/to the ATAPI device.
796  *
797  *	LOCKING:
798  *	Inherited from caller.
799  */
atapi_pio_bytes(struct ata_queued_cmd * qc)800 static void atapi_pio_bytes(struct ata_queued_cmd *qc)
801 {
802 	struct ata_port *ap = qc->ap;
803 	struct ata_device *dev = qc->dev;
804 	struct ata_eh_info *ehi = &dev->link->eh_info;
805 	unsigned int ireason, bc_lo, bc_hi, bytes;
806 	int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
807 
808 	/* Abuse qc->result_tf for temp storage of intermediate TF
809 	 * here to save some kernel stack usage.
810 	 * For normal completion, qc->result_tf is not relevant. For
811 	 * error, qc->result_tf is later overwritten by ata_qc_complete().
812 	 * So, the correctness of qc->result_tf is not affected.
813 	 */
814 	ap->ops->sff_tf_read(ap, &qc->result_tf);
815 	ireason = qc->result_tf.nsect;
816 	bc_lo = qc->result_tf.lbam;
817 	bc_hi = qc->result_tf.lbah;
818 	bytes = (bc_hi << 8) | bc_lo;
819 
820 	/* shall be cleared to zero, indicating xfer of data */
821 	if (unlikely(ireason & ATAPI_COD))
822 		goto atapi_check;
823 
824 	/* make sure transfer direction matches expected */
825 	i_write = ((ireason & ATAPI_IO) == 0) ? 1 : 0;
826 	if (unlikely(do_write != i_write))
827 		goto atapi_check;
828 
829 	if (unlikely(!bytes))
830 		goto atapi_check;
831 
832 	if (unlikely(__atapi_pio_bytes(qc, bytes)))
833 		goto err_out;
834 	ata_sff_sync(ap); /* flush */
835 
836 	return;
837 
838  atapi_check:
839 	ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
840 			  ireason, bytes);
841  err_out:
842 	qc->err_mask |= AC_ERR_HSM;
843 	ap->hsm_task_state = HSM_ST_ERR;
844 }
845 
846 /**
847  *	ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
848  *	@ap: the target ata_port
849  *	@qc: qc on going
850  *
851  *	RETURNS:
852  *	1 if ok in workqueue, 0 otherwise.
853  */
ata_hsm_ok_in_wq(struct ata_port * ap,struct ata_queued_cmd * qc)854 static inline int ata_hsm_ok_in_wq(struct ata_port *ap,
855 						struct ata_queued_cmd *qc)
856 {
857 	if (qc->tf.flags & ATA_TFLAG_POLLING)
858 		return 1;
859 
860 	if (ap->hsm_task_state == HSM_ST_FIRST) {
861 		if (qc->tf.protocol == ATA_PROT_PIO &&
862 		   (qc->tf.flags & ATA_TFLAG_WRITE))
863 		    return 1;
864 
865 		if (ata_is_atapi(qc->tf.protocol) &&
866 		   !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
867 			return 1;
868 	}
869 
870 	return 0;
871 }
872 
873 /**
874  *	ata_hsm_qc_complete - finish a qc running on standard HSM
875  *	@qc: Command to complete
876  *	@in_wq: 1 if called from workqueue, 0 otherwise
877  *
878  *	Finish @qc which is running on standard HSM.
879  *
880  *	LOCKING:
881  *	If @in_wq is zero, spin_lock_irqsave(host lock).
882  *	Otherwise, none on entry and grabs host lock.
883  */
ata_hsm_qc_complete(struct ata_queued_cmd * qc,int in_wq)884 static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
885 {
886 	struct ata_port *ap = qc->ap;
887 
888 	if (in_wq) {
889 		/* EH might have kicked in while host lock is released. */
890 		qc = ata_qc_from_tag(ap, qc->tag);
891 		if (qc) {
892 			if (likely(!(qc->err_mask & AC_ERR_HSM))) {
893 				ata_sff_irq_on(ap);
894 				ata_qc_complete(qc);
895 			} else
896 				ata_port_freeze(ap);
897 		}
898 	} else {
899 		if (likely(!(qc->err_mask & AC_ERR_HSM)))
900 			ata_qc_complete(qc);
901 		else
902 			ata_port_freeze(ap);
903 	}
904 }
905 
906 /**
907  *	ata_sff_hsm_move - move the HSM to the next state.
908  *	@ap: the target ata_port
909  *	@qc: qc on going
910  *	@status: current device status
911  *	@in_wq: 1 if called from workqueue, 0 otherwise
912  *
913  *	RETURNS:
914  *	1 when poll next status needed, 0 otherwise.
915  */
ata_sff_hsm_move(struct ata_port * ap,struct ata_queued_cmd * qc,u8 status,int in_wq)916 int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
917 		     u8 status, int in_wq)
918 {
919 	struct ata_link *link = qc->dev->link;
920 	struct ata_eh_info *ehi = &link->eh_info;
921 	int poll_next;
922 
923 	lockdep_assert_held(ap->lock);
924 
925 	WARN_ON_ONCE((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
926 
927 	/* Make sure ata_sff_qc_issue() does not throw things
928 	 * like DMA polling into the workqueue. Notice that
929 	 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
930 	 */
931 	WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc));
932 
933 fsm_start:
934 	trace_ata_sff_hsm_state(qc, status);
935 
936 	switch (ap->hsm_task_state) {
937 	case HSM_ST_FIRST:
938 		/* Send first data block or PACKET CDB */
939 
940 		/* If polling, we will stay in the work queue after
941 		 * sending the data. Otherwise, interrupt handler
942 		 * takes over after sending the data.
943 		 */
944 		poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
945 
946 		/* check device status */
947 		if (unlikely((status & ATA_DRQ) == 0)) {
948 			/* handle BSY=0, DRQ=0 as error */
949 			if (likely(status & (ATA_ERR | ATA_DF)))
950 				/* device stops HSM for abort/error */
951 				qc->err_mask |= AC_ERR_DEV;
952 			else {
953 				/* HSM violation. Let EH handle this */
954 				ata_ehi_push_desc(ehi,
955 					"ST_FIRST: !(DRQ|ERR|DF)");
956 				qc->err_mask |= AC_ERR_HSM;
957 			}
958 
959 			ap->hsm_task_state = HSM_ST_ERR;
960 			goto fsm_start;
961 		}
962 
963 		/* Device should not ask for data transfer (DRQ=1)
964 		 * when it finds something wrong.
965 		 * We ignore DRQ here and stop the HSM by
966 		 * changing hsm_task_state to HSM_ST_ERR and
967 		 * let the EH abort the command or reset the device.
968 		 */
969 		if (unlikely(status & (ATA_ERR | ATA_DF))) {
970 			/* Some ATAPI tape drives forget to clear the ERR bit
971 			 * when doing the next command (mostly request sense).
972 			 * We ignore ERR here to workaround and proceed sending
973 			 * the CDB.
974 			 */
975 			if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
976 				ata_ehi_push_desc(ehi, "ST_FIRST: "
977 					"DRQ=1 with device error, "
978 					"dev_stat 0x%X", status);
979 				qc->err_mask |= AC_ERR_HSM;
980 				ap->hsm_task_state = HSM_ST_ERR;
981 				goto fsm_start;
982 			}
983 		}
984 
985 		if (qc->tf.protocol == ATA_PROT_PIO) {
986 			/* PIO data out protocol.
987 			 * send first data block.
988 			 */
989 
990 			/* ata_pio_sectors() might change the state
991 			 * to HSM_ST_LAST. so, the state is changed here
992 			 * before ata_pio_sectors().
993 			 */
994 			ap->hsm_task_state = HSM_ST;
995 			ata_pio_sectors(qc);
996 		} else
997 			/* send CDB */
998 			atapi_send_cdb(ap, qc);
999 
1000 		/* if polling, ata_sff_pio_task() handles the rest.
1001 		 * otherwise, interrupt handler takes over from here.
1002 		 */
1003 		break;
1004 
1005 	case HSM_ST:
1006 		/* complete command or read/write the data register */
1007 		if (qc->tf.protocol == ATAPI_PROT_PIO) {
1008 			/* ATAPI PIO protocol */
1009 			if ((status & ATA_DRQ) == 0) {
1010 				/* No more data to transfer or device error.
1011 				 * Device error will be tagged in HSM_ST_LAST.
1012 				 */
1013 				ap->hsm_task_state = HSM_ST_LAST;
1014 				goto fsm_start;
1015 			}
1016 
1017 			/* Device should not ask for data transfer (DRQ=1)
1018 			 * when it finds something wrong.
1019 			 * We ignore DRQ here and stop the HSM by
1020 			 * changing hsm_task_state to HSM_ST_ERR and
1021 			 * let the EH abort the command or reset the device.
1022 			 */
1023 			if (unlikely(status & (ATA_ERR | ATA_DF))) {
1024 				ata_ehi_push_desc(ehi, "ST-ATAPI: "
1025 					"DRQ=1 with device error, "
1026 					"dev_stat 0x%X", status);
1027 				qc->err_mask |= AC_ERR_HSM;
1028 				ap->hsm_task_state = HSM_ST_ERR;
1029 				goto fsm_start;
1030 			}
1031 
1032 			atapi_pio_bytes(qc);
1033 
1034 			if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
1035 				/* bad ireason reported by device */
1036 				goto fsm_start;
1037 
1038 		} else {
1039 			/* ATA PIO protocol */
1040 			if (unlikely((status & ATA_DRQ) == 0)) {
1041 				/* handle BSY=0, DRQ=0 as error */
1042 				if (likely(status & (ATA_ERR | ATA_DF))) {
1043 					/* device stops HSM for abort/error */
1044 					qc->err_mask |= AC_ERR_DEV;
1045 
1046 					/* If diagnostic failed and this is
1047 					 * IDENTIFY, it's likely a phantom
1048 					 * device.  Mark hint.
1049 					 */
1050 					if (qc->dev->horkage &
1051 					    ATA_HORKAGE_DIAGNOSTIC)
1052 						qc->err_mask |=
1053 							AC_ERR_NODEV_HINT;
1054 				} else {
1055 					/* HSM violation. Let EH handle this.
1056 					 * Phantom devices also trigger this
1057 					 * condition.  Mark hint.
1058 					 */
1059 					ata_ehi_push_desc(ehi, "ST-ATA: "
1060 						"DRQ=0 without device error, "
1061 						"dev_stat 0x%X", status);
1062 					qc->err_mask |= AC_ERR_HSM |
1063 							AC_ERR_NODEV_HINT;
1064 				}
1065 
1066 				ap->hsm_task_state = HSM_ST_ERR;
1067 				goto fsm_start;
1068 			}
1069 
1070 			/* For PIO reads, some devices may ask for
1071 			 * data transfer (DRQ=1) alone with ERR=1.
1072 			 * We respect DRQ here and transfer one
1073 			 * block of junk data before changing the
1074 			 * hsm_task_state to HSM_ST_ERR.
1075 			 *
1076 			 * For PIO writes, ERR=1 DRQ=1 doesn't make
1077 			 * sense since the data block has been
1078 			 * transferred to the device.
1079 			 */
1080 			if (unlikely(status & (ATA_ERR | ATA_DF))) {
1081 				/* data might be corrputed */
1082 				qc->err_mask |= AC_ERR_DEV;
1083 
1084 				if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
1085 					ata_pio_sectors(qc);
1086 					status = ata_wait_idle(ap);
1087 				}
1088 
1089 				if (status & (ATA_BUSY | ATA_DRQ)) {
1090 					ata_ehi_push_desc(ehi, "ST-ATA: "
1091 						"BUSY|DRQ persists on ERR|DF, "
1092 						"dev_stat 0x%X", status);
1093 					qc->err_mask |= AC_ERR_HSM;
1094 				}
1095 
1096 				/* There are oddball controllers with
1097 				 * status register stuck at 0x7f and
1098 				 * lbal/m/h at zero which makes it
1099 				 * pass all other presence detection
1100 				 * mechanisms we have.  Set NODEV_HINT
1101 				 * for it.  Kernel bz#7241.
1102 				 */
1103 				if (status == 0x7f)
1104 					qc->err_mask |= AC_ERR_NODEV_HINT;
1105 
1106 				/* ata_pio_sectors() might change the
1107 				 * state to HSM_ST_LAST. so, the state
1108 				 * is changed after ata_pio_sectors().
1109 				 */
1110 				ap->hsm_task_state = HSM_ST_ERR;
1111 				goto fsm_start;
1112 			}
1113 
1114 			ata_pio_sectors(qc);
1115 
1116 			if (ap->hsm_task_state == HSM_ST_LAST &&
1117 			    (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
1118 				/* all data read */
1119 				status = ata_wait_idle(ap);
1120 				goto fsm_start;
1121 			}
1122 		}
1123 
1124 		poll_next = 1;
1125 		break;
1126 
1127 	case HSM_ST_LAST:
1128 		if (unlikely(!ata_ok(status))) {
1129 			qc->err_mask |= __ac_err_mask(status);
1130 			ap->hsm_task_state = HSM_ST_ERR;
1131 			goto fsm_start;
1132 		}
1133 
1134 		/* no more data to transfer */
1135 		trace_ata_sff_hsm_command_complete(qc, status);
1136 
1137 		WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM));
1138 
1139 		ap->hsm_task_state = HSM_ST_IDLE;
1140 
1141 		/* complete taskfile transaction */
1142 		ata_hsm_qc_complete(qc, in_wq);
1143 
1144 		poll_next = 0;
1145 		break;
1146 
1147 	case HSM_ST_ERR:
1148 		ap->hsm_task_state = HSM_ST_IDLE;
1149 
1150 		/* complete taskfile transaction */
1151 		ata_hsm_qc_complete(qc, in_wq);
1152 
1153 		poll_next = 0;
1154 		break;
1155 	default:
1156 		poll_next = 0;
1157 		WARN(true, "ata%d: SFF host state machine in invalid state %d",
1158 		     ap->print_id, ap->hsm_task_state);
1159 	}
1160 
1161 	return poll_next;
1162 }
1163 EXPORT_SYMBOL_GPL(ata_sff_hsm_move);
1164 
ata_sff_queue_work(struct work_struct * work)1165 void ata_sff_queue_work(struct work_struct *work)
1166 {
1167 	queue_work(ata_sff_wq, work);
1168 }
1169 EXPORT_SYMBOL_GPL(ata_sff_queue_work);
1170 
ata_sff_queue_delayed_work(struct delayed_work * dwork,unsigned long delay)1171 void ata_sff_queue_delayed_work(struct delayed_work *dwork, unsigned long delay)
1172 {
1173 	queue_delayed_work(ata_sff_wq, dwork, delay);
1174 }
1175 EXPORT_SYMBOL_GPL(ata_sff_queue_delayed_work);
1176 
ata_sff_queue_pio_task(struct ata_link * link,unsigned long delay)1177 void ata_sff_queue_pio_task(struct ata_link *link, unsigned long delay)
1178 {
1179 	struct ata_port *ap = link->ap;
1180 
1181 	WARN_ON((ap->sff_pio_task_link != NULL) &&
1182 		(ap->sff_pio_task_link != link));
1183 	ap->sff_pio_task_link = link;
1184 
1185 	/* may fail if ata_sff_flush_pio_task() in progress */
1186 	ata_sff_queue_delayed_work(&ap->sff_pio_task, msecs_to_jiffies(delay));
1187 }
1188 EXPORT_SYMBOL_GPL(ata_sff_queue_pio_task);
1189 
ata_sff_flush_pio_task(struct ata_port * ap)1190 void ata_sff_flush_pio_task(struct ata_port *ap)
1191 {
1192 	trace_ata_sff_flush_pio_task(ap);
1193 
1194 	cancel_delayed_work_sync(&ap->sff_pio_task);
1195 
1196 	/*
1197 	 * We wanna reset the HSM state to IDLE.  If we do so without
1198 	 * grabbing the port lock, critical sections protected by it which
1199 	 * expect the HSM state to stay stable may get surprised.  For
1200 	 * example, we may set IDLE in between the time
1201 	 * __ata_sff_port_intr() checks for HSM_ST_IDLE and before it calls
1202 	 * ata_sff_hsm_move() causing ata_sff_hsm_move() to BUG().
1203 	 */
1204 	spin_lock_irq(ap->lock);
1205 	ap->hsm_task_state = HSM_ST_IDLE;
1206 	spin_unlock_irq(ap->lock);
1207 
1208 	ap->sff_pio_task_link = NULL;
1209 }
1210 
ata_sff_pio_task(struct work_struct * work)1211 static void ata_sff_pio_task(struct work_struct *work)
1212 {
1213 	struct ata_port *ap =
1214 		container_of(work, struct ata_port, sff_pio_task.work);
1215 	struct ata_link *link = ap->sff_pio_task_link;
1216 	struct ata_queued_cmd *qc;
1217 	u8 status;
1218 	int poll_next;
1219 
1220 	spin_lock_irq(ap->lock);
1221 
1222 	BUG_ON(ap->sff_pio_task_link == NULL);
1223 	/* qc can be NULL if timeout occurred */
1224 	qc = ata_qc_from_tag(ap, link->active_tag);
1225 	if (!qc) {
1226 		ap->sff_pio_task_link = NULL;
1227 		goto out_unlock;
1228 	}
1229 
1230 fsm_start:
1231 	WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE);
1232 
1233 	/*
1234 	 * This is purely heuristic.  This is a fast path.
1235 	 * Sometimes when we enter, BSY will be cleared in
1236 	 * a chk-status or two.  If not, the drive is probably seeking
1237 	 * or something.  Snooze for a couple msecs, then
1238 	 * chk-status again.  If still busy, queue delayed work.
1239 	 */
1240 	status = ata_sff_busy_wait(ap, ATA_BUSY, 5);
1241 	if (status & ATA_BUSY) {
1242 		spin_unlock_irq(ap->lock);
1243 		ata_msleep(ap, 2);
1244 		spin_lock_irq(ap->lock);
1245 
1246 		status = ata_sff_busy_wait(ap, ATA_BUSY, 10);
1247 		if (status & ATA_BUSY) {
1248 			ata_sff_queue_pio_task(link, ATA_SHORT_PAUSE);
1249 			goto out_unlock;
1250 		}
1251 	}
1252 
1253 	/*
1254 	 * hsm_move() may trigger another command to be processed.
1255 	 * clean the link beforehand.
1256 	 */
1257 	ap->sff_pio_task_link = NULL;
1258 	/* move the HSM */
1259 	poll_next = ata_sff_hsm_move(ap, qc, status, 1);
1260 
1261 	/* another command or interrupt handler
1262 	 * may be running at this point.
1263 	 */
1264 	if (poll_next)
1265 		goto fsm_start;
1266 out_unlock:
1267 	spin_unlock_irq(ap->lock);
1268 }
1269 
1270 /**
1271  *	ata_sff_qc_issue - issue taskfile to a SFF controller
1272  *	@qc: command to issue to device
1273  *
1274  *	This function issues a PIO or NODATA command to a SFF
1275  *	controller.
1276  *
1277  *	LOCKING:
1278  *	spin_lock_irqsave(host lock)
1279  *
1280  *	RETURNS:
1281  *	Zero on success, AC_ERR_* mask on failure
1282  */
ata_sff_qc_issue(struct ata_queued_cmd * qc)1283 unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
1284 {
1285 	struct ata_port *ap = qc->ap;
1286 	struct ata_link *link = qc->dev->link;
1287 
1288 	/* Use polling pio if the LLD doesn't handle
1289 	 * interrupt driven pio and atapi CDB interrupt.
1290 	 */
1291 	if (ap->flags & ATA_FLAG_PIO_POLLING)
1292 		qc->tf.flags |= ATA_TFLAG_POLLING;
1293 
1294 	/* select the device */
1295 	ata_dev_select(ap, qc->dev->devno, 1, 0);
1296 
1297 	/* start the command */
1298 	switch (qc->tf.protocol) {
1299 	case ATA_PROT_NODATA:
1300 		if (qc->tf.flags & ATA_TFLAG_POLLING)
1301 			ata_qc_set_polling(qc);
1302 
1303 		ata_tf_to_host(ap, &qc->tf, qc->tag);
1304 		ap->hsm_task_state = HSM_ST_LAST;
1305 
1306 		if (qc->tf.flags & ATA_TFLAG_POLLING)
1307 			ata_sff_queue_pio_task(link, 0);
1308 
1309 		break;
1310 
1311 	case ATA_PROT_PIO:
1312 		if (qc->tf.flags & ATA_TFLAG_POLLING)
1313 			ata_qc_set_polling(qc);
1314 
1315 		ata_tf_to_host(ap, &qc->tf, qc->tag);
1316 
1317 		if (qc->tf.flags & ATA_TFLAG_WRITE) {
1318 			/* PIO data out protocol */
1319 			ap->hsm_task_state = HSM_ST_FIRST;
1320 			ata_sff_queue_pio_task(link, 0);
1321 
1322 			/* always send first data block using the
1323 			 * ata_sff_pio_task() codepath.
1324 			 */
1325 		} else {
1326 			/* PIO data in protocol */
1327 			ap->hsm_task_state = HSM_ST;
1328 
1329 			if (qc->tf.flags & ATA_TFLAG_POLLING)
1330 				ata_sff_queue_pio_task(link, 0);
1331 
1332 			/* if polling, ata_sff_pio_task() handles the
1333 			 * rest.  otherwise, interrupt handler takes
1334 			 * over from here.
1335 			 */
1336 		}
1337 
1338 		break;
1339 
1340 	case ATAPI_PROT_PIO:
1341 	case ATAPI_PROT_NODATA:
1342 		if (qc->tf.flags & ATA_TFLAG_POLLING)
1343 			ata_qc_set_polling(qc);
1344 
1345 		ata_tf_to_host(ap, &qc->tf, qc->tag);
1346 
1347 		ap->hsm_task_state = HSM_ST_FIRST;
1348 
1349 		/* send cdb by polling if no cdb interrupt */
1350 		if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
1351 		    (qc->tf.flags & ATA_TFLAG_POLLING))
1352 			ata_sff_queue_pio_task(link, 0);
1353 		break;
1354 
1355 	default:
1356 		return AC_ERR_SYSTEM;
1357 	}
1358 
1359 	return 0;
1360 }
1361 EXPORT_SYMBOL_GPL(ata_sff_qc_issue);
1362 
1363 /**
1364  *	ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read
1365  *	@qc: qc to fill result TF for
1366  *
1367  *	@qc is finished and result TF needs to be filled.  Fill it
1368  *	using ->sff_tf_read.
1369  *
1370  *	LOCKING:
1371  *	spin_lock_irqsave(host lock)
1372  */
ata_sff_qc_fill_rtf(struct ata_queued_cmd * qc)1373 void ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc)
1374 {
1375 	qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf);
1376 }
1377 EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf);
1378 
ata_sff_idle_irq(struct ata_port * ap)1379 static unsigned int ata_sff_idle_irq(struct ata_port *ap)
1380 {
1381 	ap->stats.idle_irq++;
1382 
1383 #ifdef ATA_IRQ_TRAP
1384 	if ((ap->stats.idle_irq % 1000) == 0) {
1385 		ap->ops->sff_check_status(ap);
1386 		if (ap->ops->sff_irq_clear)
1387 			ap->ops->sff_irq_clear(ap);
1388 		ata_port_warn(ap, "irq trap\n");
1389 		return 1;
1390 	}
1391 #endif
1392 	return 0;	/* irq not handled */
1393 }
1394 
__ata_sff_port_intr(struct ata_port * ap,struct ata_queued_cmd * qc,bool hsmv_on_idle)1395 static unsigned int __ata_sff_port_intr(struct ata_port *ap,
1396 					struct ata_queued_cmd *qc,
1397 					bool hsmv_on_idle)
1398 {
1399 	u8 status;
1400 
1401 	trace_ata_sff_port_intr(qc, hsmv_on_idle);
1402 
1403 	/* Check whether we are expecting interrupt in this state */
1404 	switch (ap->hsm_task_state) {
1405 	case HSM_ST_FIRST:
1406 		/* Some pre-ATAPI-4 devices assert INTRQ
1407 		 * at this state when ready to receive CDB.
1408 		 */
1409 
1410 		/* Check the ATA_DFLAG_CDB_INTR flag is enough here.
1411 		 * The flag was turned on only for atapi devices.  No
1412 		 * need to check ata_is_atapi(qc->tf.protocol) again.
1413 		 */
1414 		if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1415 			return ata_sff_idle_irq(ap);
1416 		break;
1417 	case HSM_ST_IDLE:
1418 		return ata_sff_idle_irq(ap);
1419 	default:
1420 		break;
1421 	}
1422 
1423 	/* check main status, clearing INTRQ if needed */
1424 	status = ata_sff_irq_status(ap);
1425 	if (status & ATA_BUSY) {
1426 		if (hsmv_on_idle) {
1427 			/* BMDMA engine is already stopped, we're screwed */
1428 			qc->err_mask |= AC_ERR_HSM;
1429 			ap->hsm_task_state = HSM_ST_ERR;
1430 		} else
1431 			return ata_sff_idle_irq(ap);
1432 	}
1433 
1434 	/* clear irq events */
1435 	if (ap->ops->sff_irq_clear)
1436 		ap->ops->sff_irq_clear(ap);
1437 
1438 	ata_sff_hsm_move(ap, qc, status, 0);
1439 
1440 	return 1;	/* irq handled */
1441 }
1442 
1443 /**
1444  *	ata_sff_port_intr - Handle SFF port interrupt
1445  *	@ap: Port on which interrupt arrived (possibly...)
1446  *	@qc: Taskfile currently active in engine
1447  *
1448  *	Handle port interrupt for given queued command.
1449  *
1450  *	LOCKING:
1451  *	spin_lock_irqsave(host lock)
1452  *
1453  *	RETURNS:
1454  *	One if interrupt was handled, zero if not (shared irq).
1455  */
ata_sff_port_intr(struct ata_port * ap,struct ata_queued_cmd * qc)1456 unsigned int ata_sff_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
1457 {
1458 	return __ata_sff_port_intr(ap, qc, false);
1459 }
1460 EXPORT_SYMBOL_GPL(ata_sff_port_intr);
1461 
__ata_sff_interrupt(int irq,void * dev_instance,unsigned int (* port_intr)(struct ata_port *,struct ata_queued_cmd *))1462 static inline irqreturn_t __ata_sff_interrupt(int irq, void *dev_instance,
1463 	unsigned int (*port_intr)(struct ata_port *, struct ata_queued_cmd *))
1464 {
1465 	struct ata_host *host = dev_instance;
1466 	bool retried = false;
1467 	unsigned int i;
1468 	unsigned int handled, idle, polling;
1469 	unsigned long flags;
1470 
1471 	/* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
1472 	spin_lock_irqsave(&host->lock, flags);
1473 
1474 retry:
1475 	handled = idle = polling = 0;
1476 	for (i = 0; i < host->n_ports; i++) {
1477 		struct ata_port *ap = host->ports[i];
1478 		struct ata_queued_cmd *qc;
1479 
1480 		qc = ata_qc_from_tag(ap, ap->link.active_tag);
1481 		if (qc) {
1482 			if (!(qc->tf.flags & ATA_TFLAG_POLLING))
1483 				handled |= port_intr(ap, qc);
1484 			else
1485 				polling |= 1 << i;
1486 		} else
1487 			idle |= 1 << i;
1488 	}
1489 
1490 	/*
1491 	 * If no port was expecting IRQ but the controller is actually
1492 	 * asserting IRQ line, nobody cared will ensue.  Check IRQ
1493 	 * pending status if available and clear spurious IRQ.
1494 	 */
1495 	if (!handled && !retried) {
1496 		bool retry = false;
1497 
1498 		for (i = 0; i < host->n_ports; i++) {
1499 			struct ata_port *ap = host->ports[i];
1500 
1501 			if (polling & (1 << i))
1502 				continue;
1503 
1504 			if (!ap->ops->sff_irq_check ||
1505 			    !ap->ops->sff_irq_check(ap))
1506 				continue;
1507 
1508 			if (idle & (1 << i)) {
1509 				ap->ops->sff_check_status(ap);
1510 				if (ap->ops->sff_irq_clear)
1511 					ap->ops->sff_irq_clear(ap);
1512 			} else {
1513 				/* clear INTRQ and check if BUSY cleared */
1514 				if (!(ap->ops->sff_check_status(ap) & ATA_BUSY))
1515 					retry |= true;
1516 				/*
1517 				 * With command in flight, we can't do
1518 				 * sff_irq_clear() w/o racing with completion.
1519 				 */
1520 			}
1521 		}
1522 
1523 		if (retry) {
1524 			retried = true;
1525 			goto retry;
1526 		}
1527 	}
1528 
1529 	spin_unlock_irqrestore(&host->lock, flags);
1530 
1531 	return IRQ_RETVAL(handled);
1532 }
1533 
1534 /**
1535  *	ata_sff_interrupt - Default SFF ATA host interrupt handler
1536  *	@irq: irq line (unused)
1537  *	@dev_instance: pointer to our ata_host information structure
1538  *
1539  *	Default interrupt handler for PCI IDE devices.  Calls
1540  *	ata_sff_port_intr() for each port that is not disabled.
1541  *
1542  *	LOCKING:
1543  *	Obtains host lock during operation.
1544  *
1545  *	RETURNS:
1546  *	IRQ_NONE or IRQ_HANDLED.
1547  */
ata_sff_interrupt(int irq,void * dev_instance)1548 irqreturn_t ata_sff_interrupt(int irq, void *dev_instance)
1549 {
1550 	return __ata_sff_interrupt(irq, dev_instance, ata_sff_port_intr);
1551 }
1552 EXPORT_SYMBOL_GPL(ata_sff_interrupt);
1553 
1554 /**
1555  *	ata_sff_lost_interrupt	-	Check for an apparent lost interrupt
1556  *	@ap: port that appears to have timed out
1557  *
1558  *	Called from the libata error handlers when the core code suspects
1559  *	an interrupt has been lost. If it has complete anything we can and
1560  *	then return. Interface must support altstatus for this faster
1561  *	recovery to occur.
1562  *
1563  *	Locking:
1564  *	Caller holds host lock
1565  */
1566 
ata_sff_lost_interrupt(struct ata_port * ap)1567 void ata_sff_lost_interrupt(struct ata_port *ap)
1568 {
1569 	u8 status = 0;
1570 	struct ata_queued_cmd *qc;
1571 
1572 	/* Only one outstanding command per SFF channel */
1573 	qc = ata_qc_from_tag(ap, ap->link.active_tag);
1574 	/* We cannot lose an interrupt on a non-existent or polled command */
1575 	if (!qc || qc->tf.flags & ATA_TFLAG_POLLING)
1576 		return;
1577 	/* See if the controller thinks it is still busy - if so the command
1578 	   isn't a lost IRQ but is still in progress */
1579 	if (WARN_ON_ONCE(!ata_sff_altstatus(ap, &status)))
1580 		return;
1581 	if (status & ATA_BUSY)
1582 		return;
1583 
1584 	/* There was a command running, we are no longer busy and we have
1585 	   no interrupt. */
1586 	ata_port_warn(ap, "lost interrupt (Status 0x%x)\n", status);
1587 	/* Run the host interrupt logic as if the interrupt had not been
1588 	   lost */
1589 	ata_sff_port_intr(ap, qc);
1590 }
1591 EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt);
1592 
1593 /**
1594  *	ata_sff_freeze - Freeze SFF controller port
1595  *	@ap: port to freeze
1596  *
1597  *	Freeze SFF controller port.
1598  *
1599  *	LOCKING:
1600  *	Inherited from caller.
1601  */
ata_sff_freeze(struct ata_port * ap)1602 void ata_sff_freeze(struct ata_port *ap)
1603 {
1604 	ap->ctl |= ATA_NIEN;
1605 	ap->last_ctl = ap->ctl;
1606 
1607 	ata_sff_set_devctl(ap, ap->ctl);
1608 
1609 	/* Under certain circumstances, some controllers raise IRQ on
1610 	 * ATA_NIEN manipulation.  Also, many controllers fail to mask
1611 	 * previously pending IRQ on ATA_NIEN assertion.  Clear it.
1612 	 */
1613 	ap->ops->sff_check_status(ap);
1614 
1615 	if (ap->ops->sff_irq_clear)
1616 		ap->ops->sff_irq_clear(ap);
1617 }
1618 EXPORT_SYMBOL_GPL(ata_sff_freeze);
1619 
1620 /**
1621  *	ata_sff_thaw - Thaw SFF controller port
1622  *	@ap: port to thaw
1623  *
1624  *	Thaw SFF controller port.
1625  *
1626  *	LOCKING:
1627  *	Inherited from caller.
1628  */
ata_sff_thaw(struct ata_port * ap)1629 void ata_sff_thaw(struct ata_port *ap)
1630 {
1631 	/* clear & re-enable interrupts */
1632 	ap->ops->sff_check_status(ap);
1633 	if (ap->ops->sff_irq_clear)
1634 		ap->ops->sff_irq_clear(ap);
1635 	ata_sff_irq_on(ap);
1636 }
1637 EXPORT_SYMBOL_GPL(ata_sff_thaw);
1638 
1639 /**
1640  *	ata_sff_prereset - prepare SFF link for reset
1641  *	@link: SFF link to be reset
1642  *	@deadline: deadline jiffies for the operation
1643  *
1644  *	SFF link @link is about to be reset.  Initialize it.  It first
1645  *	calls ata_std_prereset() and wait for !BSY if the port is
1646  *	being softreset.
1647  *
1648  *	LOCKING:
1649  *	Kernel thread context (may sleep)
1650  *
1651  *	RETURNS:
1652  *	Always 0.
1653  */
ata_sff_prereset(struct ata_link * link,unsigned long deadline)1654 int ata_sff_prereset(struct ata_link *link, unsigned long deadline)
1655 {
1656 	struct ata_eh_context *ehc = &link->eh_context;
1657 	int rc;
1658 
1659 	/* The standard prereset is best-effort and always returns 0 */
1660 	ata_std_prereset(link, deadline);
1661 
1662 	/* if we're about to do hardreset, nothing more to do */
1663 	if (ehc->i.action & ATA_EH_HARDRESET)
1664 		return 0;
1665 
1666 	/* wait for !BSY if we don't know that no device is attached */
1667 	if (!ata_link_offline(link)) {
1668 		rc = ata_sff_wait_ready(link, deadline);
1669 		if (rc && rc != -ENODEV) {
1670 			ata_link_warn(link,
1671 				      "device not ready (errno=%d), forcing hardreset\n",
1672 				      rc);
1673 			ehc->i.action |= ATA_EH_HARDRESET;
1674 		}
1675 	}
1676 
1677 	return 0;
1678 }
1679 EXPORT_SYMBOL_GPL(ata_sff_prereset);
1680 
1681 /**
1682  *	ata_devchk - PATA device presence detection
1683  *	@ap: ATA channel to examine
1684  *	@device: Device to examine (starting at zero)
1685  *
1686  *	This technique was originally described in
1687  *	Hale Landis's ATADRVR (www.ata-atapi.com), and
1688  *	later found its way into the ATA/ATAPI spec.
1689  *
1690  *	Write a pattern to the ATA shadow registers,
1691  *	and if a device is present, it will respond by
1692  *	correctly storing and echoing back the
1693  *	ATA shadow register contents.
1694  *
1695  *	RETURN:
1696  *	true if device is present, false if not.
1697  *
1698  *	LOCKING:
1699  *	caller.
1700  */
ata_devchk(struct ata_port * ap,unsigned int device)1701 static bool ata_devchk(struct ata_port *ap, unsigned int device)
1702 {
1703 	struct ata_ioports *ioaddr = &ap->ioaddr;
1704 	u8 nsect, lbal;
1705 
1706 	ap->ops->sff_dev_select(ap, device);
1707 
1708 	iowrite8(0x55, ioaddr->nsect_addr);
1709 	iowrite8(0xaa, ioaddr->lbal_addr);
1710 
1711 	iowrite8(0xaa, ioaddr->nsect_addr);
1712 	iowrite8(0x55, ioaddr->lbal_addr);
1713 
1714 	iowrite8(0x55, ioaddr->nsect_addr);
1715 	iowrite8(0xaa, ioaddr->lbal_addr);
1716 
1717 	nsect = ioread8(ioaddr->nsect_addr);
1718 	lbal = ioread8(ioaddr->lbal_addr);
1719 
1720 	if ((nsect == 0x55) && (lbal == 0xaa))
1721 		return true;	/* we found a device */
1722 
1723 	return false;		/* nothing found */
1724 }
1725 
1726 /**
1727  *	ata_sff_dev_classify - Parse returned ATA device signature
1728  *	@dev: ATA device to classify (starting at zero)
1729  *	@present: device seems present
1730  *	@r_err: Value of error register on completion
1731  *
1732  *	After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
1733  *	an ATA/ATAPI-defined set of values is placed in the ATA
1734  *	shadow registers, indicating the results of device detection
1735  *	and diagnostics.
1736  *
1737  *	Select the ATA device, and read the values from the ATA shadow
1738  *	registers.  Then parse according to the Error register value,
1739  *	and the spec-defined values examined by ata_dev_classify().
1740  *
1741  *	LOCKING:
1742  *	caller.
1743  *
1744  *	RETURNS:
1745  *	Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1746  */
ata_sff_dev_classify(struct ata_device * dev,int present,u8 * r_err)1747 unsigned int ata_sff_dev_classify(struct ata_device *dev, int present,
1748 				  u8 *r_err)
1749 {
1750 	struct ata_port *ap = dev->link->ap;
1751 	struct ata_taskfile tf;
1752 	unsigned int class;
1753 	u8 err;
1754 
1755 	ap->ops->sff_dev_select(ap, dev->devno);
1756 
1757 	memset(&tf, 0, sizeof(tf));
1758 
1759 	ap->ops->sff_tf_read(ap, &tf);
1760 	err = tf.error;
1761 	if (r_err)
1762 		*r_err = err;
1763 
1764 	/* see if device passed diags: continue and warn later */
1765 	if (err == 0)
1766 		/* diagnostic fail : do nothing _YET_ */
1767 		dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
1768 	else if (err == 1)
1769 		/* do nothing */ ;
1770 	else if ((dev->devno == 0) && (err == 0x81))
1771 		/* do nothing */ ;
1772 	else
1773 		return ATA_DEV_NONE;
1774 
1775 	/* determine if device is ATA or ATAPI */
1776 	class = ata_port_classify(ap, &tf);
1777 	switch (class) {
1778 	case ATA_DEV_UNKNOWN:
1779 		/*
1780 		 * If the device failed diagnostic, it's likely to
1781 		 * have reported incorrect device signature too.
1782 		 * Assume ATA device if the device seems present but
1783 		 * device signature is invalid with diagnostic
1784 		 * failure.
1785 		 */
1786 		if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
1787 			class = ATA_DEV_ATA;
1788 		else
1789 			class = ATA_DEV_NONE;
1790 		break;
1791 	case ATA_DEV_ATA:
1792 		if (ap->ops->sff_check_status(ap) == 0)
1793 			class = ATA_DEV_NONE;
1794 		break;
1795 	}
1796 	return class;
1797 }
1798 EXPORT_SYMBOL_GPL(ata_sff_dev_classify);
1799 
1800 /**
1801  *	ata_sff_wait_after_reset - wait for devices to become ready after reset
1802  *	@link: SFF link which is just reset
1803  *	@devmask: mask of present devices
1804  *	@deadline: deadline jiffies for the operation
1805  *
1806  *	Wait devices attached to SFF @link to become ready after
1807  *	reset.  It contains preceding 150ms wait to avoid accessing TF
1808  *	status register too early.
1809  *
1810  *	LOCKING:
1811  *	Kernel thread context (may sleep).
1812  *
1813  *	RETURNS:
1814  *	0 on success, -ENODEV if some or all of devices in @devmask
1815  *	don't seem to exist.  -errno on other errors.
1816  */
ata_sff_wait_after_reset(struct ata_link * link,unsigned int devmask,unsigned long deadline)1817 int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask,
1818 			     unsigned long deadline)
1819 {
1820 	struct ata_port *ap = link->ap;
1821 	struct ata_ioports *ioaddr = &ap->ioaddr;
1822 	unsigned int dev0 = devmask & (1 << 0);
1823 	unsigned int dev1 = devmask & (1 << 1);
1824 	int rc, ret = 0;
1825 
1826 	ata_msleep(ap, ATA_WAIT_AFTER_RESET);
1827 
1828 	/* always check readiness of the master device */
1829 	rc = ata_sff_wait_ready(link, deadline);
1830 	/* -ENODEV means the odd clown forgot the D7 pulldown resistor
1831 	 * and TF status is 0xff, bail out on it too.
1832 	 */
1833 	if (rc)
1834 		return rc;
1835 
1836 	/* if device 1 was found in ata_devchk, wait for register
1837 	 * access briefly, then wait for BSY to clear.
1838 	 */
1839 	if (dev1) {
1840 		int i;
1841 
1842 		ap->ops->sff_dev_select(ap, 1);
1843 
1844 		/* Wait for register access.  Some ATAPI devices fail
1845 		 * to set nsect/lbal after reset, so don't waste too
1846 		 * much time on it.  We're gonna wait for !BSY anyway.
1847 		 */
1848 		for (i = 0; i < 2; i++) {
1849 			u8 nsect, lbal;
1850 
1851 			nsect = ioread8(ioaddr->nsect_addr);
1852 			lbal = ioread8(ioaddr->lbal_addr);
1853 			if ((nsect == 1) && (lbal == 1))
1854 				break;
1855 			ata_msleep(ap, 50);	/* give drive a breather */
1856 		}
1857 
1858 		rc = ata_sff_wait_ready(link, deadline);
1859 		if (rc) {
1860 			if (rc != -ENODEV)
1861 				return rc;
1862 			ret = rc;
1863 		}
1864 	}
1865 
1866 	/* is all this really necessary? */
1867 	ap->ops->sff_dev_select(ap, 0);
1868 	if (dev1)
1869 		ap->ops->sff_dev_select(ap, 1);
1870 	if (dev0)
1871 		ap->ops->sff_dev_select(ap, 0);
1872 
1873 	return ret;
1874 }
1875 EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset);
1876 
ata_bus_softreset(struct ata_port * ap,unsigned int devmask,unsigned long deadline)1877 static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
1878 			     unsigned long deadline)
1879 {
1880 	struct ata_ioports *ioaddr = &ap->ioaddr;
1881 
1882 	if (ap->ioaddr.ctl_addr) {
1883 		/* software reset.  causes dev0 to be selected */
1884 		iowrite8(ap->ctl, ioaddr->ctl_addr);
1885 		udelay(20);	/* FIXME: flush */
1886 		iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
1887 		udelay(20);	/* FIXME: flush */
1888 		iowrite8(ap->ctl, ioaddr->ctl_addr);
1889 		ap->last_ctl = ap->ctl;
1890 	}
1891 
1892 	/* wait the port to become ready */
1893 	return ata_sff_wait_after_reset(&ap->link, devmask, deadline);
1894 }
1895 
1896 /**
1897  *	ata_sff_softreset - reset host port via ATA SRST
1898  *	@link: ATA link to reset
1899  *	@classes: resulting classes of attached devices
1900  *	@deadline: deadline jiffies for the operation
1901  *
1902  *	Reset host port using ATA SRST.
1903  *
1904  *	LOCKING:
1905  *	Kernel thread context (may sleep)
1906  *
1907  *	RETURNS:
1908  *	0 on success, -errno otherwise.
1909  */
ata_sff_softreset(struct ata_link * link,unsigned int * classes,unsigned long deadline)1910 int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
1911 		      unsigned long deadline)
1912 {
1913 	struct ata_port *ap = link->ap;
1914 	unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
1915 	unsigned int devmask = 0;
1916 	int rc;
1917 	u8 err;
1918 
1919 	/* determine if device 0/1 are present */
1920 	if (ata_devchk(ap, 0))
1921 		devmask |= (1 << 0);
1922 	if (slave_possible && ata_devchk(ap, 1))
1923 		devmask |= (1 << 1);
1924 
1925 	/* select device 0 again */
1926 	ap->ops->sff_dev_select(ap, 0);
1927 
1928 	/* issue bus reset */
1929 	rc = ata_bus_softreset(ap, devmask, deadline);
1930 	/* if link is occupied, -ENODEV too is an error */
1931 	if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
1932 		ata_link_err(link, "SRST failed (errno=%d)\n", rc);
1933 		return rc;
1934 	}
1935 
1936 	/* determine by signature whether we have ATA or ATAPI devices */
1937 	classes[0] = ata_sff_dev_classify(&link->device[0],
1938 					  devmask & (1 << 0), &err);
1939 	if (slave_possible && err != 0x81)
1940 		classes[1] = ata_sff_dev_classify(&link->device[1],
1941 						  devmask & (1 << 1), &err);
1942 
1943 	return 0;
1944 }
1945 EXPORT_SYMBOL_GPL(ata_sff_softreset);
1946 
1947 /**
1948  *	sata_sff_hardreset - reset host port via SATA phy reset
1949  *	@link: link to reset
1950  *	@class: resulting class of attached device
1951  *	@deadline: deadline jiffies for the operation
1952  *
1953  *	SATA phy-reset host port using DET bits of SControl register,
1954  *	wait for !BSY and classify the attached device.
1955  *
1956  *	LOCKING:
1957  *	Kernel thread context (may sleep)
1958  *
1959  *	RETURNS:
1960  *	0 on success, -errno otherwise.
1961  */
sata_sff_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1962 int sata_sff_hardreset(struct ata_link *link, unsigned int *class,
1963 		       unsigned long deadline)
1964 {
1965 	struct ata_eh_context *ehc = &link->eh_context;
1966 	const unsigned int *timing = sata_ehc_deb_timing(ehc);
1967 	bool online;
1968 	int rc;
1969 
1970 	rc = sata_link_hardreset(link, timing, deadline, &online,
1971 				 ata_sff_check_ready);
1972 	if (online)
1973 		*class = ata_sff_dev_classify(link->device, 1, NULL);
1974 
1975 	return rc;
1976 }
1977 EXPORT_SYMBOL_GPL(sata_sff_hardreset);
1978 
1979 /**
1980  *	ata_sff_postreset - SFF postreset callback
1981  *	@link: the target SFF ata_link
1982  *	@classes: classes of attached devices
1983  *
1984  *	This function is invoked after a successful reset.  It first
1985  *	calls ata_std_postreset() and performs SFF specific postreset
1986  *	processing.
1987  *
1988  *	LOCKING:
1989  *	Kernel thread context (may sleep)
1990  */
ata_sff_postreset(struct ata_link * link,unsigned int * classes)1991 void ata_sff_postreset(struct ata_link *link, unsigned int *classes)
1992 {
1993 	struct ata_port *ap = link->ap;
1994 
1995 	ata_std_postreset(link, classes);
1996 
1997 	/* is double-select really necessary? */
1998 	if (classes[0] != ATA_DEV_NONE)
1999 		ap->ops->sff_dev_select(ap, 1);
2000 	if (classes[1] != ATA_DEV_NONE)
2001 		ap->ops->sff_dev_select(ap, 0);
2002 
2003 	/* bail out if no device is present */
2004 	if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE)
2005 		return;
2006 
2007 	/* set up device control */
2008 	if (ata_sff_set_devctl(ap, ap->ctl))
2009 		ap->last_ctl = ap->ctl;
2010 }
2011 EXPORT_SYMBOL_GPL(ata_sff_postreset);
2012 
2013 /**
2014  *	ata_sff_drain_fifo - Stock FIFO drain logic for SFF controllers
2015  *	@qc: command
2016  *
2017  *	Drain the FIFO and device of any stuck data following a command
2018  *	failing to complete. In some cases this is necessary before a
2019  *	reset will recover the device.
2020  *
2021  */
2022 
ata_sff_drain_fifo(struct ata_queued_cmd * qc)2023 void ata_sff_drain_fifo(struct ata_queued_cmd *qc)
2024 {
2025 	int count;
2026 	struct ata_port *ap;
2027 
2028 	/* We only need to flush incoming data when a command was running */
2029 	if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
2030 		return;
2031 
2032 	ap = qc->ap;
2033 	/* Drain up to 64K of data before we give up this recovery method */
2034 	for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ)
2035 						&& count < 65536; count += 2)
2036 		ioread16(ap->ioaddr.data_addr);
2037 
2038 	if (count)
2039 		ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count);
2040 
2041 }
2042 EXPORT_SYMBOL_GPL(ata_sff_drain_fifo);
2043 
2044 /**
2045  *	ata_sff_error_handler - Stock error handler for SFF controller
2046  *	@ap: port to handle error for
2047  *
2048  *	Stock error handler for SFF controller.  It can handle both
2049  *	PATA and SATA controllers.  Many controllers should be able to
2050  *	use this EH as-is or with some added handling before and
2051  *	after.
2052  *
2053  *	LOCKING:
2054  *	Kernel thread context (may sleep)
2055  */
ata_sff_error_handler(struct ata_port * ap)2056 void ata_sff_error_handler(struct ata_port *ap)
2057 {
2058 	ata_reset_fn_t softreset = ap->ops->softreset;
2059 	ata_reset_fn_t hardreset = ap->ops->hardreset;
2060 	struct ata_queued_cmd *qc;
2061 	unsigned long flags;
2062 
2063 	qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2064 	if (qc && !(qc->flags & ATA_QCFLAG_EH))
2065 		qc = NULL;
2066 
2067 	spin_lock_irqsave(ap->lock, flags);
2068 
2069 	/*
2070 	 * We *MUST* do FIFO draining before we issue a reset as
2071 	 * several devices helpfully clear their internal state and
2072 	 * will lock solid if we touch the data port post reset. Pass
2073 	 * qc in case anyone wants to do different PIO/DMA recovery or
2074 	 * has per command fixups
2075 	 */
2076 	if (ap->ops->sff_drain_fifo)
2077 		ap->ops->sff_drain_fifo(qc);
2078 
2079 	spin_unlock_irqrestore(ap->lock, flags);
2080 
2081 	/* ignore built-in hardresets if SCR access is not available */
2082 	if ((hardreset == sata_std_hardreset ||
2083 	     hardreset == sata_sff_hardreset) && !sata_scr_valid(&ap->link))
2084 		hardreset = NULL;
2085 
2086 	ata_do_eh(ap, ap->ops->prereset, softreset, hardreset,
2087 		  ap->ops->postreset);
2088 }
2089 EXPORT_SYMBOL_GPL(ata_sff_error_handler);
2090 
2091 /**
2092  *	ata_sff_std_ports - initialize ioaddr with standard port offsets.
2093  *	@ioaddr: IO address structure to be initialized
2094  *
2095  *	Utility function which initializes data_addr, error_addr,
2096  *	feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
2097  *	device_addr, status_addr, and command_addr to standard offsets
2098  *	relative to cmd_addr.
2099  *
2100  *	Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
2101  */
ata_sff_std_ports(struct ata_ioports * ioaddr)2102 void ata_sff_std_ports(struct ata_ioports *ioaddr)
2103 {
2104 	ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
2105 	ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
2106 	ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
2107 	ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
2108 	ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
2109 	ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
2110 	ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
2111 	ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
2112 	ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
2113 	ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
2114 }
2115 EXPORT_SYMBOL_GPL(ata_sff_std_ports);
2116 
2117 #ifdef CONFIG_PCI
2118 
ata_resources_present(struct pci_dev * pdev,int port)2119 static bool ata_resources_present(struct pci_dev *pdev, int port)
2120 {
2121 	int i;
2122 
2123 	/* Check the PCI resources for this channel are enabled */
2124 	port *= 2;
2125 	for (i = 0; i < 2; i++) {
2126 		if (pci_resource_start(pdev, port + i) == 0 ||
2127 		    pci_resource_len(pdev, port + i) == 0)
2128 			return false;
2129 	}
2130 	return true;
2131 }
2132 
2133 /**
2134  *	ata_pci_sff_init_host - acquire native PCI ATA resources and init host
2135  *	@host: target ATA host
2136  *
2137  *	Acquire native PCI ATA resources for @host and initialize the
2138  *	first two ports of @host accordingly.  Ports marked dummy are
2139  *	skipped and allocation failure makes the port dummy.
2140  *
2141  *	Note that native PCI resources are valid even for legacy hosts
2142  *	as we fix up pdev resources array early in boot, so this
2143  *	function can be used for both native and legacy SFF hosts.
2144  *
2145  *	LOCKING:
2146  *	Inherited from calling layer (may sleep).
2147  *
2148  *	RETURNS:
2149  *	0 if at least one port is initialized, -ENODEV if no port is
2150  *	available.
2151  */
ata_pci_sff_init_host(struct ata_host * host)2152 int ata_pci_sff_init_host(struct ata_host *host)
2153 {
2154 	struct device *gdev = host->dev;
2155 	struct pci_dev *pdev = to_pci_dev(gdev);
2156 	unsigned int mask = 0;
2157 	int i, rc;
2158 
2159 	/* request, iomap BARs and init port addresses accordingly */
2160 	for (i = 0; i < 2; i++) {
2161 		struct ata_port *ap = host->ports[i];
2162 		int base = i * 2;
2163 		void __iomem * const *iomap;
2164 
2165 		if (ata_port_is_dummy(ap))
2166 			continue;
2167 
2168 		/* Discard disabled ports.  Some controllers show
2169 		 * their unused channels this way.  Disabled ports are
2170 		 * made dummy.
2171 		 */
2172 		if (!ata_resources_present(pdev, i)) {
2173 			ap->ops = &ata_dummy_port_ops;
2174 			continue;
2175 		}
2176 
2177 		rc = pcim_iomap_regions(pdev, 0x3 << base,
2178 					dev_driver_string(gdev));
2179 		if (rc) {
2180 			dev_warn(gdev,
2181 				 "failed to request/iomap BARs for port %d (errno=%d)\n",
2182 				 i, rc);
2183 			if (rc == -EBUSY)
2184 				pcim_pin_device(pdev);
2185 			ap->ops = &ata_dummy_port_ops;
2186 			continue;
2187 		}
2188 		host->iomap = iomap = pcim_iomap_table(pdev);
2189 
2190 		ap->ioaddr.cmd_addr = iomap[base];
2191 		ap->ioaddr.altstatus_addr =
2192 		ap->ioaddr.ctl_addr = (void __iomem *)
2193 			((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS);
2194 		ata_sff_std_ports(&ap->ioaddr);
2195 
2196 		ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
2197 			(unsigned long long)pci_resource_start(pdev, base),
2198 			(unsigned long long)pci_resource_start(pdev, base + 1));
2199 
2200 		mask |= 1 << i;
2201 	}
2202 
2203 	if (!mask) {
2204 		dev_err(gdev, "no available native port\n");
2205 		return -ENODEV;
2206 	}
2207 
2208 	return 0;
2209 }
2210 EXPORT_SYMBOL_GPL(ata_pci_sff_init_host);
2211 
2212 /**
2213  *	ata_pci_sff_prepare_host - helper to prepare PCI PIO-only SFF ATA host
2214  *	@pdev: target PCI device
2215  *	@ppi: array of port_info, must be enough for two ports
2216  *	@r_host: out argument for the initialized ATA host
2217  *
2218  *	Helper to allocate PIO-only SFF ATA host for @pdev, acquire
2219  *	all PCI resources and initialize it accordingly in one go.
2220  *
2221  *	LOCKING:
2222  *	Inherited from calling layer (may sleep).
2223  *
2224  *	RETURNS:
2225  *	0 on success, -errno otherwise.
2226  */
ata_pci_sff_prepare_host(struct pci_dev * pdev,const struct ata_port_info * const * ppi,struct ata_host ** r_host)2227 int ata_pci_sff_prepare_host(struct pci_dev *pdev,
2228 			     const struct ata_port_info * const *ppi,
2229 			     struct ata_host **r_host)
2230 {
2231 	struct ata_host *host;
2232 	int rc;
2233 
2234 	if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
2235 		return -ENOMEM;
2236 
2237 	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
2238 	if (!host) {
2239 		dev_err(&pdev->dev, "failed to allocate ATA host\n");
2240 		rc = -ENOMEM;
2241 		goto err_out;
2242 	}
2243 
2244 	rc = ata_pci_sff_init_host(host);
2245 	if (rc)
2246 		goto err_out;
2247 
2248 	devres_remove_group(&pdev->dev, NULL);
2249 	*r_host = host;
2250 	return 0;
2251 
2252 err_out:
2253 	devres_release_group(&pdev->dev, NULL);
2254 	return rc;
2255 }
2256 EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host);
2257 
2258 /**
2259  *	ata_pci_sff_activate_host - start SFF host, request IRQ and register it
2260  *	@host: target SFF ATA host
2261  *	@irq_handler: irq_handler used when requesting IRQ(s)
2262  *	@sht: scsi_host_template to use when registering the host
2263  *
2264  *	This is the counterpart of ata_host_activate() for SFF ATA
2265  *	hosts.  This separate helper is necessary because SFF hosts
2266  *	use two separate interrupts in legacy mode.
2267  *
2268  *	LOCKING:
2269  *	Inherited from calling layer (may sleep).
2270  *
2271  *	RETURNS:
2272  *	0 on success, -errno otherwise.
2273  */
ata_pci_sff_activate_host(struct ata_host * host,irq_handler_t irq_handler,const struct scsi_host_template * sht)2274 int ata_pci_sff_activate_host(struct ata_host *host,
2275 			      irq_handler_t irq_handler,
2276 			      const struct scsi_host_template *sht)
2277 {
2278 	struct device *dev = host->dev;
2279 	struct pci_dev *pdev = to_pci_dev(dev);
2280 	const char *drv_name = dev_driver_string(host->dev);
2281 	int legacy_mode = 0, rc;
2282 
2283 	rc = ata_host_start(host);
2284 	if (rc)
2285 		return rc;
2286 
2287 	if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
2288 		u8 tmp8, mask = 0;
2289 
2290 		/*
2291 		 * ATA spec says we should use legacy mode when one
2292 		 * port is in legacy mode, but disabled ports on some
2293 		 * PCI hosts appear as fixed legacy ports, e.g SB600/700
2294 		 * on which the secondary port is not wired, so
2295 		 * ignore ports that are marked as 'dummy' during
2296 		 * this check
2297 		 */
2298 		pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
2299 		if (!ata_port_is_dummy(host->ports[0]))
2300 			mask |= (1 << 0);
2301 		if (!ata_port_is_dummy(host->ports[1]))
2302 			mask |= (1 << 2);
2303 		if ((tmp8 & mask) != mask)
2304 			legacy_mode = 1;
2305 	}
2306 
2307 	if (!devres_open_group(dev, NULL, GFP_KERNEL))
2308 		return -ENOMEM;
2309 
2310 	if (!legacy_mode && pdev->irq) {
2311 		int i;
2312 
2313 		rc = devm_request_irq(dev, pdev->irq, irq_handler,
2314 				      IRQF_SHARED, drv_name, host);
2315 		if (rc)
2316 			goto out;
2317 
2318 		for (i = 0; i < 2; i++) {
2319 			if (ata_port_is_dummy(host->ports[i]))
2320 				continue;
2321 			ata_port_desc(host->ports[i], "irq %d", pdev->irq);
2322 		}
2323 	} else if (legacy_mode) {
2324 		if (!ata_port_is_dummy(host->ports[0])) {
2325 			rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev),
2326 					      irq_handler, IRQF_SHARED,
2327 					      drv_name, host);
2328 			if (rc)
2329 				goto out;
2330 
2331 			ata_port_desc(host->ports[0], "irq %d",
2332 				      ATA_PRIMARY_IRQ(pdev));
2333 		}
2334 
2335 		if (!ata_port_is_dummy(host->ports[1])) {
2336 			rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev),
2337 					      irq_handler, IRQF_SHARED,
2338 					      drv_name, host);
2339 			if (rc)
2340 				goto out;
2341 
2342 			ata_port_desc(host->ports[1], "irq %d",
2343 				      ATA_SECONDARY_IRQ(pdev));
2344 		}
2345 	}
2346 
2347 	rc = ata_host_register(host, sht);
2348 out:
2349 	if (rc == 0)
2350 		devres_remove_group(dev, NULL);
2351 	else
2352 		devres_release_group(dev, NULL);
2353 
2354 	return rc;
2355 }
2356 EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host);
2357 
ata_sff_find_valid_pi(const struct ata_port_info * const * ppi)2358 static const struct ata_port_info *ata_sff_find_valid_pi(
2359 					const struct ata_port_info * const *ppi)
2360 {
2361 	int i;
2362 
2363 	/* look up the first valid port_info */
2364 	for (i = 0; i < 2 && ppi[i]; i++)
2365 		if (ppi[i]->port_ops != &ata_dummy_port_ops)
2366 			return ppi[i];
2367 
2368 	return NULL;
2369 }
2370 
ata_pci_init_one(struct pci_dev * pdev,const struct ata_port_info * const * ppi,const struct scsi_host_template * sht,void * host_priv,int hflags,bool bmdma)2371 static int ata_pci_init_one(struct pci_dev *pdev,
2372 		const struct ata_port_info * const *ppi,
2373 		const struct scsi_host_template *sht, void *host_priv,
2374 		int hflags, bool bmdma)
2375 {
2376 	struct device *dev = &pdev->dev;
2377 	const struct ata_port_info *pi;
2378 	struct ata_host *host = NULL;
2379 	int rc;
2380 
2381 	pi = ata_sff_find_valid_pi(ppi);
2382 	if (!pi) {
2383 		dev_err(&pdev->dev, "no valid port_info specified\n");
2384 		return -EINVAL;
2385 	}
2386 
2387 	if (!devres_open_group(dev, NULL, GFP_KERNEL))
2388 		return -ENOMEM;
2389 
2390 	rc = pcim_enable_device(pdev);
2391 	if (rc)
2392 		goto out;
2393 
2394 #ifdef CONFIG_ATA_BMDMA
2395 	if (bmdma)
2396 		/* prepare and activate BMDMA host */
2397 		rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
2398 	else
2399 #endif
2400 		/* prepare and activate SFF host */
2401 		rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
2402 	if (rc)
2403 		goto out;
2404 	host->private_data = host_priv;
2405 	host->flags |= hflags;
2406 
2407 #ifdef CONFIG_ATA_BMDMA
2408 	if (bmdma) {
2409 		pci_set_master(pdev);
2410 		rc = ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
2411 	} else
2412 #endif
2413 		rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht);
2414 out:
2415 	if (rc == 0)
2416 		devres_remove_group(&pdev->dev, NULL);
2417 	else
2418 		devres_release_group(&pdev->dev, NULL);
2419 
2420 	return rc;
2421 }
2422 
2423 /**
2424  *	ata_pci_sff_init_one - Initialize/register PIO-only PCI IDE controller
2425  *	@pdev: Controller to be initialized
2426  *	@ppi: array of port_info, must be enough for two ports
2427  *	@sht: scsi_host_template to use when registering the host
2428  *	@host_priv: host private_data
2429  *	@hflag: host flags
2430  *
2431  *	This is a helper function which can be called from a driver's
2432  *	xxx_init_one() probe function if the hardware uses traditional
2433  *	IDE taskfile registers and is PIO only.
2434  *
2435  *	ASSUMPTION:
2436  *	Nobody makes a single channel controller that appears solely as
2437  *	the secondary legacy port on PCI.
2438  *
2439  *	LOCKING:
2440  *	Inherited from PCI layer (may sleep).
2441  *
2442  *	RETURNS:
2443  *	Zero on success, negative on errno-based value on error.
2444  */
ata_pci_sff_init_one(struct pci_dev * pdev,const struct ata_port_info * const * ppi,const struct scsi_host_template * sht,void * host_priv,int hflag)2445 int ata_pci_sff_init_one(struct pci_dev *pdev,
2446 		 const struct ata_port_info * const *ppi,
2447 		 const struct scsi_host_template *sht, void *host_priv, int hflag)
2448 {
2449 	return ata_pci_init_one(pdev, ppi, sht, host_priv, hflag, 0);
2450 }
2451 EXPORT_SYMBOL_GPL(ata_pci_sff_init_one);
2452 
2453 #endif /* CONFIG_PCI */
2454 
2455 /*
2456  *	BMDMA support
2457  */
2458 
2459 #ifdef CONFIG_ATA_BMDMA
2460 
2461 const struct ata_port_operations ata_bmdma_port_ops = {
2462 	.inherits		= &ata_sff_port_ops,
2463 
2464 	.error_handler		= ata_bmdma_error_handler,
2465 	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
2466 
2467 	.qc_prep		= ata_bmdma_qc_prep,
2468 	.qc_issue		= ata_bmdma_qc_issue,
2469 
2470 	.sff_irq_clear		= ata_bmdma_irq_clear,
2471 	.bmdma_setup		= ata_bmdma_setup,
2472 	.bmdma_start		= ata_bmdma_start,
2473 	.bmdma_stop		= ata_bmdma_stop,
2474 	.bmdma_status		= ata_bmdma_status,
2475 
2476 	.port_start		= ata_bmdma_port_start,
2477 };
2478 EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
2479 
2480 const struct ata_port_operations ata_bmdma32_port_ops = {
2481 	.inherits		= &ata_bmdma_port_ops,
2482 
2483 	.sff_data_xfer		= ata_sff_data_xfer32,
2484 	.port_start		= ata_bmdma_port_start32,
2485 };
2486 EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops);
2487 
2488 /**
2489  *	ata_bmdma_fill_sg - Fill PCI IDE PRD table
2490  *	@qc: Metadata associated with taskfile to be transferred
2491  *
2492  *	Fill PCI IDE PRD (scatter-gather) table with segments
2493  *	associated with the current disk command.
2494  *
2495  *	LOCKING:
2496  *	spin_lock_irqsave(host lock)
2497  *
2498  */
ata_bmdma_fill_sg(struct ata_queued_cmd * qc)2499 static void ata_bmdma_fill_sg(struct ata_queued_cmd *qc)
2500 {
2501 	struct ata_port *ap = qc->ap;
2502 	struct ata_bmdma_prd *prd = ap->bmdma_prd;
2503 	struct scatterlist *sg;
2504 	unsigned int si, pi;
2505 
2506 	pi = 0;
2507 	for_each_sg(qc->sg, sg, qc->n_elem, si) {
2508 		u32 addr, offset;
2509 		u32 sg_len, len;
2510 
2511 		/* determine if physical DMA addr spans 64K boundary.
2512 		 * Note h/w doesn't support 64-bit, so we unconditionally
2513 		 * truncate dma_addr_t to u32.
2514 		 */
2515 		addr = (u32) sg_dma_address(sg);
2516 		sg_len = sg_dma_len(sg);
2517 
2518 		while (sg_len) {
2519 			offset = addr & 0xffff;
2520 			len = sg_len;
2521 			if ((offset + sg_len) > 0x10000)
2522 				len = 0x10000 - offset;
2523 
2524 			prd[pi].addr = cpu_to_le32(addr);
2525 			prd[pi].flags_len = cpu_to_le32(len & 0xffff);
2526 
2527 			pi++;
2528 			sg_len -= len;
2529 			addr += len;
2530 		}
2531 	}
2532 
2533 	prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2534 }
2535 
2536 /**
2537  *	ata_bmdma_fill_sg_dumb - Fill PCI IDE PRD table
2538  *	@qc: Metadata associated with taskfile to be transferred
2539  *
2540  *	Fill PCI IDE PRD (scatter-gather) table with segments
2541  *	associated with the current disk command. Perform the fill
2542  *	so that we avoid writing any length 64K records for
2543  *	controllers that don't follow the spec.
2544  *
2545  *	LOCKING:
2546  *	spin_lock_irqsave(host lock)
2547  *
2548  */
ata_bmdma_fill_sg_dumb(struct ata_queued_cmd * qc)2549 static void ata_bmdma_fill_sg_dumb(struct ata_queued_cmd *qc)
2550 {
2551 	struct ata_port *ap = qc->ap;
2552 	struct ata_bmdma_prd *prd = ap->bmdma_prd;
2553 	struct scatterlist *sg;
2554 	unsigned int si, pi;
2555 
2556 	pi = 0;
2557 	for_each_sg(qc->sg, sg, qc->n_elem, si) {
2558 		u32 addr, offset;
2559 		u32 sg_len, len, blen;
2560 
2561 		/* determine if physical DMA addr spans 64K boundary.
2562 		 * Note h/w doesn't support 64-bit, so we unconditionally
2563 		 * truncate dma_addr_t to u32.
2564 		 */
2565 		addr = (u32) sg_dma_address(sg);
2566 		sg_len = sg_dma_len(sg);
2567 
2568 		while (sg_len) {
2569 			offset = addr & 0xffff;
2570 			len = sg_len;
2571 			if ((offset + sg_len) > 0x10000)
2572 				len = 0x10000 - offset;
2573 
2574 			blen = len & 0xffff;
2575 			prd[pi].addr = cpu_to_le32(addr);
2576 			if (blen == 0) {
2577 				/* Some PATA chipsets like the CS5530 can't
2578 				   cope with 0x0000 meaning 64K as the spec
2579 				   says */
2580 				prd[pi].flags_len = cpu_to_le32(0x8000);
2581 				blen = 0x8000;
2582 				prd[++pi].addr = cpu_to_le32(addr + 0x8000);
2583 			}
2584 			prd[pi].flags_len = cpu_to_le32(blen);
2585 
2586 			pi++;
2587 			sg_len -= len;
2588 			addr += len;
2589 		}
2590 	}
2591 
2592 	prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2593 }
2594 
2595 /**
2596  *	ata_bmdma_qc_prep - Prepare taskfile for submission
2597  *	@qc: Metadata associated with taskfile to be prepared
2598  *
2599  *	Prepare ATA taskfile for submission.
2600  *
2601  *	LOCKING:
2602  *	spin_lock_irqsave(host lock)
2603  */
ata_bmdma_qc_prep(struct ata_queued_cmd * qc)2604 enum ata_completion_errors ata_bmdma_qc_prep(struct ata_queued_cmd *qc)
2605 {
2606 	if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2607 		return AC_ERR_OK;
2608 
2609 	ata_bmdma_fill_sg(qc);
2610 
2611 	return AC_ERR_OK;
2612 }
2613 EXPORT_SYMBOL_GPL(ata_bmdma_qc_prep);
2614 
2615 /**
2616  *	ata_bmdma_dumb_qc_prep - Prepare taskfile for submission
2617  *	@qc: Metadata associated with taskfile to be prepared
2618  *
2619  *	Prepare ATA taskfile for submission.
2620  *
2621  *	LOCKING:
2622  *	spin_lock_irqsave(host lock)
2623  */
ata_bmdma_dumb_qc_prep(struct ata_queued_cmd * qc)2624 enum ata_completion_errors ata_bmdma_dumb_qc_prep(struct ata_queued_cmd *qc)
2625 {
2626 	if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2627 		return AC_ERR_OK;
2628 
2629 	ata_bmdma_fill_sg_dumb(qc);
2630 
2631 	return AC_ERR_OK;
2632 }
2633 EXPORT_SYMBOL_GPL(ata_bmdma_dumb_qc_prep);
2634 
2635 /**
2636  *	ata_bmdma_qc_issue - issue taskfile to a BMDMA controller
2637  *	@qc: command to issue to device
2638  *
2639  *	This function issues a PIO, NODATA or DMA command to a
2640  *	SFF/BMDMA controller.  PIO and NODATA are handled by
2641  *	ata_sff_qc_issue().
2642  *
2643  *	LOCKING:
2644  *	spin_lock_irqsave(host lock)
2645  *
2646  *	RETURNS:
2647  *	Zero on success, AC_ERR_* mask on failure
2648  */
ata_bmdma_qc_issue(struct ata_queued_cmd * qc)2649 unsigned int ata_bmdma_qc_issue(struct ata_queued_cmd *qc)
2650 {
2651 	struct ata_port *ap = qc->ap;
2652 	struct ata_link *link = qc->dev->link;
2653 
2654 	/* defer PIO handling to sff_qc_issue */
2655 	if (!ata_is_dma(qc->tf.protocol))
2656 		return ata_sff_qc_issue(qc);
2657 
2658 	/* select the device */
2659 	ata_dev_select(ap, qc->dev->devno, 1, 0);
2660 
2661 	/* start the command */
2662 	switch (qc->tf.protocol) {
2663 	case ATA_PROT_DMA:
2664 		WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
2665 
2666 		trace_ata_tf_load(ap, &qc->tf);
2667 		ap->ops->sff_tf_load(ap, &qc->tf);  /* load tf registers */
2668 		trace_ata_bmdma_setup(ap, &qc->tf, qc->tag);
2669 		ap->ops->bmdma_setup(qc);	    /* set up bmdma */
2670 		trace_ata_bmdma_start(ap, &qc->tf, qc->tag);
2671 		ap->ops->bmdma_start(qc);	    /* initiate bmdma */
2672 		ap->hsm_task_state = HSM_ST_LAST;
2673 		break;
2674 
2675 	case ATAPI_PROT_DMA:
2676 		WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
2677 
2678 		trace_ata_tf_load(ap, &qc->tf);
2679 		ap->ops->sff_tf_load(ap, &qc->tf);  /* load tf registers */
2680 		trace_ata_bmdma_setup(ap, &qc->tf, qc->tag);
2681 		ap->ops->bmdma_setup(qc);	    /* set up bmdma */
2682 		ap->hsm_task_state = HSM_ST_FIRST;
2683 
2684 		/* send cdb by polling if no cdb interrupt */
2685 		if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
2686 			ata_sff_queue_pio_task(link, 0);
2687 		break;
2688 
2689 	default:
2690 		WARN_ON(1);
2691 		return AC_ERR_SYSTEM;
2692 	}
2693 
2694 	return 0;
2695 }
2696 EXPORT_SYMBOL_GPL(ata_bmdma_qc_issue);
2697 
2698 /**
2699  *	ata_bmdma_port_intr - Handle BMDMA port interrupt
2700  *	@ap: Port on which interrupt arrived (possibly...)
2701  *	@qc: Taskfile currently active in engine
2702  *
2703  *	Handle port interrupt for given queued command.
2704  *
2705  *	LOCKING:
2706  *	spin_lock_irqsave(host lock)
2707  *
2708  *	RETURNS:
2709  *	One if interrupt was handled, zero if not (shared irq).
2710  */
ata_bmdma_port_intr(struct ata_port * ap,struct ata_queued_cmd * qc)2711 unsigned int ata_bmdma_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
2712 {
2713 	struct ata_eh_info *ehi = &ap->link.eh_info;
2714 	u8 host_stat = 0;
2715 	bool bmdma_stopped = false;
2716 	unsigned int handled;
2717 
2718 	if (ap->hsm_task_state == HSM_ST_LAST && ata_is_dma(qc->tf.protocol)) {
2719 		/* check status of DMA engine */
2720 		host_stat = ap->ops->bmdma_status(ap);
2721 		trace_ata_bmdma_status(ap, host_stat);
2722 
2723 		/* if it's not our irq... */
2724 		if (!(host_stat & ATA_DMA_INTR))
2725 			return ata_sff_idle_irq(ap);
2726 
2727 		/* before we do anything else, clear DMA-Start bit */
2728 		trace_ata_bmdma_stop(ap, &qc->tf, qc->tag);
2729 		ap->ops->bmdma_stop(qc);
2730 		bmdma_stopped = true;
2731 
2732 		if (unlikely(host_stat & ATA_DMA_ERR)) {
2733 			/* error when transferring data to/from memory */
2734 			qc->err_mask |= AC_ERR_HOST_BUS;
2735 			ap->hsm_task_state = HSM_ST_ERR;
2736 		}
2737 	}
2738 
2739 	handled = __ata_sff_port_intr(ap, qc, bmdma_stopped);
2740 
2741 	if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
2742 		ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
2743 
2744 	return handled;
2745 }
2746 EXPORT_SYMBOL_GPL(ata_bmdma_port_intr);
2747 
2748 /**
2749  *	ata_bmdma_interrupt - Default BMDMA ATA host interrupt handler
2750  *	@irq: irq line (unused)
2751  *	@dev_instance: pointer to our ata_host information structure
2752  *
2753  *	Default interrupt handler for PCI IDE devices.  Calls
2754  *	ata_bmdma_port_intr() for each port that is not disabled.
2755  *
2756  *	LOCKING:
2757  *	Obtains host lock during operation.
2758  *
2759  *	RETURNS:
2760  *	IRQ_NONE or IRQ_HANDLED.
2761  */
ata_bmdma_interrupt(int irq,void * dev_instance)2762 irqreturn_t ata_bmdma_interrupt(int irq, void *dev_instance)
2763 {
2764 	return __ata_sff_interrupt(irq, dev_instance, ata_bmdma_port_intr);
2765 }
2766 EXPORT_SYMBOL_GPL(ata_bmdma_interrupt);
2767 
2768 /**
2769  *	ata_bmdma_error_handler - Stock error handler for BMDMA controller
2770  *	@ap: port to handle error for
2771  *
2772  *	Stock error handler for BMDMA controller.  It can handle both
2773  *	PATA and SATA controllers.  Most BMDMA controllers should be
2774  *	able to use this EH as-is or with some added handling before
2775  *	and after.
2776  *
2777  *	LOCKING:
2778  *	Kernel thread context (may sleep)
2779  */
ata_bmdma_error_handler(struct ata_port * ap)2780 void ata_bmdma_error_handler(struct ata_port *ap)
2781 {
2782 	struct ata_queued_cmd *qc;
2783 	unsigned long flags;
2784 	bool thaw = false;
2785 
2786 	qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2787 	if (qc && !(qc->flags & ATA_QCFLAG_EH))
2788 		qc = NULL;
2789 
2790 	/* reset PIO HSM and stop DMA engine */
2791 	spin_lock_irqsave(ap->lock, flags);
2792 
2793 	if (qc && ata_is_dma(qc->tf.protocol)) {
2794 		u8 host_stat;
2795 
2796 		host_stat = ap->ops->bmdma_status(ap);
2797 		trace_ata_bmdma_status(ap, host_stat);
2798 
2799 		/* BMDMA controllers indicate host bus error by
2800 		 * setting DMA_ERR bit and timing out.  As it wasn't
2801 		 * really a timeout event, adjust error mask and
2802 		 * cancel frozen state.
2803 		 */
2804 		if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) {
2805 			qc->err_mask = AC_ERR_HOST_BUS;
2806 			thaw = true;
2807 		}
2808 
2809 		trace_ata_bmdma_stop(ap, &qc->tf, qc->tag);
2810 		ap->ops->bmdma_stop(qc);
2811 
2812 		/* if we're gonna thaw, make sure IRQ is clear */
2813 		if (thaw) {
2814 			ap->ops->sff_check_status(ap);
2815 			if (ap->ops->sff_irq_clear)
2816 				ap->ops->sff_irq_clear(ap);
2817 		}
2818 	}
2819 
2820 	spin_unlock_irqrestore(ap->lock, flags);
2821 
2822 	if (thaw)
2823 		ata_eh_thaw_port(ap);
2824 
2825 	ata_sff_error_handler(ap);
2826 }
2827 EXPORT_SYMBOL_GPL(ata_bmdma_error_handler);
2828 
2829 /**
2830  *	ata_bmdma_post_internal_cmd - Stock post_internal_cmd for BMDMA
2831  *	@qc: internal command to clean up
2832  *
2833  *	LOCKING:
2834  *	Kernel thread context (may sleep)
2835  */
ata_bmdma_post_internal_cmd(struct ata_queued_cmd * qc)2836 void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc)
2837 {
2838 	struct ata_port *ap = qc->ap;
2839 	unsigned long flags;
2840 
2841 	if (ata_is_dma(qc->tf.protocol)) {
2842 		spin_lock_irqsave(ap->lock, flags);
2843 		trace_ata_bmdma_stop(ap, &qc->tf, qc->tag);
2844 		ap->ops->bmdma_stop(qc);
2845 		spin_unlock_irqrestore(ap->lock, flags);
2846 	}
2847 }
2848 EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd);
2849 
2850 /**
2851  *	ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
2852  *	@ap: Port associated with this ATA transaction.
2853  *
2854  *	Clear interrupt and error flags in DMA status register.
2855  *
2856  *	May be used as the irq_clear() entry in ata_port_operations.
2857  *
2858  *	LOCKING:
2859  *	spin_lock_irqsave(host lock)
2860  */
ata_bmdma_irq_clear(struct ata_port * ap)2861 void ata_bmdma_irq_clear(struct ata_port *ap)
2862 {
2863 	void __iomem *mmio = ap->ioaddr.bmdma_addr;
2864 
2865 	if (!mmio)
2866 		return;
2867 
2868 	iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
2869 }
2870 EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
2871 
2872 /**
2873  *	ata_bmdma_setup - Set up PCI IDE BMDMA transaction
2874  *	@qc: Info associated with this ATA transaction.
2875  *
2876  *	LOCKING:
2877  *	spin_lock_irqsave(host lock)
2878  */
ata_bmdma_setup(struct ata_queued_cmd * qc)2879 void ata_bmdma_setup(struct ata_queued_cmd *qc)
2880 {
2881 	struct ata_port *ap = qc->ap;
2882 	unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
2883 	u8 dmactl;
2884 
2885 	/* load PRD table addr. */
2886 	mb();	/* make sure PRD table writes are visible to controller */
2887 	iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
2888 
2889 	/* specify data direction, triple-check start bit is clear */
2890 	dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2891 	dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
2892 	if (!rw)
2893 		dmactl |= ATA_DMA_WR;
2894 	iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2895 
2896 	/* issue r/w command */
2897 	ap->ops->sff_exec_command(ap, &qc->tf);
2898 }
2899 EXPORT_SYMBOL_GPL(ata_bmdma_setup);
2900 
2901 /**
2902  *	ata_bmdma_start - Start a PCI IDE BMDMA transaction
2903  *	@qc: Info associated with this ATA transaction.
2904  *
2905  *	LOCKING:
2906  *	spin_lock_irqsave(host lock)
2907  */
ata_bmdma_start(struct ata_queued_cmd * qc)2908 void ata_bmdma_start(struct ata_queued_cmd *qc)
2909 {
2910 	struct ata_port *ap = qc->ap;
2911 	u8 dmactl;
2912 
2913 	/* start host DMA transaction */
2914 	dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2915 	iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2916 
2917 	/* Strictly, one may wish to issue an ioread8() here, to
2918 	 * flush the mmio write.  However, control also passes
2919 	 * to the hardware at this point, and it will interrupt
2920 	 * us when we are to resume control.  So, in effect,
2921 	 * we don't care when the mmio write flushes.
2922 	 * Further, a read of the DMA status register _immediately_
2923 	 * following the write may not be what certain flaky hardware
2924 	 * is expected, so I think it is best to not add a readb()
2925 	 * without first all the MMIO ATA cards/mobos.
2926 	 * Or maybe I'm just being paranoid.
2927 	 *
2928 	 * FIXME: The posting of this write means I/O starts are
2929 	 * unnecessarily delayed for MMIO
2930 	 */
2931 }
2932 EXPORT_SYMBOL_GPL(ata_bmdma_start);
2933 
2934 /**
2935  *	ata_bmdma_stop - Stop PCI IDE BMDMA transfer
2936  *	@qc: Command we are ending DMA for
2937  *
2938  *	Clears the ATA_DMA_START flag in the dma control register
2939  *
2940  *	May be used as the bmdma_stop() entry in ata_port_operations.
2941  *
2942  *	LOCKING:
2943  *	spin_lock_irqsave(host lock)
2944  */
ata_bmdma_stop(struct ata_queued_cmd * qc)2945 void ata_bmdma_stop(struct ata_queued_cmd *qc)
2946 {
2947 	struct ata_port *ap = qc->ap;
2948 	void __iomem *mmio = ap->ioaddr.bmdma_addr;
2949 
2950 	/* clear start/stop bit */
2951 	iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
2952 		 mmio + ATA_DMA_CMD);
2953 
2954 	/* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
2955 	ata_sff_dma_pause(ap);
2956 }
2957 EXPORT_SYMBOL_GPL(ata_bmdma_stop);
2958 
2959 /**
2960  *	ata_bmdma_status - Read PCI IDE BMDMA status
2961  *	@ap: Port associated with this ATA transaction.
2962  *
2963  *	Read and return BMDMA status register.
2964  *
2965  *	May be used as the bmdma_status() entry in ata_port_operations.
2966  *
2967  *	LOCKING:
2968  *	spin_lock_irqsave(host lock)
2969  */
ata_bmdma_status(struct ata_port * ap)2970 u8 ata_bmdma_status(struct ata_port *ap)
2971 {
2972 	return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
2973 }
2974 EXPORT_SYMBOL_GPL(ata_bmdma_status);
2975 
2976 
2977 /**
2978  *	ata_bmdma_port_start - Set port up for bmdma.
2979  *	@ap: Port to initialize
2980  *
2981  *	Called just after data structures for each port are
2982  *	initialized.  Allocates space for PRD table.
2983  *
2984  *	May be used as the port_start() entry in ata_port_operations.
2985  *
2986  *	LOCKING:
2987  *	Inherited from caller.
2988  */
ata_bmdma_port_start(struct ata_port * ap)2989 int ata_bmdma_port_start(struct ata_port *ap)
2990 {
2991 	if (ap->mwdma_mask || ap->udma_mask) {
2992 		ap->bmdma_prd =
2993 			dmam_alloc_coherent(ap->host->dev, ATA_PRD_TBL_SZ,
2994 					    &ap->bmdma_prd_dma, GFP_KERNEL);
2995 		if (!ap->bmdma_prd)
2996 			return -ENOMEM;
2997 	}
2998 
2999 	return 0;
3000 }
3001 EXPORT_SYMBOL_GPL(ata_bmdma_port_start);
3002 
3003 /**
3004  *	ata_bmdma_port_start32 - Set port up for dma.
3005  *	@ap: Port to initialize
3006  *
3007  *	Called just after data structures for each port are
3008  *	initialized.  Enables 32bit PIO and allocates space for PRD
3009  *	table.
3010  *
3011  *	May be used as the port_start() entry in ata_port_operations for
3012  *	devices that are capable of 32bit PIO.
3013  *
3014  *	LOCKING:
3015  *	Inherited from caller.
3016  */
ata_bmdma_port_start32(struct ata_port * ap)3017 int ata_bmdma_port_start32(struct ata_port *ap)
3018 {
3019 	ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
3020 	return ata_bmdma_port_start(ap);
3021 }
3022 EXPORT_SYMBOL_GPL(ata_bmdma_port_start32);
3023 
3024 #ifdef CONFIG_PCI
3025 
3026 /**
3027  *	ata_pci_bmdma_clear_simplex -	attempt to kick device out of simplex
3028  *	@pdev: PCI device
3029  *
3030  *	Some PCI ATA devices report simplex mode but in fact can be told to
3031  *	enter non simplex mode. This implements the necessary logic to
3032  *	perform the task on such devices. Calling it on other devices will
3033  *	have -undefined- behaviour.
3034  */
ata_pci_bmdma_clear_simplex(struct pci_dev * pdev)3035 int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
3036 {
3037 	unsigned long bmdma = pci_resource_start(pdev, 4);
3038 	u8 simplex;
3039 
3040 	if (bmdma == 0)
3041 		return -ENOENT;
3042 
3043 	simplex = inb(bmdma + 0x02);
3044 	outb(simplex & 0x60, bmdma + 0x02);
3045 	simplex = inb(bmdma + 0x02);
3046 	if (simplex & 0x80)
3047 		return -EOPNOTSUPP;
3048 	return 0;
3049 }
3050 EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
3051 
ata_bmdma_nodma(struct ata_host * host,const char * reason)3052 static void ata_bmdma_nodma(struct ata_host *host, const char *reason)
3053 {
3054 	int i;
3055 
3056 	dev_err(host->dev, "BMDMA: %s, falling back to PIO\n", reason);
3057 
3058 	for (i = 0; i < 2; i++) {
3059 		host->ports[i]->mwdma_mask = 0;
3060 		host->ports[i]->udma_mask = 0;
3061 	}
3062 }
3063 
3064 /**
3065  *	ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
3066  *	@host: target ATA host
3067  *
3068  *	Acquire PCI BMDMA resources and initialize @host accordingly.
3069  *
3070  *	LOCKING:
3071  *	Inherited from calling layer (may sleep).
3072  */
ata_pci_bmdma_init(struct ata_host * host)3073 void ata_pci_bmdma_init(struct ata_host *host)
3074 {
3075 	struct device *gdev = host->dev;
3076 	struct pci_dev *pdev = to_pci_dev(gdev);
3077 	int i, rc;
3078 
3079 	/* No BAR4 allocation: No DMA */
3080 	if (pci_resource_start(pdev, 4) == 0) {
3081 		ata_bmdma_nodma(host, "BAR4 is zero");
3082 		return;
3083 	}
3084 
3085 	/*
3086 	 * Some controllers require BMDMA region to be initialized
3087 	 * even if DMA is not in use to clear IRQ status via
3088 	 * ->sff_irq_clear method.  Try to initialize bmdma_addr
3089 	 * regardless of dma masks.
3090 	 */
3091 	rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
3092 	if (rc)
3093 		ata_bmdma_nodma(host, "failed to set dma mask");
3094 
3095 	/* request and iomap DMA region */
3096 	rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
3097 	if (rc) {
3098 		ata_bmdma_nodma(host, "failed to request/iomap BAR4");
3099 		return;
3100 	}
3101 	host->iomap = pcim_iomap_table(pdev);
3102 
3103 	for (i = 0; i < 2; i++) {
3104 		struct ata_port *ap = host->ports[i];
3105 		void __iomem *bmdma = host->iomap[4] + 8 * i;
3106 
3107 		if (ata_port_is_dummy(ap))
3108 			continue;
3109 
3110 		ap->ioaddr.bmdma_addr = bmdma;
3111 		if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
3112 		    (ioread8(bmdma + 2) & 0x80))
3113 			host->flags |= ATA_HOST_SIMPLEX;
3114 
3115 		ata_port_desc(ap, "bmdma 0x%llx",
3116 		    (unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
3117 	}
3118 }
3119 EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
3120 
3121 /**
3122  *	ata_pci_bmdma_prepare_host - helper to prepare PCI BMDMA ATA host
3123  *	@pdev: target PCI device
3124  *	@ppi: array of port_info, must be enough for two ports
3125  *	@r_host: out argument for the initialized ATA host
3126  *
3127  *	Helper to allocate BMDMA ATA host for @pdev, acquire all PCI
3128  *	resources and initialize it accordingly in one go.
3129  *
3130  *	LOCKING:
3131  *	Inherited from calling layer (may sleep).
3132  *
3133  *	RETURNS:
3134  *	0 on success, -errno otherwise.
3135  */
ata_pci_bmdma_prepare_host(struct pci_dev * pdev,const struct ata_port_info * const * ppi,struct ata_host ** r_host)3136 int ata_pci_bmdma_prepare_host(struct pci_dev *pdev,
3137 			       const struct ata_port_info * const * ppi,
3138 			       struct ata_host **r_host)
3139 {
3140 	int rc;
3141 
3142 	rc = ata_pci_sff_prepare_host(pdev, ppi, r_host);
3143 	if (rc)
3144 		return rc;
3145 
3146 	ata_pci_bmdma_init(*r_host);
3147 	return 0;
3148 }
3149 EXPORT_SYMBOL_GPL(ata_pci_bmdma_prepare_host);
3150 
3151 /**
3152  *	ata_pci_bmdma_init_one - Initialize/register BMDMA PCI IDE controller
3153  *	@pdev: Controller to be initialized
3154  *	@ppi: array of port_info, must be enough for two ports
3155  *	@sht: scsi_host_template to use when registering the host
3156  *	@host_priv: host private_data
3157  *	@hflags: host flags
3158  *
3159  *	This function is similar to ata_pci_sff_init_one() but also
3160  *	takes care of BMDMA initialization.
3161  *
3162  *	LOCKING:
3163  *	Inherited from PCI layer (may sleep).
3164  *
3165  *	RETURNS:
3166  *	Zero on success, negative on errno-based value on error.
3167  */
ata_pci_bmdma_init_one(struct pci_dev * pdev,const struct ata_port_info * const * ppi,const struct scsi_host_template * sht,void * host_priv,int hflags)3168 int ata_pci_bmdma_init_one(struct pci_dev *pdev,
3169 			   const struct ata_port_info * const * ppi,
3170 			   const struct scsi_host_template *sht, void *host_priv,
3171 			   int hflags)
3172 {
3173 	return ata_pci_init_one(pdev, ppi, sht, host_priv, hflags, 1);
3174 }
3175 EXPORT_SYMBOL_GPL(ata_pci_bmdma_init_one);
3176 
3177 #endif /* CONFIG_PCI */
3178 #endif /* CONFIG_ATA_BMDMA */
3179 
3180 /**
3181  *	ata_sff_port_init - Initialize SFF/BMDMA ATA port
3182  *	@ap: Port to initialize
3183  *
3184  *	Called on port allocation to initialize SFF/BMDMA specific
3185  *	fields.
3186  *
3187  *	LOCKING:
3188  *	None.
3189  */
ata_sff_port_init(struct ata_port * ap)3190 void ata_sff_port_init(struct ata_port *ap)
3191 {
3192 	INIT_DELAYED_WORK(&ap->sff_pio_task, ata_sff_pio_task);
3193 	ap->ctl = ATA_DEVCTL_OBS;
3194 	ap->last_ctl = 0xFF;
3195 }
3196 
ata_sff_init(void)3197 int __init ata_sff_init(void)
3198 {
3199 	ata_sff_wq = alloc_workqueue("ata_sff", WQ_MEM_RECLAIM, WQ_MAX_ACTIVE);
3200 	if (!ata_sff_wq)
3201 		return -ENOMEM;
3202 
3203 	return 0;
3204 }
3205 
ata_sff_exit(void)3206 void ata_sff_exit(void)
3207 {
3208 	destroy_workqueue(ata_sff_wq);
3209 }
3210