1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2012 Atmel Corporation
4  */
5 
6 #include <common.h>
7 #include <asm/io.h>
8 #include <asm/arch/at91sam9x5_matrix.h>
9 #include <asm/arch/at91sam9_smc.h>
10 #include <asm/arch/at91_common.h>
11 #include <asm/arch/at91_rstc.h>
12 #include <asm/arch/clk.h>
13 #include <asm/arch/gpio.h>
14 #include <debug_uart.h>
15 #include <asm/mach-types.h>
16 
17 DECLARE_GLOBAL_DATA_PTR;
18 
19 /* ------------------------------------------------------------------------- */
20 /*
21  * Miscelaneous platform dependent initialisations
22  */
23 
24 void at91_prepare_cpu_var(void);
25 
26 #ifdef CONFIG_CMD_NAND
at91sam9x5ek_nand_hw_init(void)27 static void at91sam9x5ek_nand_hw_init(void)
28 {
29 	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
30 	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
31 	unsigned long csa;
32 
33 	/* Enable CS3 */
34 	csa = readl(&matrix->ebicsa);
35 	csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
36 	/* NAND flash on D16 */
37 	csa |= AT91_MATRIX_NFD0_ON_D16;
38 
39 	/* Configure IO drive */
40 	csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
41 
42 	writel(csa, &matrix->ebicsa);
43 
44 	/* Configure SMC CS3 for NAND/SmartMedia */
45 	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
46 		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
47 		&smc->cs[3].setup);
48 	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
49 		AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
50 		&smc->cs[3].pulse);
51 	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
52 		&smc->cs[3].cycle);
53 	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
54 		AT91_SMC_MODE_EXNW_DISABLE |
55 #ifdef CONFIG_SYS_NAND_DBW_16
56 		AT91_SMC_MODE_DBW_16 |
57 #else /* CONFIG_SYS_NAND_DBW_8 */
58 		AT91_SMC_MODE_DBW_8 |
59 #endif
60 		AT91_SMC_MODE_TDF_CYCLE(1),
61 		&smc->cs[3].mode);
62 
63 	at91_periph_clk_enable(ATMEL_ID_PIOCD);
64 
65 	/* Configure RDY/BSY */
66 	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
67 	/* Enable NandFlash */
68 	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
69 
70 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1);	/* NAND OE */
71 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1);	/* NAND WE */
72 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1);	/* NAND ALE */
73 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1);	/* NAND CLE */
74 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
75 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
76 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
77 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
78 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
79 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
80 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
81 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
82 }
83 #endif
84 
85 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)86 int board_late_init(void)
87 {
88 #ifdef CONFIG_DM_VIDEO
89 	at91_video_show_board_info();
90 #endif
91 	at91_prepare_cpu_var();
92 	return 0;
93 }
94 #endif
95 
96 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
board_debug_uart_init(void)97 void board_debug_uart_init(void)
98 {
99 	at91_seriald_hw_init();
100 }
101 #endif
102 
103 #ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f(void)104 int board_early_init_f(void)
105 {
106 #ifdef CONFIG_DEBUG_UART
107 	debug_uart_init();
108 #endif
109 	return 0;
110 }
111 #endif
112 
board_init(void)113 int board_init(void)
114 {
115 	/* arch number of AT91SAM9X5EK-Board */
116 	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK;
117 
118 	/* adress of boot parameters */
119 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
120 
121 #ifdef CONFIG_CMD_NAND
122 	at91sam9x5ek_nand_hw_init();
123 #endif
124 
125 #if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI_HCD)
126 	at91_uhp_hw_init();
127 #endif
128 	return 0;
129 }
130 
dram_init(void)131 int dram_init(void)
132 {
133 	gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
134 					CONFIG_SYS_SDRAM_SIZE);
135 	return 0;
136 }
137 
138 #if defined(CONFIG_SPL_BUILD)
139 #include <spl.h>
140 #include <nand.h>
141 
at91_spl_board_init(void)142 void at91_spl_board_init(void)
143 {
144 #ifdef CONFIG_SD_BOOT
145 	at91_mci_hw_init();
146 #elif CONFIG_NAND_BOOT
147 	at91sam9x5ek_nand_hw_init();
148 #endif
149 }
150 
151 #include <asm/arch/atmel_mpddrc.h>
ddr2_conf(struct atmel_mpddrc_config * ddr2)152 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
153 {
154 	ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
155 
156 	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
157 		    ATMEL_MPDDRC_CR_NR_ROW_13 |
158 		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
159 		    ATMEL_MPDDRC_CR_NB_8BANKS |
160 		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
161 
162 	ddr2->rtr = 0x411;
163 
164 	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
165 		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
166 		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
167 		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
168 		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
169 		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
170 		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
171 		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
172 
173 	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
174 		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
175 		      19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
176 		      18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
177 
178 	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
179 		      2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
180 		      3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
181 		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
182 		      2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
183 }
184 
mem_init(void)185 void mem_init(void)
186 {
187 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
188 	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
189 	struct atmel_mpddrc_config ddr2;
190 	unsigned long csa;
191 
192 	ddr2_conf(&ddr2);
193 
194 	/* enable DDR2 clock */
195 	writel(AT91_PMC_DDR, &pmc->scer);
196 
197 	/* Chip select 1 is for DDR2/SDRAM */
198 	csa = readl(&matrix->ebicsa);
199 	csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
200 	csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
201 	csa |= AT91_MATRIX_EBI_DBPD_OFF;
202 	csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
203 	writel(csa, &matrix->ebicsa);
204 
205 	/* DDRAM2 Controller initialize */
206 	ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
207 }
208 #endif
209