1 /*
2 * ASPEED Ast27x0 TSP SoC
3 *
4 * Copyright (C) 2025 ASPEED Technology Inc.
5 *
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
8 *
9 * SPDX-License-Identifier: GPL-2.0-or-later
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "hw/qdev-clock.h"
15 #include "hw/misc/unimp.h"
16 #include "hw/arm/aspeed_soc.h"
17
18 #define AST2700_TSP_SDRAM_SIZE (512 * MiB)
19
20 static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
21 [ASPEED_DEV_SDRAM] = 0x00000000,
22 [ASPEED_DEV_SRAM] = 0x70000000,
23 [ASPEED_DEV_INTC] = 0x72100000,
24 [ASPEED_DEV_SCU] = 0x72C02000,
25 [ASPEED_DEV_SCUIO] = 0x74C02000,
26 [ASPEED_DEV_UART0] = 0x74C33000,
27 [ASPEED_DEV_UART1] = 0x74C33100,
28 [ASPEED_DEV_UART2] = 0x74C33200,
29 [ASPEED_DEV_UART3] = 0x74C33300,
30 [ASPEED_DEV_UART4] = 0x72C1A000,
31 [ASPEED_DEV_INTCIO] = 0x74C18000,
32 [ASPEED_DEV_IPC0] = 0x72C1C000,
33 [ASPEED_DEV_IPC1] = 0x74C39000,
34 [ASPEED_DEV_UART5] = 0x74C33400,
35 [ASPEED_DEV_UART6] = 0x74C33500,
36 [ASPEED_DEV_UART7] = 0x74C33600,
37 [ASPEED_DEV_UART8] = 0x74C33700,
38 [ASPEED_DEV_UART9] = 0x74C33800,
39 [ASPEED_DEV_UART10] = 0x74C33900,
40 [ASPEED_DEV_UART11] = 0x74C33A00,
41 [ASPEED_DEV_UART12] = 0x74C33B00,
42 [ASPEED_DEV_TIMER1] = 0x72C10000,
43 };
44
45 static const int aspeed_soc_ast27x0tsp_irqmap[] = {
46 [ASPEED_DEV_SCU] = 12,
47 [ASPEED_DEV_UART0] = 164,
48 [ASPEED_DEV_UART1] = 164,
49 [ASPEED_DEV_UART2] = 164,
50 [ASPEED_DEV_UART3] = 164,
51 [ASPEED_DEV_UART4] = 8,
52 [ASPEED_DEV_UART5] = 164,
53 [ASPEED_DEV_UART6] = 164,
54 [ASPEED_DEV_UART7] = 164,
55 [ASPEED_DEV_UART8] = 164,
56 [ASPEED_DEV_UART9] = 164,
57 [ASPEED_DEV_UART10] = 164,
58 [ASPEED_DEV_UART11] = 164,
59 [ASPEED_DEV_UART12] = 164,
60 [ASPEED_DEV_TIMER1] = 16,
61 };
62
63 /* TSPINT 164 */
64 static const int ast2700_tsp132_tsp164_intcmap[] = {
65 [ASPEED_DEV_UART0] = 7,
66 [ASPEED_DEV_UART1] = 8,
67 [ASPEED_DEV_UART2] = 9,
68 [ASPEED_DEV_UART3] = 10,
69 [ASPEED_DEV_UART5] = 11,
70 [ASPEED_DEV_UART6] = 12,
71 [ASPEED_DEV_UART7] = 13,
72 [ASPEED_DEV_UART8] = 14,
73 [ASPEED_DEV_UART9] = 15,
74 [ASPEED_DEV_UART10] = 16,
75 [ASPEED_DEV_UART11] = 17,
76 [ASPEED_DEV_UART12] = 18,
77 };
78
79 struct nvic_intc_irq_info {
80 int irq;
81 int intc_idx;
82 int orgate_idx;
83 const int *ptr;
84 };
85
86 static struct nvic_intc_irq_info ast2700_tsp_intcmap[] = {
87 {160, 1, 0, NULL},
88 {161, 1, 1, NULL},
89 {162, 1, 2, NULL},
90 {163, 1, 3, NULL},
91 {164, 1, 4, ast2700_tsp132_tsp164_intcmap},
92 {165, 1, 5, NULL},
93 {166, 1, 6, NULL},
94 {167, 1, 7, NULL},
95 {168, 1, 8, NULL},
96 {169, 1, 9, NULL},
97 {128, 0, 1, NULL},
98 {129, 0, 2, NULL},
99 {130, 0, 3, NULL},
100 {131, 0, 4, NULL},
101 {132, 0, 5, ast2700_tsp132_tsp164_intcmap},
102 {133, 0, 6, NULL},
103 {134, 0, 7, NULL},
104 {135, 0, 8, NULL},
105 {136, 0, 9, NULL},
106 };
107
aspeed_soc_ast27x0tsp_get_irq(AspeedSoCState * s,int dev)108 static qemu_irq aspeed_soc_ast27x0tsp_get_irq(AspeedSoCState *s, int dev)
109 {
110 Aspeed27x0TSPSoCState *a = ASPEED27X0TSP_SOC(s);
111 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
112
113 int or_idx;
114 int idx;
115 int i;
116
117 for (i = 0; i < ARRAY_SIZE(ast2700_tsp_intcmap); i++) {
118 if (sc->irqmap[dev] == ast2700_tsp_intcmap[i].irq) {
119 assert(ast2700_tsp_intcmap[i].ptr);
120 or_idx = ast2700_tsp_intcmap[i].orgate_idx;
121 idx = ast2700_tsp_intcmap[i].intc_idx;
122 return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]),
123 ast2700_tsp_intcmap[i].ptr[dev]);
124 }
125 }
126
127 return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
128 }
129
aspeed_soc_ast27x0tsp_init(Object * obj)130 static void aspeed_soc_ast27x0tsp_init(Object *obj)
131 {
132 Aspeed27x0TSPSoCState *a = ASPEED27X0TSP_SOC(obj);
133 AspeedSoCState *s = ASPEED_SOC(obj);
134 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
135 int i;
136
137 object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
138 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
139
140 for (i = 0; i < sc->uarts_num; i++) {
141 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
142 }
143
144 object_initialize_child(obj, "intc0", &a->intc[0],
145 TYPE_ASPEED_2700TSP_INTC);
146 object_initialize_child(obj, "intc1", &a->intc[1],
147 TYPE_ASPEED_2700TSP_INTCIO);
148
149 object_initialize_child(obj, "timerctrl", &s->timerctrl,
150 TYPE_UNIMPLEMENTED_DEVICE);
151 object_initialize_child(obj, "ipc0", &a->ipc[0],
152 TYPE_UNIMPLEMENTED_DEVICE);
153 object_initialize_child(obj, "ipc1", &a->ipc[1],
154 TYPE_UNIMPLEMENTED_DEVICE);
155 object_initialize_child(obj, "scuio", &a->scuio,
156 TYPE_UNIMPLEMENTED_DEVICE);
157 }
158
aspeed_soc_ast27x0tsp_realize(DeviceState * dev_soc,Error ** errp)159 static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
160 {
161 Aspeed27x0TSPSoCState *a = ASPEED27X0TSP_SOC(dev_soc);
162 AspeedSoCState *s = ASPEED_SOC(dev_soc);
163 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
164 DeviceState *armv7m;
165 g_autofree char *name = NULL;
166 int i;
167
168 if (!clock_has_source(s->sysclk)) {
169 error_setg(errp, "sysclk clock must be wired up by the board code");
170 return;
171 }
172
173 /* AST27X0 TSP Core */
174 armv7m = DEVICE(&a->armv7m);
175 qdev_prop_set_uint32(armv7m, "num-irq", 256);
176 qdev_prop_set_string(armv7m, "cpu-type", aspeed_soc_cpu_type(sc));
177 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
178 object_property_set_link(OBJECT(&a->armv7m), "memory",
179 OBJECT(s->memory), &error_abort);
180 /*
181 * The TSP starts in a powered-down state and can be powered up
182 * by setting the TSP Control Register through the SCU
183 * (System Control Unit)
184 */
185 object_property_set_bool(OBJECT(&a->armv7m), "start-powered-off", true,
186 &error_abort);
187 sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
188
189 /* SDRAM */
190 name = g_strdup_printf("aspeed.sdram-container.%d",
191 CPU(a->armv7m.cpu)->cpu_index);
192
193 if (!memory_region_init_ram(&s->dram_container, OBJECT(s), name,
194 AST2700_TSP_SDRAM_SIZE, errp)) {
195 return;
196 }
197 /* SDRAM remap alias used by PSP to access TSP SDRAM */
198 memory_region_add_subregion(&s->dram_container, 0, &a->sdram_remap_alias);
199 memory_region_add_subregion(s->memory,
200 sc->memmap[ASPEED_DEV_SDRAM],
201 &s->dram_container);
202
203 /* SRAM */
204 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM],
205 &a->sram_mr_alias);
206
207 /* SCU */
208 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU],
209 &a->scu_mr_alias);
210
211 /* INTC */
212 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
213 return;
214 }
215
216 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0,
217 sc->memmap[ASPEED_DEV_INTC]);
218
219 /* INTCIO */
220 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) {
221 return;
222 }
223
224 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0,
225 sc->memmap[ASPEED_DEV_INTCIO]);
226
227 /* irq source orgates -> INTC */
228 for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_inpins; i++) {
229 qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0,
230 qdev_get_gpio_in(DEVICE(&a->intc[0]), i));
231 }
232 for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_outpins; i++) {
233 assert(i < ARRAY_SIZE(ast2700_tsp_intcmap));
234 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i,
235 qdev_get_gpio_in(DEVICE(&a->armv7m),
236 ast2700_tsp_intcmap[i].irq));
237 }
238 /* irq source orgates -> INTC */
239 for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_inpins; i++) {
240 qdev_connect_gpio_out(DEVICE(&a->intc[1].orgates[i]), 0,
241 qdev_get_gpio_in(DEVICE(&a->intc[1]), i));
242 }
243 /* INTCIO -> INTC */
244 for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_outpins; i++) {
245 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i,
246 qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
247 }
248 /* UART */
249 if (!aspeed_soc_uart_realize(s, errp)) {
250 return;
251 }
252
253 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->timerctrl),
254 "aspeed.timerctrl",
255 sc->memmap[ASPEED_DEV_TIMER1], 0x200);
256 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->ipc[0]),
257 "aspeed.ipc0",
258 sc->memmap[ASPEED_DEV_IPC0], 0x1000);
259 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->ipc[1]),
260 "aspeed.ipc1",
261 sc->memmap[ASPEED_DEV_IPC1], 0x1000);
262 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->scuio),
263 "aspeed.scuio",
264 sc->memmap[ASPEED_DEV_SCUIO], 0x1000);
265 }
266
aspeed_soc_ast27x0tsp_class_init(ObjectClass * klass,const void * data)267 static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass, const void *data)
268 {
269 static const char * const valid_cpu_types[] = {
270 ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */
271 NULL
272 };
273 DeviceClass *dc = DEVICE_CLASS(klass);
274 AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
275
276 /* Reason: The Aspeed SoC can only be instantiated from a board */
277 dc->user_creatable = false;
278 dc->realize = aspeed_soc_ast27x0tsp_realize;
279
280 sc->valid_cpu_types = valid_cpu_types;
281 sc->spis_num = 0;
282 sc->ehcis_num = 0;
283 sc->wdts_num = 0;
284 sc->macs_num = 0;
285 sc->uarts_num = 13;
286 sc->uarts_base = ASPEED_DEV_UART0;
287 sc->irqmap = aspeed_soc_ast27x0tsp_irqmap;
288 sc->memmap = aspeed_soc_ast27x0tsp_memmap;
289 sc->num_cpus = 1;
290 sc->get_irq = aspeed_soc_ast27x0tsp_get_irq;
291 }
292
293 static const TypeInfo aspeed_soc_ast27x0tsp_types[] = {
294 {
295 .name = TYPE_ASPEED27X0TSP_SOC,
296 .parent = TYPE_ASPEED_SOC,
297 .instance_size = sizeof(Aspeed27x0TSPSoCState),
298 .instance_init = aspeed_soc_ast27x0tsp_init,
299 .class_init = aspeed_soc_ast27x0tsp_class_init,
300 },
301 };
302
303 DEFINE_TYPES(aspeed_soc_ast27x0tsp_types)
304