1 /*
2 * OpenPOWER Palmetto BMC
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "hw/arm/boot.h"
15 #include "hw/arm/aspeed.h"
16 #include "hw/arm/aspeed_soc.h"
17 #include "hw/arm/aspeed_eeprom.h"
18 #include "hw/block/flash.h"
19 #include "hw/i2c/i2c_mux_pca954x.h"
20 #include "hw/i2c/smbus_eeprom.h"
21 #include "hw/gpio/pca9552.h"
22 #include "hw/nvram/eeprom_at24c.h"
23 #include "hw/sensor/tmp105.h"
24 #include "hw/misc/led.h"
25 #include "hw/qdev-properties.h"
26 #include "sysemu/block-backend.h"
27 #include "sysemu/reset.h"
28 #include "hw/loader.h"
29 #include "qemu/error-report.h"
30 #include "qemu/units.h"
31 #include "hw/qdev-clock.h"
32 #include "sysemu/sysemu.h"
33
34 static struct arm_boot_info aspeed_board_binfo = {
35 .board_id = -1, /* device-tree-only board */
36 };
37
38 struct AspeedMachineState {
39 /* Private */
40 MachineState parent_obj;
41 /* Public */
42
43 AspeedSoCState *soc;
44 MemoryRegion boot_rom;
45 bool mmio_exec;
46 uint32_t uart_chosen;
47 char *fmc_model;
48 char *spi_model;
49 uint32_t hw_strap1;
50 };
51
52 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
53 #if HOST_LONG_BITS == 32
54 #define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB)
55 #else
56 #define ASPEED_RAM_SIZE(sz) (sz)
57 #endif
58
59 /* Palmetto hardware value: 0x120CE416 */
60 #define PALMETTO_BMC_HW_STRAP1 ( \
61 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
62 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
63 SCU_AST2400_HW_STRAP_ACPI_DIS | \
64 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
65 SCU_HW_STRAP_VGA_CLASS_CODE | \
66 SCU_HW_STRAP_LPC_RESET_PIN | \
67 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
68 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
69 SCU_HW_STRAP_SPI_WIDTH | \
70 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
71 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
72
73 /* TODO: Find the actual hardware value */
74 #define SUPERMICROX11_BMC_HW_STRAP1 ( \
75 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
76 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \
77 SCU_AST2400_HW_STRAP_ACPI_DIS | \
78 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
79 SCU_HW_STRAP_VGA_CLASS_CODE | \
80 SCU_HW_STRAP_LPC_RESET_PIN | \
81 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
82 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
83 SCU_HW_STRAP_SPI_WIDTH | \
84 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
85 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
86
87 /* TODO: Find the actual hardware value */
88 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \
89 AST2500_HW_STRAP1_DEFAULTS | \
90 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
91 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
92 SCU_AST2500_HW_STRAP_UART_DEBUG | \
93 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
94 SCU_HW_STRAP_SPI_WIDTH | \
95 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN))
96
97 /* AST2500 evb hardware value: 0xF100C2E6 */
98 #define AST2500_EVB_HW_STRAP1 (( \
99 AST2500_HW_STRAP1_DEFAULTS | \
100 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
101 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
102 SCU_AST2500_HW_STRAP_UART_DEBUG | \
103 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
104 SCU_HW_STRAP_MAC1_RGMII | \
105 SCU_HW_STRAP_MAC0_RGMII) & \
106 ~SCU_HW_STRAP_2ND_BOOT_WDT)
107
108 /* Romulus hardware value: 0xF10AD206 */
109 #define ROMULUS_BMC_HW_STRAP1 ( \
110 AST2500_HW_STRAP1_DEFAULTS | \
111 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
112 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
113 SCU_AST2500_HW_STRAP_UART_DEBUG | \
114 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
115 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
116 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
117
118 /* Sonorapass hardware value: 0xF100D216 */
119 #define SONORAPASS_BMC_HW_STRAP1 ( \
120 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
121 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
122 SCU_AST2500_HW_STRAP_UART_DEBUG | \
123 SCU_AST2500_HW_STRAP_RESERVED28 | \
124 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
125 SCU_HW_STRAP_VGA_CLASS_CODE | \
126 SCU_HW_STRAP_LPC_RESET_PIN | \
127 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
128 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
129 SCU_HW_STRAP_VGA_BIOS_ROM | \
130 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
131 SCU_AST2500_HW_STRAP_RESERVED1)
132
133 #define G220A_BMC_HW_STRAP1 ( \
134 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
135 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
136 SCU_AST2500_HW_STRAP_UART_DEBUG | \
137 SCU_AST2500_HW_STRAP_RESERVED28 | \
138 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
139 SCU_HW_STRAP_2ND_BOOT_WDT | \
140 SCU_HW_STRAP_VGA_CLASS_CODE | \
141 SCU_HW_STRAP_LPC_RESET_PIN | \
142 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
143 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
144 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \
145 SCU_AST2500_HW_STRAP_RESERVED1)
146
147 /* FP5280G2 hardware value: 0XF100D286 */
148 #define FP5280G2_BMC_HW_STRAP1 ( \
149 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
150 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
151 SCU_AST2500_HW_STRAP_UART_DEBUG | \
152 SCU_AST2500_HW_STRAP_RESERVED28 | \
153 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
154 SCU_HW_STRAP_VGA_CLASS_CODE | \
155 SCU_HW_STRAP_LPC_RESET_PIN | \
156 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
157 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
158 SCU_HW_STRAP_MAC1_RGMII | \
159 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
160 SCU_AST2500_HW_STRAP_RESERVED1)
161
162 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
163 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
164
165 /* Quanta-Q71l hardware value */
166 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \
167 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
168 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
169 SCU_AST2400_HW_STRAP_ACPI_DIS | \
170 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \
171 SCU_HW_STRAP_VGA_CLASS_CODE | \
172 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \
173 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
174 SCU_HW_STRAP_SPI_WIDTH | \
175 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \
176 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
177
178 /* AST2600 evb hardware value */
179 #define AST2600_EVB_HW_STRAP1 0x000000C0
180 #define AST2600_EVB_HW_STRAP2 0x00000003
181
182 #ifdef TARGET_AARCH64
183 /* AST2700 evb hardware value */
184 #define AST2700_EVB_HW_STRAP1 0x000000C0
185 #define AST2700_EVB_HW_STRAP2 0x00000003
186 #endif
187
188 /* Rainier hardware value: (QEMU prototype) */
189 #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC)
190 #define RAINIER_BMC_HW_STRAP2 0x80000848
191
192 /* Fuji hardware value */
193 #define FUJI_BMC_HW_STRAP1 0x00000000
194 #define FUJI_BMC_HW_STRAP2 0x00000000
195
196 /* Bletchley hardware value */
197 /* TODO: Leave same as EVB for now. */
198 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
199 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
200
201 /* Qualcomm DC-SCM hardware value */
202 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000
203 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041
204
205 #define AST_SMP_MAILBOX_BASE 0x1e6e2180
206 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
207 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
208 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
209 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
210 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
211 #define AST_SMP_MBOX_GOSIGN 0xabbaab00
212
aspeed_write_smpboot(ARMCPU * cpu,const struct arm_boot_info * info)213 static void aspeed_write_smpboot(ARMCPU *cpu,
214 const struct arm_boot_info *info)
215 {
216 AddressSpace *as = arm_boot_address_space(cpu, info);
217 static const ARMInsnFixup poll_mailbox_ready[] = {
218 /*
219 * r2 = per-cpu go sign value
220 * r1 = AST_SMP_MBOX_FIELD_ENTRY
221 * r0 = AST_SMP_MBOX_FIELD_GOSIGN
222 */
223 { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */
224 { 0xe21000ff }, /* ands r0, r0, #255 */
225 { 0xe59f201c }, /* ldr r2, [pc, #28] */
226 { 0xe1822000 }, /* orr r2, r2, r0 */
227
228 { 0xe59f1018 }, /* ldr r1, [pc, #24] */
229 { 0xe59f0018 }, /* ldr r0, [pc, #24] */
230
231 { 0xe320f002 }, /* wfe */
232 { 0xe5904000 }, /* ldr r4, [r0] */
233 { 0xe1520004 }, /* cmp r2, r4 */
234 { 0x1afffffb }, /* bne <wfe> */
235 { 0xe591f000 }, /* ldr pc, [r1] */
236 { AST_SMP_MBOX_GOSIGN },
237 { AST_SMP_MBOX_FIELD_ENTRY },
238 { AST_SMP_MBOX_FIELD_GOSIGN },
239 { 0, FIXUP_TERMINATOR }
240 };
241 static const uint32_t fixupcontext[FIXUP_MAX] = { 0 };
242
243 arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start,
244 poll_mailbox_ready, fixupcontext);
245 }
246
aspeed_reset_secondary(ARMCPU * cpu,const struct arm_boot_info * info)247 static void aspeed_reset_secondary(ARMCPU *cpu,
248 const struct arm_boot_info *info)
249 {
250 AddressSpace *as = arm_boot_address_space(cpu, info);
251 CPUState *cs = CPU(cpu);
252
253 /* info->smp_bootreg_addr */
254 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
255 MEMTXATTRS_UNSPECIFIED, NULL);
256 cpu_set_pc(cs, info->smp_loader_start);
257 }
258
write_boot_rom(BlockBackend * blk,hwaddr addr,size_t rom_size,Error ** errp)259 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
260 Error **errp)
261 {
262 g_autofree void *storage = NULL;
263 int64_t size;
264
265 /*
266 * The block backend size should have already been 'validated' by
267 * the creation of the m25p80 object.
268 */
269 size = blk_getlength(blk);
270 if (size <= 0) {
271 error_setg(errp, "failed to get flash size");
272 return;
273 }
274
275 if (rom_size > size) {
276 rom_size = size;
277 }
278
279 storage = g_malloc0(rom_size);
280 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) {
281 error_setg(errp, "failed to read the initial flash content");
282 return;
283 }
284
285 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
286 }
287
288 /*
289 * Create a ROM and copy the flash contents at the expected address
290 * (0x0). Boots faster than execute-in-place.
291 */
aspeed_install_boot_rom(AspeedMachineState * bmc,BlockBackend * blk,uint64_t rom_size)292 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
293 uint64_t rom_size)
294 {
295 AspeedSoCState *soc = bmc->soc;
296 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(soc);
297
298 memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size,
299 &error_abort);
300 memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
301 &bmc->boot_rom, 1);
302 write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT],
303 rom_size, &error_abort);
304 }
305
aspeed_board_init_flashes(AspeedSMCState * s,const char * flashtype,unsigned int count,int unit0)306 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
307 unsigned int count, int unit0)
308 {
309 int i;
310
311 if (!flashtype) {
312 return;
313 }
314
315 for (i = 0; i < count; ++i) {
316 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i);
317 DeviceState *dev;
318
319 dev = qdev_new(flashtype);
320 if (dinfo) {
321 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
322 }
323 qdev_prop_set_uint8(dev, "cs", i);
324 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal);
325 }
326 }
327
sdhci_attach_drive(SDHCIState * sdhci,DriveInfo * dinfo,bool emmc,bool boot_emmc)328 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo, bool emmc,
329 bool boot_emmc)
330 {
331 DeviceState *card;
332
333 if (!dinfo) {
334 return;
335 }
336 card = qdev_new(emmc ? TYPE_EMMC : TYPE_SD_CARD);
337
338 /*
339 * Force the boot properties of the eMMC device only when the
340 * machine is strapped to boot from eMMC. Without these
341 * settings, the machine would not boot.
342 *
343 * This also allows the machine to use an eMMC device without
344 * boot areas when booting from the flash device (or -kernel)
345 * Ideally, the device and its properties should be defined on
346 * the command line.
347 */
348 if (emmc && boot_emmc) {
349 qdev_prop_set_uint64(card, "boot-partition-size", 1 * MiB);
350 qdev_prop_set_uint8(card, "boot-config", 0x1 << 3);
351 }
352 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
353 &error_fatal);
354 qdev_realize_and_unref(card, BUS(&sdhci->sdbus), &error_fatal);
355 }
356
connect_serial_hds_to_uarts(AspeedMachineState * bmc)357 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
358 {
359 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
360 AspeedSoCState *s = bmc->soc;
361 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
362 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
363
364 aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0));
365 for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
366 if (uart == uart_chosen) {
367 continue;
368 }
369 aspeed_soc_uart_set_chr(s, uart, serial_hd(i));
370 }
371 }
372
aspeed_machine_init(MachineState * machine)373 static void aspeed_machine_init(MachineState *machine)
374 {
375 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
376 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
377 AspeedSoCClass *sc;
378 int i;
379 DriveInfo *emmc0 = NULL;
380 bool boot_emmc;
381
382 bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
383 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
384 object_unref(OBJECT(bmc->soc));
385 sc = ASPEED_SOC_GET_CLASS(bmc->soc);
386
387 /*
388 * This will error out if the RAM size is not supported by the
389 * memory controller of the SoC.
390 */
391 object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size,
392 &error_fatal);
393
394 for (i = 0; i < sc->macs_num; i++) {
395 if ((amc->macs_mask & (1 << i)) &&
396 !qemu_configure_nic_device(DEVICE(&bmc->soc->ftgmac100[i]),
397 true, NULL)) {
398 break; /* No configs left; stop asking */
399 }
400 }
401
402 object_property_set_int(OBJECT(bmc->soc), "hw-strap1", bmc->hw_strap1,
403 &error_abort);
404 object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2,
405 &error_abort);
406 object_property_set_link(OBJECT(bmc->soc), "memory",
407 OBJECT(get_system_memory()), &error_abort);
408 object_property_set_link(OBJECT(bmc->soc), "dram",
409 OBJECT(machine->ram), &error_abort);
410 if (amc->sdhci_wp_inverted) {
411 for (i = 0; i < bmc->soc->sdhci.num_slots; i++) {
412 object_property_set_bool(OBJECT(&bmc->soc->sdhci.slots[i]),
413 "wp-inverted", true, &error_abort);
414 }
415 }
416 if (machine->kernel_filename) {
417 /*
418 * When booting with a -kernel command line there is no u-boot
419 * that runs to unlock the SCU. In this case set the default to
420 * be unlocked as the kernel expects
421 */
422 object_property_set_int(OBJECT(bmc->soc), "hw-prot-key",
423 ASPEED_SCU_PROT_KEY, &error_abort);
424 }
425 connect_serial_hds_to_uarts(bmc);
426 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
427
428 if (defaults_enabled()) {
429 aspeed_board_init_flashes(&bmc->soc->fmc,
430 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
431 amc->num_cs, 0);
432 aspeed_board_init_flashes(&bmc->soc->spi[0],
433 bmc->spi_model ? bmc->spi_model : amc->spi_model,
434 1, amc->num_cs);
435 }
436
437 if (machine->kernel_filename && sc->num_cpus > 1) {
438 /* With no u-boot we must set up a boot stub for the secondary CPU */
439 MemoryRegion *smpboot = g_new(MemoryRegion, 1);
440 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
441 0x80, &error_abort);
442 memory_region_add_subregion(get_system_memory(),
443 AST_SMP_MAILBOX_BASE, smpboot);
444
445 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
446 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
447 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
448 }
449
450 aspeed_board_binfo.ram_size = machine->ram_size;
451 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
452
453 if (amc->i2c_init) {
454 amc->i2c_init(bmc);
455 }
456
457 for (i = 0; i < bmc->soc->sdhci.num_slots && defaults_enabled(); i++) {
458 sdhci_attach_drive(&bmc->soc->sdhci.slots[i],
459 drive_get(IF_SD, 0, i), false, false);
460 }
461
462 boot_emmc = sc->boot_from_emmc(bmc->soc);
463
464 if (bmc->soc->emmc.num_slots && defaults_enabled()) {
465 emmc0 = drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots);
466 sdhci_attach_drive(&bmc->soc->emmc.slots[0], emmc0, true, boot_emmc);
467 }
468
469 if (!bmc->mmio_exec) {
470 DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0);
471 BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL;
472
473 if (fmc0 && !boot_emmc) {
474 uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot);
475 aspeed_install_boot_rom(bmc, fmc0, rom_size);
476 } else if (emmc0) {
477 aspeed_install_boot_rom(bmc, blk_by_legacy_dinfo(emmc0), 64 * KiB);
478 }
479 }
480
481 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
482 }
483
palmetto_bmc_i2c_init(AspeedMachineState * bmc)484 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
485 {
486 AspeedSoCState *soc = bmc->soc;
487 DeviceState *dev;
488 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
489
490 /*
491 * The palmetto platform expects a ds3231 RTC but a ds1338 is
492 * enough to provide basic RTC features. Alarms will be missing
493 */
494 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
495
496 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
497 eeprom_buf);
498
499 /* add a TMP423 temperature sensor */
500 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
501 "tmp423", 0x4c));
502 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
503 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
504 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
505 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
506 }
507
quanta_q71l_bmc_i2c_init(AspeedMachineState * bmc)508 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
509 {
510 AspeedSoCState *soc = bmc->soc;
511
512 /*
513 * The quanta-q71l platform expects tmp75s which are compatible with
514 * tmp105s.
515 */
516 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
517 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
518 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
519
520 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
521 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
522 /* TODO: Add Memory Riser i2c mux and eeproms. */
523
524 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
525 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
526
527 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
528
529 /* i2c-7 */
530 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
531 /* - i2c@0: pmbus@59 */
532 /* - i2c@1: pmbus@58 */
533 /* - i2c@2: pmbus@58 */
534 /* - i2c@3: pmbus@59 */
535
536 /* TODO: i2c-7: Add PDB FRU eeprom@52 */
537 /* TODO: i2c-8: Add BMC FRU eeprom@50 */
538 }
539
ast2500_evb_i2c_init(AspeedMachineState * bmc)540 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
541 {
542 AspeedSoCState *soc = bmc->soc;
543 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
544
545 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
546 eeprom_buf);
547
548 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
549 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
550 TYPE_TMP105, 0x4d);
551 }
552
ast2600_evb_i2c_init(AspeedMachineState * bmc)553 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
554 {
555 AspeedSoCState *soc = bmc->soc;
556 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
557
558 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
559 eeprom_buf);
560
561 /* LM75 is compatible with TMP105 driver */
562 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
563 TYPE_TMP105, 0x4d);
564 }
565
yosemitev2_bmc_i2c_init(AspeedMachineState * bmc)566 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
567 {
568 AspeedSoCState *soc = bmc->soc;
569
570 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB);
571 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB,
572 yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len);
573 /* TMP421 */
574 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f);
575 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e);
576 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f);
577
578 }
579
romulus_bmc_i2c_init(AspeedMachineState * bmc)580 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
581 {
582 AspeedSoCState *soc = bmc->soc;
583
584 /*
585 * The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
586 * good enough
587 */
588 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
589 }
590
tiogapass_bmc_i2c_init(AspeedMachineState * bmc)591 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
592 {
593 AspeedSoCState *soc = bmc->soc;
594
595 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB);
596 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB,
597 tiogapass_bmc_fruid, tiogapass_bmc_fruid_len);
598 /* TMP421 */
599 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f);
600 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f);
601 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e);
602 }
603
create_pca9552(AspeedSoCState * soc,int bus_id,int addr)604 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
605 {
606 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
607 TYPE_PCA9552, addr);
608 }
609
sonorapass_bmc_i2c_init(AspeedMachineState * bmc)610 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
611 {
612 AspeedSoCState *soc = bmc->soc;
613
614 /* bus 2 : */
615 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
616 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
617 /* bus 2 : pca9546 @ 0x73 */
618
619 /* bus 3 : pca9548 @ 0x70 */
620
621 /* bus 4 : */
622 uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
623 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
624 eeprom4_54);
625 /* PCA9539 @ 0x76, but PCA9552 is compatible */
626 create_pca9552(soc, 4, 0x76);
627 /* PCA9539 @ 0x77, but PCA9552 is compatible */
628 create_pca9552(soc, 4, 0x77);
629
630 /* bus 6 : */
631 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
632 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
633 /* bus 6 : pca9546 @ 0x73 */
634
635 /* bus 8 : */
636 uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
637 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
638 eeprom8_56);
639 create_pca9552(soc, 8, 0x60);
640 create_pca9552(soc, 8, 0x61);
641 /* bus 8 : adc128d818 @ 0x1d */
642 /* bus 8 : adc128d818 @ 0x1f */
643
644 /*
645 * bus 13 : pca9548 @ 0x71
646 * - channel 3:
647 * - tmm421 @ 0x4c
648 * - tmp421 @ 0x4e
649 * - tmp421 @ 0x4f
650 */
651
652 }
653
witherspoon_bmc_i2c_init(AspeedMachineState * bmc)654 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
655 {
656 static const struct {
657 unsigned gpio_id;
658 LEDColor color;
659 const char *description;
660 bool gpio_polarity;
661 } pca1_leds[] = {
662 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW},
663 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW},
664 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW},
665 };
666 AspeedSoCState *soc = bmc->soc;
667 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
668 DeviceState *dev;
669 LEDState *led;
670
671 /* Bus 3: TODO bmp280@77 */
672 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
673 qdev_prop_set_string(dev, "description", "pca1");
674 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
675 aspeed_i2c_get_bus(&soc->i2c, 3),
676 &error_fatal);
677
678 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
679 led = led_create_simple(OBJECT(bmc),
680 pca1_leds[i].gpio_polarity,
681 pca1_leds[i].color,
682 pca1_leds[i].description);
683 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
684 qdev_get_gpio_in(DEVICE(led), 0));
685 }
686
687 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps",
688 0x68);
689 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps",
690 0x69);
691 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76);
692
693 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52);
694 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
695 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ir35221", 0x70);
696 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ir35221", 0x71);
697
698 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
699 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "ir35221", 0x70);
700 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "ir35221", 0x71);
701
702 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
703 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
704 0x4a);
705
706 /*
707 * The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
708 * good enough
709 */
710 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
711
712 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
713 eeprom_buf);
714 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
715 qdev_prop_set_string(dev, "description", "pca0");
716 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
717 aspeed_i2c_get_bus(&soc->i2c, 11),
718 &error_fatal);
719 /* Bus 11: TODO ucd90160@64 */
720 }
721
g220a_bmc_i2c_init(AspeedMachineState * bmc)722 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
723 {
724 AspeedSoCState *soc = bmc->soc;
725 DeviceState *dev;
726
727 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
728 "emc1413", 0x4c));
729 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
730 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
731 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
732
733 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
734 "emc1413", 0x4c));
735 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
736 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
737 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
738
739 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
740 "emc1413", 0x4c));
741 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
742 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
743 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
744
745 static uint8_t eeprom_buf[2 * 1024] = {
746 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
747 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
748 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
749 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
750 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
751 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
752 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
753 };
754 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
755 eeprom_buf);
756 }
757
fp5280g2_bmc_i2c_init(AspeedMachineState * bmc)758 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
759 {
760 AspeedSoCState *soc = bmc->soc;
761 I2CSlave *i2c_mux;
762
763 /* The at24c256 */
764 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768);
765
766 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */
767 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
768 0x48);
769 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
770 0x49);
771
772 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
773 "pca9546", 0x70);
774 /* It expects a TMP112 but a TMP105 is compatible */
775 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105,
776 0x4a);
777
778 /* It expects a ds3232 but a ds1338 is good enough */
779 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
780
781 /* It expects a pca9555 but a pca9552 is compatible */
782 create_pca9552(soc, 8, 0x30);
783 }
784
rainier_bmc_i2c_init(AspeedMachineState * bmc)785 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
786 {
787 AspeedSoCState *soc = bmc->soc;
788 I2CSlave *i2c_mux;
789
790 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
791
792 create_pca9552(soc, 3, 0x61);
793
794 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps",
795 0x68);
796 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps",
797 0x69);
798 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps",
799 0x6a);
800 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps",
801 0x6b);
802
803 /* The rainier expects a TMP275 but a TMP105 is compatible */
804 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
805 0x48);
806 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
807 0x49);
808 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
809 0x4a);
810 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
811 "pca9546", 0x70);
812 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
813 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
814 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
815 create_pca9552(soc, 4, 0x60);
816
817 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
818 0x48);
819 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
820 0x49);
821 create_pca9552(soc, 5, 0x60);
822 create_pca9552(soc, 5, 0x61);
823 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
824 "pca9546", 0x70);
825 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
826 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
827
828 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
829 0x48);
830 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
831 0x4a);
832 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
833 0x4b);
834 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
835 "pca9546", 0x70);
836 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
837 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
838 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
839 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
840
841 create_pca9552(soc, 7, 0x30);
842 create_pca9552(soc, 7, 0x31);
843 create_pca9552(soc, 7, 0x32);
844 create_pca9552(soc, 7, 0x33);
845 create_pca9552(soc, 7, 0x60);
846 create_pca9552(soc, 7, 0x61);
847 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
848 /* Bus 7: TODO si7021-a20@20 */
849 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
850 0x48);
851 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52);
852 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
853 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
854
855 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
856 0x48);
857 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
858 0x4a);
859 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50,
860 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len);
861 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51,
862 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len);
863 create_pca9552(soc, 8, 0x60);
864 create_pca9552(soc, 8, 0x61);
865 /* Bus 8: ucd90320@11 */
866 /* Bus 8: ucd90320@b */
867 /* Bus 8: ucd90320@c */
868
869 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x42);
870 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x43);
871 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x44);
872 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x72);
873 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x73);
874 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x74);
875 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
876 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
877 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
878
879 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x42);
880 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x43);
881 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x44);
882 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x72);
883 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x73);
884 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x74);
885 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
886 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
887 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
888
889 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
890 0x48);
891 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
892 0x49);
893 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
894 "pca9546", 0x70);
895 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
896 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
897 create_pca9552(soc, 11, 0x60);
898
899
900 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
901 create_pca9552(soc, 13, 0x60);
902
903 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
904 create_pca9552(soc, 14, 0x60);
905
906 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
907 create_pca9552(soc, 15, 0x60);
908 }
909
get_pca9548_channels(I2CBus * bus,uint8_t mux_addr,I2CBus ** channels)910 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
911 I2CBus **channels)
912 {
913 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr);
914 for (int i = 0; i < 8; i++) {
915 channels[i] = pca954x_i2c_get_bus(mux, i);
916 }
917 }
918
919 #define TYPE_LM75 TYPE_TMP105
920 #define TYPE_TMP75 TYPE_TMP105
921 #define TYPE_TMP422 "tmp422"
922
fuji_bmc_i2c_init(AspeedMachineState * bmc)923 static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
924 {
925 AspeedSoCState *soc = bmc->soc;
926 I2CBus *i2c[144] = {};
927
928 for (int i = 0; i < 16; i++) {
929 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
930 }
931 I2CBus *i2c180 = i2c[2];
932 I2CBus *i2c480 = i2c[8];
933 I2CBus *i2c600 = i2c[11];
934
935 get_pca9548_channels(i2c180, 0x70, &i2c[16]);
936 get_pca9548_channels(i2c480, 0x70, &i2c[24]);
937 /* NOTE: The device tree skips [32, 40) in the alias numbering */
938 get_pca9548_channels(i2c600, 0x77, &i2c[40]);
939 get_pca9548_channels(i2c[24], 0x71, &i2c[48]);
940 get_pca9548_channels(i2c[25], 0x72, &i2c[56]);
941 get_pca9548_channels(i2c[26], 0x76, &i2c[64]);
942 get_pca9548_channels(i2c[27], 0x76, &i2c[72]);
943 for (int i = 0; i < 8; i++) {
944 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]);
945 }
946
947 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
948 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
949
950 /*
951 * EEPROM 24c64 size is 64Kbits or 8 Kbytes
952 * 24c02 size is 2Kbits or 256 bytes
953 */
954 at24c_eeprom_init(i2c[19], 0x52, 8 * KiB);
955 at24c_eeprom_init(i2c[20], 0x50, 256);
956 at24c_eeprom_init(i2c[22], 0x52, 256);
957
958 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
959 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
960 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
961 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
962
963 at24c_eeprom_init(i2c[8], 0x51, 8 * KiB);
964 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
965
966 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
967 at24c_eeprom_init(i2c[50], 0x52, 8 * KiB);
968 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
969 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
970
971 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
972 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
973
974 at24c_eeprom_init(i2c[65], 0x53, 8 * KiB);
975 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
976 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
977 at24c_eeprom_init(i2c[68], 0x52, 8 * KiB);
978 at24c_eeprom_init(i2c[69], 0x52, 8 * KiB);
979 at24c_eeprom_init(i2c[70], 0x52, 8 * KiB);
980 at24c_eeprom_init(i2c[71], 0x52, 8 * KiB);
981
982 at24c_eeprom_init(i2c[73], 0x53, 8 * KiB);
983 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
984 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
985 at24c_eeprom_init(i2c[76], 0x52, 8 * KiB);
986 at24c_eeprom_init(i2c[77], 0x52, 8 * KiB);
987 at24c_eeprom_init(i2c[78], 0x52, 8 * KiB);
988 at24c_eeprom_init(i2c[79], 0x52, 8 * KiB);
989 at24c_eeprom_init(i2c[28], 0x50, 256);
990
991 for (int i = 0; i < 8; i++) {
992 at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
993 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
994 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
995 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
996 }
997 }
998
999 #define TYPE_TMP421 "tmp421"
1000
bletchley_bmc_i2c_init(AspeedMachineState * bmc)1001 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
1002 {
1003 AspeedSoCState *soc = bmc->soc;
1004 I2CBus *i2c[13] = {};
1005 for (int i = 0; i < 13; i++) {
1006 if ((i == 8) || (i == 11)) {
1007 continue;
1008 }
1009 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
1010 }
1011
1012 /* Bus 0 - 5 all have the same config. */
1013 for (int i = 0; i < 6; i++) {
1014 /* Missing model: ti,ina230 @ 0x45 */
1015 /* Missing model: mps,mp5023 @ 0x40 */
1016 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f);
1017 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */
1018 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76);
1019 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67);
1020 /* Missing model: fsc,fusb302 @ 0x22 */
1021 }
1022
1023 /* Bus 6 */
1024 at24c_eeprom_init(i2c[6], 0x56, 65536);
1025 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */
1026 i2c_slave_create_simple(i2c[6], "ds1338", 0x51);
1027
1028
1029 /* Bus 7 */
1030 at24c_eeprom_init(i2c[7], 0x54, 65536);
1031
1032 /* Bus 9 */
1033 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f);
1034
1035 /* Bus 10 */
1036 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f);
1037 /* Missing model: ti,hdc1080 @ 0x40 */
1038 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67);
1039
1040 /* Bus 12 */
1041 /* Missing model: adi,adm1278 @ 0x11 */
1042 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c);
1043 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d);
1044 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
1045 }
1046
fby35_i2c_init(AspeedMachineState * bmc)1047 static void fby35_i2c_init(AspeedMachineState *bmc)
1048 {
1049 AspeedSoCState *soc = bmc->soc;
1050 I2CBus *i2c[16];
1051
1052 for (int i = 0; i < 16; i++) {
1053 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
1054 }
1055
1056 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f);
1057 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f);
1058 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */
1059 i2c_slave_create_simple(i2c[11], "adm1272", 0x44);
1060 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);
1061 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);
1062
1063 at24c_eeprom_init(i2c[4], 0x51, 128 * KiB);
1064 at24c_eeprom_init(i2c[6], 0x51, 128 * KiB);
1065 at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid,
1066 fby35_nic_fruid_len);
1067 at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid,
1068 fby35_bb_fruid_len);
1069 at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid,
1070 fby35_bmc_fruid_len);
1071
1072 /*
1073 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
1074 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on
1075 * each.
1076 */
1077 }
1078
qcom_dc_scm_bmc_i2c_init(AspeedMachineState * bmc)1079 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
1080 {
1081 AspeedSoCState *soc = bmc->soc;
1082
1083 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
1084 }
1085
qcom_dc_scm_firework_i2c_init(AspeedMachineState * bmc)1086 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
1087 {
1088 AspeedSoCState *soc = bmc->soc;
1089 I2CSlave *therm_mux, *cpuvr_mux;
1090
1091 /* Create the generic DC-SCM hardware */
1092 qcom_dc_scm_bmc_i2c_init(bmc);
1093
1094 /* Now create the Firework specific hardware */
1095
1096 /* I2C7 CPUVR MUX */
1097 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
1098 "pca9546", 0x70);
1099 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72);
1100 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72);
1101 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72);
1102 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72);
1103
1104 /* I2C8 Thermal Diodes*/
1105 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
1106 "pca9548", 0x70);
1107 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C);
1108 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C);
1109 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48);
1110 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48);
1111 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48);
1112
1113 /* I2C9 Fan Controller (MAX31785) */
1114 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52);
1115 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54);
1116 }
1117
aspeed_get_mmio_exec(Object * obj,Error ** errp)1118 static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
1119 {
1120 return ASPEED_MACHINE(obj)->mmio_exec;
1121 }
1122
aspeed_set_mmio_exec(Object * obj,bool value,Error ** errp)1123 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
1124 {
1125 ASPEED_MACHINE(obj)->mmio_exec = value;
1126 }
1127
aspeed_machine_instance_init(Object * obj)1128 static void aspeed_machine_instance_init(Object *obj)
1129 {
1130 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(obj);
1131
1132 ASPEED_MACHINE(obj)->mmio_exec = false;
1133 ASPEED_MACHINE(obj)->hw_strap1 = amc->hw_strap1;
1134 }
1135
aspeed_get_fmc_model(Object * obj,Error ** errp)1136 static char *aspeed_get_fmc_model(Object *obj, Error **errp)
1137 {
1138 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1139 return g_strdup(bmc->fmc_model);
1140 }
1141
aspeed_set_fmc_model(Object * obj,const char * value,Error ** errp)1142 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
1143 {
1144 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1145
1146 g_free(bmc->fmc_model);
1147 bmc->fmc_model = g_strdup(value);
1148 }
1149
aspeed_get_spi_model(Object * obj,Error ** errp)1150 static char *aspeed_get_spi_model(Object *obj, Error **errp)
1151 {
1152 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1153 return g_strdup(bmc->spi_model);
1154 }
1155
aspeed_set_spi_model(Object * obj,const char * value,Error ** errp)1156 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
1157 {
1158 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1159
1160 g_free(bmc->spi_model);
1161 bmc->spi_model = g_strdup(value);
1162 }
1163
aspeed_get_bmc_console(Object * obj,Error ** errp)1164 static char *aspeed_get_bmc_console(Object *obj, Error **errp)
1165 {
1166 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1167 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
1168 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
1169
1170 return g_strdup_printf("uart%d", aspeed_uart_index(uart_chosen));
1171 }
1172
aspeed_set_bmc_console(Object * obj,const char * value,Error ** errp)1173 static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp)
1174 {
1175 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1176 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
1177 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name));
1178 int val;
1179 int uart_first = aspeed_uart_first(sc);
1180 int uart_last = aspeed_uart_last(sc);
1181
1182 if (sscanf(value, "uart%u", &val) != 1) {
1183 error_setg(errp, "Bad value for \"uart\" property");
1184 return;
1185 }
1186
1187 /* The number of UART depends on the SoC */
1188 if (val < uart_first || val > uart_last) {
1189 error_setg(errp, "\"uart\" should be in range [%d - %d]",
1190 uart_first, uart_last);
1191 return;
1192 }
1193 bmc->uart_chosen = val + ASPEED_DEV_UART0;
1194 }
1195
aspeed_machine_class_props_init(ObjectClass * oc)1196 static void aspeed_machine_class_props_init(ObjectClass *oc)
1197 {
1198 object_class_property_add_bool(oc, "execute-in-place",
1199 aspeed_get_mmio_exec,
1200 aspeed_set_mmio_exec);
1201 object_class_property_set_description(oc, "execute-in-place",
1202 "boot directly from CE0 flash device");
1203
1204 object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console,
1205 aspeed_set_bmc_console);
1206 object_class_property_set_description(oc, "bmc-console",
1207 "Change the default UART to \"uartX\"");
1208
1209 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
1210 aspeed_set_fmc_model);
1211 object_class_property_set_description(oc, "fmc-model",
1212 "Change the FMC Flash model");
1213 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
1214 aspeed_set_spi_model);
1215 object_class_property_set_description(oc, "spi-model",
1216 "Change the SPI Flash model");
1217 }
1218
aspeed_machine_class_init_cpus_defaults(MachineClass * mc)1219 static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc)
1220 {
1221 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc);
1222 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name));
1223
1224 mc->default_cpus = sc->num_cpus;
1225 mc->min_cpus = sc->num_cpus;
1226 mc->max_cpus = sc->num_cpus;
1227 mc->valid_cpu_types = sc->valid_cpu_types;
1228 }
1229
aspeed_machine_ast2600_get_boot_from_emmc(Object * obj,Error ** errp)1230 static bool aspeed_machine_ast2600_get_boot_from_emmc(Object *obj, Error **errp)
1231 {
1232 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1233
1234 return !!(bmc->hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC);
1235 }
1236
aspeed_machine_ast2600_set_boot_from_emmc(Object * obj,bool value,Error ** errp)1237 static void aspeed_machine_ast2600_set_boot_from_emmc(Object *obj, bool value,
1238 Error **errp)
1239 {
1240 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1241
1242 if (value) {
1243 bmc->hw_strap1 |= SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC;
1244 } else {
1245 bmc->hw_strap1 &= ~SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC;
1246 }
1247 }
1248
aspeed_machine_ast2600_class_emmc_init(ObjectClass * oc)1249 static void aspeed_machine_ast2600_class_emmc_init(ObjectClass *oc)
1250 {
1251 object_class_property_add_bool(oc, "boot-emmc",
1252 aspeed_machine_ast2600_get_boot_from_emmc,
1253 aspeed_machine_ast2600_set_boot_from_emmc);
1254 object_class_property_set_description(oc, "boot-emmc",
1255 "Set or unset boot from EMMC");
1256 }
1257
aspeed_machine_class_init(ObjectClass * oc,void * data)1258 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
1259 {
1260 MachineClass *mc = MACHINE_CLASS(oc);
1261 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1262
1263 mc->init = aspeed_machine_init;
1264 mc->no_floppy = 1;
1265 mc->no_cdrom = 1;
1266 mc->no_parallel = 1;
1267 mc->default_ram_id = "ram";
1268 amc->macs_mask = ASPEED_MAC0_ON;
1269 amc->uart_default = ASPEED_DEV_UART5;
1270
1271 aspeed_machine_class_props_init(oc);
1272 }
1273
aspeed_machine_palmetto_class_init(ObjectClass * oc,void * data)1274 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
1275 {
1276 MachineClass *mc = MACHINE_CLASS(oc);
1277 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1278
1279 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
1280 amc->soc_name = "ast2400-a1";
1281 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
1282 amc->fmc_model = "n25q256a";
1283 amc->spi_model = "mx25l25635f";
1284 amc->num_cs = 1;
1285 amc->i2c_init = palmetto_bmc_i2c_init;
1286 mc->default_ram_size = 256 * MiB;
1287 aspeed_machine_class_init_cpus_defaults(mc);
1288 };
1289
aspeed_machine_quanta_q71l_class_init(ObjectClass * oc,void * data)1290 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
1291 {
1292 MachineClass *mc = MACHINE_CLASS(oc);
1293 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1294
1295 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)";
1296 amc->soc_name = "ast2400-a1";
1297 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
1298 amc->fmc_model = "n25q256a";
1299 amc->spi_model = "mx25l25635e";
1300 amc->num_cs = 1;
1301 amc->i2c_init = quanta_q71l_bmc_i2c_init;
1302 mc->default_ram_size = 128 * MiB;
1303 aspeed_machine_class_init_cpus_defaults(mc);
1304 }
1305
aspeed_machine_supermicrox11_bmc_class_init(ObjectClass * oc,void * data)1306 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
1307 void *data)
1308 {
1309 MachineClass *mc = MACHINE_CLASS(oc);
1310 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1311
1312 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)";
1313 amc->soc_name = "ast2400-a1";
1314 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
1315 amc->fmc_model = "mx25l25635e";
1316 amc->spi_model = "mx25l25635e";
1317 amc->num_cs = 1;
1318 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1319 amc->i2c_init = palmetto_bmc_i2c_init;
1320 mc->default_ram_size = 256 * MiB;
1321 aspeed_machine_class_init_cpus_defaults(mc);
1322 }
1323
aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass * oc,void * data)1324 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
1325 void *data)
1326 {
1327 MachineClass *mc = MACHINE_CLASS(oc);
1328 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1329
1330 mc->desc = "Supermicro X11 SPI BMC (ARM1176)";
1331 amc->soc_name = "ast2500-a1";
1332 amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1;
1333 amc->fmc_model = "mx25l25635e";
1334 amc->spi_model = "mx25l25635e";
1335 amc->num_cs = 1;
1336 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1337 amc->i2c_init = palmetto_bmc_i2c_init;
1338 mc->default_ram_size = 512 * MiB;
1339 aspeed_machine_class_init_cpus_defaults(mc);
1340 }
1341
aspeed_machine_ast2500_evb_class_init(ObjectClass * oc,void * data)1342 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
1343 {
1344 MachineClass *mc = MACHINE_CLASS(oc);
1345 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1346
1347 mc->desc = "Aspeed AST2500 EVB (ARM1176)";
1348 amc->soc_name = "ast2500-a1";
1349 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1350 amc->fmc_model = "mx25l25635e";
1351 amc->spi_model = "mx25l25635f";
1352 amc->num_cs = 1;
1353 amc->i2c_init = ast2500_evb_i2c_init;
1354 mc->default_ram_size = 512 * MiB;
1355 aspeed_machine_class_init_cpus_defaults(mc);
1356 };
1357
aspeed_machine_yosemitev2_class_init(ObjectClass * oc,void * data)1358 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data)
1359 {
1360 MachineClass *mc = MACHINE_CLASS(oc);
1361 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1362
1363 mc->desc = "Facebook YosemiteV2 BMC (ARM1176)";
1364 amc->soc_name = "ast2500-a1";
1365 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1366 amc->hw_strap2 = 0;
1367 amc->fmc_model = "n25q256a";
1368 amc->spi_model = "mx25l25635e";
1369 amc->num_cs = 2;
1370 amc->i2c_init = yosemitev2_bmc_i2c_init;
1371 mc->default_ram_size = 512 * MiB;
1372 aspeed_machine_class_init_cpus_defaults(mc);
1373 };
1374
aspeed_machine_romulus_class_init(ObjectClass * oc,void * data)1375 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
1376 {
1377 MachineClass *mc = MACHINE_CLASS(oc);
1378 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1379
1380 mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
1381 amc->soc_name = "ast2500-a1";
1382 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
1383 amc->fmc_model = "n25q256a";
1384 amc->spi_model = "mx66l1g45g";
1385 amc->num_cs = 2;
1386 amc->i2c_init = romulus_bmc_i2c_init;
1387 mc->default_ram_size = 512 * MiB;
1388 aspeed_machine_class_init_cpus_defaults(mc);
1389 };
1390
aspeed_machine_tiogapass_class_init(ObjectClass * oc,void * data)1391 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
1392 {
1393 MachineClass *mc = MACHINE_CLASS(oc);
1394 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1395
1396 mc->desc = "Facebook Tiogapass BMC (ARM1176)";
1397 amc->soc_name = "ast2500-a1";
1398 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1399 amc->hw_strap2 = 0;
1400 amc->fmc_model = "n25q256a";
1401 amc->spi_model = "mx25l25635e";
1402 amc->num_cs = 2;
1403 amc->i2c_init = tiogapass_bmc_i2c_init;
1404 mc->default_ram_size = 1 * GiB;
1405 aspeed_machine_class_init_cpus_defaults(mc);
1406 };
1407
aspeed_machine_sonorapass_class_init(ObjectClass * oc,void * data)1408 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
1409 {
1410 MachineClass *mc = MACHINE_CLASS(oc);
1411 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1412
1413 mc->desc = "OCP SonoraPass BMC (ARM1176)";
1414 amc->soc_name = "ast2500-a1";
1415 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
1416 amc->fmc_model = "mx66l1g45g";
1417 amc->spi_model = "mx66l1g45g";
1418 amc->num_cs = 2;
1419 amc->i2c_init = sonorapass_bmc_i2c_init;
1420 mc->default_ram_size = 512 * MiB;
1421 aspeed_machine_class_init_cpus_defaults(mc);
1422 };
1423
aspeed_machine_witherspoon_class_init(ObjectClass * oc,void * data)1424 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
1425 {
1426 MachineClass *mc = MACHINE_CLASS(oc);
1427 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1428
1429 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
1430 amc->soc_name = "ast2500-a1";
1431 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
1432 amc->fmc_model = "mx25l25635f";
1433 amc->spi_model = "mx66l1g45g";
1434 amc->num_cs = 2;
1435 amc->i2c_init = witherspoon_bmc_i2c_init;
1436 mc->default_ram_size = 512 * MiB;
1437 aspeed_machine_class_init_cpus_defaults(mc);
1438 };
1439
aspeed_machine_ast2600_evb_class_init(ObjectClass * oc,void * data)1440 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
1441 {
1442 MachineClass *mc = MACHINE_CLASS(oc);
1443 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1444
1445 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)";
1446 amc->soc_name = "ast2600-a3";
1447 amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
1448 amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
1449 amc->fmc_model = "mx66u51235f";
1450 amc->spi_model = "mx66u51235f";
1451 amc->num_cs = 1;
1452 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
1453 ASPEED_MAC3_ON;
1454 amc->sdhci_wp_inverted = true;
1455 amc->i2c_init = ast2600_evb_i2c_init;
1456 mc->default_ram_size = 1 * GiB;
1457 aspeed_machine_class_init_cpus_defaults(mc);
1458 aspeed_machine_ast2600_class_emmc_init(oc);
1459 };
1460
aspeed_machine_g220a_class_init(ObjectClass * oc,void * data)1461 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
1462 {
1463 MachineClass *mc = MACHINE_CLASS(oc);
1464 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1465
1466 mc->desc = "Bytedance G220A BMC (ARM1176)";
1467 amc->soc_name = "ast2500-a1";
1468 amc->hw_strap1 = G220A_BMC_HW_STRAP1;
1469 amc->fmc_model = "n25q512a";
1470 amc->spi_model = "mx25l25635e";
1471 amc->num_cs = 2;
1472 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1473 amc->i2c_init = g220a_bmc_i2c_init;
1474 mc->default_ram_size = 1024 * MiB;
1475 aspeed_machine_class_init_cpus_defaults(mc);
1476 };
1477
aspeed_machine_fp5280g2_class_init(ObjectClass * oc,void * data)1478 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
1479 {
1480 MachineClass *mc = MACHINE_CLASS(oc);
1481 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1482
1483 mc->desc = "Inspur FP5280G2 BMC (ARM1176)";
1484 amc->soc_name = "ast2500-a1";
1485 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1;
1486 amc->fmc_model = "n25q512a";
1487 amc->spi_model = "mx25l25635e";
1488 amc->num_cs = 2;
1489 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1490 amc->i2c_init = fp5280g2_bmc_i2c_init;
1491 mc->default_ram_size = 512 * MiB;
1492 aspeed_machine_class_init_cpus_defaults(mc);
1493 };
1494
aspeed_machine_rainier_class_init(ObjectClass * oc,void * data)1495 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
1496 {
1497 MachineClass *mc = MACHINE_CLASS(oc);
1498 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1499
1500 mc->desc = "IBM Rainier BMC (Cortex-A7)";
1501 amc->soc_name = "ast2600-a3";
1502 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
1503 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
1504 amc->fmc_model = "mx66l1g45g";
1505 amc->spi_model = "mx66l1g45g";
1506 amc->num_cs = 2;
1507 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1508 amc->i2c_init = rainier_bmc_i2c_init;
1509 mc->default_ram_size = 1 * GiB;
1510 aspeed_machine_class_init_cpus_defaults(mc);
1511 aspeed_machine_ast2600_class_emmc_init(oc);
1512 };
1513
1514 #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
1515
aspeed_machine_fuji_class_init(ObjectClass * oc,void * data)1516 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
1517 {
1518 MachineClass *mc = MACHINE_CLASS(oc);
1519 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1520
1521 mc->desc = "Facebook Fuji BMC (Cortex-A7)";
1522 amc->soc_name = "ast2600-a3";
1523 amc->hw_strap1 = FUJI_BMC_HW_STRAP1;
1524 amc->hw_strap2 = FUJI_BMC_HW_STRAP2;
1525 amc->fmc_model = "mx66l1g45g";
1526 amc->spi_model = "mx66l1g45g";
1527 amc->num_cs = 2;
1528 amc->macs_mask = ASPEED_MAC3_ON;
1529 amc->i2c_init = fuji_bmc_i2c_init;
1530 amc->uart_default = ASPEED_DEV_UART1;
1531 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1532 aspeed_machine_class_init_cpus_defaults(mc);
1533 };
1534
1535 #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
1536
aspeed_machine_bletchley_class_init(ObjectClass * oc,void * data)1537 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
1538 {
1539 MachineClass *mc = MACHINE_CLASS(oc);
1540 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1541
1542 mc->desc = "Facebook Bletchley BMC (Cortex-A7)";
1543 amc->soc_name = "ast2600-a3";
1544 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1;
1545 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2;
1546 amc->fmc_model = "w25q01jvq";
1547 amc->spi_model = NULL;
1548 amc->num_cs = 2;
1549 amc->macs_mask = ASPEED_MAC2_ON;
1550 amc->i2c_init = bletchley_bmc_i2c_init;
1551 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
1552 aspeed_machine_class_init_cpus_defaults(mc);
1553 }
1554
fby35_reset(MachineState * state,ResetType type)1555 static void fby35_reset(MachineState *state, ResetType type)
1556 {
1557 AspeedMachineState *bmc = ASPEED_MACHINE(state);
1558 AspeedGPIOState *gpio = &bmc->soc->gpio;
1559
1560 qemu_devices_reset(type);
1561
1562 /* Board ID: 7 (Class-1, 4 slots) */
1563 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal);
1564 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal);
1565 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal);
1566 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal);
1567
1568 /* Slot presence pins, inverse polarity. (False means present) */
1569 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal);
1570 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal);
1571 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal);
1572 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal);
1573
1574 /* Slot 12v power pins, normal polarity. (True means powered-on) */
1575 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal);
1576 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal);
1577 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal);
1578 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal);
1579 }
1580
aspeed_machine_fby35_class_init(ObjectClass * oc,void * data)1581 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data)
1582 {
1583 MachineClass *mc = MACHINE_CLASS(oc);
1584 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1585
1586 mc->desc = "Facebook fby35 BMC (Cortex-A7)";
1587 mc->reset = fby35_reset;
1588 amc->fmc_model = "mx66l1g45g";
1589 amc->num_cs = 2;
1590 amc->macs_mask = ASPEED_MAC3_ON;
1591 amc->i2c_init = fby35_i2c_init;
1592 /* FIXME: Replace this macro with something more general */
1593 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1594 aspeed_machine_class_init_cpus_defaults(mc);
1595 }
1596
1597 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
1598 /* Main SYSCLK frequency in Hz (200MHz) */
1599 #define SYSCLK_FRQ 200000000ULL
1600
aspeed_minibmc_machine_init(MachineState * machine)1601 static void aspeed_minibmc_machine_init(MachineState *machine)
1602 {
1603 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
1604 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
1605 Clock *sysclk;
1606
1607 sysclk = clock_new(OBJECT(machine), "SYSCLK");
1608 clock_set_hz(sysclk, SYSCLK_FRQ);
1609
1610 bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
1611 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
1612 object_unref(OBJECT(bmc->soc));
1613 qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk);
1614
1615 object_property_set_link(OBJECT(bmc->soc), "memory",
1616 OBJECT(get_system_memory()), &error_abort);
1617 connect_serial_hds_to_uarts(bmc);
1618 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
1619
1620 if (defaults_enabled()) {
1621 aspeed_board_init_flashes(&bmc->soc->fmc,
1622 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
1623 amc->num_cs,
1624 0);
1625
1626 aspeed_board_init_flashes(&bmc->soc->spi[0],
1627 bmc->spi_model ? bmc->spi_model : amc->spi_model,
1628 amc->num_cs, amc->num_cs);
1629
1630 aspeed_board_init_flashes(&bmc->soc->spi[1],
1631 bmc->spi_model ? bmc->spi_model : amc->spi_model,
1632 amc->num_cs, (amc->num_cs * 2));
1633 }
1634
1635 if (amc->i2c_init) {
1636 amc->i2c_init(bmc);
1637 }
1638
1639 armv7m_load_kernel(ARM_CPU(first_cpu),
1640 machine->kernel_filename,
1641 0,
1642 AST1030_INTERNAL_FLASH_SIZE);
1643 }
1644
ast1030_evb_i2c_init(AspeedMachineState * bmc)1645 static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
1646 {
1647 AspeedSoCState *soc = bmc->soc;
1648
1649 /* U10 24C08 connects to SDA/SCL Group 1 by default */
1650 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
1651 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf);
1652
1653 /* U11 LM75 connects to SDA/SCL Group 2 by default */
1654 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d);
1655 }
1656
aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass * oc,void * data)1657 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
1658 void *data)
1659 {
1660 MachineClass *mc = MACHINE_CLASS(oc);
1661 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1662
1663 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)";
1664 amc->soc_name = "ast1030-a1";
1665 amc->hw_strap1 = 0;
1666 amc->hw_strap2 = 0;
1667 mc->init = aspeed_minibmc_machine_init;
1668 amc->i2c_init = ast1030_evb_i2c_init;
1669 mc->default_ram_size = 0;
1670 amc->fmc_model = "w25q80bl";
1671 amc->spi_model = "w25q256";
1672 amc->num_cs = 2;
1673 amc->macs_mask = 0;
1674 aspeed_machine_class_init_cpus_defaults(mc);
1675 }
1676
1677 #ifdef TARGET_AARCH64
ast2700_evb_i2c_init(AspeedMachineState * bmc)1678 static void ast2700_evb_i2c_init(AspeedMachineState *bmc)
1679 {
1680 AspeedSoCState *soc = bmc->soc;
1681
1682 /* LM75 is compatible with TMP105 driver */
1683 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0),
1684 TYPE_TMP105, 0x4d);
1685 }
1686
aspeed_machine_ast2700_evb_class_init(ObjectClass * oc,void * data)1687 static void aspeed_machine_ast2700_evb_class_init(ObjectClass *oc, void *data)
1688 {
1689 MachineClass *mc = MACHINE_CLASS(oc);
1690 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1691
1692 mc->desc = "Aspeed AST2700 EVB (Cortex-A35)";
1693 amc->soc_name = "ast2700-a0";
1694 amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
1695 amc->hw_strap2 = AST2700_EVB_HW_STRAP2;
1696 amc->fmc_model = "w25q01jvq";
1697 amc->spi_model = "w25q512jv";
1698 amc->num_cs = 2;
1699 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON;
1700 amc->uart_default = ASPEED_DEV_UART12;
1701 amc->i2c_init = ast2700_evb_i2c_init;
1702 mc->default_ram_size = 1 * GiB;
1703 aspeed_machine_class_init_cpus_defaults(mc);
1704 }
1705 #endif
1706
aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass * oc,void * data)1707 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
1708 void *data)
1709 {
1710 MachineClass *mc = MACHINE_CLASS(oc);
1711 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1712
1713 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)";
1714 amc->soc_name = "ast2600-a3";
1715 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1716 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1717 amc->fmc_model = "n25q512a";
1718 amc->spi_model = "n25q512a";
1719 amc->num_cs = 2;
1720 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1721 amc->i2c_init = qcom_dc_scm_bmc_i2c_init;
1722 mc->default_ram_size = 1 * GiB;
1723 aspeed_machine_class_init_cpus_defaults(mc);
1724 };
1725
aspeed_machine_qcom_firework_class_init(ObjectClass * oc,void * data)1726 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
1727 void *data)
1728 {
1729 MachineClass *mc = MACHINE_CLASS(oc);
1730 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1731
1732 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)";
1733 amc->soc_name = "ast2600-a3";
1734 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1735 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1736 amc->fmc_model = "n25q512a";
1737 amc->spi_model = "n25q512a";
1738 amc->num_cs = 2;
1739 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1740 amc->i2c_init = qcom_dc_scm_firework_i2c_init;
1741 mc->default_ram_size = 1 * GiB;
1742 aspeed_machine_class_init_cpus_defaults(mc);
1743 };
1744
1745 static const TypeInfo aspeed_machine_types[] = {
1746 {
1747 .name = MACHINE_TYPE_NAME("palmetto-bmc"),
1748 .parent = TYPE_ASPEED_MACHINE,
1749 .class_init = aspeed_machine_palmetto_class_init,
1750 }, {
1751 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
1752 .parent = TYPE_ASPEED_MACHINE,
1753 .class_init = aspeed_machine_supermicrox11_bmc_class_init,
1754 }, {
1755 .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"),
1756 .parent = TYPE_ASPEED_MACHINE,
1757 .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init,
1758 }, {
1759 .name = MACHINE_TYPE_NAME("ast2500-evb"),
1760 .parent = TYPE_ASPEED_MACHINE,
1761 .class_init = aspeed_machine_ast2500_evb_class_init,
1762 }, {
1763 .name = MACHINE_TYPE_NAME("romulus-bmc"),
1764 .parent = TYPE_ASPEED_MACHINE,
1765 .class_init = aspeed_machine_romulus_class_init,
1766 }, {
1767 .name = MACHINE_TYPE_NAME("sonorapass-bmc"),
1768 .parent = TYPE_ASPEED_MACHINE,
1769 .class_init = aspeed_machine_sonorapass_class_init,
1770 }, {
1771 .name = MACHINE_TYPE_NAME("witherspoon-bmc"),
1772 .parent = TYPE_ASPEED_MACHINE,
1773 .class_init = aspeed_machine_witherspoon_class_init,
1774 }, {
1775 .name = MACHINE_TYPE_NAME("ast2600-evb"),
1776 .parent = TYPE_ASPEED_MACHINE,
1777 .class_init = aspeed_machine_ast2600_evb_class_init,
1778 }, {
1779 .name = MACHINE_TYPE_NAME("yosemitev2-bmc"),
1780 .parent = TYPE_ASPEED_MACHINE,
1781 .class_init = aspeed_machine_yosemitev2_class_init,
1782 }, {
1783 .name = MACHINE_TYPE_NAME("tiogapass-bmc"),
1784 .parent = TYPE_ASPEED_MACHINE,
1785 .class_init = aspeed_machine_tiogapass_class_init,
1786 }, {
1787 .name = MACHINE_TYPE_NAME("g220a-bmc"),
1788 .parent = TYPE_ASPEED_MACHINE,
1789 .class_init = aspeed_machine_g220a_class_init,
1790 }, {
1791 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"),
1792 .parent = TYPE_ASPEED_MACHINE,
1793 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init,
1794 }, {
1795 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"),
1796 .parent = TYPE_ASPEED_MACHINE,
1797 .class_init = aspeed_machine_qcom_firework_class_init,
1798 }, {
1799 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"),
1800 .parent = TYPE_ASPEED_MACHINE,
1801 .class_init = aspeed_machine_fp5280g2_class_init,
1802 }, {
1803 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
1804 .parent = TYPE_ASPEED_MACHINE,
1805 .class_init = aspeed_machine_quanta_q71l_class_init,
1806 }, {
1807 .name = MACHINE_TYPE_NAME("rainier-bmc"),
1808 .parent = TYPE_ASPEED_MACHINE,
1809 .class_init = aspeed_machine_rainier_class_init,
1810 }, {
1811 .name = MACHINE_TYPE_NAME("fuji-bmc"),
1812 .parent = TYPE_ASPEED_MACHINE,
1813 .class_init = aspeed_machine_fuji_class_init,
1814 }, {
1815 .name = MACHINE_TYPE_NAME("bletchley-bmc"),
1816 .parent = TYPE_ASPEED_MACHINE,
1817 .class_init = aspeed_machine_bletchley_class_init,
1818 }, {
1819 .name = MACHINE_TYPE_NAME("fby35-bmc"),
1820 .parent = MACHINE_TYPE_NAME("ast2600-evb"),
1821 .class_init = aspeed_machine_fby35_class_init,
1822 }, {
1823 .name = MACHINE_TYPE_NAME("ast1030-evb"),
1824 .parent = TYPE_ASPEED_MACHINE,
1825 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
1826 #ifdef TARGET_AARCH64
1827 }, {
1828 .name = MACHINE_TYPE_NAME("ast2700-evb"),
1829 .parent = TYPE_ASPEED_MACHINE,
1830 .class_init = aspeed_machine_ast2700_evb_class_init,
1831 #endif
1832 }, {
1833 .name = TYPE_ASPEED_MACHINE,
1834 .parent = TYPE_MACHINE,
1835 .instance_size = sizeof(AspeedMachineState),
1836 .instance_init = aspeed_machine_instance_init,
1837 .class_size = sizeof(AspeedMachineClass),
1838 .class_init = aspeed_machine_class_init,
1839 .abstract = true,
1840 }
1841 };
1842
1843 DEFINE_TYPES(aspeed_machine_types)
1844