1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) ASPEED Technology Inc.
4 *
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <ram.h>
12 #include <regmap.h>
13 #include <reset.h>
14 #include <asm/io.h>
15 #include <asm/arch/scu_ast2600.h>
16 #include <asm/arch/sdram_ast2600.h>
17 #include <linux/err.h>
18 #include <linux/kernel.h>
19 #include <dt-bindings/clock/ast2600-clock.h>
20 #include <linux/bitfield.h>
21 #include <linux/bitops.h>
22 #include "sdram_phy_ast2600.h"
23
24 /* in order to speed up DRAM init time, write pre-defined values to registers
25 * directly */
26 #define AST2600_SDRAMMC_MANUAL_CLK
27
28 /* register offset */
29 #define AST_SCU_FPGA_STATUS 0x004
30 #define AST_SCU_HANDSHAKE 0x100
31 #define AST_SCU_MPLL 0x220
32 #define AST_SCU_MPLL_EXT 0x224
33 #define AST_SCU_FPGA_PLL 0x400
34 #define AST_SCU_HW_STRAP 0x500
35 #define AST_SCU_EFUSE_DATA 0x594
36
37
38 /* bit-field of AST_SCU_HW_STRAP */
39 #define SCU_HWSTRAP_VGAMEM_SHIFT 13
40 #define SCU_HWSTRAP_VGAMEM_MASK GENMASK(14, 13)
41
42 /* bit-field of AST_SCU_EFUSE_DATA */
43 #define SCU_EFUSE_DATA_VGA_DIS_MASK BIT(14)
44
45 /* bit-field of AST_SCU_HANDSHAKE */
46 #define SCU_SDRAM_SUPPORT_IKVM_HIGH_RES BIT(0)
47 #define SCU_SDRAM_INIT_READY_MASK BIT(6)
48 #define SCU_SDRAM_INIT_BY_SOC_MASK BIT(7)
49 #define SCU_P2A_BRIDGE_DISABLE BIT(12)
50 #define SCU_HANDSHAKE_MASK \
51 (SCU_SDRAM_INIT_READY_MASK | SCU_SDRAM_INIT_BY_SOC_MASK | \
52 SCU_P2A_BRIDGE_DISABLE | SCU_SDRAM_SUPPORT_IKVM_HIGH_RES)
53
54 /* bit-field of AST_SCU_MPLL */
55 #define SCU_MPLL_RESET BIT(25)
56 #define SCU_MPLL_BYPASS BIT(24)
57 #define SCU_MPLL_TURN_OFF BIT(23)
58 #define SCU_MPLL_FREQ_MASK GENMASK(22, 0)
59
60 #define SCU_MPLL_FREQ_400M 0x0008405F
61 #define SCU_MPLL_EXT_400M 0x0000002F
62 //#define SCU_MPLL_FREQ_400M 0x0038007F
63 //#define SCU_MPLL_EXT_400M 0x0000003F
64 #define SCU_MPLL_FREQ_333M 0x00488299
65 #define SCU_MPLL_EXT_333M 0x0000014C
66 #define SCU_MPLL_FREQ_200M 0x0078007F
67 #define SCU_MPLL_EXT_200M 0x0000003F
68 #define SCU_MPLL_FREQ_100M 0x0078003F
69 #define SCU_MPLL_EXT_100M 0x0000001F
70 /* MPLL configuration */
71 #if defined(CONFIG_ASPEED_DDR4_1600)
72 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_400M
73 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_400M
74 #elif defined(CONFIG_ASPEED_DDR4_1333)
75 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_333M
76 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_333M
77 #elif defined(CONFIG_ASPEED_DDR4_800)
78 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_200M
79 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_200M
80 #elif defined(CONFIG_ASPEED_DDR4_400)
81 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_100M
82 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_100M
83 #else
84 #error "undefined DDR4 target rate\n"
85 #endif
86
87 /**
88 * MR01[26:24] - ODT configuration (DRAM side)
89 * b'001 : 60 ohm
90 * b'101 : 48 ohm
91 * b'011 : 40 ohm (default)
92 */
93 #if defined(CONFIG_ASPEED_DDR4_DRAM_ODT60)
94 #define MR01_DRAM_ODT (0x1 << 24)
95 #elif defined(CONFIG_ASPEED_DDR4_DRAM_ODT48)
96 #define MR01_DRAM_ODT (0x5 << 24)
97 #else
98 #define MR01_DRAM_ODT (0x3 << 24)
99 #endif
100
101 /* AC timing and SDRAM mode registers */
102 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM)
103 /* mode register settings for FPGA are fixed */
104 #define DDR4_MR01_MODE (MR01_DRAM_ODT | 0x00010100)
105 #define DDR4_MR23_MODE 0x00000000
106 #define DDR4_MR45_MODE 0x04C00000
107 #define DDR4_MR6_MODE 0x00000050
108 #define DDR4_TRFC_FPGA 0x17263434
109 #define DDR4_TRFI 0x5d
110
111 /* FPGA need for an additional initialization procedure: search read window */
112 #define SEARCH_RDWIN_ANCHOR_0 (CONFIG_SYS_SDRAM_BASE + 0x0000)
113 #define SEARCH_RDWIN_ANCHOR_1 (CONFIG_SYS_SDRAM_BASE + 0x0004)
114 #define SEARCH_RDWIN_PTRN_0 0x12345678
115 #define SEARCH_RDWIN_PTRN_1 0xaabbccdd
116 #define SEARCH_RDWIN_PTRN_SUM 0xbcf02355
117 #else
118 /* mode register setting for real chip are derived from the model GDDR4-1600 */
119 #define DDR4_MR01_MODE ((MR1_VAL << 16) | MR0_VAL)
120 #define DDR4_MR23_MODE ((MR3_VAL << 16) | MR2_VAL)
121 #define DDR4_MR45_MODE ((MR5_VAL << 16) | MR4_VAL)
122 #define DDR4_MR6_MODE MR6_VAL
123
124 #define DDR4_TRFC_1600 0x467299f1
125 #define DDR4_TRFC_1333 0x3a5f80c9
126 #define DDR4_TRFC_800 0x23394c78
127 #define DDR4_TRFC_400 0x111c263c
128 /*
129 * tRFI calculation
130 * DDR4 spec. :
131 * tRFI = 7.8 us if temperature is Less/equal than 85 degree celsius
132 * tRFI = 3.9 us if temperature is greater than 85 degree celsius
133 *
134 * tRFI in MCR0C = floor(tRFI * 12.5M) - margin
135 * normal temp. -> floor(7.8 * 12.5) - 2 = 0x5f
136 * high temp. -> floor(3.9 * 12.5) - 1 = 0x2f
137 */
138 #ifdef CONFIG_ASPEED_HI_TEMP_TRFI
139 #define DDR4_TRFI 0x2f /* High temperature tRFI */
140 #else
141 #define DDR4_TRFI 0x5f /* Normal temperature tRFI */
142 #endif /* end of "#ifdef CONFIG_ASPEED_HI_TEMP_TRFI" */
143 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \
144 defined(CONFIG_ASPEED_PALLADIUM)" */
145
146 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM)
147 #define DDR4_TRFC DDR4_TRFC_FPGA
148 #else
149 /* real chip setting */
150 #if defined(CONFIG_ASPEED_DDR4_1600)
151 #define DDR4_TRFC DDR4_TRFC_1600
152 #define DDR4_PHY_TRAIN_TRFC 0xc30
153 #elif defined(CONFIG_ASPEED_DDR4_1333)
154 #define DDR4_TRFC DDR4_TRFC_1333
155 #define DDR4_PHY_TRAIN_TRFC 0xa25
156 #elif defined(CONFIG_ASPEED_DDR4_800)
157 #define DDR4_TRFC DDR4_TRFC_800
158 #define DDR4_PHY_TRAIN_TRFC 0x618
159 #elif defined(CONFIG_ASPEED_DDR4_400)
160 #define DDR4_TRFC DDR4_TRFC_400
161 #define DDR4_PHY_TRAIN_TRFC 0x30c
162 #else
163 #error "undefined tRFC setting"
164 #endif /* end of "#if (SCU_MPLL_FREQ_CFG == SCU_MPLL_FREQ_400M)" */
165 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \
166 defined(CONFIG_ASPEED_PALLADIUM)" */
167
168 /* supported SDRAM size */
169 #define SDRAM_SIZE_1KB (1024U)
170 #define SDRAM_SIZE_1MB (SDRAM_SIZE_1KB * SDRAM_SIZE_1KB)
171 #define SDRAM_MIN_SIZE (256 * SDRAM_SIZE_1MB)
172 #define SDRAM_MAX_SIZE (2048 * SDRAM_SIZE_1MB)
173
174
175 DECLARE_GLOBAL_DATA_PTR;
176
177 /*
178 * Bandwidth configuration parameters for different SDRAM requests.
179 * These are hardcoded settings taken from Aspeed SDK.
180 */
181 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM)
182 static const u32 ddr4_ac_timing[4] = { 0x030C0207, 0x04451133, 0x0E010200,
183 0x00000140 };
184
185 static const u32 ddr_max_grant_params[4] = { 0x88888888, 0x88888888, 0x88888888,
186 0x88888888 };
187 #else
188 static const u32 ddr4_ac_timing[4] = { 0x040e0307, 0x0f4711f1, 0x0e060304,
189 0x00001240 };
190
191 static const u32 ddr_max_grant_params[4] = { 0x44484488, 0xee4444ee, 0x44444444,
192 0x44444444 };
193 #endif
194
195 struct dram_info {
196 struct ram_info info;
197 struct clk ddr_clk;
198 struct ast2600_sdrammc_regs *regs;
199 void __iomem *scu;
200 struct ast2600_ddr_phy *phy;
201 void __iomem *phy_setting;
202 void __iomem *phy_status;
203 ulong clock_rate;
204 };
205
ast2600_sdramphy_kick_training(struct dram_info * info)206 static void ast2600_sdramphy_kick_training(struct dram_info *info)
207 {
208 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM)
209 struct ast2600_sdrammc_regs *regs = info->regs;
210 u32 volatile data;
211
212 writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]);
213 udelay(5);
214 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]);
215 udelay(1000);
216
217 while (1) {
218 data = readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT;
219 if (data == 0)
220 break;
221 }
222 #endif
223 }
224
225 /**
226 * @brief load DDR-PHY configurations table to the PHY registers
227 * @param[in] p_tbl - pointer to the configuration table
228 * @param[in] info - pointer to the DRAM info struct
229 *
230 * There are two sets of MRS (Mode Registers) configuration in ast2600 memory
231 * system: one is in the SDRAM MC (memory controller) which is used in run
232 * time, and the other is in the DDR-PHY IP which is used during DDR-PHY
233 * training.
234 */
ast2600_sdramphy_init(u32 * p_tbl,struct dram_info * info)235 static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info)
236 {
237 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM)
238 u32 reg_base = (u32)info->phy_setting;
239 u32 addr = p_tbl[0];
240 u32 data;
241 int i = 1;
242
243 writel(0, &info->regs->phy_ctrl[0]);
244 udelay(10);
245 //writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]);
246
247 /* load PHY configuration table into PHY-setting registers */
248 while (1) {
249 if (addr < reg_base) {
250 debug("invalid DDR-PHY addr: 0x%08x\n", addr);
251 break;
252 }
253 data = p_tbl[i++];
254
255 if (data == DDR_PHY_TBL_END) {
256 break;
257 } else if (data == DDR_PHY_TBL_CHG_ADDR) {
258 addr = p_tbl[i++];
259 } else {
260 writel(data, addr);
261 addr += 4;
262 }
263 }
264
265 data = readl(info->phy_setting + 0x84) & ~GENMASK(16, 0);
266 data |= DDR4_PHY_TRAIN_TRFC;
267 writel(data, info->phy_setting + 0x84);
268 #endif
269 }
270
ast2600_sdramphy_check_status(struct dram_info * info)271 static int ast2600_sdramphy_check_status(struct dram_info *info)
272 {
273 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM)
274 u32 value, tmp;
275 u32 reg_base = (u32)info->phy_status;
276 int need_retrain = 0;
277
278 debug("\nSDRAM PHY training report:\n");
279 /* training status */
280 value = readl(reg_base + 0x00);
281 debug("\nrO_DDRPHY_reg offset 0x00 = 0x%08x\n", value);
282 if (value & BIT(3))
283 debug("\tinitial PVT calibration fail\n");
284
285 if (value & BIT(5))
286 debug("\truntime calibration fail\n");
287
288 /* PU & PD */
289 value = readl(reg_base + 0x30);
290 debug("\nrO_DDRPHY_reg offset 0x30 = 0x%08x\n", value);
291 debug(" PU = 0x%02lx\n", FIELD_GET(GENMASK(7, 0), value));
292 debug(" PD = 0x%02lx\n", FIELD_GET(GENMASK(23, 16), value));
293
294 /* read eye window */
295 value = readl(reg_base + 0x68);
296 if (FIELD_GET(GENMASK(7, 0), value) == 0)
297 need_retrain = 1;
298
299 debug("\nrO_DDRPHY_reg offset 0x68 = 0x%08x\n", value);
300 debug(" rising edge of read data eye training pass window\n");
301 tmp = FIELD_GET(GENMASK(7, 0), value) * 100 / 255;
302 debug(" B0:%d%%\n", tmp);
303 tmp = FIELD_GET(GENMASK(15, 8), value) * 100 / 255;
304 debug(" B1:%d%%\n", tmp);
305
306 value = readl(reg_base + 0xC8);
307 debug("\nrO_DDRPHY_reg offset 0xC8 = 0x%08x\n", value);
308 debug(" falling edge of read data eye training pass window\n");
309 tmp = FIELD_GET(GENMASK(7, 0), value) * 100 / 255;
310 debug(" B0:%d%%\n", tmp);
311 tmp = FIELD_GET(GENMASK(15, 8), value) * 100 / 255;
312 debug(" B1:%d%%\n", tmp);
313
314 /* write eye window */
315 value = readl(reg_base + 0x7c);
316 if (FIELD_GET(GENMASK(7, 0), value) == 0)
317 need_retrain = 1;
318
319 debug("\nrO_DDRPHY_reg offset 0x7C = 0x%08x\n", value);
320 debug(" write data eye training pass window\n");
321 tmp = FIELD_GET(GENMASK(7, 0), value) * 100 / 255;
322 debug(" B0:%d%%\n", tmp);
323 tmp = FIELD_GET(GENMASK(15, 8), value) * 100 / 255;
324 debug(" B1:%d%%\n", tmp);
325
326 /* read Vref (PHY side) training result */
327 value = readl(reg_base + 0x88);
328 debug("\nrO_DDRPHY_reg offset 0x88 = 0x%08x\n", value);
329 debug(" Read VrefDQ training result\n");
330 tmp = FIELD_GET(GENMASK(7, 0), value) * 10000 / 128;
331 debug(" B0:%d.%d%%\n", tmp / 100, tmp % 100);
332 tmp = FIELD_GET(GENMASK(15, 8), value) * 10000 / 128;
333 debug(" B1:%d.%d%%\n", tmp / 100, tmp % 100);
334
335 /* write Vref (DRAM side) training result */
336 value = readl(reg_base + 0x90);
337 debug("\nrO_DDRPHY_reg offset 0x90 = 0x%08x\n", value);
338 tmp = readl(info->phy_setting + 0x60) & BIT(6);
339 if (tmp) {
340 value = 4500 + 65 * value;
341 debug(" Write Vref training result: %d.%d%% (range 2)\n",
342 value / 100, value % 100);
343 } else {
344 value = 6000 + 65 * value;
345 debug(" Write Vref training result: %d.%d%% (range 1)\n",
346 value / 100, value % 100);
347 }
348
349 /* gate train */
350 value = readl(reg_base + 0x50);
351 debug("\nrO_DDRPHY_reg offset 0x50 = 0x%08x\n", value);
352 if ((FIELD_GET(GENMASK(15, 0), value) == 0) ||
353 (FIELD_GET(GENMASK(31, 16), value) == 0))
354 need_retrain = 1;
355
356 debug(" gate training pass window\n");
357 debug(" module 0: 0x%04lx\n", FIELD_GET(GENMASK(15, 0), value));
358 debug(" module 1: 0x%04lx\n", FIELD_GET(GENMASK(31, 16), value));
359
360 return need_retrain;
361 #else
362 return 0;
363 #endif
364 }
365 #ifndef CONFIG_ASPEED_BYPASS_SELFTEST
366 #define MC_TEST_PATTERN_N 8
367 static u32 as2600_sdrammc_test_pattern[MC_TEST_PATTERN_N] = {
368 0xcc33cc33, 0xff00ff00, 0xaa55aa55, 0x88778877,
369 0x92cc4d6e, 0x543d3cde, 0xf1e843c7, 0x7c61d253
370 };
371
372 #define TIMEOUT_DRAM 5000000
ast2600_sdrammc_dg_test(struct dram_info * info,unsigned int datagen,u32 mode)373 int ast2600_sdrammc_dg_test(struct dram_info *info, unsigned int datagen, u32 mode)
374 {
375 unsigned int data;
376 unsigned int timeout = 0;
377 struct ast2600_sdrammc_regs *regs = info->regs;
378
379 writel(0, ®s->ecc_test_ctrl);
380 if (mode == 0)
381 writel(0x00000085 | (datagen << 3), ®s->ecc_test_ctrl);
382 else
383 writel(0x000000C1 | (datagen << 3), ®s->ecc_test_ctrl);
384
385 do {
386 data = readl(®s->ecc_test_ctrl) & GENMASK(13, 12);
387
388 if (data & BIT(13))
389 return 0;
390
391 if (++timeout > TIMEOUT_DRAM) {
392 printf("Timeout!!\n");
393 writel(0, ®s->ecc_test_ctrl);
394
395 return 0;
396 }
397 } while (!data);
398
399 writel(0, ®s->ecc_test_ctrl);
400
401 return 1;
402 }
403
ast2600_sdrammc_cbr_test(struct dram_info * info)404 int ast2600_sdrammc_cbr_test(struct dram_info *info)
405 {
406 struct ast2600_sdrammc_regs *regs = info->regs;
407 u32 i;
408
409 clrsetbits_le32(®s->test_addr, GENMASK(30, 4), 0x7ffff0);
410
411 /* single */
412 for (i = 0; i < 8; i++) {
413 if (!ast2600_sdrammc_dg_test(info, i, 0))
414 return (0);
415 }
416
417 /* burst */
418 for (i = 0; i < 8; i++) {
419 if (!ast2600_sdrammc_dg_test(info, i, i))
420 return (0);
421 }
422
423 return(1);
424 }
425
ast2600_sdrammc_test(struct dram_info * info)426 static int ast2600_sdrammc_test(struct dram_info *info)
427 {
428 struct ast2600_sdrammc_regs *regs = info->regs;
429
430 u32 pass_cnt = 0;
431 u32 fail_cnt = 0;
432 u32 target_cnt = 2;
433 u32 test_cnt = 0;
434 u32 pattern;
435 u32 i = 0;
436 bool finish = false;
437
438 debug("sdram mc test:\n");
439 while (finish == false) {
440 pattern = as2600_sdrammc_test_pattern[i++];
441 i = i % MC_TEST_PATTERN_N;
442 debug(" pattern = %08x : ", pattern);
443 writel(pattern, ®s->test_init_val);
444
445 if (!ast2600_sdrammc_cbr_test(info)) {
446 debug("fail\n");
447 fail_cnt++;
448 } else {
449 debug("pass\n");
450 pass_cnt++;
451 }
452
453 if (++test_cnt == target_cnt) {
454 finish = true;
455 }
456 }
457 debug("statistics: pass/fail/total:%d/%d/%d\n", pass_cnt, fail_cnt,
458 target_cnt);
459 return fail_cnt;
460 }
461 #endif
462 /**
463 * scu500[14:13]
464 * 2b'00: VGA memory size = 16MB
465 * 2b'01: VGA memory size = 16MB
466 * 2b'10: VGA memory size = 32MB
467 * 2b'11: VGA memory size = 64MB
468 *
469 * mcr04[3:2]
470 * 2b'00: VGA memory size = 8MB
471 * 2b'01: VGA memory size = 16MB
472 * 2b'10: VGA memory size = 32MB
473 * 2b'11: VGA memory size = 64MB
474 */
ast2600_sdrammc_get_vga_mem_size(struct dram_info * info)475 static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info)
476 {
477 u32 vga_hwconf;
478 size_t vga_mem_size_base = 8 * 1024 * 1024;
479
480 vga_hwconf = (readl(info->scu + AST_SCU_HW_STRAP) &
481 SCU_HWSTRAP_VGAMEM_MASK) >>
482 SCU_HWSTRAP_VGAMEM_SHIFT;
483
484 if (vga_hwconf == 0) {
485 vga_hwconf = 1;
486 writel(vga_hwconf << SCU_HWSTRAP_VGAMEM_SHIFT,
487 info->scu + AST_SCU_HW_STRAP);
488 }
489
490 clrsetbits_le32(&info->regs->config, SDRAM_CONF_VGA_SIZE_MASK,
491 ((vga_hwconf << SDRAM_CONF_VGA_SIZE_SHIFT) &
492 SDRAM_CONF_VGA_SIZE_MASK));
493
494 /* no need to reserve VGA memory if efuse[VGA disable] is set */
495 if (readl(info->scu + AST_SCU_EFUSE_DATA) & SCU_EFUSE_DATA_VGA_DIS_MASK)
496 return 0;
497
498 return vga_mem_size_base << vga_hwconf;
499 }
500 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM)
ast2600_sdrammc_fpga_set_pll(struct dram_info * info)501 static void ast2600_sdrammc_fpga_set_pll(struct dram_info *info)
502 {
503 u32 data;
504 u32 scu_base = (u32)info->scu;
505
506 writel(0x00000303, scu_base + AST_SCU_FPGA_PLL);
507
508 do {
509 data = readl(scu_base + AST_SCU_FPGA_STATUS);
510 } while (!(data & 0x100));
511
512 writel(0x00000103, scu_base + AST_SCU_FPGA_PLL);
513 }
514
ast2600_sdrammc_search_read_window(struct dram_info * info)515 static int ast2600_sdrammc_search_read_window(struct dram_info *info)
516 {
517 u32 pll, pll_min, pll_max, dat1, offset;
518 u32 win = 0x03, gwin = 0, gwinsize = 0;
519 u32 phy_setting = (u32)info->phy_setting;
520
521 #ifdef CONFIG_ASPEED_PALLADIUM
522 writel(0xc, phy_setting + 0x0000);
523 return 1;
524 #endif
525 writel(SEARCH_RDWIN_PTRN_0, SEARCH_RDWIN_ANCHOR_0);
526 writel(SEARCH_RDWIN_PTRN_1, SEARCH_RDWIN_ANCHOR_1);
527
528 while (gwin == 0) {
529 while (!(win & 0x80)) {
530 debug("Window = 0x%X\n", win);
531 writel(win, phy_setting + 0x0000);
532
533 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
534 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
535 while (dat1 == SEARCH_RDWIN_PTRN_SUM) {
536 ast2600_sdrammc_fpga_set_pll(info);
537 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
538 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
539 }
540
541 pll_min = 0xfff;
542 pll_max = 0x0;
543 pll = 0;
544 while (pll_max > 0 || pll < 256) {
545 ast2600_sdrammc_fpga_set_pll(info);
546 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
547 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
548 if (dat1 == SEARCH_RDWIN_PTRN_SUM) {
549 if (pll_min > pll)
550 pll_min = pll;
551
552 if (pll_max < pll)
553 pll_max = pll;
554
555 debug("%3d_(%3d:%3d)\n", pll, pll_min,
556 pll_max);
557 } else if (pll_max > 0) {
558 pll_min = pll_max - pll_min;
559 if (gwinsize < pll_min) {
560 gwin = win;
561 gwinsize = pll_min;
562 }
563 break;
564 }
565 pll += 1;
566 }
567
568 if (gwin != 0 && pll_max == 0)
569 break;
570
571 win = win << 1;
572 }
573 if (gwin == 0)
574 win = 0x7;
575 }
576 debug("Set PLL Read Gating Window = %x\n", gwin);
577 writel(gwin, phy_setting + 0x0000);
578
579 debug("PLL Read Window training\n");
580 pll_min = 0xfff;
581 pll_max = 0x0;
582
583 debug("Search Window Start\n");
584 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
585 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
586 while (dat1 == SEARCH_RDWIN_PTRN_SUM) {
587 ast2600_sdrammc_fpga_set_pll(info);
588 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
589 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
590 }
591
592 debug("Search Window Margin\n");
593 pll = 0;
594 while (pll_max > 0 || pll < 256) {
595 ast2600_sdrammc_fpga_set_pll(info);
596 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
597 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
598 if (dat1 == SEARCH_RDWIN_PTRN_SUM) {
599 if (pll_min > pll)
600 pll_min = pll;
601
602 if (pll_max < pll)
603 pll_max = pll;
604
605 debug("%3d_(%3d:%3d)\n", pll, pll_min, pll_max);
606 } else if (pll_max > 0 && (pll_max - pll_min) > 20) {
607 break;
608 } else if (pll_max > 0) {
609 pll_min = 0xfff;
610 pll_max = 0x0;
611 }
612 pll += 1;
613 }
614 if (pll_min < pll_max) {
615 debug("PLL Read window = %d\n", (pll_max - pll_min));
616 offset = (pll_max - pll_min) >> 1;
617 pll_min = 0xfff;
618 pll = 0;
619 while (pll < (pll_min + offset)) {
620 ast2600_sdrammc_fpga_set_pll(info);
621 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
622 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
623 if (dat1 == SEARCH_RDWIN_PTRN_SUM) {
624 if (pll_min > pll) {
625 pll_min = pll;
626 }
627 debug("%d\n", pll);
628 } else {
629 pll_min = 0xfff;
630 pll_max = 0x0;
631 }
632 pll += 1;
633 }
634 return (1);
635 } else {
636 debug("PLL Read window training fail\n");
637 return 0;
638 }
639 }
640 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \
641 defined(CONFIG_ASPEED_PALLADIUM)" */
642
643 /*
644 * Find out RAM size and save it in dram_info
645 *
646 * The procedure is taken from Aspeed SDK
647 */
ast2600_sdrammc_calc_size(struct dram_info * info)648 static void ast2600_sdrammc_calc_size(struct dram_info *info)
649 {
650 /* The controller supports 256/512/1024/2048 MB ram */
651 size_t ram_size = SDRAM_MIN_SIZE;
652 const int write_test_offset = 0x100000;
653 u32 test_pattern = 0xdeadbeef;
654 u32 cap_param = SDRAM_CONF_CAP_2048M;
655 u32 refresh_timing_param = DDR4_TRFC;
656 const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset;
657
658 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
659 ram_size >>= 1) {
660 writel(test_pattern, write_addr_base + (ram_size >> 1));
661 test_pattern = (test_pattern >> 4) | (test_pattern << 28);
662 }
663
664 /* One last write to overwrite all wrapped values */
665 writel(test_pattern, write_addr_base);
666
667 /* Reset the pattern and see which value was really written */
668 test_pattern = 0xdeadbeef;
669 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
670 ram_size >>= 1) {
671 if (readl(write_addr_base + (ram_size >> 1)) == test_pattern)
672 break;
673
674 --cap_param;
675 refresh_timing_param >>= 8;
676 test_pattern = (test_pattern >> 4) | (test_pattern << 28);
677 }
678
679 clrsetbits_le32(&info->regs->ac_timing[1],
680 (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT),
681 ((refresh_timing_param & SDRAM_AC_TRFC_MASK)
682 << SDRAM_AC_TRFC_SHIFT));
683
684 info->info.base = CONFIG_SYS_SDRAM_BASE;
685 info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info) - CONFIG_ASPEED_SSP_RERV_MEM;
686
687 clrsetbits_le32(
688 &info->regs->config, SDRAM_CONF_CAP_MASK,
689 ((cap_param << SDRAM_CONF_CAP_SHIFT) & SDRAM_CONF_CAP_MASK));
690 }
691
ast2600_sdrammc_init_ddr4(struct dram_info * info)692 static int ast2600_sdrammc_init_ddr4(struct dram_info *info)
693 {
694 const u32 power_ctrl = MCR34_CKE_EN | MCR34_AUTOPWRDN_EN |
695 MCR34_MREQ_BYPASS_DIS | MCR34_RESETN_DIS |
696 MCR34_ODT_EN | MCR34_ODT_AUTO_ON |
697 (0x1 << MCR34_ODT_EXT_SHIFT);
698
699 /* init SDRAM-PHY only on real chip */
700 ast2600_sdramphy_init(ast2600_sdramphy_config, info);
701 writel((MCR34_CKE_EN | MCR34_MREQI_DIS | MCR34_RESETN_DIS),
702 &info->regs->power_ctrl);
703 udelay(5);
704 ast2600_sdramphy_kick_training(info);
705 udelay(500);
706 writel(SDRAM_RESET_DLL_ZQCL_EN, &info->regs->refresh_timing);
707
708 writel(MCR30_SET_MR(3), &info->regs->mode_setting_control);
709 writel(MCR30_SET_MR(6), &info->regs->mode_setting_control);
710 writel(MCR30_SET_MR(5), &info->regs->mode_setting_control);
711 writel(MCR30_SET_MR(4), &info->regs->mode_setting_control);
712 writel(MCR30_SET_MR(2), &info->regs->mode_setting_control);
713 writel(MCR30_SET_MR(1), &info->regs->mode_setting_control);
714 writel(MCR30_SET_MR(0) | MCR30_RESET_DLL_DELAY_EN,
715 &info->regs->mode_setting_control);
716
717 writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN |
718 (DDR4_TRFI << SDRAM_REFRESH_PERIOD_SHIFT),
719 &info->regs->refresh_timing);
720
721 /* wait self-refresh idle */
722 while (readl(&info->regs->power_ctrl) & MCR34_SELF_REFRESH_STATUS_MASK)
723 ;
724
725 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM)
726 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN |
727 SDRAM_REFRESH_ZQCS_EN |
728 (DDR4_TRFI << SDRAM_REFRESH_PERIOD_SHIFT) |
729 (0x4000 << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT),
730 &info->regs->refresh_timing);
731 #else
732 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN |
733 SDRAM_REFRESH_ZQCS_EN |
734 (DDR4_TRFI << SDRAM_REFRESH_PERIOD_SHIFT) |
735 (0x42aa << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT),
736 &info->regs->refresh_timing);
737 #endif
738
739 writel(power_ctrl, &info->regs->power_ctrl);
740 udelay(500);
741
742 #if defined(CONFIG_FPGA_ASPEED)
743 /* toggle Vref training */
744 setbits_le32(&info->regs->mr6_mode_setting, 0x80);
745 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6),
746 &info->regs->mode_setting_control);
747 clrbits_le32(&info->regs->mr6_mode_setting, 0x80);
748 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6),
749 &info->regs->mode_setting_control);
750 #endif
751 return 0;
752 }
753
ast2600_sdrammc_unlock(struct dram_info * info)754 static void ast2600_sdrammc_unlock(struct dram_info *info)
755 {
756 writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key);
757 while (!readl(&info->regs->protection_key))
758 ;
759 }
760
ast2600_sdrammc_lock(struct dram_info * info)761 static void ast2600_sdrammc_lock(struct dram_info *info)
762 {
763 writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key);
764 while (readl(&info->regs->protection_key))
765 ;
766 }
767
ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs * regs)768 static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs)
769 {
770 int i;
771 u32 reg;
772
773 writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, ®s->power_ctrl);
774 writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key);
775 /* [6:0] : Group 1 request queued number = 16
776 * [14:8] : Group 2 request queued number = 16
777 * [20:16] : R/W max-grant count for RQ output arbitration = 16
778 */
779 writel(0x101010, ®s->arbitration_ctrl);
780 /* Request Queued Limitation for REQ8/9 USB1/2 */
781 writel(0x0FFF3CEF, ®s->req_limit_mask);
782
783 for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i)
784 writel(ddr_max_grant_params[i], ®s->max_grant_len[i]);
785
786 writel(MCR50_RESET_ALL_INTR, ®s->intr_ctrl);
787
788 /* FIXME: the sample code does NOT match the datasheet */
789 writel(0x07FFFFFF, ®s->ecc_range_ctrl);
790
791 writel(0, ®s->ecc_test_ctrl);
792 writel(0x80000001, ®s->test_addr);
793 writel(0, ®s->test_fail_dq_bit);
794 writel(0, ®s->test_init_val);
795
796 writel(0xFFFFFFFF, ®s->req_input_ctrl);
797 writel(0x300, ®s->req_high_pri_ctrl);
798
799 udelay(600);
800
801 #ifdef CONFIG_ASPEED_DDR4_DUALX8
802 writel(0xa037, ®s->config);
803 #else
804 writel(0xa017, ®s->config);
805 #endif
806
807 /* load controller setting */
808 for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i)
809 writel(ddr4_ac_timing[i], ®s->ac_timing[i]);
810
811 /* update CL and WL */
812 reg = readl(®s->ac_timing[1]);
813 reg &= ~(SDRAM_WL_SETTING | SDRAM_CL_SETTING);
814 reg |= FIELD_PREP(SDRAM_WL_SETTING, CONFIG_WL - 5) |
815 FIELD_PREP(SDRAM_CL_SETTING, CONFIG_RL - 5);
816 writel(reg, ®s->ac_timing[1]);
817
818 writel(DDR4_MR01_MODE, ®s->mr01_mode_setting);
819 writel(DDR4_MR23_MODE, ®s->mr23_mode_setting);
820 writel(DDR4_MR45_MODE, ®s->mr45_mode_setting);
821 writel(DDR4_MR6_MODE, ®s->mr6_mode_setting);
822 }
823 /*
824 * Update size info according to the ECC HW setting
825 *
826 * Assume SDRAM has been initialized by SPL or the host. To get the RAM size, we
827 * don't need to calculate the ECC size again but read from MCR04 and derive the
828 * size from its value.
829 */
ast2600_sdrammc_update_size(struct dram_info * info)830 static void ast2600_sdrammc_update_size(struct dram_info *info)
831 {
832 struct ast2600_sdrammc_regs *regs = info->regs;
833 size_t hw_size;
834 size_t ram_size = SDRAM_MAX_SIZE;
835 u32 cap_param;
836
837 cap_param = (readl(&info->regs->config) & SDRAM_CONF_CAP_MASK) >> SDRAM_CONF_CAP_SHIFT;
838 switch (cap_param)
839 {
840 case SDRAM_CONF_CAP_2048M:
841 ram_size = 2048 * SDRAM_SIZE_1MB;
842 break;
843 case SDRAM_CONF_CAP_1024M:
844 ram_size = 1024 * SDRAM_SIZE_1MB;
845 break;
846 case SDRAM_CONF_CAP_512M:
847 ram_size = 512 * SDRAM_SIZE_1MB;
848 break;
849 case SDRAM_CONF_CAP_256M:
850 ram_size = 256 * SDRAM_SIZE_1MB;
851 break;
852 }
853
854 info->info.base = CONFIG_SYS_SDRAM_BASE;
855 info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info) - CONFIG_ASPEED_SSP_RERV_MEM;
856
857 if (0 == (readl(®s->config) & SDRAM_CONF_ECC_SETUP))
858 return;
859
860 hw_size = readl(®s->ecc_range_ctrl) & GENMASK(30, 20);
861 hw_size += (1 << 20);
862
863 info->info.size = hw_size;
864 }
865
ast2600_sdrammc_ecc_enable(struct dram_info * info,u32 conf_size_mb)866 static void ast2600_sdrammc_ecc_enable(struct dram_info *info, u32 conf_size_mb)
867 {
868 struct ast2600_sdrammc_regs *regs = info->regs;
869 size_t conf_size;
870 u32 reg;
871
872 conf_size = conf_size_mb * SDRAM_SIZE_1MB;
873 if (conf_size > info->info.size) {
874 printf("warning: ECC configured %dMB but actual size is %dMB\n",
875 conf_size_mb,
876 info->info.size / SDRAM_SIZE_1MB);
877 conf_size = info->info.size;
878 } else if (conf_size == 0) {
879 conf_size = info->info.size;
880 }
881
882 info->info.size = (((conf_size / 9) * 8) >> 20) << 20;
883 writel(((info->info.size >> 20) - 1) << 20, ®s->ecc_range_ctrl);
884 reg = readl(®s->config) | SDRAM_CONF_ECC_SETUP;
885 writel(reg, ®s->config);
886
887 writel(0, ®s->test_init_val);
888 writel(0x80000001, ®s->test_addr);
889 writel(0x221, ®s->ecc_test_ctrl);
890 while (0 == (readl(®s->ecc_test_ctrl) & BIT(12)))
891 ;
892 writel(0, ®s->ecc_test_ctrl);
893 writel(BIT(31), ®s->intr_ctrl);
894 writel(0, ®s->intr_ctrl);
895 }
896
ast2600_sdrammc_init_required(struct udevice * dev)897 static bool ast2600_sdrammc_init_required(struct udevice *dev)
898 {
899 struct dram_info *priv = dev_get_priv(dev);
900 struct ast2600_sdrammc_regs *regs = priv->regs;
901 bool ecc_requested;
902 bool ecc_enabled;
903 bool dram_ready;
904
905 ecc_requested = dev_read_bool(dev, "aspeed,ecc-enabled");
906 ecc_enabled = readl(®s->config) & SDRAM_CONF_ECC_SETUP;
907 dram_ready = readl(priv->scu + AST_SCU_HANDSHAKE) & SCU_SDRAM_INIT_READY_MASK;
908
909 debug("ECC: requested %d enabled %d dram ready %d\n",
910 ecc_requested, ecc_enabled, dram_ready);
911
912 if (!dram_ready)
913 return true;
914
915 if (ecc_requested != ecc_enabled)
916 return true;
917
918 return false;
919 }
920
ast2600_sdrammc_probe(struct udevice * dev)921 static int ast2600_sdrammc_probe(struct udevice *dev)
922 {
923 struct dram_info *priv = (struct dram_info *)dev_get_priv(dev);
924 struct ast2600_sdrammc_regs *regs = priv->regs;
925 struct udevice *clk_dev;
926 int ret;
927 volatile uint32_t reg;
928
929 /* find SCU base address from clock device */
930 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu),
931 &clk_dev);
932 if (ret) {
933 debug("clock device not defined\n");
934 return ret;
935 }
936
937 priv->scu = devfdt_get_addr_ptr(clk_dev);
938 if (IS_ERR(priv->scu)) {
939 debug("%s(): can't get SCU\n", __func__);
940 return PTR_ERR(priv->scu);
941 }
942
943 if (!ast2600_sdrammc_init_required(dev)) {
944 printf("already initialized, ");
945 setbits_le32(priv->scu + AST_SCU_HANDSHAKE, SCU_HANDSHAKE_MASK);
946 ast2600_sdrammc_update_size(priv);
947 return 0;
948 }
949
950 #ifdef AST2600_SDRAMMC_MANUAL_CLK
951 reg = readl(priv->scu + AST_SCU_MPLL);
952 reg &= ~(BIT(24) | GENMASK(22, 0));
953 reg |= (BIT(25) | SCU_MPLL_FREQ_CFG);
954 writel(reg, priv->scu + AST_SCU_MPLL);
955 writel(SCU_MPLL_EXT_CFG, priv->scu + AST_SCU_MPLL_EXT);
956 udelay(100);
957 reg &= ~BIT(25);
958 writel(reg, priv->scu + AST_SCU_MPLL);
959 while (0 == (readl(priv->scu + AST_SCU_MPLL_EXT) & BIT(31)))
960 ;
961 #else
962 ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
963 if (ret) {
964 debug("DDR:No CLK\n");
965 return ret;
966 }
967 clk_set_rate(&priv->ddr_clk, priv->clock_rate);
968 #endif
969
970 #if 0
971 /* FIXME: enable the following code if reset-driver is ready */
972 struct reset_ctl reset_ctl;
973 ret = reset_get_by_index(dev, 0, &reset_ctl);
974 if (ret) {
975 debug("%s(): Failed to get reset signal\n", __func__);
976 return ret;
977 }
978
979 ret = reset_assert(&reset_ctl);
980 if (ret) {
981 debug("%s(): SDRAM reset failed: %u\n", __func__, ret);
982 return ret;
983 }
984 #endif
985
986 ast2600_sdrammc_unlock(priv);
987 ast2600_sdrammc_common_init(regs);
988 L_ast2600_sdramphy_train:
989 ast2600_sdrammc_init_ddr4(priv);
990
991 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM)
992 ast2600_sdrammc_search_read_window(priv);
993 #endif
994
995 ret = ast2600_sdramphy_check_status(priv);
996 if (ret) {
997 printf("DDR4 PHY training fail, retrain\n");
998 goto L_ast2600_sdramphy_train;
999 }
1000
1001 ast2600_sdrammc_calc_size(priv);
1002
1003 #ifndef CONFIG_ASPEED_BYPASS_SELFTEST
1004 ret = ast2600_sdrammc_test(priv);
1005 if (ret) {
1006 printf("%s: DDR4 init fail\n", __func__);
1007 return -EINVAL;
1008 }
1009 #endif
1010
1011 if (dev_read_bool(dev, "aspeed,ecc-enabled")) {
1012 u32 ecc_size;
1013
1014 ecc_size = dev_read_u32_default(dev, "aspeed,ecc-size-mb", 0);
1015 ast2600_sdrammc_ecc_enable(priv, ecc_size);
1016 }
1017
1018 setbits_le32(priv->scu + AST_SCU_HANDSHAKE, SCU_HANDSHAKE_MASK);
1019 clrbits_le32(®s->intr_ctrl, MCR50_RESET_ALL_INTR);
1020 ast2600_sdrammc_lock(priv);
1021 return 0;
1022 }
1023
ast2600_sdrammc_ofdata_to_platdata(struct udevice * dev)1024 static int ast2600_sdrammc_ofdata_to_platdata(struct udevice *dev)
1025 {
1026 struct dram_info *priv = dev_get_priv(dev);
1027
1028 priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0);
1029 priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1);
1030 priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2);
1031
1032 priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
1033 "clock-frequency", 0);
1034 if (!priv->clock_rate) {
1035 debug("DDR Clock Rate not defined\n");
1036 return -EINVAL;
1037 }
1038
1039 return 0;
1040 }
1041
ast2600_sdrammc_get_info(struct udevice * dev,struct ram_info * info)1042 static int ast2600_sdrammc_get_info(struct udevice *dev, struct ram_info *info)
1043 {
1044 struct dram_info *priv = dev_get_priv(dev);
1045
1046 *info = priv->info;
1047
1048 return 0;
1049 }
1050
1051 static struct ram_ops ast2600_sdrammc_ops = {
1052 .get_info = ast2600_sdrammc_get_info,
1053 };
1054
1055 static const struct udevice_id ast2600_sdrammc_ids[] = {
1056 { .compatible = "aspeed,ast2600-sdrammc" },
1057 { }
1058 };
1059
1060 U_BOOT_DRIVER(sdrammc_ast2600) = {
1061 .name = "aspeed_ast2600_sdrammc",
1062 .id = UCLASS_RAM,
1063 .of_match = ast2600_sdrammc_ids,
1064 .ops = &ast2600_sdrammc_ops,
1065 .ofdata_to_platdata = ast2600_sdrammc_ofdata_to_platdata,
1066 .probe = ast2600_sdrammc_probe,
1067 .priv_auto_alloc_size = sizeof(struct dram_info),
1068 };
1069