1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2012-2020 ASPEED Technology Inc.
4 *
5 * Copyright 2016 Google, Inc
6 */
7
8 #include <common.h>
9 #include <clk.h>
10 #include <dm.h>
11 #include <errno.h>
12 #include <ram.h>
13 #include <regmap.h>
14 #include <reset.h>
15 #include <asm/io.h>
16 #include <asm/arch/scu_ast2500.h>
17 #include <asm/arch/sdram_ast2500.h>
18 #include <linux/err.h>
19 #include <linux/kernel.h>
20 #include <dt-bindings/clock/ast2500-clock.h>
21
22 /* in order to speed up DRAM init time, write pre-defined values to registers
23 * directly */
24 #define AST2500_SDRAMMC_MANUAL_CLK
25
26 /* bit-field of m_pll_param */
27 #define SCU_MPLL_FREQ_MASK (SCU_MPLL_DENUM_MASK | SCU_MPLL_NUM_MASK | SCU_MPLL_POST_MASK)
28 #define SCU_MPLL_FREQ_400M 0x93002400
29 #define SCU_MPLL_FREQ_360M 0x930023A0
30 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_360M
31
32 #define SCU_MPLL_TURN_OFF BIT(19)
33 #define SCU_MPLL_BYPASS BIT(20)
34 #define SCU_MPLL_RESET BIT(21)
35
36 /* These configuration parameters are taken from Aspeed SDK */
37 #define DDR4_MR46_MODE 0x08000000
38 #define DDR4_MR5_MODE 0x400
39 #define DDR4_MR13_MODE 0x101
40 #define DDR4_MR02_MODE 0x410
41 #define DDR4_TRFC 0x45457188
42
43 #define PHY_CFG_SIZE 15
44
45 static const u32 ddr4_ac_timing[3] = {0x63604e37, 0xe97afa99, 0x00019000};
46 static const struct {
47 u32 index[PHY_CFG_SIZE];
48 u32 value[PHY_CFG_SIZE];
49 } ddr4_phy_config = {
50 .index = {0, 1, 3, 4, 5, 56, 57, 58, 59, 60, 61, 62, 36, 49, 50},
51 .value = {
52 0x42492aae, 0x09002000, 0x55e00b0b, 0x20000000, 0x24,
53 0x03002900, 0x0e0000a0, 0x000e001c, 0x35b8c106, 0x08080607,
54 0x9b000900, 0x0e400a00, 0x00100008, 0x3c183c3c, 0x00631e0e,
55 },
56 };
57
58 /* supported SDRAM size */
59 #define SDRAM_SIZE_1KB (1024U)
60 #define SDRAM_SIZE_1MB (SDRAM_SIZE_1KB * SDRAM_SIZE_1KB)
61 #define SDRAM_MIN_SIZE (128 * SDRAM_SIZE_1MB)
62 #define SDRAM_MAX_SIZE (1024 * SDRAM_SIZE_1MB)
63
64 DECLARE_GLOBAL_DATA_PTR;
65
66 /*
67 * Bandwidth configuration parameters for different SDRAM requests.
68 * These are hardcoded settings taken from Aspeed SDK.
69 */
70 static const u32 ddr_max_grant_params[4] = {
71 0x88448844, 0x24422288, 0x22222222, 0x22222222
72 };
73
74 /*
75 * These registers are not documented by Aspeed at all.
76 * All writes and reads are taken pretty much as is from SDK.
77 */
78 struct ast2500_ddr_phy {
79 u32 phy[117];
80 };
81
82 struct dram_info {
83 struct ram_info info;
84 struct clk ddr_clk;
85 struct ast2500_sdrammc_regs *regs;
86 struct ast2500_scu *scu;
87 struct ast2500_ddr_phy *phy;
88 ulong clock_rate;
89 };
90
ast2500_sdrammc_init_phy(struct ast2500_ddr_phy * phy)91 static int ast2500_sdrammc_init_phy(struct ast2500_ddr_phy *phy)
92 {
93 writel(0, &phy->phy[2]);
94 writel(0, &phy->phy[6]);
95 writel(0, &phy->phy[8]);
96 writel(0, &phy->phy[10]);
97 writel(0, &phy->phy[12]);
98 writel(0, &phy->phy[42]);
99 writel(0, &phy->phy[44]);
100
101 writel(0x86000000, &phy->phy[16]);
102 writel(0x00008600, &phy->phy[17]);
103 writel(0x80000000, &phy->phy[18]);
104 writel(0x80808080, &phy->phy[19]);
105
106 return 0;
107 }
108
ast2500_ddr_phy_init_process(struct dram_info * info)109 static void ast2500_ddr_phy_init_process(struct dram_info *info)
110 {
111 struct ast2500_sdrammc_regs *regs = info->regs;
112
113 writel(0, ®s->phy_ctrl[0]);
114 writel(0x4040, &info->phy->phy[51]);
115
116 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]);
117 while ((readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT))
118 ;
119 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_AUTO_UPDATE,
120 ®s->phy_ctrl[0]);
121 }
122
ast2500_sdrammc_set_vref(struct dram_info * info,u32 vref)123 static void ast2500_sdrammc_set_vref(struct dram_info *info, u32 vref)
124 {
125 writel(0, &info->regs->phy_ctrl[0]);
126 writel((vref << 8) | 0x6, &info->phy->phy[48]);
127 ast2500_ddr_phy_init_process(info);
128 }
129
ast2500_ddr_cbr_test(struct dram_info * info)130 static int ast2500_ddr_cbr_test(struct dram_info *info)
131 {
132 struct ast2500_sdrammc_regs *regs = info->regs;
133 int i;
134 const u32 test_params = SDRAM_TEST_EN
135 | SDRAM_TEST_ERRSTOP
136 | SDRAM_TEST_TWO_MODES;
137 int ret = 0;
138
139 writel((1 << SDRAM_REFRESH_CYCLES_SHIFT) |
140 (0x5c << SDRAM_REFRESH_PERIOD_SHIFT), ®s->refresh_timing);
141 writel((0xfff << SDRAM_TEST_LEN_SHIFT), ®s->test_addr);
142 writel(0xff00ff00, ®s->test_init_val);
143 writel(SDRAM_TEST_EN | (SDRAM_TEST_MODE_RW << SDRAM_TEST_MODE_SHIFT) |
144 SDRAM_TEST_ERRSTOP, ®s->ecc_test_ctrl);
145
146 while (!(readl(®s->ecc_test_ctrl) & SDRAM_TEST_DONE))
147 ;
148
149 if (readl(®s->ecc_test_ctrl) & SDRAM_TEST_FAIL) {
150 ret = -EIO;
151 } else {
152 for (i = 0; i <= SDRAM_TEST_GEN_MODE_MASK; ++i) {
153 writel((i << SDRAM_TEST_GEN_MODE_SHIFT) | test_params,
154 ®s->ecc_test_ctrl);
155 while (!(readl(®s->ecc_test_ctrl) & SDRAM_TEST_DONE))
156 ;
157 if (readl(®s->ecc_test_ctrl) & SDRAM_TEST_FAIL) {
158 ret = -EIO;
159 break;
160 }
161 }
162 }
163
164 writel(0, ®s->refresh_timing);
165 writel(0, ®s->ecc_test_ctrl);
166
167 return ret;
168 }
169
ast2500_sdrammc_ddr4_calibrate_vref(struct dram_info * info)170 static int ast2500_sdrammc_ddr4_calibrate_vref(struct dram_info *info)
171 {
172 int i;
173 int vref_min = 0xff;
174 int vref_max = 0;
175 int range_size = 0;
176
177 for (i = 1; i < 0x40; ++i) {
178 int res;
179
180 ast2500_sdrammc_set_vref(info, i);
181 res = ast2500_ddr_cbr_test(info);
182 if (res < 0) {
183 if (range_size > 0)
184 break;
185 } else {
186 ++range_size;
187 vref_min = min(vref_min, i);
188 vref_max = max(vref_max, i);
189 }
190 }
191
192 /* Pick average setting */
193 ast2500_sdrammc_set_vref(info, (vref_min + vref_max + 1) / 2);
194
195 return 0;
196 }
197
ast2500_sdrammc_get_vga_mem_size(struct dram_info * info)198 static size_t ast2500_sdrammc_get_vga_mem_size(struct dram_info *info)
199 {
200 size_t vga_mem_size_base = 8 * 1024 * 1024;
201 u32 vga_hwconf = (readl(&info->scu->hwstrap) & SCU_HWSTRAP_VGAMEM_MASK)
202 >> SCU_HWSTRAP_VGAMEM_SHIFT;
203
204 return vga_mem_size_base << vga_hwconf;
205 }
206
ast2500_sdrammc_update_size(struct dram_info * info)207 static void ast2500_sdrammc_update_size(struct dram_info *info)
208 {
209 struct ast2500_sdrammc_regs *regs = info->regs;
210 size_t hw_size;
211 size_t ram_size_tbl[4] = { 128 * SDRAM_SIZE_1MB,
212 256 * SDRAM_SIZE_1MB,
213 512 * SDRAM_SIZE_1MB,
214 1024 * SDRAM_SIZE_1MB };
215 size_t ram_size = SDRAM_MAX_SIZE;
216 u32 cap_param;
217
218 cap_param = (readl(&info->regs->config) & SDRAM_CONF_CAP_MASK) >> SDRAM_CONF_CAP_SHIFT;
219 ram_size = ram_size_tbl[cap_param];
220
221 info->info.base = CONFIG_SYS_SDRAM_BASE;
222 info->info.size = ram_size - ast2500_sdrammc_get_vga_mem_size(info);
223
224 if (0 == (readl(®s->config) & SDRAM_CONF_ECC_EN))
225 return;
226
227 hw_size = readl(®s->ecc_range_ctrl) & GENMASK(29, 20);
228 hw_size += (1 << 20);
229
230 info->info.size = hw_size;
231 }
232 /*
233 * Find out RAM size and save it in dram_info
234 *
235 * The procedure is taken from Aspeed SDK
236 */
ast2500_sdrammc_calc_size(struct dram_info * info)237 static void ast2500_sdrammc_calc_size(struct dram_info *info)
238 {
239 /* The controller supports 128/256/512/1024 MB ram */
240 size_t ram_size = SDRAM_MIN_SIZE;
241 const int write_test_offset = 0x100000;
242 u32 test_pattern = 0xdeadbeef;
243 u32 cap_param = SDRAM_CONF_CAP_1024M;
244 u32 refresh_timing_param = DDR4_TRFC;
245 const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset;
246
247 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
248 ram_size >>= 1) {
249 writel(test_pattern, write_addr_base + (ram_size >> 1));
250 test_pattern = (test_pattern >> 4) | (test_pattern << 28);
251 }
252
253 /* One last write to overwrite all wrapped values */
254 writel(test_pattern, write_addr_base);
255
256 /* Reset the pattern and see which value was really written */
257 test_pattern = 0xdeadbeef;
258 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
259 ram_size >>= 1) {
260 if (readl(write_addr_base + (ram_size >> 1)) == test_pattern)
261 break;
262
263 --cap_param;
264 refresh_timing_param >>= 8;
265 test_pattern = (test_pattern >> 4) | (test_pattern << 28);
266 }
267
268 clrsetbits_le32(&info->regs->ac_timing[1],
269 (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT),
270 ((refresh_timing_param & SDRAM_AC_TRFC_MASK)
271 << SDRAM_AC_TRFC_SHIFT));
272
273 info->info.base = CONFIG_SYS_SDRAM_BASE;
274 info->info.size = ram_size - ast2500_sdrammc_get_vga_mem_size(info);
275 clrsetbits_le32(&info->regs->config,
276 (SDRAM_CONF_CAP_MASK << SDRAM_CONF_CAP_SHIFT),
277 ((cap_param & SDRAM_CONF_CAP_MASK)
278 << SDRAM_CONF_CAP_SHIFT));
279 }
280
ast2500_sdrammc_ecc_enable(struct dram_info * info,u32 conf_size_mb)281 static void ast2500_sdrammc_ecc_enable(struct dram_info *info, u32 conf_size_mb)
282 {
283 struct ast2500_sdrammc_regs *regs = info->regs;
284 size_t conf_size;
285 u32 reg;
286
287 conf_size = conf_size_mb * SDRAM_SIZE_1MB;
288 if (conf_size > info->info.size) {
289 printf("warning: ECC configured %dMB but actual size is %dMB\n",
290 conf_size_mb,
291 info->info.size / SDRAM_SIZE_1MB);
292 conf_size = info->info.size;
293 } else if (conf_size == 0) {
294 conf_size = info->info.size;
295 }
296
297 info->info.size = (((conf_size / 9) * 8) >> 20) << 20;
298 writel(((info->info.size >> 20) - 1) << 20, ®s->ecc_range_ctrl);
299 reg = readl(®s->config) |
300 (SDRAM_CONF_ECC_EN | SDRAM_CONF_CACHE_ADDR_CTRL);
301 writel(reg, ®s->config);
302
303 writel(0, ®s->test_init_val);
304 writel(0, ®s->test_addr);
305 writel(0x221, ®s->ecc_test_ctrl);
306 while (0 == (readl(®s->ecc_test_ctrl) & BIT(12)))
307 ;
308 writel(0, ®s->ecc_test_ctrl);
309 writel(BIT(31), ®s->intr_ctrl);
310 writel(0, ®s->intr_ctrl);
311
312 writel(0x400, ®s->ecc_test_ctrl);
313 printf("ECC enable, ");
314 }
315
ast2500_sdrammc_init_ddr4(struct udevice * dev)316 static int ast2500_sdrammc_init_ddr4(struct udevice *dev)
317 {
318 struct dram_info *info = dev_get_priv(dev);
319 int i;
320 const u32 power_control = SDRAM_PCR_CKE_EN
321 | (1 << SDRAM_PCR_CKE_DELAY_SHIFT)
322 | (2 << SDRAM_PCR_TCKE_PW_SHIFT)
323 | SDRAM_PCR_RESETN_DIS
324 | SDRAM_PCR_RGAP_CTRL_EN | SDRAM_PCR_ODT_EN | SDRAM_PCR_ODT_EXT_EN;
325 const u32 conf = (SDRAM_CONF_CAP_1024M << SDRAM_CONF_CAP_SHIFT)
326 #ifdef CONFIG_DUALX8_RAM
327 | SDRAM_CONF_DUALX8
328 #endif
329 | SDRAM_CONF_SCRAMBLE | SDRAM_CONF_SCRAMBLE_PAT2 | SDRAM_CONF_DDR4;
330 int ret;
331
332 writel(conf, &info->regs->config);
333 for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i)
334 writel(ddr4_ac_timing[i], &info->regs->ac_timing[i]);
335
336 writel(DDR4_MR46_MODE, &info->regs->mr46_mode_setting);
337 writel(DDR4_MR5_MODE, &info->regs->mr5_mode_setting);
338 writel(DDR4_MR02_MODE, &info->regs->mr02_mode_setting);
339 writel(DDR4_MR13_MODE, &info->regs->mr13_mode_setting);
340
341 for (i = 0; i < PHY_CFG_SIZE; ++i) {
342 writel(ddr4_phy_config.value[i],
343 &info->phy->phy[ddr4_phy_config.index[i]]);
344 }
345
346 writel(power_control, &info->regs->power_control);
347
348 ast2500_ddr_phy_init_process(info);
349
350 ret = ast2500_sdrammc_ddr4_calibrate_vref(info);
351 if (ret < 0) {
352 debug("Vref calibration failed!\n");
353 return ret;
354 }
355
356 writel((1 << SDRAM_REFRESH_CYCLES_SHIFT)
357 | SDRAM_REFRESH_ZQCS_EN | (0x2f << SDRAM_REFRESH_PERIOD_SHIFT),
358 &info->regs->refresh_timing);
359
360 setbits_le32(&info->regs->power_control,
361 SDRAM_PCR_AUTOPWRDN_EN | SDRAM_PCR_ODT_AUTO_ON);
362
363 ast2500_sdrammc_calc_size(info);
364
365 setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_INIT_EN);
366 while (!(readl(&info->regs->config) & SDRAM_CONF_CACHE_INIT_DONE))
367 ;
368 setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_EN);
369
370 writel(SDRAM_MISC_DDR4_TREFRESH, &info->regs->misc_control);
371
372 if (dev_read_bool(dev, "aspeed,ecc-enabled")) {
373 u32 ecc_size;
374
375 ecc_size = dev_read_u32_default(dev, "aspeed,ecc-size-mb", 0);
376 ast2500_sdrammc_ecc_enable(info, ecc_size);
377 }
378
379 /* Enable all requests except video & display */
380 writel(SDRAM_REQ_USB20_EHCI1
381 | SDRAM_REQ_USB20_EHCI2
382 | SDRAM_REQ_CPU
383 | SDRAM_REQ_AHB2
384 | SDRAM_REQ_AHB
385 | SDRAM_REQ_MAC0
386 | SDRAM_REQ_MAC1
387 | SDRAM_REQ_PCIE
388 | SDRAM_REQ_XDMA
389 | SDRAM_REQ_ENCRYPTION
390 | SDRAM_REQ_VIDEO_FLAG
391 | SDRAM_REQ_VIDEO_LOW_PRI_WRITE
392 | SDRAM_REQ_2D_RW
393 | SDRAM_REQ_MEMCHECK, &info->regs->req_limit_mask);
394
395 return 0;
396 }
397
ast2500_sdrammc_unlock(struct dram_info * info)398 static void ast2500_sdrammc_unlock(struct dram_info *info)
399 {
400 writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key);
401 while (!readl(&info->regs->protection_key))
402 ;
403 }
404
ast2500_sdrammc_lock(struct dram_info * info)405 static void ast2500_sdrammc_lock(struct dram_info *info)
406 {
407 writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key);
408 while (readl(&info->regs->protection_key))
409 ;
410 }
411
ast2500_sdrammc_init_required(struct udevice * dev)412 static bool ast2500_sdrammc_init_required(struct udevice *dev)
413 {
414 struct dram_info *priv = dev_get_priv(dev);
415 struct ast2500_sdrammc_regs *regs = priv->regs;
416 bool ecc_requested;
417 bool ecc_enabled;
418 bool dram_ready;
419
420 ecc_requested = dev_read_bool(dev, "aspeed,ecc-enabled");
421 ecc_enabled = readl(®s->config) & SDRAM_CONF_ECC_EN;
422 dram_ready = readl(&priv->scu->vga_handshake[0]) & BIT(6);
423
424 if (!dram_ready)
425 return true;
426
427 if (ecc_requested != ecc_enabled)
428 return true;
429
430 return false;
431 }
432
ast2500_sdrammc_probe(struct udevice * dev)433 static int ast2500_sdrammc_probe(struct udevice *dev)
434 {
435 struct dram_info *priv = (struct dram_info *)dev_get_priv(dev);
436 struct ast2500_sdrammc_regs *regs = priv->regs;
437 struct udevice *clk_dev;
438 int i;
439 int ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
440 uint32_t reg;
441
442 if (ret) {
443 debug("DDR:No CLK\n");
444 return ret;
445 }
446
447 /* find the SCU base address from the aspeed clock device */
448 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu),
449 &clk_dev);
450 if (ret) {
451 debug("clock device not defined\n");
452 return ret;
453 }
454 priv->scu = devfdt_get_addr_ptr(clk_dev);
455
456 if (IS_ERR(priv->scu)) {
457 debug("%s(): can't get SCU\n", __func__);
458 return PTR_ERR(priv->scu);
459 }
460
461 if (!ast2500_sdrammc_init_required(dev)) {
462 ast2500_sdrammc_update_size(priv);
463
464 if (!(readl(&priv->regs->config) & SDRAM_CONF_CACHE_EN)) {
465 setbits_le32(&priv->regs->config,
466 SDRAM_CONF_CACHE_INIT_EN);
467 while (!(readl(&priv->regs->config) &
468 SDRAM_CONF_CACHE_INIT_DONE))
469 ;
470 setbits_le32(&priv->regs->config, SDRAM_CONF_CACHE_EN);
471 }
472
473 writel(SDRAM_MISC_DDR4_TREFRESH, &priv->regs->misc_control);
474 return 0;
475 }
476
477 #ifdef AST2500_SDRAMMC_MANUAL_CLK
478 reg = readl(&priv->scu->m_pll_param);
479 reg |= (SCU_MPLL_RESET | SCU_MPLL_TURN_OFF);
480 writel(reg, &priv->scu->m_pll_param);
481 reg &= ~(SCU_MPLL_RESET | SCU_MPLL_TURN_OFF| SCU_MPLL_FREQ_MASK);
482 reg |= SCU_MPLL_FREQ_CFG;
483 writel(reg, &priv->scu->m_pll_param);
484 #else
485 clk_set_rate(&priv->ddr_clk, priv->clock_rate);
486 #endif
487
488 ast2500_sdrammc_unlock(priv);
489
490 writel(SDRAM_PCR_MREQI_DIS | SDRAM_PCR_RESETN_DIS,
491 ®s->power_control);
492 writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key);
493
494 /* Mask all requests except CPU and AHB during PHY init */
495 writel(~(SDRAM_REQ_CPU | SDRAM_REQ_AHB), ®s->req_limit_mask);
496
497 for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i)
498 writel(ddr_max_grant_params[i], ®s->max_grant_len[i]);
499
500 setbits_le32(®s->intr_ctrl, SDRAM_ICR_RESET_ALL);
501
502 ast2500_sdrammc_init_phy(priv->phy);
503 if (readl(&priv->scu->hwstrap) & SCU_HWSTRAP_DDR4) {
504 ast2500_sdrammc_init_ddr4(dev);
505 } else {
506 debug("Unsupported DRAM3\n");
507 return -EINVAL;
508 }
509
510 clrbits_le32(®s->intr_ctrl, SDRAM_ICR_RESET_ALL);
511 ast2500_sdrammc_lock(priv);
512
513 setbits_le32(&priv->scu->vga_handshake[0], BIT(6) | BIT(7));
514
515 return 0;
516 }
517
ast2500_sdrammc_ofdata_to_platdata(struct udevice * dev)518 static int ast2500_sdrammc_ofdata_to_platdata(struct udevice *dev)
519 {
520 struct dram_info *priv = dev_get_priv(dev);
521
522 priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0);
523 priv->phy = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1);
524
525 priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
526 "clock-frequency", 0);
527 if (!priv->clock_rate) {
528 debug("DDR Clock Rate not defined\n");
529 return -EINVAL;
530 }
531
532 return 0;
533 }
534
ast2500_sdrammc_get_info(struct udevice * dev,struct ram_info * info)535 static int ast2500_sdrammc_get_info(struct udevice *dev, struct ram_info *info)
536 {
537 struct dram_info *priv = dev_get_priv(dev);
538
539 *info = priv->info;
540
541 return 0;
542 }
543
544 static struct ram_ops ast2500_sdrammc_ops = {
545 .get_info = ast2500_sdrammc_get_info,
546 };
547
548 static const struct udevice_id ast2500_sdrammc_ids[] = {
549 { .compatible = "aspeed,ast2500-sdrammc" },
550 { }
551 };
552
553 U_BOOT_DRIVER(sdrammc_ast2500) = {
554 .name = "aspeed_ast2500_sdrammc",
555 .id = UCLASS_RAM,
556 .of_match = ast2500_sdrammc_ids,
557 .ops = &ast2500_sdrammc_ops,
558 .ofdata_to_platdata = ast2500_sdrammc_ofdata_to_platdata,
559 .probe = ast2500_sdrammc_probe,
560 .priv_auto_alloc_size = sizeof(struct dram_info),
561 };
562