1 /*
2 * ASPEED SoC family
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 * Jeremy Kerr <jk@ozlabs.org>
6 *
7 * Copyright 2016 IBM Corp.
8 *
9 * This code is licensed under the GPL version 2 or later. See
10 * the COPYING file in the top-level directory.
11 */
12
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "hw/qdev-properties.h"
16 #include "hw/misc/unimp.h"
17 #include "hw/arm/aspeed_soc.h"
18 #include "hw/char/serial.h"
19
20
aspeed_soc_cpu_type(AspeedSoCClass * sc)21 const char *aspeed_soc_cpu_type(AspeedSoCClass *sc)
22 {
23 assert(sc->valid_cpu_types);
24 assert(sc->valid_cpu_types[0]);
25 assert(!sc->valid_cpu_types[1]);
26 return sc->valid_cpu_types[0];
27 }
28
aspeed_soc_get_irq(AspeedSoCState * s,int dev)29 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
30 {
31 return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
32 }
33
aspeed_soc_uart_realize(AspeedSoCState * s,Error ** errp)34 bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
35 {
36 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
37 SerialMM *smm;
38
39 for (int i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
40 smm = &s->uart[i];
41
42 /* Chardev property is set by the machine. */
43 qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
44 qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
45 qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
46 qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
47 if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
48 return false;
49 }
50
51 sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
52 aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
53 }
54
55 return true;
56 }
57
aspeed_soc_uart_set_chr(AspeedSoCState * s,int dev,Chardev * chr)58 void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
59 {
60 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
61 int uart_first = aspeed_uart_first(sc);
62 int uart_index = aspeed_uart_index(dev);
63 int i = uart_index - uart_first;
64
65 g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
66 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
67 }
68
69 /*
70 * SDMC should be realized first to get correct RAM size and max size
71 * values
72 */
aspeed_soc_dram_init(AspeedSoCState * s,Error ** errp)73 bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
74 {
75 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
76 ram_addr_t ram_size, max_ram_size;
77
78 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
79 &error_abort);
80 max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
81 &error_abort);
82
83 memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
84 max_ram_size);
85 memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
86
87 /*
88 * Add a memory region beyond the RAM region to let firmwares scan
89 * the address space with load/store and guess how much RAM the
90 * SoC has.
91 */
92 if (ram_size < max_ram_size) {
93 DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
94
95 qdev_prop_set_string(dev, "name", "ram-empty");
96 qdev_prop_set_uint64(dev, "size", max_ram_size - ram_size);
97 if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
98 return false;
99 }
100
101 memory_region_add_subregion_overlap(&s->dram_container, ram_size,
102 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
103 }
104
105 memory_region_add_subregion(s->memory,
106 sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
107 return true;
108 }
109
aspeed_mmio_map(AspeedSoCState * s,SysBusDevice * dev,int n,hwaddr addr)110 void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
111 {
112 memory_region_add_subregion(s->memory, addr,
113 sysbus_mmio_get_region(dev, n));
114 }
115
aspeed_mmio_map_unimplemented(AspeedSoCState * s,SysBusDevice * dev,const char * name,hwaddr addr,uint64_t size)116 void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
117 const char *name, hwaddr addr, uint64_t size)
118 {
119 qdev_prop_set_string(DEVICE(dev), "name", name);
120 qdev_prop_set_uint64(DEVICE(dev), "size", size);
121 sysbus_realize(dev, &error_abort);
122
123 memory_region_add_subregion_overlap(s->memory, addr,
124 sysbus_mmio_get_region(dev, 0), -1000);
125 }
126
aspeed_soc_realize(DeviceState * dev,Error ** errp)127 static void aspeed_soc_realize(DeviceState *dev, Error **errp)
128 {
129 AspeedSoCState *s = ASPEED_SOC(dev);
130
131 if (!s->memory) {
132 error_setg(errp, "'memory' link is not set");
133 return;
134 }
135 }
136
aspeed_soc_boot_from_emmc(AspeedSoCState * s)137 static bool aspeed_soc_boot_from_emmc(AspeedSoCState *s)
138 {
139 return false;
140 }
141
142 static Property aspeed_soc_properties[] = {
143 DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
144 MemoryRegion *),
145 DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
146 MemoryRegion *),
147 DEFINE_PROP_END_OF_LIST(),
148 };
149
aspeed_soc_class_init(ObjectClass * oc,void * data)150 static void aspeed_soc_class_init(ObjectClass *oc, void *data)
151 {
152 DeviceClass *dc = DEVICE_CLASS(oc);
153 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
154
155 dc->realize = aspeed_soc_realize;
156 device_class_set_props(dc, aspeed_soc_properties);
157 sc->boot_from_emmc = aspeed_soc_boot_from_emmc;
158 }
159
160 static const TypeInfo aspeed_soc_types[] = {
161 {
162 .name = TYPE_ASPEED_SOC,
163 .parent = TYPE_DEVICE,
164 .instance_size = sizeof(AspeedSoCState),
165 .class_size = sizeof(AspeedSoCClass),
166 .class_init = aspeed_soc_class_init,
167 .abstract = true,
168 },
169 };
170
171 DEFINE_TYPES(aspeed_soc_types)
172