1 /*
2 * ASPEED SoC family
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 * Jeremy Kerr <jk@ozlabs.org>
6 *
7 * Copyright 2016 IBM Corp.
8 *
9 * This code is licensed under the GPL version 2 or later. See
10 * the COPYING file in the top-level directory.
11 */
12
13 #include "qemu/osdep.h"
14 #include "qemu/units.h"
15 #include "qapi/error.h"
16 #include "hw/misc/unimp.h"
17 #include "hw/arm/aspeed_soc.h"
18 #include "hw/char/serial-mm.h"
19 #include "qemu/module.h"
20 #include "qemu/error-report.h"
21 #include "hw/i2c/aspeed_i2c.h"
22 #include "net/net.h"
23 #include "sysemu/sysemu.h"
24 #include "target/arm/cpu-qom.h"
25
26 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
27
28 static const hwaddr aspeed_soc_ast2400_memmap[] = {
29 [ASPEED_DEV_SPI_BOOT] = 0x00000000,
30 [ASPEED_DEV_IOMEM] = 0x1E600000,
31 [ASPEED_DEV_FMC] = 0x1E620000,
32 [ASPEED_DEV_SPI1] = 0x1E630000,
33 [ASPEED_DEV_EHCI1] = 0x1E6A1000,
34 [ASPEED_DEV_UHCI] = 0x1E6B0000,
35 [ASPEED_DEV_VIC] = 0x1E6C0000,
36 [ASPEED_DEV_SDMC] = 0x1E6E0000,
37 [ASPEED_DEV_SCU] = 0x1E6E2000,
38 [ASPEED_DEV_HACE] = 0x1E6E3000,
39 [ASPEED_DEV_GFX] = 0x1E6E6000,
40 [ASPEED_DEV_XDMA] = 0x1E6E7000,
41 [ASPEED_DEV_VIDEO] = 0x1E700000,
42 [ASPEED_DEV_ADC] = 0x1E6E9000,
43 [ASPEED_DEV_SRAM] = 0x1E720000,
44 [ASPEED_DEV_SDHCI] = 0x1E740000,
45 [ASPEED_DEV_GPIO] = 0x1E780000,
46 [ASPEED_DEV_RTC] = 0x1E781000,
47 [ASPEED_DEV_TIMER1] = 0x1E782000,
48 [ASPEED_DEV_WDT] = 0x1E785000,
49 [ASPEED_DEV_PWM] = 0x1E786000,
50 [ASPEED_DEV_LPC] = 0x1E789000,
51 [ASPEED_DEV_IBT] = 0x1E789140,
52 [ASPEED_DEV_I2C] = 0x1E78A000,
53 [ASPEED_DEV_PECI] = 0x1E78B000,
54 [ASPEED_DEV_ETH1] = 0x1E660000,
55 [ASPEED_DEV_ETH2] = 0x1E680000,
56 [ASPEED_DEV_UART1] = 0x1E783000,
57 [ASPEED_DEV_UART2] = 0x1E78D000,
58 [ASPEED_DEV_UART3] = 0x1E78E000,
59 [ASPEED_DEV_UART4] = 0x1E78F000,
60 [ASPEED_DEV_UART5] = 0x1E784000,
61 [ASPEED_DEV_VUART] = 0x1E787000,
62 [ASPEED_DEV_SDRAM] = 0x40000000,
63 };
64
65 static const hwaddr aspeed_soc_ast2500_memmap[] = {
66 [ASPEED_DEV_SPI_BOOT] = 0x00000000,
67 [ASPEED_DEV_IOMEM] = 0x1E600000,
68 [ASPEED_DEV_FMC] = 0x1E620000,
69 [ASPEED_DEV_SPI1] = 0x1E630000,
70 [ASPEED_DEV_SPI2] = 0x1E631000,
71 [ASPEED_DEV_EHCI1] = 0x1E6A1000,
72 [ASPEED_DEV_EHCI2] = 0x1E6A3000,
73 [ASPEED_DEV_UHCI] = 0x1E6B0000,
74 [ASPEED_DEV_VIC] = 0x1E6C0000,
75 [ASPEED_DEV_SDMC] = 0x1E6E0000,
76 [ASPEED_DEV_SCU] = 0x1E6E2000,
77 [ASPEED_DEV_HACE] = 0x1E6E3000,
78 [ASPEED_DEV_GFX] = 0x1E6E6000,
79 [ASPEED_DEV_XDMA] = 0x1E6E7000,
80 [ASPEED_DEV_ADC] = 0x1E6E9000,
81 [ASPEED_DEV_VIDEO] = 0x1E700000,
82 [ASPEED_DEV_SRAM] = 0x1E720000,
83 [ASPEED_DEV_SDHCI] = 0x1E740000,
84 [ASPEED_DEV_GPIO] = 0x1E780000,
85 [ASPEED_DEV_RTC] = 0x1E781000,
86 [ASPEED_DEV_TIMER1] = 0x1E782000,
87 [ASPEED_DEV_WDT] = 0x1E785000,
88 [ASPEED_DEV_PWM] = 0x1E786000,
89 [ASPEED_DEV_LPC] = 0x1E789000,
90 [ASPEED_DEV_IBT] = 0x1E789140,
91 [ASPEED_DEV_I2C] = 0x1E78A000,
92 [ASPEED_DEV_PECI] = 0x1E78B000,
93 [ASPEED_DEV_ETH1] = 0x1E660000,
94 [ASPEED_DEV_ETH2] = 0x1E680000,
95 [ASPEED_DEV_UART1] = 0x1E783000,
96 [ASPEED_DEV_UART2] = 0x1E78D000,
97 [ASPEED_DEV_UART3] = 0x1E78E000,
98 [ASPEED_DEV_UART4] = 0x1E78F000,
99 [ASPEED_DEV_UART5] = 0x1E784000,
100 [ASPEED_DEV_VUART] = 0x1E787000,
101 [ASPEED_DEV_SDRAM] = 0x80000000,
102 };
103
104 static const int aspeed_soc_ast2400_irqmap[] = {
105 [ASPEED_DEV_UART1] = 9,
106 [ASPEED_DEV_UART2] = 32,
107 [ASPEED_DEV_UART3] = 33,
108 [ASPEED_DEV_UART4] = 34,
109 [ASPEED_DEV_UART5] = 10,
110 [ASPEED_DEV_VUART] = 8,
111 [ASPEED_DEV_FMC] = 19,
112 [ASPEED_DEV_EHCI1] = 5,
113 [ASPEED_DEV_EHCI2] = 13,
114 [ASPEED_DEV_UHCI] = 14,
115 [ASPEED_DEV_SDMC] = 0,
116 [ASPEED_DEV_SCU] = 21,
117 [ASPEED_DEV_ADC] = 31,
118 [ASPEED_DEV_GFX] = 25,
119 [ASPEED_DEV_GPIO] = 20,
120 [ASPEED_DEV_RTC] = 22,
121 [ASPEED_DEV_TIMER1] = 16,
122 [ASPEED_DEV_TIMER2] = 17,
123 [ASPEED_DEV_TIMER3] = 18,
124 [ASPEED_DEV_TIMER4] = 35,
125 [ASPEED_DEV_TIMER5] = 36,
126 [ASPEED_DEV_TIMER6] = 37,
127 [ASPEED_DEV_TIMER7] = 38,
128 [ASPEED_DEV_TIMER8] = 39,
129 [ASPEED_DEV_WDT] = 27,
130 [ASPEED_DEV_PWM] = 28,
131 [ASPEED_DEV_LPC] = 8,
132 [ASPEED_DEV_I2C] = 12,
133 [ASPEED_DEV_PECI] = 15,
134 [ASPEED_DEV_ETH1] = 2,
135 [ASPEED_DEV_ETH2] = 3,
136 [ASPEED_DEV_XDMA] = 6,
137 [ASPEED_DEV_SDHCI] = 26,
138 [ASPEED_DEV_HACE] = 4,
139 };
140
141 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
142
aspeed_soc_ast2400_get_irq(AspeedSoCState * s,int dev)143 static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev)
144 {
145 Aspeed2400SoCState *a = ASPEED2400_SOC(s);
146 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
147
148 return qdev_get_gpio_in(DEVICE(&a->vic), sc->irqmap[dev]);
149 }
150
aspeed_ast2400_soc_init(Object * obj)151 static void aspeed_ast2400_soc_init(Object *obj)
152 {
153 Aspeed2400SoCState *a = ASPEED2400_SOC(obj);
154 AspeedSoCState *s = ASPEED_SOC(obj);
155 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
156 int i;
157 char socname[8];
158 char typename[64];
159
160 if (sscanf(sc->name, "%7s", socname) != 1) {
161 g_assert_not_reached();
162 }
163
164 for (i = 0; i < sc->num_cpus; i++) {
165 object_initialize_child(obj, "cpu[*]", &a->cpu[i],
166 aspeed_soc_cpu_type(sc));
167 }
168
169 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
170 object_initialize_child(obj, "scu", &s->scu, typename);
171 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
172 sc->silicon_rev);
173 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
174 "hw-strap1");
175 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
176 "hw-strap2");
177 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
178 "hw-prot-key");
179
180 object_initialize_child(obj, "vic", &a->vic, TYPE_ASPEED_VIC);
181
182 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
183
184 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
185 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
186
187 for (i = 0; i < sc->wdts_num; i++) {
188 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
189 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
190 }
191
192 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
193 object_initialize_child(obj, "adc", &s->adc, typename);
194
195 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
196 object_initialize_child(obj, "i2c", &s->i2c, typename);
197
198 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
199
200 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
201 object_initialize_child(obj, "fmc", &s->fmc, typename);
202
203 for (i = 0; i < sc->spis_num; i++) {
204 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
205 object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
206 }
207
208 for (i = 0; i < sc->ehcis_num; i++) {
209 object_initialize_child(obj, "ehci[*]", &s->ehci[i],
210 TYPE_PLATFORM_EHCI);
211 }
212
213 object_initialize_child(obj, "uhci", &s->uhci, TYPE_ASPEED_UHCI);
214
215 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
216 object_initialize_child(obj, "sdmc", &s->sdmc, typename);
217 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
218 "ram-size");
219
220 for (i = 0; i < sc->macs_num; i++) {
221 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
222 TYPE_FTGMAC100);
223 }
224
225 for (i = 0; i < sc->uarts_num; i++) {
226 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
227 }
228
229 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname);
230 object_initialize_child(obj, "xdma", &s->xdma, typename);
231
232 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
233 object_initialize_child(obj, "gpio", &s->gpio, typename);
234
235 snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname);
236 object_initialize_child(obj, "sdc", &s->sdhci, typename);
237
238 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort);
239
240 /* Init sd card slot class here so that they're under the correct parent */
241 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
242 object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i],
243 TYPE_SYSBUS_SDHCI);
244 }
245
246 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
247
248 object_initialize_child(obj, "ibt", &s->ibt, TYPE_ASPEED_IBT);
249
250 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
251 object_initialize_child(obj, "hace", &s->hace, typename);
252
253 object_initialize_child(obj, "gfx", &s->gfx, TYPE_ASPEED_GFX);
254
255 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
256 object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE);
257
258 object_initialize_child(obj, "pwm", &s->pwm, TYPE_ASPEED_PWM);
259 }
260
aspeed_ast2400_soc_realize(DeviceState * dev,Error ** errp)261 static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
262 {
263 int i;
264 Aspeed2400SoCState *a = ASPEED2400_SOC(dev);
265 AspeedSoCState *s = ASPEED_SOC(dev);
266 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
267 g_autofree char *sram_name = NULL;
268
269 /* Default boot region (SPI memory or ROMs) */
270 memory_region_init(&s->spi_boot_container, OBJECT(s),
271 "aspeed.spi_boot_container", 0x10000000);
272 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT],
273 &s->spi_boot_container);
274
275 /* IO space */
276 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io",
277 sc->memmap[ASPEED_DEV_IOMEM],
278 ASPEED_SOC_IOMEM_SIZE);
279
280 /* Video engine stub */
281 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video",
282 sc->memmap[ASPEED_DEV_VIDEO], 0x1000);
283
284 /* CPU */
285 for (i = 0; i < sc->num_cpus; i++) {
286 object_property_set_link(OBJECT(&a->cpu[i]), "memory",
287 OBJECT(s->memory), &error_abort);
288 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
289 return;
290 }
291 }
292
293 /* SRAM */
294 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
295 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size,
296 errp)) {
297 return;
298 }
299 memory_region_add_subregion(s->memory,
300 sc->memmap[ASPEED_DEV_SRAM], &s->sram);
301
302 /* SCU */
303 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
304 return;
305 }
306 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
307
308 /* VIC */
309 if (!sysbus_realize(SYS_BUS_DEVICE(&a->vic), errp)) {
310 return;
311 }
312 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->vic), 0, sc->memmap[ASPEED_DEV_VIC]);
313 sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 0,
314 qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_IRQ));
315 sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 1,
316 qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_FIQ));
317
318 /* RTC */
319 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
320 return;
321 }
322 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]);
323 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
324 aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
325
326 /* Timer */
327 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
328 &error_abort);
329 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
330 return;
331 }
332 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0,
333 sc->memmap[ASPEED_DEV_TIMER1]);
334 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
335 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
336 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
337 }
338
339 /* Watch dog */
340 for (i = 0; i < sc->wdts_num; i++) {
341 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
342
343 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
344 &error_abort);
345 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
346 return;
347 }
348 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0,
349 sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize);
350 }
351
352 /* ADC */
353 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
354 return;
355 }
356 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
357 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
358 aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
359
360 /* UART */
361 if (!aspeed_soc_uart_realize(s, errp)) {
362 return;
363 }
364
365 /* I2C */
366 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
367 &error_abort);
368 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
369 return;
370 }
371 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
372 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
373 aspeed_soc_get_irq(s, ASPEED_DEV_I2C));
374
375 /* PECI */
376 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
377 return;
378 }
379 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0,
380 sc->memmap[ASPEED_DEV_PECI]);
381 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
382 aspeed_soc_get_irq(s, ASPEED_DEV_PECI));
383
384 /* FMC, The number of CS is set at the board level */
385 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
386 &error_abort);
387 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
388 return;
389 }
390 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
391 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1,
392 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
393 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
394 aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
395
396 /* Set up an alias on the FMC CE0 region (boot default) */
397 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio;
398 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot",
399 fmc0_mmio, 0, memory_region_size(fmc0_mmio));
400 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot);
401
402 /* SPI */
403 for (i = 0; i < sc->spis_num; i++) {
404 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
405 return;
406 }
407 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0,
408 sc->memmap[ASPEED_DEV_SPI1 + i]);
409 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1,
410 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
411 }
412
413 /* EHCI */
414 for (i = 0; i < sc->ehcis_num; i++) {
415 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
416 return;
417 }
418 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0,
419 sc->memmap[ASPEED_DEV_EHCI1 + i]);
420 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
421 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
422 }
423
424 /* UHCI */
425 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uhci), errp)) {
426 return;
427 }
428 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->uhci), 0,
429 sc->memmap[ASPEED_DEV_UHCI]);
430 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uhci), 0,
431 aspeed_soc_get_irq(s, ASPEED_DEV_UHCI));
432
433 /* SDMC - SDRAM Memory Controller */
434 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
435 return;
436 }
437 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0,
438 sc->memmap[ASPEED_DEV_SDMC]);
439
440 /* RAM */
441 if (!aspeed_soc_dram_init(s, errp)) {
442 return;
443 }
444
445 /* Net */
446 for (i = 0; i < sc->macs_num; i++) {
447 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
448 &error_abort);
449 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
450 return;
451 }
452 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
453 sc->memmap[ASPEED_DEV_ETH1 + i]);
454 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
455 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
456 }
457
458 /* XDMA */
459 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) {
460 return;
461 }
462 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0,
463 sc->memmap[ASPEED_DEV_XDMA]);
464 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
465 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA));
466
467 /* GPIO */
468 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
469 return;
470 }
471 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0,
472 sc->memmap[ASPEED_DEV_GPIO]);
473 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
474 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
475
476 /* SDHCI */
477 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
478 return;
479 }
480 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0,
481 sc->memmap[ASPEED_DEV_SDHCI]);
482 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
483 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
484
485 /* LPC */
486 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
487 return;
488 }
489 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
490
491 /* Connect the LPC IRQ to the VIC */
492 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
493 aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
494
495 /*
496 * On the AST2400 and AST2500 the one LPC IRQ is shared between all of the
497 * subdevices. Connect the LPC subdevice IRQs to the LPC controller IRQ (by
498 * contrast, on the AST2600, the subdevice IRQs are connected straight to
499 * the GIC).
500 *
501 * LPC subdevice IRQ sources are offset from 1 because the shared IRQ output
502 * to the VIC is at offset 0.
503 */
504 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
505 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_1));
506
507 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
508 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_2));
509
510 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
511 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_3));
512
513 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
514 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_4));
515
516 /* iBT */
517 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ibt), errp)) {
518 return;
519 }
520 memory_region_add_subregion(&s->lpc.iomem,
521 sc->memmap[ASPEED_DEV_IBT] - sc->memmap[ASPEED_DEV_LPC],
522 &s->ibt.iomem);
523 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_ibt,
524 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_ibt));
525
526 /* HACE */
527 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr),
528 &error_abort);
529 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
530 return;
531 }
532 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
533 sc->memmap[ASPEED_DEV_HACE]);
534 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
535 aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
536
537 /* GFX */
538 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gfx), errp)) {
539 return;
540 }
541 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gfx), 0, sc->memmap[ASPEED_DEV_GFX]);
542 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gfx), 0,
543 aspeed_soc_get_irq(s, ASPEED_DEV_GFX));
544
545 /* PWM */
546 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm), errp)) {
547 return;
548 }
549 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pwm), 0, sc->memmap[ASPEED_DEV_PWM]);
550 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwm), 0,
551 aspeed_soc_get_irq(s, ASPEED_DEV_PWM));
552 }
553
aspeed_soc_ast2400_class_init(ObjectClass * oc,void * data)554 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
555 {
556 static const char * const valid_cpu_types[] = {
557 ARM_CPU_TYPE_NAME("arm926"),
558 NULL
559 };
560 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
561 DeviceClass *dc = DEVICE_CLASS(oc);
562
563 dc->realize = aspeed_ast2400_soc_realize;
564 /* Reason: Uses serial_hds and nd_table in realize() directly */
565 dc->user_creatable = false;
566
567 sc->name = "ast2400-a1";
568 sc->valid_cpu_types = valid_cpu_types;
569 sc->silicon_rev = AST2400_A1_SILICON_REV;
570 sc->sram_size = 0x8000;
571 sc->spis_num = 1;
572 sc->ehcis_num = 1;
573 sc->wdts_num = 2;
574 sc->macs_num = 2;
575 sc->uarts_num = 5;
576 sc->uarts_base = ASPEED_DEV_UART1;
577 sc->irqmap = aspeed_soc_ast2400_irqmap;
578 sc->memmap = aspeed_soc_ast2400_memmap;
579 sc->num_cpus = 1;
580 sc->get_irq = aspeed_soc_ast2400_get_irq;
581 }
582
aspeed_soc_ast2500_class_init(ObjectClass * oc,void * data)583 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
584 {
585 static const char * const valid_cpu_types[] = {
586 ARM_CPU_TYPE_NAME("arm1176"),
587 NULL
588 };
589 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
590 DeviceClass *dc = DEVICE_CLASS(oc);
591
592 dc->realize = aspeed_ast2400_soc_realize;
593 /* Reason: Uses serial_hds and nd_table in realize() directly */
594 dc->user_creatable = false;
595
596 sc->name = "ast2500-a1";
597 sc->valid_cpu_types = valid_cpu_types;
598 sc->silicon_rev = AST2500_A1_SILICON_REV;
599 sc->sram_size = 0x9000;
600 sc->spis_num = 2;
601 sc->ehcis_num = 2;
602 sc->wdts_num = 3;
603 sc->macs_num = 2;
604 sc->uarts_num = 5;
605 sc->uarts_base = ASPEED_DEV_UART1;
606 sc->irqmap = aspeed_soc_ast2500_irqmap;
607 sc->memmap = aspeed_soc_ast2500_memmap;
608 sc->num_cpus = 1;
609 sc->get_irq = aspeed_soc_ast2400_get_irq;
610 }
611
612 static const TypeInfo aspeed_soc_ast2400_types[] = {
613 {
614 .name = TYPE_ASPEED2400_SOC,
615 .parent = TYPE_ASPEED_SOC,
616 .instance_init = aspeed_ast2400_soc_init,
617 .instance_size = sizeof(Aspeed2400SoCState),
618 .abstract = true,
619 }, {
620 .name = "ast2400-a1",
621 .parent = TYPE_ASPEED2400_SOC,
622 .class_init = aspeed_soc_ast2400_class_init,
623 }, {
624 .name = "ast2500-a1",
625 .parent = TYPE_ASPEED2400_SOC,
626 .class_init = aspeed_soc_ast2500_class_init,
627 },
628 };
629
630 DEFINE_TYPES(aspeed_soc_ast2400_types)
631