1 /*
2 * ASPEED SoC family
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 * Jeremy Kerr <jk@ozlabs.org>
6 *
7 * Copyright 2016 IBM Corp.
8 *
9 * This code is licensed under the GPL version 2 or later. See
10 * the COPYING file in the top-level directory.
11 */
12
13 #include "qemu/osdep.h"
14 #include "qemu/units.h"
15 #include "qapi/error.h"
16 #include "hw/misc/unimp.h"
17 #include "hw/arm/aspeed_soc.h"
18 #include "hw/char/serial-mm.h"
19 #include "qemu/module.h"
20 #include "qemu/error-report.h"
21 #include "hw/i2c/aspeed_i2c.h"
22 #include "net/net.h"
23 #include "system/system.h"
24 #include "target/arm/cpu-qom.h"
25
26 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
27
28 static const hwaddr aspeed_soc_ast2400_memmap[] = {
29 [ASPEED_DEV_SPI_BOOT] = 0x00000000,
30 [ASPEED_DEV_IOMEM] = 0x1E600000,
31 [ASPEED_DEV_FMC] = 0x1E620000,
32 [ASPEED_DEV_SPI1] = 0x1E630000,
33 [ASPEED_DEV_EHCI1] = 0x1E6A1000,
34 [ASPEED_DEV_VIC] = 0x1E6C0000,
35 [ASPEED_DEV_SDMC] = 0x1E6E0000,
36 [ASPEED_DEV_SCU] = 0x1E6E2000,
37 [ASPEED_DEV_HACE] = 0x1E6E3000,
38 [ASPEED_DEV_GFX] = 0x1E6E6000,
39 [ASPEED_DEV_XDMA] = 0x1E6E7000,
40 [ASPEED_DEV_VIDEO] = 0x1E700000,
41 [ASPEED_DEV_ADC] = 0x1E6E9000,
42 [ASPEED_DEV_SRAM] = 0x1E720000,
43 [ASPEED_DEV_SDHCI] = 0x1E740000,
44 [ASPEED_DEV_GPIO] = 0x1E780000,
45 [ASPEED_DEV_RTC] = 0x1E781000,
46 [ASPEED_DEV_TIMER1] = 0x1E782000,
47 [ASPEED_DEV_WDT] = 0x1E785000,
48 [ASPEED_DEV_PWM] = 0x1E786000,
49 [ASPEED_DEV_LPC] = 0x1E789000,
50 [ASPEED_DEV_IBT] = 0x1E789140,
51 [ASPEED_DEV_I2C] = 0x1E78A000,
52 [ASPEED_DEV_PECI] = 0x1E78B000,
53 [ASPEED_DEV_ETH1] = 0x1E660000,
54 [ASPEED_DEV_ETH2] = 0x1E680000,
55 [ASPEED_DEV_UART1] = 0x1E783000,
56 [ASPEED_DEV_UART2] = 0x1E78D000,
57 [ASPEED_DEV_UART3] = 0x1E78E000,
58 [ASPEED_DEV_UART4] = 0x1E78F000,
59 [ASPEED_DEV_UART5] = 0x1E784000,
60 [ASPEED_DEV_VUART] = 0x1E787000,
61 [ASPEED_DEV_SDRAM] = 0x40000000,
62 };
63
64 static const hwaddr aspeed_soc_ast2500_memmap[] = {
65 [ASPEED_DEV_SPI_BOOT] = 0x00000000,
66 [ASPEED_DEV_IOMEM] = 0x1E600000,
67 [ASPEED_DEV_FMC] = 0x1E620000,
68 [ASPEED_DEV_SPI1] = 0x1E630000,
69 [ASPEED_DEV_SPI2] = 0x1E631000,
70 [ASPEED_DEV_EHCI1] = 0x1E6A1000,
71 [ASPEED_DEV_EHCI2] = 0x1E6A3000,
72 [ASPEED_DEV_VIC] = 0x1E6C0000,
73 [ASPEED_DEV_SDMC] = 0x1E6E0000,
74 [ASPEED_DEV_SCU] = 0x1E6E2000,
75 [ASPEED_DEV_HACE] = 0x1E6E3000,
76 [ASPEED_DEV_GFX] = 0x1E6E6000,
77 [ASPEED_DEV_XDMA] = 0x1E6E7000,
78 [ASPEED_DEV_ADC] = 0x1E6E9000,
79 [ASPEED_DEV_VIDEO] = 0x1E700000,
80 [ASPEED_DEV_SRAM] = 0x1E720000,
81 [ASPEED_DEV_SDHCI] = 0x1E740000,
82 [ASPEED_DEV_GPIO] = 0x1E780000,
83 [ASPEED_DEV_RTC] = 0x1E781000,
84 [ASPEED_DEV_TIMER1] = 0x1E782000,
85 [ASPEED_DEV_WDT] = 0x1E785000,
86 [ASPEED_DEV_PWM] = 0x1E786000,
87 [ASPEED_DEV_LPC] = 0x1E789000,
88 [ASPEED_DEV_IBT] = 0x1E789140,
89 [ASPEED_DEV_I2C] = 0x1E78A000,
90 [ASPEED_DEV_PECI] = 0x1E78B000,
91 [ASPEED_DEV_ETH1] = 0x1E660000,
92 [ASPEED_DEV_ETH2] = 0x1E680000,
93 [ASPEED_DEV_UART1] = 0x1E783000,
94 [ASPEED_DEV_UART2] = 0x1E78D000,
95 [ASPEED_DEV_UART3] = 0x1E78E000,
96 [ASPEED_DEV_UART4] = 0x1E78F000,
97 [ASPEED_DEV_UART5] = 0x1E784000,
98 [ASPEED_DEV_VUART] = 0x1E787000,
99 [ASPEED_DEV_SDRAM] = 0x80000000,
100 };
101
102 static const int aspeed_soc_ast2400_irqmap[] = {
103 [ASPEED_DEV_UART1] = 9,
104 [ASPEED_DEV_UART2] = 32,
105 [ASPEED_DEV_UART3] = 33,
106 [ASPEED_DEV_UART4] = 34,
107 [ASPEED_DEV_UART5] = 10,
108 [ASPEED_DEV_VUART] = 8,
109 [ASPEED_DEV_FMC] = 19,
110 [ASPEED_DEV_EHCI1] = 5,
111 [ASPEED_DEV_EHCI2] = 13,
112 [ASPEED_DEV_SDMC] = 0,
113 [ASPEED_DEV_SCU] = 21,
114 [ASPEED_DEV_ADC] = 31,
115 [ASPEED_DEV_GFX] = 25,
116 [ASPEED_DEV_GPIO] = 20,
117 [ASPEED_DEV_RTC] = 22,
118 [ASPEED_DEV_TIMER1] = 16,
119 [ASPEED_DEV_TIMER2] = 17,
120 [ASPEED_DEV_TIMER3] = 18,
121 [ASPEED_DEV_TIMER4] = 35,
122 [ASPEED_DEV_TIMER5] = 36,
123 [ASPEED_DEV_TIMER6] = 37,
124 [ASPEED_DEV_TIMER7] = 38,
125 [ASPEED_DEV_TIMER8] = 39,
126 [ASPEED_DEV_WDT] = 27,
127 [ASPEED_DEV_PWM] = 28,
128 [ASPEED_DEV_LPC] = 8,
129 [ASPEED_DEV_I2C] = 12,
130 [ASPEED_DEV_PECI] = 15,
131 [ASPEED_DEV_ETH1] = 2,
132 [ASPEED_DEV_ETH2] = 3,
133 [ASPEED_DEV_XDMA] = 6,
134 [ASPEED_DEV_SDHCI] = 26,
135 [ASPEED_DEV_HACE] = 4,
136 };
137
138 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
139
aspeed_soc_ast2400_get_irq(AspeedSoCState * s,int dev)140 static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev)
141 {
142 Aspeed2400SoCState *a = ASPEED2400_SOC(s);
143 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
144
145 return qdev_get_gpio_in(DEVICE(&a->vic), sc->irqmap[dev]);
146 }
147
aspeed_ast2400_soc_init(Object * obj)148 static void aspeed_ast2400_soc_init(Object *obj)
149 {
150 Aspeed2400SoCState *a = ASPEED2400_SOC(obj);
151 AspeedSoCState *s = ASPEED_SOC(obj);
152 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
153 int i;
154 char socname[8];
155 char typename[64];
156
157 if (sscanf(object_get_typename(obj), "%7s", socname) != 1) {
158 g_assert_not_reached();
159 }
160
161 for (i = 0; i < sc->num_cpus; i++) {
162 object_initialize_child(obj, "cpu[*]", &a->cpu[i],
163 aspeed_soc_cpu_type(sc));
164 }
165
166 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
167 object_initialize_child(obj, "scu", &s->scu, typename);
168 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
169 sc->silicon_rev);
170 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
171 "hw-strap1");
172 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
173 "hw-strap2");
174 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
175 "hw-prot-key");
176
177 object_initialize_child(obj, "vic", &a->vic, TYPE_ASPEED_VIC);
178
179 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
180
181 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
182 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
183
184 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
185 object_initialize_child(obj, "adc", &s->adc, typename);
186
187 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
188 object_initialize_child(obj, "i2c", &s->i2c, typename);
189
190 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
191
192 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
193 object_initialize_child(obj, "fmc", &s->fmc, typename);
194
195 for (i = 0; i < sc->spis_num; i++) {
196 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
197 object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
198 }
199
200 for (i = 0; i < sc->ehcis_num; i++) {
201 object_initialize_child(obj, "ehci[*]", &s->ehci[i],
202 TYPE_PLATFORM_EHCI);
203 }
204
205 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
206 object_initialize_child(obj, "sdmc", &s->sdmc, typename);
207 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
208 "ram-size");
209
210 for (i = 0; i < sc->wdts_num; i++) {
211 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
212 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
213 }
214
215 for (i = 0; i < sc->macs_num; i++) {
216 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
217 TYPE_FTGMAC100);
218 }
219
220 for (i = 0; i < sc->uarts_num; i++) {
221 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
222 }
223
224 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname);
225 object_initialize_child(obj, "xdma", &s->xdma, typename);
226
227 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
228 object_initialize_child(obj, "gpio", &s->gpio, typename);
229
230 snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname);
231 object_initialize_child(obj, "sdc", &s->sdhci, typename);
232
233 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort);
234
235 /* Init sd card slot class here so that they're under the correct parent */
236 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
237 object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i],
238 TYPE_SYSBUS_SDHCI);
239 }
240
241 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
242
243 object_initialize_child(obj, "ibt", &s->ibt, TYPE_ASPEED_IBT);
244
245 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
246 object_initialize_child(obj, "hace", &s->hace, typename);
247
248 object_initialize_child(obj, "gfx", &s->gfx, TYPE_ASPEED_GFX);
249
250 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
251 object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE);
252
253 object_initialize_child(obj, "pwm", &s->pwm, TYPE_ASPEED_PWM);
254 }
255
aspeed_ast2400_soc_realize(DeviceState * dev,Error ** errp)256 static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
257 {
258 int i;
259 Aspeed2400SoCState *a = ASPEED2400_SOC(dev);
260 AspeedSoCState *s = ASPEED_SOC(dev);
261 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
262 g_autofree char *sram_name = NULL;
263
264 /* Default boot region (SPI memory or ROMs) */
265 memory_region_init(&s->spi_boot_container, OBJECT(s),
266 "aspeed.spi_boot_container", 0x10000000);
267 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT],
268 &s->spi_boot_container);
269
270 /* IO space */
271 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io",
272 sc->memmap[ASPEED_DEV_IOMEM],
273 ASPEED_SOC_IOMEM_SIZE);
274
275 /* Video engine stub */
276 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video",
277 sc->memmap[ASPEED_DEV_VIDEO], 0x1000);
278
279 /* CPU */
280 for (i = 0; i < sc->num_cpus; i++) {
281 object_property_set_link(OBJECT(&a->cpu[i]), "memory",
282 OBJECT(s->memory), &error_abort);
283 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
284 return;
285 }
286 }
287
288 /* SRAM */
289 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
290 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size,
291 errp)) {
292 return;
293 }
294 memory_region_add_subregion(s->memory,
295 sc->memmap[ASPEED_DEV_SRAM], &s->sram);
296
297 /* SCU */
298 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
299 return;
300 }
301 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
302
303 /* VIC */
304 if (!sysbus_realize(SYS_BUS_DEVICE(&a->vic), errp)) {
305 return;
306 }
307 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->vic), 0, sc->memmap[ASPEED_DEV_VIC]);
308 sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 0,
309 qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_IRQ));
310 sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 1,
311 qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_FIQ));
312
313 /* RTC */
314 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
315 return;
316 }
317 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]);
318 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
319 aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
320
321 /* Timer */
322 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
323 &error_abort);
324 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
325 return;
326 }
327 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0,
328 sc->memmap[ASPEED_DEV_TIMER1]);
329 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
330 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
331 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
332 }
333
334 /* ADC */
335 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
336 return;
337 }
338 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
339 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
340 aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
341
342 /* UART */
343 if (!aspeed_soc_uart_realize(s, errp)) {
344 return;
345 }
346
347 /* I2C */
348 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
349 &error_abort);
350 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
351 return;
352 }
353 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
354 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
355 aspeed_soc_get_irq(s, ASPEED_DEV_I2C));
356
357 /* PECI */
358 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
359 return;
360 }
361 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0,
362 sc->memmap[ASPEED_DEV_PECI]);
363 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
364 aspeed_soc_get_irq(s, ASPEED_DEV_PECI));
365
366 /* FMC, The number of CS is set at the board level */
367 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
368 &error_abort);
369 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
370 return;
371 }
372 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
373 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1,
374 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
375 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
376 aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
377
378 /* Set up an alias on the FMC CE0 region (boot default) */
379 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio;
380 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot",
381 fmc0_mmio, 0, memory_region_size(fmc0_mmio));
382 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot);
383
384 /* SPI */
385 for (i = 0; i < sc->spis_num; i++) {
386 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
387 return;
388 }
389 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0,
390 sc->memmap[ASPEED_DEV_SPI1 + i]);
391 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1,
392 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
393 }
394
395 /* EHCI */
396 for (i = 0; i < sc->ehcis_num; i++) {
397 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
398 return;
399 }
400 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0,
401 sc->memmap[ASPEED_DEV_EHCI1 + i]);
402 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
403 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
404 }
405
406 /* SDMC - SDRAM Memory Controller */
407 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
408 return;
409 }
410 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0,
411 sc->memmap[ASPEED_DEV_SDMC]);
412
413 /* Watch dog */
414 for (i = 0; i < sc->wdts_num; i++) {
415 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
416 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
417
418 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
419 &error_abort);
420 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
421 return;
422 }
423 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
424 }
425
426 /* RAM */
427 if (!aspeed_soc_dram_init(s, errp)) {
428 return;
429 }
430
431 /* Net */
432 for (i = 0; i < sc->macs_num; i++) {
433 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
434 &error_abort);
435 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
436 return;
437 }
438 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
439 sc->memmap[ASPEED_DEV_ETH1 + i]);
440 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
441 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
442 }
443
444 /* XDMA */
445 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) {
446 return;
447 }
448 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0,
449 sc->memmap[ASPEED_DEV_XDMA]);
450 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
451 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA));
452
453 /* GPIO */
454 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
455 return;
456 }
457 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0,
458 sc->memmap[ASPEED_DEV_GPIO]);
459 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
460 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
461
462 /* SDHCI */
463 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
464 return;
465 }
466 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0,
467 sc->memmap[ASPEED_DEV_SDHCI]);
468 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
469 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
470
471 /* LPC */
472 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
473 return;
474 }
475 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
476
477 /* Connect the LPC IRQ to the VIC */
478 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
479 aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
480
481 /*
482 * On the AST2400 and AST2500 the one LPC IRQ is shared between all of the
483 * subdevices. Connect the LPC subdevice IRQs to the LPC controller IRQ (by
484 * contrast, on the AST2600, the subdevice IRQs are connected straight to
485 * the GIC).
486 *
487 * LPC subdevice IRQ sources are offset from 1 because the shared IRQ output
488 * to the VIC is at offset 0.
489 */
490 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
491 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_1));
492
493 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
494 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_2));
495
496 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
497 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_3));
498
499 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
500 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_4));
501
502 /* iBT */
503 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ibt), errp)) {
504 return;
505 }
506 memory_region_add_subregion(&s->lpc.iomem,
507 sc->memmap[ASPEED_DEV_IBT] - sc->memmap[ASPEED_DEV_LPC],
508 &s->ibt.iomem);
509 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_ibt,
510 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_ibt));
511
512 /* HACE */
513 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr),
514 &error_abort);
515 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
516 return;
517 }
518 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
519 sc->memmap[ASPEED_DEV_HACE]);
520 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
521 aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
522
523 /* GFX */
524 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gfx), errp)) {
525 return;
526 }
527 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gfx), 0, sc->memmap[ASPEED_DEV_GFX]);
528 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gfx), 0,
529 aspeed_soc_get_irq(s, ASPEED_DEV_GFX));
530
531 /* PWM */
532 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm), errp)) {
533 return;
534 }
535 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pwm), 0, sc->memmap[ASPEED_DEV_PWM]);
536 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwm), 0,
537 aspeed_soc_get_irq(s, ASPEED_DEV_PWM));
538 }
539
aspeed_soc_ast2400_class_init(ObjectClass * oc,const void * data)540 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, const void *data)
541 {
542 static const char * const valid_cpu_types[] = {
543 ARM_CPU_TYPE_NAME("arm926"),
544 NULL
545 };
546 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
547 DeviceClass *dc = DEVICE_CLASS(oc);
548
549 dc->realize = aspeed_ast2400_soc_realize;
550 /* Reason: Uses serial_hds and nd_table in realize() directly */
551 dc->user_creatable = false;
552
553 sc->valid_cpu_types = valid_cpu_types;
554 sc->silicon_rev = AST2400_A1_SILICON_REV;
555 sc->sram_size = 0x8000;
556 sc->spis_num = 1;
557 sc->ehcis_num = 1;
558 sc->wdts_num = 2;
559 sc->macs_num = 2;
560 sc->uarts_num = 5;
561 sc->uarts_base = ASPEED_DEV_UART1;
562 sc->irqmap = aspeed_soc_ast2400_irqmap;
563 sc->memmap = aspeed_soc_ast2400_memmap;
564 sc->num_cpus = 1;
565 sc->get_irq = aspeed_soc_ast2400_get_irq;
566 }
567
aspeed_soc_ast2500_class_init(ObjectClass * oc,const void * data)568 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, const void *data)
569 {
570 static const char * const valid_cpu_types[] = {
571 ARM_CPU_TYPE_NAME("arm1176"),
572 NULL
573 };
574 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
575 DeviceClass *dc = DEVICE_CLASS(oc);
576
577 dc->realize = aspeed_ast2400_soc_realize;
578 /* Reason: Uses serial_hds and nd_table in realize() directly */
579 dc->user_creatable = false;
580
581 sc->valid_cpu_types = valid_cpu_types;
582 sc->silicon_rev = AST2500_A1_SILICON_REV;
583 sc->sram_size = 0x9000;
584 sc->spis_num = 2;
585 sc->ehcis_num = 2;
586 sc->wdts_num = 3;
587 sc->macs_num = 2;
588 sc->uarts_num = 5;
589 sc->uarts_base = ASPEED_DEV_UART1;
590 sc->irqmap = aspeed_soc_ast2500_irqmap;
591 sc->memmap = aspeed_soc_ast2500_memmap;
592 sc->num_cpus = 1;
593 sc->get_irq = aspeed_soc_ast2400_get_irq;
594 }
595
596 static const TypeInfo aspeed_soc_ast2400_types[] = {
597 {
598 .name = TYPE_ASPEED2400_SOC,
599 .parent = TYPE_ASPEED_SOC,
600 .instance_init = aspeed_ast2400_soc_init,
601 .instance_size = sizeof(Aspeed2400SoCState),
602 .abstract = true,
603 }, {
604 .name = "ast2400-a1",
605 .parent = TYPE_ASPEED2400_SOC,
606 .class_init = aspeed_soc_ast2400_class_init,
607 }, {
608 .name = "ast2500-a1",
609 .parent = TYPE_ASPEED2400_SOC,
610 .class_init = aspeed_soc_ast2500_class_init,
611 },
612 };
613
614 DEFINE_TYPES(aspeed_soc_ast2400_types)
615