1 /*
2 * OpenPOWER Palmetto BMC
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "hw/arm/boot.h"
15 #include "hw/arm/aspeed.h"
16 #include "hw/arm/aspeed_soc.h"
17 #include "hw/arm/aspeed_eeprom.h"
18 #include "hw/block/flash.h"
19 #include "hw/i2c/i2c_mux_pca954x.h"
20 #include "hw/i2c/smbus_eeprom.h"
21 #include "hw/gpio/pca9552.h"
22 #include "hw/gpio/pca9554.h"
23 #include "hw/nvram/eeprom_at24c.h"
24 #include "hw/sensor/tmp105.h"
25 #include "hw/misc/led.h"
26 #include "hw/qdev-properties.h"
27 #include "system/block-backend.h"
28 #include "system/reset.h"
29 #include "hw/loader.h"
30 #include "qemu/error-report.h"
31 #include "qemu/datadir.h"
32 #include "qemu/units.h"
33 #include "hw/qdev-clock.h"
34 #include "system/system.h"
35
36 static struct arm_boot_info aspeed_board_binfo = {
37 .board_id = -1, /* device-tree-only board */
38 };
39
40 struct AspeedMachineState {
41 /* Private */
42 MachineState parent_obj;
43 /* Public */
44
45 AspeedSoCState *soc;
46 MemoryRegion boot_rom;
47 bool mmio_exec;
48 uint32_t uart_chosen;
49 char *fmc_model;
50 char *spi_model;
51 uint32_t hw_strap1;
52 };
53
54 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
55 #if HOST_LONG_BITS == 32
56 #define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB)
57 #else
58 #define ASPEED_RAM_SIZE(sz) (sz)
59 #endif
60
61 /* Palmetto hardware value: 0x120CE416 */
62 #define PALMETTO_BMC_HW_STRAP1 ( \
63 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
64 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
65 SCU_AST2400_HW_STRAP_ACPI_DIS | \
66 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
67 SCU_HW_STRAP_VGA_CLASS_CODE | \
68 SCU_HW_STRAP_LPC_RESET_PIN | \
69 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
70 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
71 SCU_HW_STRAP_SPI_WIDTH | \
72 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
73 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
74
75 /* TODO: Find the actual hardware value */
76 #define SUPERMICROX11_BMC_HW_STRAP1 ( \
77 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
78 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \
79 SCU_AST2400_HW_STRAP_ACPI_DIS | \
80 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
81 SCU_HW_STRAP_VGA_CLASS_CODE | \
82 SCU_HW_STRAP_LPC_RESET_PIN | \
83 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
84 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
85 SCU_HW_STRAP_SPI_WIDTH | \
86 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
87 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
88
89 /* TODO: Find the actual hardware value */
90 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \
91 AST2500_HW_STRAP1_DEFAULTS | \
92 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
93 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
94 SCU_AST2500_HW_STRAP_UART_DEBUG | \
95 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
96 SCU_HW_STRAP_SPI_WIDTH | \
97 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN))
98
99 /* AST2500 evb hardware value: 0xF100C2E6 */
100 #define AST2500_EVB_HW_STRAP1 (( \
101 AST2500_HW_STRAP1_DEFAULTS | \
102 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
103 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
104 SCU_AST2500_HW_STRAP_UART_DEBUG | \
105 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
106 SCU_HW_STRAP_MAC1_RGMII | \
107 SCU_HW_STRAP_MAC0_RGMII) & \
108 ~SCU_HW_STRAP_2ND_BOOT_WDT)
109
110 /* Romulus hardware value: 0xF10AD206 */
111 #define ROMULUS_BMC_HW_STRAP1 ( \
112 AST2500_HW_STRAP1_DEFAULTS | \
113 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
114 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
115 SCU_AST2500_HW_STRAP_UART_DEBUG | \
116 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
117 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
118 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
119
120 /* Sonorapass hardware value: 0xF100D216 */
121 #define SONORAPASS_BMC_HW_STRAP1 ( \
122 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
123 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
124 SCU_AST2500_HW_STRAP_UART_DEBUG | \
125 SCU_AST2500_HW_STRAP_RESERVED28 | \
126 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
127 SCU_HW_STRAP_VGA_CLASS_CODE | \
128 SCU_HW_STRAP_LPC_RESET_PIN | \
129 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
130 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
131 SCU_HW_STRAP_VGA_BIOS_ROM | \
132 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
133 SCU_AST2500_HW_STRAP_RESERVED1)
134
135 #define G220A_BMC_HW_STRAP1 ( \
136 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
137 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
138 SCU_AST2500_HW_STRAP_UART_DEBUG | \
139 SCU_AST2500_HW_STRAP_RESERVED28 | \
140 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
141 SCU_HW_STRAP_2ND_BOOT_WDT | \
142 SCU_HW_STRAP_VGA_CLASS_CODE | \
143 SCU_HW_STRAP_LPC_RESET_PIN | \
144 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
145 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
146 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \
147 SCU_AST2500_HW_STRAP_RESERVED1)
148
149 /* FP5280G2 hardware value: 0XF100D286 */
150 #define FP5280G2_BMC_HW_STRAP1 ( \
151 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
152 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
153 SCU_AST2500_HW_STRAP_UART_DEBUG | \
154 SCU_AST2500_HW_STRAP_RESERVED28 | \
155 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
156 SCU_HW_STRAP_VGA_CLASS_CODE | \
157 SCU_HW_STRAP_LPC_RESET_PIN | \
158 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
159 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
160 SCU_HW_STRAP_MAC1_RGMII | \
161 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
162 SCU_AST2500_HW_STRAP_RESERVED1)
163
164 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
165 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
166
167 /* Quanta-Q71l hardware value */
168 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \
169 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
170 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
171 SCU_AST2400_HW_STRAP_ACPI_DIS | \
172 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \
173 SCU_HW_STRAP_VGA_CLASS_CODE | \
174 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \
175 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
176 SCU_HW_STRAP_SPI_WIDTH | \
177 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \
178 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
179
180 /* AST2600 evb hardware value */
181 #define AST2600_EVB_HW_STRAP1 0x000000C0
182 #define AST2600_EVB_HW_STRAP2 0x00000003
183
184 #ifdef TARGET_AARCH64
185 /* AST2700 evb hardware value */
186 /* SCU HW Strap1 */
187 #define AST2700_EVB_HW_STRAP1 0x00000800
188 /* SCUIO HW Strap1 */
189 #define AST2700_EVB_HW_STRAP2 0x00000700
190 #endif
191
192 /* Rainier hardware value: (QEMU prototype) */
193 #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC)
194 #define RAINIER_BMC_HW_STRAP2 0x80000848
195
196 /* Fuji hardware value */
197 #define FUJI_BMC_HW_STRAP1 0x00000000
198 #define FUJI_BMC_HW_STRAP2 0x00000000
199
200 /* Bletchley hardware value */
201 #define BLETCHLEY_BMC_HW_STRAP1 0x00002000
202 #define BLETCHLEY_BMC_HW_STRAP2 0x00000801
203
204 /* GB200NVL hardware value */
205 #define GB200NVL_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
206 #define GB200NVL_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
207
208 /* Qualcomm DC-SCM hardware value */
209 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000
210 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041
211
212 #define AST_SMP_MAILBOX_BASE 0x1e6e2180
213 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
214 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
215 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
216 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
217 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
218 #define AST_SMP_MBOX_GOSIGN 0xabbaab00
219
aspeed_write_smpboot(ARMCPU * cpu,const struct arm_boot_info * info)220 static void aspeed_write_smpboot(ARMCPU *cpu,
221 const struct arm_boot_info *info)
222 {
223 AddressSpace *as = arm_boot_address_space(cpu, info);
224 static const ARMInsnFixup poll_mailbox_ready[] = {
225 /*
226 * r2 = per-cpu go sign value
227 * r1 = AST_SMP_MBOX_FIELD_ENTRY
228 * r0 = AST_SMP_MBOX_FIELD_GOSIGN
229 */
230 { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */
231 { 0xe21000ff }, /* ands r0, r0, #255 */
232 { 0xe59f201c }, /* ldr r2, [pc, #28] */
233 { 0xe1822000 }, /* orr r2, r2, r0 */
234
235 { 0xe59f1018 }, /* ldr r1, [pc, #24] */
236 { 0xe59f0018 }, /* ldr r0, [pc, #24] */
237
238 { 0xe320f002 }, /* wfe */
239 { 0xe5904000 }, /* ldr r4, [r0] */
240 { 0xe1520004 }, /* cmp r2, r4 */
241 { 0x1afffffb }, /* bne <wfe> */
242 { 0xe591f000 }, /* ldr pc, [r1] */
243 { AST_SMP_MBOX_GOSIGN },
244 { AST_SMP_MBOX_FIELD_ENTRY },
245 { AST_SMP_MBOX_FIELD_GOSIGN },
246 { 0, FIXUP_TERMINATOR }
247 };
248 static const uint32_t fixupcontext[FIXUP_MAX] = { 0 };
249
250 arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start,
251 poll_mailbox_ready, fixupcontext);
252 }
253
aspeed_reset_secondary(ARMCPU * cpu,const struct arm_boot_info * info)254 static void aspeed_reset_secondary(ARMCPU *cpu,
255 const struct arm_boot_info *info)
256 {
257 AddressSpace *as = arm_boot_address_space(cpu, info);
258 CPUState *cs = CPU(cpu);
259
260 /* info->smp_bootreg_addr */
261 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
262 MEMTXATTRS_UNSPECIFIED, NULL);
263 cpu_set_pc(cs, info->smp_loader_start);
264 }
265
write_boot_rom(BlockBackend * blk,hwaddr addr,size_t rom_size,Error ** errp)266 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
267 Error **errp)
268 {
269 g_autofree void *storage = NULL;
270 int64_t size;
271
272 /*
273 * The block backend size should have already been 'validated' by
274 * the creation of the m25p80 object.
275 */
276 size = blk_getlength(blk);
277 if (size <= 0) {
278 error_setg(errp, "failed to get flash size");
279 return;
280 }
281
282 if (rom_size > size) {
283 rom_size = size;
284 }
285
286 storage = g_malloc0(rom_size);
287 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) {
288 error_setg(errp, "failed to read the initial flash content");
289 return;
290 }
291
292 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
293 }
294
295 /*
296 * Create a ROM and copy the flash contents at the expected address
297 * (0x0). Boots faster than execute-in-place.
298 */
aspeed_install_boot_rom(AspeedMachineState * bmc,BlockBackend * blk,uint64_t rom_size)299 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
300 uint64_t rom_size)
301 {
302 AspeedSoCState *soc = bmc->soc;
303 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(soc);
304
305 memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size,
306 &error_abort);
307 memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
308 &bmc->boot_rom, 1);
309 write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT],
310 rom_size, &error_abort);
311 }
312
313 #define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin"
314
315 /*
316 * This function locates the vbootrom image file specified via the command line
317 * using the -bios option. It loads the specified image into the vbootrom
318 * memory region and handles errors if the file cannot be found or loaded.
319 */
aspeed_load_vbootrom(AspeedMachineState * bmc,const char * bios_name,Error ** errp)320 static void aspeed_load_vbootrom(AspeedMachineState *bmc, const char *bios_name,
321 Error **errp)
322 {
323 g_autofree char *filename = NULL;
324 AspeedSoCState *soc = bmc->soc;
325 int ret;
326
327 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
328 if (!filename) {
329 error_setg(errp, "Could not find vbootrom image '%s'", bios_name);
330 return;
331 }
332
333 ret = load_image_mr(filename, &soc->vbootrom);
334 if (ret < 0) {
335 error_setg(errp, "Failed to load vbootrom image '%s'", bios_name);
336 return;
337 }
338 }
339
aspeed_board_init_flashes(AspeedSMCState * s,const char * flashtype,unsigned int count,int unit0)340 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
341 unsigned int count, int unit0)
342 {
343 int i;
344
345 if (!flashtype) {
346 return;
347 }
348
349 for (i = 0; i < count; ++i) {
350 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i);
351 DeviceState *dev;
352
353 dev = qdev_new(flashtype);
354 if (dinfo) {
355 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
356 }
357 qdev_prop_set_uint8(dev, "cs", i);
358 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal);
359 }
360 }
361
sdhci_attach_drive(SDHCIState * sdhci,DriveInfo * dinfo,bool emmc,bool boot_emmc)362 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo, bool emmc,
363 bool boot_emmc)
364 {
365 DeviceState *card;
366
367 if (!dinfo) {
368 return;
369 }
370 card = qdev_new(emmc ? TYPE_EMMC : TYPE_SD_CARD);
371
372 /*
373 * Force the boot properties of the eMMC device only when the
374 * machine is strapped to boot from eMMC. Without these
375 * settings, the machine would not boot.
376 *
377 * This also allows the machine to use an eMMC device without
378 * boot areas when booting from the flash device (or -kernel)
379 * Ideally, the device and its properties should be defined on
380 * the command line.
381 */
382 if (emmc && boot_emmc) {
383 qdev_prop_set_uint64(card, "boot-partition-size", 1 * MiB);
384 qdev_prop_set_uint8(card, "boot-config", 0x1 << 3);
385 }
386 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
387 &error_fatal);
388 qdev_realize_and_unref(card,
389 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
390 &error_fatal);
391 }
392
connect_serial_hds_to_uarts(AspeedMachineState * bmc)393 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
394 {
395 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
396 AspeedSoCState *s = bmc->soc;
397 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
398 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
399
400 aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0));
401 for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; uart++) {
402 if (uart == uart_chosen) {
403 continue;
404 }
405 aspeed_soc_uart_set_chr(s, uart, serial_hd(i++));
406 }
407 }
408
aspeed_machine_init(MachineState * machine)409 static void aspeed_machine_init(MachineState *machine)
410 {
411 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
412 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
413 AspeedSoCClass *sc;
414 int i;
415 const char *bios_name = NULL;
416 DriveInfo *emmc0 = NULL;
417 bool boot_emmc;
418
419 bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
420 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
421 object_unref(OBJECT(bmc->soc));
422 sc = ASPEED_SOC_GET_CLASS(bmc->soc);
423
424 /*
425 * This will error out if the RAM size is not supported by the
426 * memory controller of the SoC.
427 */
428 object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size,
429 &error_fatal);
430
431 for (i = 0; i < sc->macs_num; i++) {
432 if ((amc->macs_mask & (1 << i)) &&
433 !qemu_configure_nic_device(DEVICE(&bmc->soc->ftgmac100[i]),
434 true, NULL)) {
435 break; /* No configs left; stop asking */
436 }
437 }
438
439 object_property_set_int(OBJECT(bmc->soc), "hw-strap1", bmc->hw_strap1,
440 &error_abort);
441 object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2,
442 &error_abort);
443 object_property_set_link(OBJECT(bmc->soc), "memory",
444 OBJECT(get_system_memory()), &error_abort);
445 object_property_set_link(OBJECT(bmc->soc), "dram",
446 OBJECT(machine->ram), &error_abort);
447 if (amc->sdhci_wp_inverted) {
448 for (i = 0; i < bmc->soc->sdhci.num_slots; i++) {
449 object_property_set_bool(OBJECT(&bmc->soc->sdhci.slots[i]),
450 "wp-inverted", true, &error_abort);
451 }
452 }
453 if (machine->kernel_filename) {
454 /*
455 * When booting with a -kernel command line there is no u-boot
456 * that runs to unlock the SCU. In this case set the default to
457 * be unlocked as the kernel expects
458 */
459 object_property_set_int(OBJECT(bmc->soc), "hw-prot-key",
460 ASPEED_SCU_PROT_KEY, &error_abort);
461 }
462 connect_serial_hds_to_uarts(bmc);
463 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
464
465 if (defaults_enabled()) {
466 aspeed_board_init_flashes(&bmc->soc->fmc,
467 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
468 amc->num_cs, 0);
469 aspeed_board_init_flashes(&bmc->soc->spi[0],
470 bmc->spi_model ? bmc->spi_model : amc->spi_model,
471 1, amc->num_cs);
472 aspeed_board_init_flashes(&bmc->soc->spi[1],
473 amc->spi2_model, 1, amc->num_cs2);
474 }
475
476 if (machine->kernel_filename && sc->num_cpus > 1) {
477 /* With no u-boot we must set up a boot stub for the secondary CPU */
478 MemoryRegion *smpboot = g_new(MemoryRegion, 1);
479 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
480 0x80, &error_abort);
481 memory_region_add_subregion(get_system_memory(),
482 AST_SMP_MAILBOX_BASE, smpboot);
483
484 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
485 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
486 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
487 }
488
489 aspeed_board_binfo.ram_size = machine->ram_size;
490 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
491
492 if (amc->i2c_init) {
493 amc->i2c_init(bmc);
494 }
495
496 for (i = 0; i < bmc->soc->sdhci.num_slots && defaults_enabled(); i++) {
497 sdhci_attach_drive(&bmc->soc->sdhci.slots[i],
498 drive_get(IF_SD, 0, i), false, false);
499 }
500
501 boot_emmc = sc->boot_from_emmc(bmc->soc);
502
503 if (bmc->soc->emmc.num_slots && defaults_enabled()) {
504 emmc0 = drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots);
505 sdhci_attach_drive(&bmc->soc->emmc.slots[0], emmc0, true, boot_emmc);
506 }
507
508 if (!bmc->mmio_exec) {
509 DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0);
510 BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL;
511
512 if (fmc0 && !boot_emmc) {
513 uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot);
514 aspeed_install_boot_rom(bmc, fmc0, rom_size);
515 } else if (emmc0) {
516 aspeed_install_boot_rom(bmc, blk_by_legacy_dinfo(emmc0), 64 * KiB);
517 }
518 }
519
520 if (amc->vbootrom) {
521 bios_name = machine->firmware ?: VBOOTROM_FILE_NAME;
522 aspeed_load_vbootrom(bmc, bios_name, &error_abort);
523 }
524
525 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
526 }
527
palmetto_bmc_i2c_init(AspeedMachineState * bmc)528 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
529 {
530 AspeedSoCState *soc = bmc->soc;
531 DeviceState *dev;
532 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
533
534 /*
535 * The palmetto platform expects a ds3231 RTC but a ds1338 is
536 * enough to provide basic RTC features. Alarms will be missing
537 */
538 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
539
540 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
541 eeprom_buf);
542
543 /* add a TMP423 temperature sensor */
544 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
545 "tmp423", 0x4c));
546 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
547 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
548 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
549 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
550 }
551
quanta_q71l_bmc_i2c_init(AspeedMachineState * bmc)552 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
553 {
554 AspeedSoCState *soc = bmc->soc;
555
556 /*
557 * The quanta-q71l platform expects tmp75s which are compatible with
558 * tmp105s.
559 */
560 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
561 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
562 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
563
564 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
565 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
566 /* TODO: Add Memory Riser i2c mux and eeproms. */
567
568 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
569 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
570
571 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
572
573 /* i2c-7 */
574 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
575 /* - i2c@0: pmbus@59 */
576 /* - i2c@1: pmbus@58 */
577 /* - i2c@2: pmbus@58 */
578 /* - i2c@3: pmbus@59 */
579
580 /* TODO: i2c-7: Add PDB FRU eeprom@52 */
581 /* TODO: i2c-8: Add BMC FRU eeprom@50 */
582 }
583
ast2500_evb_i2c_init(AspeedMachineState * bmc)584 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
585 {
586 AspeedSoCState *soc = bmc->soc;
587 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
588
589 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
590 eeprom_buf);
591
592 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
593 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
594 TYPE_TMP105, 0x4d);
595 }
596
ast2600_evb_i2c_init(AspeedMachineState * bmc)597 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
598 {
599 AspeedSoCState *soc = bmc->soc;
600 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
601
602 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
603 eeprom_buf);
604
605 /* LM75 is compatible with TMP105 driver */
606 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
607 TYPE_TMP105, 0x4d);
608 }
609
yosemitev2_bmc_i2c_init(AspeedMachineState * bmc)610 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
611 {
612 AspeedSoCState *soc = bmc->soc;
613
614 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB);
615 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB,
616 yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len);
617 /* TMP421 */
618 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f);
619 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e);
620 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f);
621
622 }
623
romulus_bmc_i2c_init(AspeedMachineState * bmc)624 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
625 {
626 AspeedSoCState *soc = bmc->soc;
627
628 /*
629 * The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
630 * good enough
631 */
632 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
633 }
634
tiogapass_bmc_i2c_init(AspeedMachineState * bmc)635 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
636 {
637 AspeedSoCState *soc = bmc->soc;
638
639 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB);
640 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB,
641 tiogapass_bmc_fruid, tiogapass_bmc_fruid_len);
642 /* TMP421 */
643 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f);
644 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f);
645 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e);
646 }
647
create_pca9552(AspeedSoCState * soc,int bus_id,int addr)648 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
649 {
650 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
651 TYPE_PCA9552, addr);
652 }
653
create_pca9554(AspeedSoCState * soc,int bus_id,int addr)654 static I2CSlave *create_pca9554(AspeedSoCState *soc, int bus_id, int addr)
655 {
656 return i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
657 TYPE_PCA9554, addr);
658 }
659
sonorapass_bmc_i2c_init(AspeedMachineState * bmc)660 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
661 {
662 AspeedSoCState *soc = bmc->soc;
663
664 /* bus 2 : */
665 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
666 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
667 /* bus 2 : pca9546 @ 0x73 */
668
669 /* bus 3 : pca9548 @ 0x70 */
670
671 /* bus 4 : */
672 uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
673 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
674 eeprom4_54);
675 /* PCA9539 @ 0x76, but PCA9552 is compatible */
676 create_pca9552(soc, 4, 0x76);
677 /* PCA9539 @ 0x77, but PCA9552 is compatible */
678 create_pca9552(soc, 4, 0x77);
679
680 /* bus 6 : */
681 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
682 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
683 /* bus 6 : pca9546 @ 0x73 */
684
685 /* bus 8 : */
686 uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
687 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
688 eeprom8_56);
689 create_pca9552(soc, 8, 0x60);
690 create_pca9552(soc, 8, 0x61);
691 /* bus 8 : adc128d818 @ 0x1d */
692 /* bus 8 : adc128d818 @ 0x1f */
693
694 /*
695 * bus 13 : pca9548 @ 0x71
696 * - channel 3:
697 * - tmm421 @ 0x4c
698 * - tmp421 @ 0x4e
699 * - tmp421 @ 0x4f
700 */
701
702 }
703
witherspoon_bmc_i2c_init(AspeedMachineState * bmc)704 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
705 {
706 static const struct {
707 unsigned gpio_id;
708 LEDColor color;
709 const char *description;
710 bool gpio_polarity;
711 } pca1_leds[] = {
712 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW},
713 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW},
714 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW},
715 };
716 AspeedSoCState *soc = bmc->soc;
717 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
718 DeviceState *dev;
719 LEDState *led;
720
721 /* Bus 3: TODO bmp280@77 */
722 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
723 qdev_prop_set_string(dev, "description", "pca1");
724 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
725 aspeed_i2c_get_bus(&soc->i2c, 3),
726 &error_fatal);
727
728 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
729 led = led_create_simple(OBJECT(bmc),
730 pca1_leds[i].gpio_polarity,
731 pca1_leds[i].color,
732 pca1_leds[i].description);
733 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
734 qdev_get_gpio_in(DEVICE(led), 0));
735 }
736
737 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps",
738 0x68);
739 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps",
740 0x69);
741 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76);
742
743 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52);
744 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
745 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ir35221", 0x70);
746 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ir35221", 0x71);
747
748 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
749 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "ir35221", 0x70);
750 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "ir35221", 0x71);
751
752 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
753 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
754 0x4a);
755
756 /*
757 * The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
758 * good enough
759 */
760 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
761
762 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
763 eeprom_buf);
764 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
765 qdev_prop_set_string(dev, "description", "pca0");
766 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
767 aspeed_i2c_get_bus(&soc->i2c, 11),
768 &error_fatal);
769 /* Bus 11: TODO ucd90160@64 */
770 }
771
g220a_bmc_i2c_init(AspeedMachineState * bmc)772 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
773 {
774 AspeedSoCState *soc = bmc->soc;
775 DeviceState *dev;
776
777 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
778 "emc1413", 0x4c));
779 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
780 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
781 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
782
783 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
784 "emc1413", 0x4c));
785 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
786 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
787 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
788
789 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
790 "emc1413", 0x4c));
791 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
792 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
793 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
794
795 static uint8_t eeprom_buf[2 * 1024] = {
796 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
797 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
798 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
799 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
800 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
801 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
802 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
803 };
804 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
805 eeprom_buf);
806 }
807
fp5280g2_bmc_i2c_init(AspeedMachineState * bmc)808 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
809 {
810 AspeedSoCState *soc = bmc->soc;
811 I2CSlave *i2c_mux;
812
813 /* The at24c256 */
814 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768);
815
816 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */
817 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
818 0x48);
819 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
820 0x49);
821
822 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
823 "pca9546", 0x70);
824 /* It expects a TMP112 but a TMP105 is compatible */
825 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105,
826 0x4a);
827
828 /* It expects a ds3232 but a ds1338 is good enough */
829 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
830
831 /* It expects a pca9555 but a pca9552 is compatible */
832 create_pca9552(soc, 8, 0x30);
833 }
834
rainier_bmc_i2c_init(AspeedMachineState * bmc)835 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
836 {
837 AspeedSoCState *soc = bmc->soc;
838 I2CSlave *i2c_mux;
839
840 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
841
842 create_pca9552(soc, 3, 0x61);
843
844 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps",
845 0x68);
846 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps",
847 0x69);
848 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps",
849 0x6a);
850 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps",
851 0x6b);
852
853 /* The rainier expects a TMP275 but a TMP105 is compatible */
854 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
855 0x48);
856 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
857 0x49);
858 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
859 0x4a);
860 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
861 "pca9546", 0x70);
862 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
863 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
864 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
865 create_pca9552(soc, 4, 0x60);
866
867 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
868 0x48);
869 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
870 0x49);
871 create_pca9552(soc, 5, 0x60);
872 create_pca9552(soc, 5, 0x61);
873 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
874 "pca9546", 0x70);
875 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
876 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
877
878 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
879 0x48);
880 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
881 0x4a);
882 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
883 0x4b);
884 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
885 "pca9546", 0x70);
886 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
887 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
888 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
889 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
890
891 create_pca9552(soc, 7, 0x30);
892 create_pca9552(soc, 7, 0x31);
893 create_pca9552(soc, 7, 0x32);
894 create_pca9552(soc, 7, 0x33);
895 create_pca9552(soc, 7, 0x60);
896 create_pca9552(soc, 7, 0x61);
897 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
898 /* Bus 7: TODO si7021-a20@20 */
899 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
900 0x48);
901 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52);
902 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
903 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
904
905 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
906 0x48);
907 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
908 0x4a);
909 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50,
910 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len);
911 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51,
912 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len);
913 create_pca9552(soc, 8, 0x60);
914 create_pca9552(soc, 8, 0x61);
915 /* Bus 8: ucd90320@11 */
916 /* Bus 8: ucd90320@b */
917 /* Bus 8: ucd90320@c */
918
919 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x42);
920 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x43);
921 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x44);
922 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x72);
923 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x73);
924 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x74);
925 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
926 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
927 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
928
929 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x42);
930 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x43);
931 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x44);
932 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x72);
933 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x73);
934 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x74);
935 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
936 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
937 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
938
939 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
940 0x48);
941 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
942 0x49);
943 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
944 "pca9546", 0x70);
945 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
946 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
947 create_pca9552(soc, 11, 0x60);
948
949
950 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
951 create_pca9552(soc, 13, 0x60);
952
953 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
954 create_pca9552(soc, 14, 0x60);
955
956 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
957 create_pca9552(soc, 15, 0x60);
958 }
959
get_pca9548_channels(I2CBus * bus,uint8_t mux_addr,I2CBus ** channels)960 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
961 I2CBus **channels)
962 {
963 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr);
964 for (int i = 0; i < 8; i++) {
965 channels[i] = pca954x_i2c_get_bus(mux, i);
966 }
967 }
968
969 #define TYPE_LM75 TYPE_TMP105
970 #define TYPE_TMP75 TYPE_TMP105
971 #define TYPE_TMP422 "tmp422"
972
fuji_bmc_i2c_init(AspeedMachineState * bmc)973 static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
974 {
975 AspeedSoCState *soc = bmc->soc;
976 I2CBus *i2c[144] = {};
977
978 for (int i = 0; i < 16; i++) {
979 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
980 }
981 I2CBus *i2c180 = i2c[2];
982 I2CBus *i2c480 = i2c[8];
983 I2CBus *i2c600 = i2c[11];
984
985 get_pca9548_channels(i2c180, 0x70, &i2c[16]);
986 get_pca9548_channels(i2c480, 0x70, &i2c[24]);
987 /* NOTE: The device tree skips [32, 40) in the alias numbering */
988 get_pca9548_channels(i2c600, 0x77, &i2c[40]);
989 get_pca9548_channels(i2c[24], 0x71, &i2c[48]);
990 get_pca9548_channels(i2c[25], 0x72, &i2c[56]);
991 get_pca9548_channels(i2c[26], 0x76, &i2c[64]);
992 get_pca9548_channels(i2c[27], 0x76, &i2c[72]);
993 for (int i = 0; i < 8; i++) {
994 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]);
995 }
996
997 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
998 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
999
1000 /*
1001 * EEPROM 24c64 size is 64Kbits or 8 Kbytes
1002 * 24c02 size is 2Kbits or 256 bytes
1003 */
1004 at24c_eeprom_init(i2c[19], 0x52, 8 * KiB);
1005 at24c_eeprom_init(i2c[20], 0x50, 256);
1006 at24c_eeprom_init(i2c[22], 0x52, 256);
1007
1008 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
1009 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
1010 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
1011 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
1012
1013 at24c_eeprom_init(i2c[8], 0x51, 8 * KiB);
1014 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
1015
1016 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
1017 at24c_eeprom_init(i2c[50], 0x52, 8 * KiB);
1018 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
1019 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
1020
1021 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
1022 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
1023
1024 at24c_eeprom_init(i2c[65], 0x53, 8 * KiB);
1025 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
1026 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
1027 at24c_eeprom_init(i2c[68], 0x52, 8 * KiB);
1028 at24c_eeprom_init(i2c[69], 0x52, 8 * KiB);
1029 at24c_eeprom_init(i2c[70], 0x52, 8 * KiB);
1030 at24c_eeprom_init(i2c[71], 0x52, 8 * KiB);
1031
1032 at24c_eeprom_init(i2c[73], 0x53, 8 * KiB);
1033 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
1034 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
1035 at24c_eeprom_init(i2c[76], 0x52, 8 * KiB);
1036 at24c_eeprom_init(i2c[77], 0x52, 8 * KiB);
1037 at24c_eeprom_init(i2c[78], 0x52, 8 * KiB);
1038 at24c_eeprom_init(i2c[79], 0x52, 8 * KiB);
1039 at24c_eeprom_init(i2c[28], 0x50, 256);
1040
1041 for (int i = 0; i < 8; i++) {
1042 at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
1043 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
1044 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
1045 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
1046 }
1047 }
1048
1049 #define TYPE_TMP421 "tmp421"
1050 #define TYPE_DS1338 "ds1338"
1051
1052 /* Catalina hardware value */
1053 #define CATALINA_BMC_HW_STRAP1 0x00002002
1054 #define CATALINA_BMC_HW_STRAP2 0x00000800
1055
1056 #define CATALINA_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
1057
catalina_bmc_i2c_init(AspeedMachineState * bmc)1058 static void catalina_bmc_i2c_init(AspeedMachineState *bmc)
1059 {
1060 /* Reference from v6.16-rc2 aspeed-bmc-facebook-catalina.dts */
1061
1062 AspeedSoCState *soc = bmc->soc;
1063 I2CBus *i2c[16] = {};
1064 I2CSlave *i2c_mux;
1065
1066 /* busses 0-15 are all used. */
1067 for (int i = 0; i < ARRAY_SIZE(i2c); i++) {
1068 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
1069 }
1070
1071 /* &i2c0 */
1072 /* i2c-mux@71 (PCA9546) on i2c0 */
1073 i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x71);
1074
1075 /* i2c-mux@72 (PCA9546) on i2c0 */
1076 i2c_mux = i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x72);
1077
1078 /* i2c0mux1ch1 */
1079 /* io_expander7 - pca9535@20 */
1080 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1),
1081 TYPE_PCA9552, 0x20);
1082 /* eeprom@50 */
1083 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x50, 8 * KiB);
1084
1085 /* i2c-mux@73 (PCA9546) on i2c0 */
1086 i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x73);
1087
1088 /* i2c-mux@75 (PCA9546) on i2c0 */
1089 i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x75);
1090
1091 /* i2c-mux@76 (PCA9546) on i2c0 */
1092 i2c_mux = i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x76);
1093
1094 /* i2c0mux4ch1 */
1095 /* io_expander8 - pca9535@21 */
1096 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1),
1097 TYPE_PCA9552, 0x21);
1098 /* eeprom@50 */
1099 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x50, 8 * KiB);
1100
1101 /* i2c-mux@77 (PCA9546) on i2c0 */
1102 i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x77);
1103
1104
1105 /* &i2c1 */
1106 /* i2c-mux@70 (PCA9548) on i2c1 */
1107 i2c_mux = i2c_slave_create_simple(i2c[1], TYPE_PCA9548, 0x70);
1108 /* i2c1mux0ch0 */
1109 /* ina238@41 - no model */
1110 /* ina238@42 - no model */
1111 /* ina238@44 - no model */
1112 /* i2c1mux0ch1 */
1113 /* ina238@41 - no model */
1114 /* ina238@43 - no model */
1115 /* i2c1mux0ch4 */
1116 /* ltc4287@42 - no model */
1117 /* ltc4287@43 - no model */
1118
1119 /* i2c1mux0ch5 */
1120 /* eeprom@54 */
1121 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 5), 0x54, 8 * KiB);
1122 /* tpm75@4f */
1123 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5), TYPE_TMP75, 0x4f);
1124
1125 /* i2c1mux0ch6 */
1126 /* io_expander5 - pca9554@27 */
1127 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6),
1128 TYPE_PCA9554, 0x27);
1129 /* io_expander6 - pca9555@25 */
1130 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6),
1131 TYPE_PCA9552, 0x25);
1132 /* eeprom@51 */
1133 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 6), 0x51, 8 * KiB);
1134
1135 /* i2c1mux0ch7 */
1136 /* eeprom@53 */
1137 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 7), 0x53, 8 * KiB);
1138 /* temperature-sensor@4b - tmp75 */
1139 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 7), TYPE_TMP75, 0x4b);
1140
1141 /* &i2c2 */
1142 /* io_expander0 - pca9555@20 */
1143 i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x20);
1144 /* io_expander0 - pca9555@21 */
1145 i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x21);
1146 /* io_expander0 - pca9555@27 */
1147 i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x27);
1148 /* eeprom@50 */
1149 at24c_eeprom_init(i2c[2], 0x50, 8 * KiB);
1150 /* eeprom@51 */
1151 at24c_eeprom_init(i2c[2], 0x51, 8 * KiB);
1152
1153 /* &i2c5 */
1154 /* i2c-mux@70 (PCA9548) on i2c5 */
1155 i2c_mux = i2c_slave_create_simple(i2c[5], TYPE_PCA9548, 0x70);
1156 /* i2c5mux0ch6 */
1157 /* eeprom@52 */
1158 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 6), 0x52, 8 * KiB);
1159 /* i2c5mux0ch7 */
1160 /* ina230@40 - no model */
1161 /* ina230@41 - no model */
1162 /* ina230@44 - no model */
1163 /* ina230@45 - no model */
1164
1165 /* &i2c6 */
1166 /* io_expander3 - pca9555@21 */
1167 i2c_slave_create_simple(i2c[6], TYPE_PCA9552, 0x21);
1168 /* rtc@6f - nct3018y */
1169 i2c_slave_create_simple(i2c[6], TYPE_DS1338, 0x6f);
1170
1171 /* &i2c9 */
1172 /* io_expander4 - pca9555@4f */
1173 i2c_slave_create_simple(i2c[9], TYPE_PCA9552, 0x4f);
1174 /* temperature-sensor@4b - tpm75 */
1175 i2c_slave_create_simple(i2c[9], TYPE_TMP75, 0x4b);
1176 /* eeprom@50 */
1177 at24c_eeprom_init(i2c[9], 0x50, 8 * KiB);
1178 /* eeprom@56 */
1179 at24c_eeprom_init(i2c[9], 0x56, 8 * KiB);
1180
1181 /* &i2c10 */
1182 /* temperature-sensor@1f - tpm421 */
1183 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x1f);
1184 /* eeprom@50 */
1185 at24c_eeprom_init(i2c[10], 0x50, 8 * KiB);
1186
1187 /* &i2c11 */
1188 /* ssif-bmc@10 - no model */
1189
1190 /* &i2c12 */
1191 /* eeprom@50 */
1192 at24c_eeprom_init(i2c[12], 0x50, 8 * KiB);
1193
1194 /* &i2c13 */
1195 /* eeprom@50 */
1196 at24c_eeprom_init(i2c[13], 0x50, 8 * KiB);
1197 /* eeprom@54 */
1198 at24c_eeprom_init(i2c[13], 0x54, 256);
1199 /* eeprom@55 */
1200 at24c_eeprom_init(i2c[13], 0x55, 256);
1201 /* eeprom@57 */
1202 at24c_eeprom_init(i2c[13], 0x57, 256);
1203
1204 /* &i2c14 */
1205 /* io_expander9 - pca9555@10 */
1206 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x10);
1207 /* io_expander10 - pca9555@11 */
1208 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x11);
1209 /* io_expander11 - pca9555@12 */
1210 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x12);
1211 /* io_expander12 - pca9555@13 */
1212 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x13);
1213 /* io_expander13 - pca9555@14 */
1214 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x14);
1215 /* io_expander14 - pca9555@15 */
1216 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x15);
1217
1218 /* &i2c15 */
1219 /* temperature-sensor@1f - tmp421 */
1220 i2c_slave_create_simple(i2c[15], TYPE_TMP421, 0x1f);
1221 /* eeprom@52 */
1222 at24c_eeprom_init(i2c[15], 0x52, 8 * KiB);
1223 }
1224
bletchley_bmc_i2c_init(AspeedMachineState * bmc)1225 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
1226 {
1227 AspeedSoCState *soc = bmc->soc;
1228 I2CBus *i2c[13] = {};
1229 for (int i = 0; i < 13; i++) {
1230 if ((i == 8) || (i == 11)) {
1231 continue;
1232 }
1233 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
1234 }
1235
1236 /* Bus 0 - 5 all have the same config. */
1237 for (int i = 0; i < 6; i++) {
1238 /* Missing model: ti,ina230 @ 0x45 */
1239 /* Missing model: mps,mp5023 @ 0x40 */
1240 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f);
1241 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */
1242 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76);
1243 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67);
1244 /* Missing model: fsc,fusb302 @ 0x22 */
1245 }
1246
1247 /* Bus 6 */
1248 at24c_eeprom_init(i2c[6], 0x56, 65536);
1249 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */
1250 i2c_slave_create_simple(i2c[6], "ds1338", 0x51);
1251
1252
1253 /* Bus 7 */
1254 at24c_eeprom_init(i2c[7], 0x54, 65536);
1255
1256 /* Bus 9 */
1257 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f);
1258
1259 /* Bus 10 */
1260 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f);
1261 /* Missing model: ti,hdc1080 @ 0x40 */
1262 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67);
1263
1264 /* Bus 12 */
1265 /* Missing model: adi,adm1278 @ 0x11 */
1266 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c);
1267 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d);
1268 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
1269 }
1270
1271
gb200nvl_bmc_i2c_init(AspeedMachineState * bmc)1272 static void gb200nvl_bmc_i2c_init(AspeedMachineState *bmc)
1273 {
1274 AspeedSoCState *soc = bmc->soc;
1275 I2CBus *i2c[15] = {};
1276 DeviceState *dev;
1277 for (int i = 0; i < sizeof(i2c) / sizeof(i2c[0]); i++) {
1278 if ((i == 11) || (i == 12) || (i == 13)) {
1279 continue;
1280 }
1281 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
1282 }
1283
1284 /* Bus 5 Expander */
1285 create_pca9554(soc, 4, 0x21);
1286
1287 /* Mux I2c Expanders */
1288 i2c_slave_create_simple(i2c[5], "pca9546", 0x71);
1289 i2c_slave_create_simple(i2c[5], "pca9546", 0x72);
1290 i2c_slave_create_simple(i2c[5], "pca9546", 0x73);
1291 i2c_slave_create_simple(i2c[5], "pca9546", 0x75);
1292 i2c_slave_create_simple(i2c[5], "pca9546", 0x76);
1293 i2c_slave_create_simple(i2c[5], "pca9546", 0x77);
1294
1295 /* Bus 10 */
1296 dev = DEVICE(create_pca9554(soc, 9, 0x20));
1297
1298 /* Set FPGA_READY */
1299 object_property_set_str(OBJECT(dev), "pin1", "high", &error_fatal);
1300
1301 create_pca9554(soc, 9, 0x21);
1302 at24c_eeprom_init(i2c[9], 0x50, 64 * KiB);
1303 at24c_eeprom_init(i2c[9], 0x51, 64 * KiB);
1304
1305 /* Bus 11 */
1306 at24c_eeprom_init_rom(i2c[10], 0x50, 256, gb200nvl_bmc_fruid,
1307 gb200nvl_bmc_fruid_len);
1308 }
1309
fby35_i2c_init(AspeedMachineState * bmc)1310 static void fby35_i2c_init(AspeedMachineState *bmc)
1311 {
1312 AspeedSoCState *soc = bmc->soc;
1313 I2CBus *i2c[16];
1314
1315 for (int i = 0; i < 16; i++) {
1316 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
1317 }
1318
1319 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f);
1320 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f);
1321 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */
1322 i2c_slave_create_simple(i2c[11], "adm1272", 0x44);
1323 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);
1324 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);
1325
1326 at24c_eeprom_init(i2c[4], 0x51, 128 * KiB);
1327 at24c_eeprom_init(i2c[6], 0x51, 128 * KiB);
1328 at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid,
1329 fby35_nic_fruid_len);
1330 at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid,
1331 fby35_bb_fruid_len);
1332 at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid,
1333 fby35_bmc_fruid_len);
1334
1335 /*
1336 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
1337 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on
1338 * each.
1339 */
1340 }
1341
qcom_dc_scm_bmc_i2c_init(AspeedMachineState * bmc)1342 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
1343 {
1344 AspeedSoCState *soc = bmc->soc;
1345
1346 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
1347 }
1348
qcom_dc_scm_firework_i2c_init(AspeedMachineState * bmc)1349 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
1350 {
1351 AspeedSoCState *soc = bmc->soc;
1352 I2CSlave *therm_mux, *cpuvr_mux;
1353
1354 /* Create the generic DC-SCM hardware */
1355 qcom_dc_scm_bmc_i2c_init(bmc);
1356
1357 /* Now create the Firework specific hardware */
1358
1359 /* I2C7 CPUVR MUX */
1360 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
1361 "pca9546", 0x70);
1362 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72);
1363 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72);
1364 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72);
1365 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72);
1366
1367 /* I2C8 Thermal Diodes*/
1368 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
1369 "pca9548", 0x70);
1370 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C);
1371 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C);
1372 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48);
1373 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48);
1374 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48);
1375
1376 /* I2C9 Fan Controller (MAX31785) */
1377 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52);
1378 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54);
1379 }
1380
aspeed_get_mmio_exec(Object * obj,Error ** errp)1381 static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
1382 {
1383 return ASPEED_MACHINE(obj)->mmio_exec;
1384 }
1385
aspeed_set_mmio_exec(Object * obj,bool value,Error ** errp)1386 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
1387 {
1388 ASPEED_MACHINE(obj)->mmio_exec = value;
1389 }
1390
aspeed_machine_instance_init(Object * obj)1391 static void aspeed_machine_instance_init(Object *obj)
1392 {
1393 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(obj);
1394
1395 ASPEED_MACHINE(obj)->mmio_exec = false;
1396 ASPEED_MACHINE(obj)->hw_strap1 = amc->hw_strap1;
1397 }
1398
aspeed_get_fmc_model(Object * obj,Error ** errp)1399 static char *aspeed_get_fmc_model(Object *obj, Error **errp)
1400 {
1401 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1402 return g_strdup(bmc->fmc_model);
1403 }
1404
aspeed_set_fmc_model(Object * obj,const char * value,Error ** errp)1405 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
1406 {
1407 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1408
1409 g_free(bmc->fmc_model);
1410 bmc->fmc_model = g_strdup(value);
1411 }
1412
aspeed_get_spi_model(Object * obj,Error ** errp)1413 static char *aspeed_get_spi_model(Object *obj, Error **errp)
1414 {
1415 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1416 return g_strdup(bmc->spi_model);
1417 }
1418
aspeed_set_spi_model(Object * obj,const char * value,Error ** errp)1419 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
1420 {
1421 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1422
1423 g_free(bmc->spi_model);
1424 bmc->spi_model = g_strdup(value);
1425 }
1426
aspeed_get_bmc_console(Object * obj,Error ** errp)1427 static char *aspeed_get_bmc_console(Object *obj, Error **errp)
1428 {
1429 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1430 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
1431 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
1432
1433 return g_strdup_printf("uart%d", aspeed_uart_index(uart_chosen));
1434 }
1435
aspeed_set_bmc_console(Object * obj,const char * value,Error ** errp)1436 static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp)
1437 {
1438 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1439 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
1440 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name));
1441 int val;
1442 int uart_first = aspeed_uart_first(sc);
1443 int uart_last = aspeed_uart_last(sc);
1444
1445 if (sscanf(value, "uart%u", &val) != 1) {
1446 error_setg(errp, "Bad value for \"uart\" property");
1447 return;
1448 }
1449
1450 /* The number of UART depends on the SoC */
1451 if (val < uart_first || val > uart_last) {
1452 error_setg(errp, "\"uart\" should be in range [%d - %d]",
1453 uart_first, uart_last);
1454 return;
1455 }
1456 bmc->uart_chosen = val + ASPEED_DEV_UART0;
1457 }
1458
aspeed_machine_class_props_init(ObjectClass * oc)1459 static void aspeed_machine_class_props_init(ObjectClass *oc)
1460 {
1461 object_class_property_add_bool(oc, "execute-in-place",
1462 aspeed_get_mmio_exec,
1463 aspeed_set_mmio_exec);
1464 object_class_property_set_description(oc, "execute-in-place",
1465 "boot directly from CE0 flash device");
1466
1467 object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console,
1468 aspeed_set_bmc_console);
1469 object_class_property_set_description(oc, "bmc-console",
1470 "Change the default UART to \"uartX\"");
1471
1472 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
1473 aspeed_set_fmc_model);
1474 object_class_property_set_description(oc, "fmc-model",
1475 "Change the FMC Flash model");
1476 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
1477 aspeed_set_spi_model);
1478 object_class_property_set_description(oc, "spi-model",
1479 "Change the SPI Flash model");
1480 }
1481
aspeed_machine_class_init_cpus_defaults(MachineClass * mc)1482 static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc)
1483 {
1484 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc);
1485 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name));
1486
1487 mc->default_cpus = sc->num_cpus;
1488 mc->min_cpus = sc->num_cpus;
1489 mc->max_cpus = sc->num_cpus;
1490 mc->valid_cpu_types = sc->valid_cpu_types;
1491 }
1492
aspeed_machine_ast2600_get_boot_from_emmc(Object * obj,Error ** errp)1493 static bool aspeed_machine_ast2600_get_boot_from_emmc(Object *obj, Error **errp)
1494 {
1495 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1496
1497 return !!(bmc->hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC);
1498 }
1499
aspeed_machine_ast2600_set_boot_from_emmc(Object * obj,bool value,Error ** errp)1500 static void aspeed_machine_ast2600_set_boot_from_emmc(Object *obj, bool value,
1501 Error **errp)
1502 {
1503 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1504
1505 if (value) {
1506 bmc->hw_strap1 |= SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC;
1507 } else {
1508 bmc->hw_strap1 &= ~SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC;
1509 }
1510 }
1511
aspeed_machine_ast2600_class_emmc_init(ObjectClass * oc)1512 static void aspeed_machine_ast2600_class_emmc_init(ObjectClass *oc)
1513 {
1514 object_class_property_add_bool(oc, "boot-emmc",
1515 aspeed_machine_ast2600_get_boot_from_emmc,
1516 aspeed_machine_ast2600_set_boot_from_emmc);
1517 object_class_property_set_description(oc, "boot-emmc",
1518 "Set or unset boot from EMMC");
1519 }
1520
aspeed_machine_class_init(ObjectClass * oc,const void * data)1521 static void aspeed_machine_class_init(ObjectClass *oc, const void *data)
1522 {
1523 MachineClass *mc = MACHINE_CLASS(oc);
1524 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1525
1526 mc->init = aspeed_machine_init;
1527 mc->no_floppy = 1;
1528 mc->no_cdrom = 1;
1529 mc->no_parallel = 1;
1530 mc->default_ram_id = "ram";
1531 amc->macs_mask = ASPEED_MAC0_ON;
1532 amc->uart_default = ASPEED_DEV_UART5;
1533
1534 aspeed_machine_class_props_init(oc);
1535 }
1536
aspeed_machine_palmetto_class_init(ObjectClass * oc,const void * data)1537 static void aspeed_machine_palmetto_class_init(ObjectClass *oc,
1538 const void *data)
1539 {
1540 MachineClass *mc = MACHINE_CLASS(oc);
1541 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1542
1543 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
1544 amc->soc_name = "ast2400-a1";
1545 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
1546 amc->fmc_model = "n25q256a";
1547 amc->spi_model = "mx25l25635f";
1548 amc->num_cs = 1;
1549 amc->i2c_init = palmetto_bmc_i2c_init;
1550 mc->auto_create_sdcard = true;
1551 mc->default_ram_size = 256 * MiB;
1552 aspeed_machine_class_init_cpus_defaults(mc);
1553 };
1554
aspeed_machine_quanta_q71l_class_init(ObjectClass * oc,const void * data)1555 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc,
1556 const void *data)
1557 {
1558 MachineClass *mc = MACHINE_CLASS(oc);
1559 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1560
1561 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)";
1562 amc->soc_name = "ast2400-a1";
1563 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
1564 amc->fmc_model = "n25q256a";
1565 amc->spi_model = "mx25l25635e";
1566 amc->num_cs = 1;
1567 amc->i2c_init = quanta_q71l_bmc_i2c_init;
1568 mc->auto_create_sdcard = true;
1569 mc->default_ram_size = 128 * MiB;
1570 aspeed_machine_class_init_cpus_defaults(mc);
1571 }
1572
aspeed_machine_supermicrox11_bmc_class_init(ObjectClass * oc,const void * data)1573 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
1574 const void *data)
1575 {
1576 MachineClass *mc = MACHINE_CLASS(oc);
1577 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1578
1579 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)";
1580 amc->soc_name = "ast2400-a1";
1581 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
1582 amc->fmc_model = "mx25l25635e";
1583 amc->spi_model = "mx25l25635e";
1584 amc->num_cs = 1;
1585 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1586 amc->i2c_init = palmetto_bmc_i2c_init;
1587 mc->auto_create_sdcard = true;
1588 mc->default_ram_size = 256 * MiB;
1589 aspeed_machine_class_init_cpus_defaults(mc);
1590 }
1591
aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass * oc,const void * data)1592 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
1593 const void *data)
1594 {
1595 MachineClass *mc = MACHINE_CLASS(oc);
1596 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1597
1598 mc->desc = "Supermicro X11 SPI BMC (ARM1176)";
1599 amc->soc_name = "ast2500-a1";
1600 amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1;
1601 amc->fmc_model = "mx25l25635e";
1602 amc->spi_model = "mx25l25635e";
1603 amc->num_cs = 1;
1604 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1605 amc->i2c_init = palmetto_bmc_i2c_init;
1606 mc->auto_create_sdcard = true;
1607 mc->default_ram_size = 512 * MiB;
1608 aspeed_machine_class_init_cpus_defaults(mc);
1609 }
1610
aspeed_machine_ast2500_evb_class_init(ObjectClass * oc,const void * data)1611 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc,
1612 const void *data)
1613 {
1614 MachineClass *mc = MACHINE_CLASS(oc);
1615 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1616
1617 mc->desc = "Aspeed AST2500 EVB (ARM1176)";
1618 amc->soc_name = "ast2500-a1";
1619 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1620 amc->fmc_model = "mx25l25635e";
1621 amc->spi_model = "mx25l25635f";
1622 amc->num_cs = 1;
1623 amc->i2c_init = ast2500_evb_i2c_init;
1624 mc->auto_create_sdcard = true;
1625 mc->default_ram_size = 512 * MiB;
1626 aspeed_machine_class_init_cpus_defaults(mc);
1627 };
1628
aspeed_machine_yosemitev2_class_init(ObjectClass * oc,const void * data)1629 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc,
1630 const void *data)
1631 {
1632 MachineClass *mc = MACHINE_CLASS(oc);
1633 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1634
1635 mc->desc = "Facebook YosemiteV2 BMC (ARM1176)";
1636 amc->soc_name = "ast2500-a1";
1637 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1638 amc->hw_strap2 = 0;
1639 amc->fmc_model = "n25q256a";
1640 amc->spi_model = "mx25l25635e";
1641 amc->num_cs = 2;
1642 amc->i2c_init = yosemitev2_bmc_i2c_init;
1643 mc->auto_create_sdcard = true;
1644 mc->default_ram_size = 512 * MiB;
1645 aspeed_machine_class_init_cpus_defaults(mc);
1646 };
1647
aspeed_machine_romulus_class_init(ObjectClass * oc,const void * data)1648 static void aspeed_machine_romulus_class_init(ObjectClass *oc,
1649 const void *data)
1650 {
1651 MachineClass *mc = MACHINE_CLASS(oc);
1652 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1653
1654 mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
1655 amc->soc_name = "ast2500-a1";
1656 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
1657 amc->fmc_model = "n25q256a";
1658 amc->spi_model = "mx66l1g45g";
1659 amc->num_cs = 2;
1660 amc->i2c_init = romulus_bmc_i2c_init;
1661 mc->auto_create_sdcard = true;
1662 mc->default_ram_size = 512 * MiB;
1663 aspeed_machine_class_init_cpus_defaults(mc);
1664 };
1665
aspeed_machine_tiogapass_class_init(ObjectClass * oc,const void * data)1666 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc,
1667 const void *data)
1668 {
1669 MachineClass *mc = MACHINE_CLASS(oc);
1670 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1671
1672 mc->desc = "Facebook Tiogapass BMC (ARM1176)";
1673 amc->soc_name = "ast2500-a1";
1674 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1675 amc->hw_strap2 = 0;
1676 amc->fmc_model = "n25q256a";
1677 amc->spi_model = "mx25l25635e";
1678 amc->num_cs = 2;
1679 amc->i2c_init = tiogapass_bmc_i2c_init;
1680 mc->auto_create_sdcard = true;
1681 mc->default_ram_size = 1 * GiB;
1682 aspeed_machine_class_init_cpus_defaults(mc);
1683 };
1684
aspeed_machine_sonorapass_class_init(ObjectClass * oc,const void * data)1685 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc,
1686 const void *data)
1687 {
1688 MachineClass *mc = MACHINE_CLASS(oc);
1689 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1690
1691 mc->desc = "OCP SonoraPass BMC (ARM1176)";
1692 amc->soc_name = "ast2500-a1";
1693 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
1694 amc->fmc_model = "mx66l1g45g";
1695 amc->spi_model = "mx66l1g45g";
1696 amc->num_cs = 2;
1697 amc->i2c_init = sonorapass_bmc_i2c_init;
1698 mc->auto_create_sdcard = true;
1699 mc->default_ram_size = 512 * MiB;
1700 aspeed_machine_class_init_cpus_defaults(mc);
1701 };
1702
aspeed_machine_witherspoon_class_init(ObjectClass * oc,const void * data)1703 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc,
1704 const void *data)
1705 {
1706 MachineClass *mc = MACHINE_CLASS(oc);
1707 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1708
1709 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
1710 amc->soc_name = "ast2500-a1";
1711 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
1712 amc->fmc_model = "mx25l25635f";
1713 amc->spi_model = "mx66l1g45g";
1714 amc->num_cs = 2;
1715 amc->i2c_init = witherspoon_bmc_i2c_init;
1716 mc->auto_create_sdcard = true;
1717 mc->default_ram_size = 512 * MiB;
1718 aspeed_machine_class_init_cpus_defaults(mc);
1719 };
1720
aspeed_machine_ast2600_evb_class_init(ObjectClass * oc,const void * data)1721 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc,
1722 const void *data)
1723 {
1724 MachineClass *mc = MACHINE_CLASS(oc);
1725 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1726
1727 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)";
1728 amc->soc_name = "ast2600-a3";
1729 amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
1730 amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
1731 amc->fmc_model = "mx66u51235f";
1732 amc->spi_model = "mx66u51235f";
1733 amc->num_cs = 1;
1734 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
1735 ASPEED_MAC3_ON;
1736 amc->sdhci_wp_inverted = true;
1737 amc->i2c_init = ast2600_evb_i2c_init;
1738 mc->auto_create_sdcard = true;
1739 mc->default_ram_size = 1 * GiB;
1740 aspeed_machine_class_init_cpus_defaults(mc);
1741 aspeed_machine_ast2600_class_emmc_init(oc);
1742 };
1743
aspeed_machine_g220a_class_init(ObjectClass * oc,const void * data)1744 static void aspeed_machine_g220a_class_init(ObjectClass *oc, const void *data)
1745 {
1746 MachineClass *mc = MACHINE_CLASS(oc);
1747 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1748
1749 mc->desc = "Bytedance G220A BMC (ARM1176)";
1750 amc->soc_name = "ast2500-a1";
1751 amc->hw_strap1 = G220A_BMC_HW_STRAP1;
1752 amc->fmc_model = "n25q512a";
1753 amc->spi_model = "mx25l25635e";
1754 amc->num_cs = 2;
1755 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1756 amc->i2c_init = g220a_bmc_i2c_init;
1757 mc->auto_create_sdcard = true;
1758 mc->default_ram_size = 1024 * MiB;
1759 aspeed_machine_class_init_cpus_defaults(mc);
1760 };
1761
aspeed_machine_fp5280g2_class_init(ObjectClass * oc,const void * data)1762 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc,
1763 const void *data)
1764 {
1765 MachineClass *mc = MACHINE_CLASS(oc);
1766 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1767
1768 mc->desc = "Inspur FP5280G2 BMC (ARM1176)";
1769 amc->soc_name = "ast2500-a1";
1770 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1;
1771 amc->fmc_model = "n25q512a";
1772 amc->spi_model = "mx25l25635e";
1773 amc->num_cs = 2;
1774 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1775 amc->i2c_init = fp5280g2_bmc_i2c_init;
1776 mc->auto_create_sdcard = true;
1777 mc->default_ram_size = 512 * MiB;
1778 aspeed_machine_class_init_cpus_defaults(mc);
1779 };
1780
aspeed_machine_rainier_class_init(ObjectClass * oc,const void * data)1781 static void aspeed_machine_rainier_class_init(ObjectClass *oc, const void *data)
1782 {
1783 MachineClass *mc = MACHINE_CLASS(oc);
1784 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1785
1786 mc->desc = "IBM Rainier BMC (Cortex-A7)";
1787 amc->soc_name = "ast2600-a3";
1788 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
1789 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
1790 amc->fmc_model = "mx66l1g45g";
1791 amc->spi_model = "mx66l1g45g";
1792 amc->num_cs = 2;
1793 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1794 amc->i2c_init = rainier_bmc_i2c_init;
1795 mc->auto_create_sdcard = true;
1796 mc->default_ram_size = 1 * GiB;
1797 aspeed_machine_class_init_cpus_defaults(mc);
1798 aspeed_machine_ast2600_class_emmc_init(oc);
1799 };
1800
1801 #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
1802
aspeed_machine_fuji_class_init(ObjectClass * oc,const void * data)1803 static void aspeed_machine_fuji_class_init(ObjectClass *oc, const void *data)
1804 {
1805 MachineClass *mc = MACHINE_CLASS(oc);
1806 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1807
1808 mc->desc = "Facebook Fuji BMC (Cortex-A7)";
1809 amc->soc_name = "ast2600-a3";
1810 amc->hw_strap1 = FUJI_BMC_HW_STRAP1;
1811 amc->hw_strap2 = FUJI_BMC_HW_STRAP2;
1812 amc->fmc_model = "mx66l1g45g";
1813 amc->spi_model = "mx66l1g45g";
1814 amc->num_cs = 2;
1815 amc->macs_mask = ASPEED_MAC3_ON;
1816 amc->i2c_init = fuji_bmc_i2c_init;
1817 amc->uart_default = ASPEED_DEV_UART1;
1818 mc->auto_create_sdcard = true;
1819 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1820 aspeed_machine_class_init_cpus_defaults(mc);
1821 };
1822
1823 #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
1824
aspeed_machine_bletchley_class_init(ObjectClass * oc,const void * data)1825 static void aspeed_machine_bletchley_class_init(ObjectClass *oc,
1826 const void *data)
1827 {
1828 MachineClass *mc = MACHINE_CLASS(oc);
1829 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1830
1831 mc->desc = "Facebook Bletchley BMC (Cortex-A7)";
1832 amc->soc_name = "ast2600-a3";
1833 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1;
1834 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2;
1835 amc->fmc_model = "w25q01jvq";
1836 amc->spi_model = NULL;
1837 amc->num_cs = 2;
1838 amc->macs_mask = ASPEED_MAC2_ON;
1839 amc->i2c_init = bletchley_bmc_i2c_init;
1840 mc->auto_create_sdcard = true;
1841 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
1842 aspeed_machine_class_init_cpus_defaults(mc);
1843 }
1844
aspeed_machine_catalina_class_init(ObjectClass * oc,const void * data)1845 static void aspeed_machine_catalina_class_init(ObjectClass *oc,
1846 const void *data)
1847 {
1848 MachineClass *mc = MACHINE_CLASS(oc);
1849 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1850
1851 mc->desc = "Facebook Catalina BMC (Cortex-A7)";
1852 amc->soc_name = "ast2600-a3";
1853 amc->hw_strap1 = CATALINA_BMC_HW_STRAP1;
1854 amc->hw_strap2 = CATALINA_BMC_HW_STRAP2;
1855 amc->fmc_model = "w25q01jvq";
1856 amc->spi_model = NULL;
1857 amc->num_cs = 2;
1858 amc->macs_mask = ASPEED_MAC2_ON;
1859 amc->i2c_init = catalina_bmc_i2c_init;
1860 mc->auto_create_sdcard = true;
1861 mc->default_ram_size = CATALINA_BMC_RAM_SIZE;
1862 aspeed_machine_class_init_cpus_defaults(mc);
1863 aspeed_machine_ast2600_class_emmc_init(oc);
1864 }
1865
1866 #define GB200NVL_BMC_RAM_SIZE ASPEED_RAM_SIZE(1 * GiB)
1867
aspeed_machine_gb200nvl_class_init(ObjectClass * oc,const void * data)1868 static void aspeed_machine_gb200nvl_class_init(ObjectClass *oc,
1869 const void *data)
1870 {
1871 MachineClass *mc = MACHINE_CLASS(oc);
1872 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1873
1874 mc->desc = "Nvidia GB200NVL BMC (Cortex-A7)";
1875 amc->soc_name = "ast2600-a3";
1876 amc->hw_strap1 = GB200NVL_BMC_HW_STRAP1;
1877 amc->hw_strap2 = GB200NVL_BMC_HW_STRAP2;
1878 amc->fmc_model = "mx66u51235f";
1879 amc->spi_model = "mx66u51235f";
1880 amc->num_cs = 2;
1881
1882 amc->spi2_model = "mx66u51235f";
1883 amc->num_cs2 = 1;
1884 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1885 amc->i2c_init = gb200nvl_bmc_i2c_init;
1886 mc->default_ram_size = GB200NVL_BMC_RAM_SIZE;
1887 aspeed_machine_class_init_cpus_defaults(mc);
1888 aspeed_machine_ast2600_class_emmc_init(oc);
1889 }
1890
fby35_reset(MachineState * state,ResetType type)1891 static void fby35_reset(MachineState *state, ResetType type)
1892 {
1893 AspeedMachineState *bmc = ASPEED_MACHINE(state);
1894 AspeedGPIOState *gpio = &bmc->soc->gpio;
1895
1896 qemu_devices_reset(type);
1897
1898 /* Board ID: 7 (Class-1, 4 slots) */
1899 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal);
1900 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal);
1901 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal);
1902 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal);
1903
1904 /* Slot presence pins, inverse polarity. (False means present) */
1905 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal);
1906 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal);
1907 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal);
1908 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal);
1909
1910 /* Slot 12v power pins, normal polarity. (True means powered-on) */
1911 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal);
1912 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal);
1913 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal);
1914 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal);
1915 }
1916
aspeed_machine_fby35_class_init(ObjectClass * oc,const void * data)1917 static void aspeed_machine_fby35_class_init(ObjectClass *oc, const void *data)
1918 {
1919 MachineClass *mc = MACHINE_CLASS(oc);
1920 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1921
1922 mc->desc = "Facebook fby35 BMC (Cortex-A7)";
1923 mc->reset = fby35_reset;
1924 amc->fmc_model = "mx66l1g45g";
1925 amc->num_cs = 2;
1926 amc->macs_mask = ASPEED_MAC3_ON;
1927 amc->i2c_init = fby35_i2c_init;
1928 mc->auto_create_sdcard = true;
1929 /* FIXME: Replace this macro with something more general */
1930 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1931 aspeed_machine_class_init_cpus_defaults(mc);
1932 }
1933
1934 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
1935 /* Main SYSCLK frequency in Hz (200MHz) */
1936 #define SYSCLK_FRQ 200000000ULL
1937
aspeed_minibmc_machine_init(MachineState * machine)1938 static void aspeed_minibmc_machine_init(MachineState *machine)
1939 {
1940 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
1941 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
1942 Clock *sysclk;
1943
1944 sysclk = clock_new(OBJECT(machine), "SYSCLK");
1945 clock_set_hz(sysclk, SYSCLK_FRQ);
1946
1947 bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
1948 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
1949 object_unref(OBJECT(bmc->soc));
1950 qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk);
1951
1952 object_property_set_link(OBJECT(bmc->soc), "memory",
1953 OBJECT(get_system_memory()), &error_abort);
1954 connect_serial_hds_to_uarts(bmc);
1955 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
1956
1957 if (defaults_enabled()) {
1958 aspeed_board_init_flashes(&bmc->soc->fmc,
1959 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
1960 amc->num_cs,
1961 0);
1962
1963 aspeed_board_init_flashes(&bmc->soc->spi[0],
1964 bmc->spi_model ? bmc->spi_model : amc->spi_model,
1965 amc->num_cs, amc->num_cs);
1966
1967 aspeed_board_init_flashes(&bmc->soc->spi[1],
1968 bmc->spi_model ? bmc->spi_model : amc->spi_model,
1969 amc->num_cs, (amc->num_cs * 2));
1970 }
1971
1972 if (amc->i2c_init) {
1973 amc->i2c_init(bmc);
1974 }
1975
1976 armv7m_load_kernel(ARM_CPU(first_cpu),
1977 machine->kernel_filename,
1978 0,
1979 AST1030_INTERNAL_FLASH_SIZE);
1980 }
1981
ast1030_evb_i2c_init(AspeedMachineState * bmc)1982 static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
1983 {
1984 AspeedSoCState *soc = bmc->soc;
1985
1986 /* U10 24C08 connects to SDA/SCL Group 1 by default */
1987 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
1988 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf);
1989
1990 /* U11 LM75 connects to SDA/SCL Group 2 by default */
1991 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d);
1992 }
1993
aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass * oc,const void * data)1994 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
1995 const void *data)
1996 {
1997 MachineClass *mc = MACHINE_CLASS(oc);
1998 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1999
2000 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)";
2001 amc->soc_name = "ast1030-a1";
2002 amc->hw_strap1 = 0;
2003 amc->hw_strap2 = 0;
2004 mc->init = aspeed_minibmc_machine_init;
2005 amc->i2c_init = ast1030_evb_i2c_init;
2006 mc->default_ram_size = 0;
2007 amc->fmc_model = "w25q80bl";
2008 amc->spi_model = "w25q256";
2009 amc->num_cs = 2;
2010 amc->macs_mask = 0;
2011 aspeed_machine_class_init_cpus_defaults(mc);
2012 }
2013
2014 #ifdef TARGET_AARCH64
ast2700_evb_i2c_init(AspeedMachineState * bmc)2015 static void ast2700_evb_i2c_init(AspeedMachineState *bmc)
2016 {
2017 AspeedSoCState *soc = bmc->soc;
2018
2019 /* LM75 is compatible with TMP105 driver */
2020 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0),
2021 TYPE_TMP105, 0x4d);
2022 }
2023
aspeed_machine_ast2700a0_evb_class_init(ObjectClass * oc,const void * data)2024 static void aspeed_machine_ast2700a0_evb_class_init(ObjectClass *oc,
2025 const void *data)
2026 {
2027 MachineClass *mc = MACHINE_CLASS(oc);
2028 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
2029
2030 mc->alias = "ast2700-evb";
2031 mc->desc = "Aspeed AST2700 A0 EVB (Cortex-A35)";
2032 amc->soc_name = "ast2700-a0";
2033 amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
2034 amc->hw_strap2 = AST2700_EVB_HW_STRAP2;
2035 amc->fmc_model = "w25q01jvq";
2036 amc->spi_model = "w25q512jv";
2037 amc->num_cs = 2;
2038 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON;
2039 amc->uart_default = ASPEED_DEV_UART12;
2040 amc->i2c_init = ast2700_evb_i2c_init;
2041 amc->vbootrom = true;
2042 mc->auto_create_sdcard = true;
2043 mc->default_ram_size = 1 * GiB;
2044 aspeed_machine_class_init_cpus_defaults(mc);
2045 }
2046
aspeed_machine_ast2700a1_evb_class_init(ObjectClass * oc,const void * data)2047 static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc,
2048 const void *data)
2049 {
2050 MachineClass *mc = MACHINE_CLASS(oc);
2051 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
2052
2053 mc->desc = "Aspeed AST2700 A1 EVB (Cortex-A35)";
2054 amc->soc_name = "ast2700-a1";
2055 amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
2056 amc->hw_strap2 = AST2700_EVB_HW_STRAP2;
2057 amc->fmc_model = "w25q01jvq";
2058 amc->spi_model = "w25q512jv";
2059 amc->num_cs = 2;
2060 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON;
2061 amc->uart_default = ASPEED_DEV_UART12;
2062 amc->i2c_init = ast2700_evb_i2c_init;
2063 amc->vbootrom = true;
2064 mc->auto_create_sdcard = true;
2065 mc->default_ram_size = 1 * GiB;
2066 aspeed_machine_class_init_cpus_defaults(mc);
2067 }
2068 #endif
2069
aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass * oc,const void * data)2070 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
2071 const void *data)
2072 {
2073 MachineClass *mc = MACHINE_CLASS(oc);
2074 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
2075
2076 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)";
2077 amc->soc_name = "ast2600-a3";
2078 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
2079 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
2080 amc->fmc_model = "n25q512a";
2081 amc->spi_model = "n25q512a";
2082 amc->num_cs = 2;
2083 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
2084 amc->i2c_init = qcom_dc_scm_bmc_i2c_init;
2085 mc->auto_create_sdcard = true;
2086 mc->default_ram_size = 1 * GiB;
2087 aspeed_machine_class_init_cpus_defaults(mc);
2088 };
2089
aspeed_machine_qcom_firework_class_init(ObjectClass * oc,const void * data)2090 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
2091 const void *data)
2092 {
2093 MachineClass *mc = MACHINE_CLASS(oc);
2094 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
2095
2096 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)";
2097 amc->soc_name = "ast2600-a3";
2098 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
2099 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
2100 amc->fmc_model = "n25q512a";
2101 amc->spi_model = "n25q512a";
2102 amc->num_cs = 2;
2103 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
2104 amc->i2c_init = qcom_dc_scm_firework_i2c_init;
2105 mc->auto_create_sdcard = true;
2106 mc->default_ram_size = 1 * GiB;
2107 aspeed_machine_class_init_cpus_defaults(mc);
2108 };
2109
2110 static const TypeInfo aspeed_machine_types[] = {
2111 {
2112 .name = MACHINE_TYPE_NAME("palmetto-bmc"),
2113 .parent = TYPE_ASPEED_MACHINE,
2114 .class_init = aspeed_machine_palmetto_class_init,
2115 }, {
2116 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
2117 .parent = TYPE_ASPEED_MACHINE,
2118 .class_init = aspeed_machine_supermicrox11_bmc_class_init,
2119 }, {
2120 .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"),
2121 .parent = TYPE_ASPEED_MACHINE,
2122 .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init,
2123 }, {
2124 .name = MACHINE_TYPE_NAME("ast2500-evb"),
2125 .parent = TYPE_ASPEED_MACHINE,
2126 .class_init = aspeed_machine_ast2500_evb_class_init,
2127 }, {
2128 .name = MACHINE_TYPE_NAME("romulus-bmc"),
2129 .parent = TYPE_ASPEED_MACHINE,
2130 .class_init = aspeed_machine_romulus_class_init,
2131 }, {
2132 .name = MACHINE_TYPE_NAME("sonorapass-bmc"),
2133 .parent = TYPE_ASPEED_MACHINE,
2134 .class_init = aspeed_machine_sonorapass_class_init,
2135 }, {
2136 .name = MACHINE_TYPE_NAME("witherspoon-bmc"),
2137 .parent = TYPE_ASPEED_MACHINE,
2138 .class_init = aspeed_machine_witherspoon_class_init,
2139 }, {
2140 .name = MACHINE_TYPE_NAME("ast2600-evb"),
2141 .parent = TYPE_ASPEED_MACHINE,
2142 .class_init = aspeed_machine_ast2600_evb_class_init,
2143 }, {
2144 .name = MACHINE_TYPE_NAME("yosemitev2-bmc"),
2145 .parent = TYPE_ASPEED_MACHINE,
2146 .class_init = aspeed_machine_yosemitev2_class_init,
2147 }, {
2148 .name = MACHINE_TYPE_NAME("tiogapass-bmc"),
2149 .parent = TYPE_ASPEED_MACHINE,
2150 .class_init = aspeed_machine_tiogapass_class_init,
2151 }, {
2152 .name = MACHINE_TYPE_NAME("g220a-bmc"),
2153 .parent = TYPE_ASPEED_MACHINE,
2154 .class_init = aspeed_machine_g220a_class_init,
2155 }, {
2156 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"),
2157 .parent = TYPE_ASPEED_MACHINE,
2158 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init,
2159 }, {
2160 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"),
2161 .parent = TYPE_ASPEED_MACHINE,
2162 .class_init = aspeed_machine_qcom_firework_class_init,
2163 }, {
2164 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"),
2165 .parent = TYPE_ASPEED_MACHINE,
2166 .class_init = aspeed_machine_fp5280g2_class_init,
2167 }, {
2168 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
2169 .parent = TYPE_ASPEED_MACHINE,
2170 .class_init = aspeed_machine_quanta_q71l_class_init,
2171 }, {
2172 .name = MACHINE_TYPE_NAME("rainier-bmc"),
2173 .parent = TYPE_ASPEED_MACHINE,
2174 .class_init = aspeed_machine_rainier_class_init,
2175 }, {
2176 .name = MACHINE_TYPE_NAME("fuji-bmc"),
2177 .parent = TYPE_ASPEED_MACHINE,
2178 .class_init = aspeed_machine_fuji_class_init,
2179 }, {
2180 .name = MACHINE_TYPE_NAME("bletchley-bmc"),
2181 .parent = TYPE_ASPEED_MACHINE,
2182 .class_init = aspeed_machine_bletchley_class_init,
2183 }, {
2184 .name = MACHINE_TYPE_NAME("gb200nvl-bmc"),
2185 .parent = TYPE_ASPEED_MACHINE,
2186 .class_init = aspeed_machine_gb200nvl_class_init,
2187 }, {
2188 .name = MACHINE_TYPE_NAME("catalina-bmc"),
2189 .parent = TYPE_ASPEED_MACHINE,
2190 .class_init = aspeed_machine_catalina_class_init,
2191 }, {
2192 .name = MACHINE_TYPE_NAME("fby35-bmc"),
2193 .parent = MACHINE_TYPE_NAME("ast2600-evb"),
2194 .class_init = aspeed_machine_fby35_class_init,
2195 }, {
2196 .name = MACHINE_TYPE_NAME("ast1030-evb"),
2197 .parent = TYPE_ASPEED_MACHINE,
2198 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
2199 #ifdef TARGET_AARCH64
2200 }, {
2201 .name = MACHINE_TYPE_NAME("ast2700a0-evb"),
2202 .parent = TYPE_ASPEED_MACHINE,
2203 .class_init = aspeed_machine_ast2700a0_evb_class_init,
2204 }, {
2205 .name = MACHINE_TYPE_NAME("ast2700a1-evb"),
2206 .parent = TYPE_ASPEED_MACHINE,
2207 .class_init = aspeed_machine_ast2700a1_evb_class_init,
2208 #endif
2209 }, {
2210 .name = TYPE_ASPEED_MACHINE,
2211 .parent = TYPE_MACHINE,
2212 .instance_size = sizeof(AspeedMachineState),
2213 .instance_init = aspeed_machine_instance_init,
2214 .class_size = sizeof(AspeedMachineClass),
2215 .class_init = aspeed_machine_class_init,
2216 .abstract = true,
2217 }
2218 };
2219
2220 DEFINE_TYPES(aspeed_machine_types)
2221