1 /*
2 * ARM hflags
3 *
4 * This code is licensed under the GNU GPL v2 or later.
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
8 #include "qemu/osdep.h"
9 #include "cpu.h"
10 #include "internals.h"
11 #include "cpu-features.h"
12 #include "exec/translation-block.h"
13 #include "accel/tcg/cpu-ops.h"
14 #include "cpregs.h"
15
16 #define HELPER_H "tcg/helper.h"
17 #include "exec/helper-proto.h.inc"
18
fgt_svc(CPUARMState * env,int el)19 static inline bool fgt_svc(CPUARMState *env, int el)
20 {
21 /*
22 * Assuming fine-grained-traps are active, return true if we
23 * should be trapping on SVC instructions. Only AArch64 can
24 * trap on an SVC at EL1, but we don't need to special-case this
25 * because if this is AArch32 EL1 then arm_fgt_active() is false.
26 * We also know el is 0 or 1.
27 */
28 return el == 0 ?
29 FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0) :
30 FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1);
31 }
32
33 /* Return true if memory alignment should be enforced. */
aprofile_require_alignment(CPUARMState * env,int el,uint64_t sctlr)34 static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t sctlr)
35 {
36 #ifdef CONFIG_USER_ONLY
37 return false;
38 #else
39 /* Check the alignment enable bit. */
40 if (sctlr & SCTLR_A) {
41 return true;
42 }
43
44 /*
45 * With PMSA, when the MPU is disabled, all memory types in the
46 * default map are Normal, so don't need aligment enforcing.
47 */
48 if (arm_feature(env, ARM_FEATURE_PMSA)) {
49 return false;
50 }
51
52 /*
53 * With VMSA, if translation is disabled, then the default memory type
54 * is Device(-nGnRnE) instead of Normal, which requires that alignment
55 * be enforced. Since this affects all ram, it is most efficient
56 * to handle this during translation.
57 */
58 if (sctlr & SCTLR_M) {
59 /* Translation enabled: memory type in PTE via MAIR_ELx. */
60 return false;
61 }
62 if (el < 2 && (arm_hcr_el2_eff(env) & (HCR_DC | HCR_VM))) {
63 /* Stage 2 translation enabled: memory type in PTE. */
64 return false;
65 }
66 return true;
67 #endif
68 }
69
access_secure_reg(CPUARMState * env)70 bool access_secure_reg(CPUARMState *env)
71 {
72 bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
73 !arm_el_is_aa64(env, 3) &&
74 !(env->cp15.scr_el3 & SCR_NS));
75
76 return ret;
77 }
78
rebuild_hflags_common(CPUARMState * env,int fp_el,ARMMMUIdx mmu_idx,CPUARMTBFlags flags)79 static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
80 ARMMMUIdx mmu_idx,
81 CPUARMTBFlags flags)
82 {
83 DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el);
84 DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx));
85
86 if (arm_singlestep_active(env)) {
87 DP_TBFLAG_ANY(flags, SS_ACTIVE, 1);
88 }
89
90 return flags;
91 }
92
rebuild_hflags_common_32(CPUARMState * env,int fp_el,ARMMMUIdx mmu_idx,CPUARMTBFlags flags)93 static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el,
94 ARMMMUIdx mmu_idx,
95 CPUARMTBFlags flags)
96 {
97 bool sctlr_b = arm_sctlr_b(env);
98
99 if (sctlr_b) {
100 DP_TBFLAG_A32(flags, SCTLR__B, 1);
101 }
102 if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) {
103 DP_TBFLAG_ANY(flags, BE_DATA, 1);
104 }
105 DP_TBFLAG_A32(flags, NS, !access_secure_reg(env));
106
107 return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
108 }
109
rebuild_hflags_m32(CPUARMState * env,int fp_el,ARMMMUIdx mmu_idx)110 static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el,
111 ARMMMUIdx mmu_idx)
112 {
113 CPUARMTBFlags flags = {};
114 uint32_t ccr = env->v7m.ccr[env->v7m.secure];
115
116 /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */
117 if (ccr & R_V7M_CCR_UNALIGN_TRP_MASK) {
118 DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
119 }
120
121 if (arm_v7m_is_handler_mode(env)) {
122 DP_TBFLAG_M32(flags, HANDLER, 1);
123 }
124
125 /*
126 * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
127 * is suppressing them because the requested execution priority
128 * is less than 0.
129 */
130 if (arm_feature(env, ARM_FEATURE_V8) &&
131 !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) &&
132 (ccr & R_V7M_CCR_STKOFHFNMIGN_MASK))) {
133 DP_TBFLAG_M32(flags, STACKCHECK, 1);
134 }
135
136 if (arm_feature(env, ARM_FEATURE_M_SECURITY) && env->v7m.secure) {
137 DP_TBFLAG_M32(flags, SECURE, 1);
138 }
139
140 return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
141 }
142
143 /* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */
sme_fa64(CPUARMState * env,int el)144 static bool sme_fa64(CPUARMState *env, int el)
145 {
146 if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) {
147 return false;
148 }
149
150 if (el <= 1 && !el_is_in_host(env, el)) {
151 if (!FIELD_EX64(env->vfp.smcr_el[1], SMCR, FA64)) {
152 return false;
153 }
154 }
155 if (el <= 2 && arm_is_el2_enabled(env)) {
156 if (!FIELD_EX64(env->vfp.smcr_el[2], SMCR, FA64)) {
157 return false;
158 }
159 }
160 if (arm_feature(env, ARM_FEATURE_EL3)) {
161 if (!FIELD_EX64(env->vfp.smcr_el[3], SMCR, FA64)) {
162 return false;
163 }
164 }
165
166 return true;
167 }
168
rebuild_hflags_a32(CPUARMState * env,int fp_el,ARMMMUIdx mmu_idx)169 static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
170 ARMMMUIdx mmu_idx)
171 {
172 CPUARMTBFlags flags = {};
173 int el = arm_current_el(env);
174 uint64_t sctlr = arm_sctlr(env, el);
175
176 if (aprofile_require_alignment(env, el, sctlr)) {
177 DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
178 }
179
180 if (arm_el_is_aa64(env, 1)) {
181 DP_TBFLAG_A32(flags, VFPEN, 1);
182 }
183
184 if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) &&
185 (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
186 DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1);
187 }
188
189 if (arm_fgt_active(env, el)) {
190 DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
191 if (fgt_svc(env, el)) {
192 DP_TBFLAG_ANY(flags, FGT_SVC, 1);
193 }
194 }
195
196 if (env->uncached_cpsr & CPSR_IL) {
197 DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
198 }
199
200 /*
201 * The SME exception we are testing for is raised via
202 * AArch64.CheckFPAdvSIMDEnabled(), as called from
203 * AArch32.CheckAdvSIMDOrFPEnabled().
204 */
205 if (el == 0
206 && FIELD_EX64(env->svcr, SVCR, SM)
207 && (!arm_is_el2_enabled(env)
208 || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE)))
209 && arm_el_is_aa64(env, 1)
210 && !sme_fa64(env, el)) {
211 DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1);
212 }
213
214 return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
215 }
216
217 /*
218 * Return the exception level to which exceptions should be taken for ZT0.
219 * C.f. the ARM pseudocode function CheckSMEZT0Enabled, after the ZA check.
220 */
zt0_exception_el(CPUARMState * env,int el)221 static int zt0_exception_el(CPUARMState *env, int el)
222 {
223 #ifndef CONFIG_USER_ONLY
224 if (el <= 1
225 && !el_is_in_host(env, el)
226 && !FIELD_EX64(env->vfp.smcr_el[1], SMCR, EZT0)) {
227 return 1;
228 }
229 if (el <= 2
230 && arm_is_el2_enabled(env)
231 && !FIELD_EX64(env->vfp.smcr_el[2], SMCR, EZT0)) {
232 return 2;
233 }
234 if (arm_feature(env, ARM_FEATURE_EL3)
235 && !FIELD_EX64(env->vfp.smcr_el[3], SMCR, EZT0)) {
236 return 3;
237 }
238 #endif
239 return 0;
240 }
241
rebuild_hflags_a64(CPUARMState * env,int el,int fp_el,ARMMMUIdx mmu_idx)242 static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
243 ARMMMUIdx mmu_idx)
244 {
245 CPUARMTBFlags flags = {};
246 ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
247 uint64_t tcr = regime_tcr(env, mmu_idx);
248 uint64_t hcr = arm_hcr_el2_eff(env);
249 uint64_t sctlr;
250 int tbii, tbid;
251
252 DP_TBFLAG_ANY(flags, AARCH64_STATE, 1);
253
254 /* Get control bits for tagged addresses. */
255 tbid = aa64_va_parameter_tbi(tcr, mmu_idx);
256 tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx);
257
258 DP_TBFLAG_A64(flags, TBII, tbii);
259 DP_TBFLAG_A64(flags, TBID, tbid);
260
261 if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
262 int sve_el = sve_exception_el(env, el);
263
264 /*
265 * If either FP or SVE are disabled, translator does not need len.
266 * If SVE EL > FP EL, FP exception has precedence, and translator
267 * does not need SVE EL. Save potential re-translations by forcing
268 * the unneeded data to zero.
269 */
270 if (fp_el != 0) {
271 if (sve_el > fp_el) {
272 sve_el = 0;
273 }
274 } else if (sve_el == 0) {
275 DP_TBFLAG_A64(flags, VL, sve_vqm1_for_el(env, el));
276 }
277 DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el);
278 }
279 if (cpu_isar_feature(aa64_sme, env_archcpu(env))) {
280 int sme_el = sme_exception_el(env, el);
281 bool sm = FIELD_EX64(env->svcr, SVCR, SM);
282
283 DP_TBFLAG_A64(flags, SMEEXC_EL, sme_el);
284 if (sme_el == 0) {
285 /* Similarly, do not compute SVL if SME is disabled. */
286 int svl = sve_vqm1_for_el_sm(env, el, true);
287 DP_TBFLAG_A64(flags, SVL, svl);
288 if (sm) {
289 /* If SVE is disabled, we will not have set VL above. */
290 DP_TBFLAG_A64(flags, VL, svl);
291 }
292 }
293 if (sm) {
294 DP_TBFLAG_A64(flags, PSTATE_SM, 1);
295 DP_TBFLAG_A64(flags, SME_TRAP_NONSTREAMING, !sme_fa64(env, el));
296 }
297
298 if (FIELD_EX64(env->svcr, SVCR, ZA)) {
299 DP_TBFLAG_A64(flags, PSTATE_ZA, 1);
300 if (cpu_isar_feature(aa64_sme2, env_archcpu(env))) {
301 int zt0_el = zt0_exception_el(env, el);
302 DP_TBFLAG_A64(flags, ZT0EXC_EL, zt0_el);
303 }
304 }
305 }
306
307 sctlr = regime_sctlr(env, stage1);
308
309 if (aprofile_require_alignment(env, el, sctlr)) {
310 DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
311 }
312
313 if (arm_cpu_data_is_big_endian_a64(el, sctlr)) {
314 DP_TBFLAG_ANY(flags, BE_DATA, 1);
315 }
316
317 if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) {
318 /*
319 * In order to save space in flags, we record only whether
320 * pauth is "inactive", meaning all insns are implemented as
321 * a nop, or "active" when some action must be performed.
322 * The decision of which action to take is left to a helper.
323 */
324 if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) {
325 DP_TBFLAG_A64(flags, PAUTH_ACTIVE, 1);
326 }
327 }
328
329 if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
330 /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
331 if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) {
332 DP_TBFLAG_A64(flags, BT, 1);
333 }
334 }
335
336 if (cpu_isar_feature(aa64_lse2, env_archcpu(env))) {
337 if (sctlr & SCTLR_nAA) {
338 DP_TBFLAG_A64(flags, NAA, 1);
339 }
340 }
341
342 /* Compute the condition for using AccType_UNPRIV for LDTR et al. */
343 if (!(env->pstate & PSTATE_UAO)) {
344 switch (mmu_idx) {
345 case ARMMMUIdx_E10_1:
346 case ARMMMUIdx_E10_1_PAN:
347 /* FEAT_NV: NV,NV1 == 1,1 means we don't do UNPRIV accesses */
348 if ((hcr & (HCR_NV | HCR_NV1)) != (HCR_NV | HCR_NV1)) {
349 DP_TBFLAG_A64(flags, UNPRIV, 1);
350 }
351 break;
352 case ARMMMUIdx_E20_2:
353 case ARMMMUIdx_E20_2_PAN:
354 /*
355 * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
356 * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
357 */
358 if (env->cp15.hcr_el2 & HCR_TGE) {
359 DP_TBFLAG_A64(flags, UNPRIV, 1);
360 }
361 break;
362 default:
363 break;
364 }
365 }
366
367 if (env->pstate & PSTATE_IL) {
368 DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
369 }
370
371 if (arm_fgt_active(env, el)) {
372 DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
373 if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) {
374 DP_TBFLAG_A64(flags, TRAP_ERET, 1);
375 }
376 if (fgt_svc(env, el)) {
377 DP_TBFLAG_ANY(flags, FGT_SVC, 1);
378 }
379 }
380
381 /*
382 * ERET can also be trapped for FEAT_NV. arm_hcr_el2_eff() takes care
383 * of "is EL2 enabled" and the NV bit can only be set if FEAT_NV is present.
384 */
385 if (el == 1 && (hcr & HCR_NV)) {
386 DP_TBFLAG_A64(flags, TRAP_ERET, 1);
387 DP_TBFLAG_A64(flags, NV, 1);
388 if (hcr & HCR_NV1) {
389 DP_TBFLAG_A64(flags, NV1, 1);
390 }
391 if (hcr & HCR_NV2) {
392 DP_TBFLAG_A64(flags, NV2, 1);
393 if (hcr & HCR_E2H) {
394 DP_TBFLAG_A64(flags, NV2_MEM_E20, 1);
395 }
396 if (env->cp15.sctlr_el[2] & SCTLR_EE) {
397 DP_TBFLAG_A64(flags, NV2_MEM_BE, 1);
398 }
399 }
400 }
401
402 if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
403 /*
404 * Set MTE_ACTIVE if any access may be Checked, and leave clear
405 * if all accesses must be Unchecked:
406 * 1) If no TBI, then there are no tags in the address to check,
407 * 2) If Tag Check Override, then all accesses are Unchecked,
408 * 3) If Tag Check Fail == 0, then Checked access have no effect,
409 * 4) If no Allocation Tag Access, then all accesses are Unchecked.
410 */
411 if (allocation_tag_access_enabled(env, el, sctlr)) {
412 DP_TBFLAG_A64(flags, ATA, 1);
413 if (tbid
414 && !(env->pstate & PSTATE_TCO)
415 && (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) {
416 DP_TBFLAG_A64(flags, MTE_ACTIVE, 1);
417 if (!EX_TBFLAG_A64(flags, UNPRIV)) {
418 /*
419 * In non-unpriv contexts (eg EL0), unpriv load/stores
420 * act like normal ones; duplicate the MTE info to
421 * avoid translate-a64.c having to check UNPRIV to see
422 * whether it is OK to index into MTE_ACTIVE[].
423 */
424 DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1);
425 }
426 }
427 }
428 /* And again for unprivileged accesses, if required. */
429 if (EX_TBFLAG_A64(flags, UNPRIV)
430 && tbid
431 && !(env->pstate & PSTATE_TCO)
432 && (sctlr & SCTLR_TCF0)
433 && allocation_tag_access_enabled(env, 0, sctlr)) {
434 DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1);
435 }
436 /*
437 * For unpriv tag-setting accesses we also need ATA0. Again, in
438 * contexts where unpriv and normal insns are the same we
439 * duplicate the ATA bit to save effort for translate-a64.c.
440 */
441 if (EX_TBFLAG_A64(flags, UNPRIV)) {
442 if (allocation_tag_access_enabled(env, 0, sctlr)) {
443 DP_TBFLAG_A64(flags, ATA0, 1);
444 }
445 } else {
446 DP_TBFLAG_A64(flags, ATA0, EX_TBFLAG_A64(flags, ATA));
447 }
448 /* Cache TCMA as well as TBI. */
449 DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx));
450 }
451
452 if (env->vfp.fpcr & FPCR_AH) {
453 DP_TBFLAG_A64(flags, AH, 1);
454 }
455 if (env->vfp.fpcr & FPCR_NEP) {
456 /*
457 * In streaming-SVE without FA64, NEP behaves as if zero;
458 * compare pseudocode IsMerging()
459 */
460 if (!(EX_TBFLAG_A64(flags, PSTATE_SM) && !sme_fa64(env, el))) {
461 DP_TBFLAG_A64(flags, NEP, 1);
462 }
463 }
464
465 return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
466 }
467
rebuild_hflags_internal(CPUARMState * env)468 static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env)
469 {
470 int el = arm_current_el(env);
471 int fp_el = fp_exception_el(env, el);
472 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
473
474 if (is_a64(env)) {
475 return rebuild_hflags_a64(env, el, fp_el, mmu_idx);
476 } else if (arm_feature(env, ARM_FEATURE_M)) {
477 return rebuild_hflags_m32(env, fp_el, mmu_idx);
478 } else {
479 return rebuild_hflags_a32(env, fp_el, mmu_idx);
480 }
481 }
482
arm_rebuild_hflags(CPUARMState * env)483 void arm_rebuild_hflags(CPUARMState *env)
484 {
485 env->hflags = rebuild_hflags_internal(env);
486 }
487
488 /*
489 * If we have triggered a EL state change we can't rely on the
490 * translator having passed it to us, we need to recompute.
491 */
HELPER(rebuild_hflags_m32_newel)492 void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env)
493 {
494 int el = arm_current_el(env);
495 int fp_el = fp_exception_el(env, el);
496 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
497
498 env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
499 }
500
HELPER(rebuild_hflags_m32)501 void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el)
502 {
503 int fp_el = fp_exception_el(env, el);
504 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
505
506 env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
507 }
508
509 /*
510 * If we have triggered a EL state change we can't rely on the
511 * translator having passed it to us, we need to recompute.
512 */
HELPER(rebuild_hflags_a32_newel)513 void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env)
514 {
515 int el = arm_current_el(env);
516 int fp_el = fp_exception_el(env, el);
517 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
518 env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx);
519 }
520
HELPER(rebuild_hflags_a32)521 void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el)
522 {
523 int fp_el = fp_exception_el(env, el);
524 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
525
526 env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx);
527 }
528
HELPER(rebuild_hflags_a64)529 void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el)
530 {
531 int fp_el = fp_exception_el(env, el);
532 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
533
534 env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx);
535 }
536
assert_hflags_rebuild_correctly(CPUARMState * env)537 static void assert_hflags_rebuild_correctly(CPUARMState *env)
538 {
539 #ifdef CONFIG_DEBUG_TCG
540 CPUARMTBFlags c = env->hflags;
541 CPUARMTBFlags r = rebuild_hflags_internal(env);
542
543 if (unlikely(c.flags != r.flags || c.flags2 != r.flags2)) {
544 fprintf(stderr, "TCG hflags mismatch "
545 "(current:(0x%08x,0x%016" PRIx64 ")"
546 " rebuilt:(0x%08x,0x%016" PRIx64 ")\n",
547 c.flags, c.flags2, r.flags, r.flags2);
548 abort();
549 }
550 #endif
551 }
552
mve_no_pred(CPUARMState * env)553 static bool mve_no_pred(CPUARMState *env)
554 {
555 /*
556 * Return true if there is definitely no predication of MVE
557 * instructions by VPR or LTPSIZE. (Returning false even if there
558 * isn't any predication is OK; generated code will just be
559 * a little worse.)
560 * If the CPU does not implement MVE then this TB flag is always 0.
561 *
562 * NOTE: if you change this logic, the "recalculate s->mve_no_pred"
563 * logic in gen_update_fp_context() needs to be updated to match.
564 *
565 * We do not include the effect of the ECI bits here -- they are
566 * tracked in other TB flags. This simplifies the logic for
567 * "when did we emit code that changes the MVE_NO_PRED TB flag
568 * and thus need to end the TB?".
569 */
570 if (cpu_isar_feature(aa32_mve, env_archcpu(env))) {
571 return false;
572 }
573 if (env->v7m.vpr) {
574 return false;
575 }
576 if (env->v7m.ltpsize < 4) {
577 return false;
578 }
579 return true;
580 }
581
arm_get_tb_cpu_state(CPUState * cs)582 TCGTBCPUState arm_get_tb_cpu_state(CPUState *cs)
583 {
584 CPUARMState *env = cpu_env(cs);
585 CPUARMTBFlags flags;
586 vaddr pc;
587
588 assert_hflags_rebuild_correctly(env);
589 flags = env->hflags;
590
591 if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) {
592 pc = env->pc;
593 if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
594 DP_TBFLAG_A64(flags, BTYPE, env->btype);
595 }
596 } else {
597 pc = env->regs[15];
598
599 if (arm_feature(env, ARM_FEATURE_M)) {
600 if (arm_feature(env, ARM_FEATURE_M_SECURITY) &&
601 FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S)
602 != env->v7m.secure) {
603 DP_TBFLAG_M32(flags, FPCCR_S_WRONG, 1);
604 }
605
606 if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) &&
607 (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) ||
608 (env->v7m.secure &&
609 !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) {
610 /*
611 * ASPEN is set, but FPCA/SFPA indicate that there is no
612 * active FP context; we must create a new FP context before
613 * executing any FP insn.
614 */
615 DP_TBFLAG_M32(flags, NEW_FP_CTXT_NEEDED, 1);
616 }
617
618 bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK;
619 if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) {
620 DP_TBFLAG_M32(flags, LSPACT, 1);
621 }
622
623 if (mve_no_pred(env)) {
624 DP_TBFLAG_M32(flags, MVE_NO_PRED, 1);
625 }
626 } else {
627 /*
628 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
629 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
630 */
631 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
632 DP_TBFLAG_A32(flags, XSCALE_CPAR, env->cp15.c15_cpar);
633 } else {
634 DP_TBFLAG_A32(flags, VECLEN, env->vfp.vec_len);
635 DP_TBFLAG_A32(flags, VECSTRIDE, env->vfp.vec_stride);
636 }
637 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
638 DP_TBFLAG_A32(flags, VFPEN, 1);
639 }
640 }
641
642 DP_TBFLAG_AM32(flags, THUMB, env->thumb);
643 DP_TBFLAG_AM32(flags, CONDEXEC, env->condexec_bits);
644 }
645
646 /*
647 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
648 * states defined in the ARM ARM for software singlestep:
649 * SS_ACTIVE PSTATE.SS State
650 * 0 x Inactive (the TB flag for SS is always 0)
651 * 1 0 Active-pending
652 * 1 1 Active-not-pending
653 * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB.
654 */
655 if (EX_TBFLAG_ANY(flags, SS_ACTIVE) && (env->pstate & PSTATE_SS)) {
656 DP_TBFLAG_ANY(flags, PSTATE__SS, 1);
657 }
658
659 return (TCGTBCPUState){
660 .pc = pc,
661 .flags = flags.flags,
662 .cs_base = flags.flags2,
663 };
664 }
665