1 /*
2 * ARM11MPCore Snoop Control Unit (SCU) emulation
3 *
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Copyright (c) 2013 SUSE LINUX Products GmbH
6 * Written by Paul Brook and Andreas Färber
7 *
8 * This code is licensed under the GPL.
9 */
10
11 #include "qemu/osdep.h"
12 #include "hw/misc/arm11scu.h"
13 #include "hw/qdev-properties.h"
14 #include "qemu/log.h"
15 #include "qemu/module.h"
16
mpcore_scu_read(void * opaque,hwaddr offset,unsigned size)17 static uint64_t mpcore_scu_read(void *opaque, hwaddr offset,
18 unsigned size)
19 {
20 ARM11SCUState *s = (ARM11SCUState *)opaque;
21 int id;
22 /* SCU */
23 switch (offset) {
24 case 0x00: /* Control. */
25 return s->control;
26 case 0x04: /* Configuration. */
27 id = ((1 << s->num_cpu) - 1) << 4;
28 return id | (s->num_cpu - 1);
29 case 0x08: /* CPU status. */
30 return 0;
31 case 0x0c: /* Invalidate all. */
32 return 0;
33 default:
34 qemu_log_mask(LOG_GUEST_ERROR,
35 "mpcore_priv_read: Bad offset %x\n", (int)offset);
36 return 0;
37 }
38 }
39
mpcore_scu_write(void * opaque,hwaddr offset,uint64_t value,unsigned size)40 static void mpcore_scu_write(void *opaque, hwaddr offset,
41 uint64_t value, unsigned size)
42 {
43 ARM11SCUState *s = (ARM11SCUState *)opaque;
44 /* SCU */
45 switch (offset) {
46 case 0: /* Control register. */
47 s->control = value & 1;
48 break;
49 case 0x0c: /* Invalidate all. */
50 /* This is a no-op as cache is not emulated. */
51 break;
52 default:
53 qemu_log_mask(LOG_GUEST_ERROR,
54 "mpcore_priv_read: Bad offset %x\n", (int)offset);
55 }
56 }
57
58 static const MemoryRegionOps mpcore_scu_ops = {
59 .read = mpcore_scu_read,
60 .write = mpcore_scu_write,
61 .endianness = DEVICE_NATIVE_ENDIAN,
62 };
63
arm11_scu_realize(DeviceState * dev,Error ** errp)64 static void arm11_scu_realize(DeviceState *dev, Error **errp)
65 {
66 }
67
arm11_scu_init(Object * obj)68 static void arm11_scu_init(Object *obj)
69 {
70 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
71 ARM11SCUState *s = ARM11_SCU(obj);
72
73 memory_region_init_io(&s->iomem, OBJECT(s),
74 &mpcore_scu_ops, s, "mpcore-scu", 0x100);
75 sysbus_init_mmio(sbd, &s->iomem);
76 }
77
78 static Property arm11_scu_properties[] = {
79 DEFINE_PROP_UINT32("num-cpu", ARM11SCUState, num_cpu, 1),
80 DEFINE_PROP_END_OF_LIST()
81 };
82
arm11_scu_class_init(ObjectClass * oc,void * data)83 static void arm11_scu_class_init(ObjectClass *oc, void *data)
84 {
85 DeviceClass *dc = DEVICE_CLASS(oc);
86
87 dc->realize = arm11_scu_realize;
88 device_class_set_props(dc, arm11_scu_properties);
89 }
90
91 static const TypeInfo arm11_scu_type_info = {
92 .name = TYPE_ARM11_SCU,
93 .parent = TYPE_SYS_BUS_DEVICE,
94 .instance_size = sizeof(ARM11SCUState),
95 .instance_init = arm11_scu_init,
96 .class_init = arm11_scu_class_init,
97 };
98
arm11_scu_register_types(void)99 static void arm11_scu_register_types(void)
100 {
101 type_register_static(&arm11_scu_type_info);
102 }
103
104 type_init(arm11_scu_register_types)
105