1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
4  */
5 #include <linux/kernel.h>
6 #include <linux/init.h>
7 #include <linux/syscore_ops.h>
8 #include <linux/amba/bus.h>
9 #include <linux/io.h>
10 #include <linux/irqchip.h>
11 #include <linux/of_irq.h>
12 #include <linux/of_address.h>
13 #include <linux/of_platform.h>
14 #include <linux/uaccess.h>
15 #include <linux/termios.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/regmap.h>
18 
19 #include <asm/mach/arch.h>
20 #include <asm/mach/map.h>
21 
22 #include "integrator-hardware.h"
23 #include "integrator-cm.h"
24 #include "integrator.h"
25 
26 /* Regmap to the AP system controller */
27 static struct regmap *ap_syscon_map;
28 
29 /*
30  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
31  * is the (PA >> 12).
32  *
33  * Setup a VA for the Integrator interrupt controller (for header #0,
34  * just for now).
35  */
36 #define VA_IC_BASE	__io_address(INTEGRATOR_IC_BASE)
37 
38 /*
39  * Logical      Physical
40  * f1400000	14000000	Interrupt controller
41  * f1600000	16000000	UART 0
42  */
43 
44 static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
45 	{
46 		.virtual	= IO_ADDRESS(INTEGRATOR_IC_BASE),
47 		.pfn		= __phys_to_pfn(INTEGRATOR_IC_BASE),
48 		.length		= SZ_4K,
49 		.type		= MT_DEVICE
50 	}, {
51 		.virtual	= IO_ADDRESS(INTEGRATOR_UART0_BASE),
52 		.pfn		= __phys_to_pfn(INTEGRATOR_UART0_BASE),
53 		.length		= SZ_4K,
54 		.type		= MT_DEVICE
55 	}
56 };
57 
ap_map_io(void)58 static void __init ap_map_io(void)
59 {
60 	iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
61 }
62 
63 #ifdef CONFIG_PM
64 static unsigned long ic_irq_enable;
65 
irq_suspend(void)66 static int irq_suspend(void)
67 {
68 	ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
69 	return 0;
70 }
71 
irq_resume(void)72 static void irq_resume(void)
73 {
74 	/* disable all irq sources */
75 	cm_clear_irqs();
76 	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
77 	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
78 
79 	writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
80 }
81 #else
82 #define irq_suspend NULL
83 #define irq_resume NULL
84 #endif
85 
86 static struct syscore_ops irq_syscore_ops = {
87 	.suspend	= irq_suspend,
88 	.resume		= irq_resume,
89 };
90 
irq_syscore_init(void)91 static int __init irq_syscore_init(void)
92 {
93 	register_syscore_ops(&irq_syscore_ops);
94 
95 	return 0;
96 }
97 
98 device_initcall(irq_syscore_init);
99 
100 /*
101  * For the PL010 found in the Integrator/AP some of the UART control is
102  * implemented in the system controller and accessed using a callback
103  * from the driver.
104  */
integrator_uart_set_mctrl(struct amba_device * dev,void __iomem * base,unsigned int mctrl)105 static void integrator_uart_set_mctrl(struct amba_device *dev,
106 				void __iomem *base, unsigned int mctrl)
107 {
108 	unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
109 	u32 phybase = dev->res.start;
110 	int ret;
111 
112 	if (phybase == INTEGRATOR_UART0_BASE) {
113 		/* UART0 */
114 		rts_mask = 1 << 4;
115 		dtr_mask = 1 << 5;
116 	} else {
117 		/* UART1 */
118 		rts_mask = 1 << 6;
119 		dtr_mask = 1 << 7;
120 	}
121 
122 	if (mctrl & TIOCM_RTS)
123 		ctrlc |= rts_mask;
124 	else
125 		ctrls |= rts_mask;
126 
127 	if (mctrl & TIOCM_DTR)
128 		ctrlc |= dtr_mask;
129 	else
130 		ctrls |= dtr_mask;
131 
132 	ret = regmap_write(ap_syscon_map,
133 			   INTEGRATOR_SC_CTRLS_OFFSET,
134 			   ctrls);
135 	if (ret)
136 		pr_err("MODEM: unable to write PL010 UART CTRLS\n");
137 
138 	ret = regmap_write(ap_syscon_map,
139 			   INTEGRATOR_SC_CTRLC_OFFSET,
140 			   ctrlc);
141 	if (ret)
142 		pr_err("MODEM: unable to write PL010 UART CRTLC\n");
143 }
144 
145 struct amba_pl010_data ap_uart_data = {
146 	.set_mctrl = integrator_uart_set_mctrl,
147 };
148 
ap_init_irq_of(void)149 static void __init ap_init_irq_of(void)
150 {
151 	cm_init();
152 	irqchip_init();
153 }
154 
155 /* For the Device Tree, add in the UART callbacks as AUXDATA */
156 static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
157 	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
158 		"uart0", &ap_uart_data),
159 	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
160 		"uart1", &ap_uart_data),
161 	{ /* sentinel */ },
162 };
163 
164 static const struct of_device_id ap_syscon_match[] = {
165 	{ .compatible = "arm,integrator-ap-syscon"},
166 	{ },
167 };
168 
ap_init_of(void)169 static void __init ap_init_of(void)
170 {
171 	struct device_node *syscon;
172 
173 	of_platform_default_populate(NULL, ap_auxdata_lookup, NULL);
174 
175 	syscon = of_find_matching_node(NULL, ap_syscon_match);
176 	if (!syscon)
177 		return;
178 	ap_syscon_map = syscon_node_to_regmap(syscon);
179 	if (IS_ERR(ap_syscon_map)) {
180 		pr_crit("could not find Integrator/AP system controller\n");
181 		return;
182 	}
183 }
184 
185 static const char * ap_dt_board_compat[] = {
186 	"arm,integrator-ap",
187 	NULL,
188 };
189 
190 DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
191 	.reserve	= integrator_reserve,
192 	.map_io		= ap_map_io,
193 	.init_irq	= ap_init_irq_of,
194 	.init_machine	= ap_init_of,
195 	.dt_compat      = ap_dt_board_compat,
196 MACHINE_END
197