1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/firmware.h>
25 #include <linux/slab.h>
26 #include <linux/module.h>
27 
28 #include "amdgpu.h"
29 #include "amdgpu_ucode.h"
30 
amdgpu_ucode_print_common_hdr(const struct common_firmware_header * hdr)31 static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr)
32 {
33 	DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
34 	DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes));
35 	DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major));
36 	DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor));
37 	DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));
38 	DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));
39 	DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));
40 	DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));
41 	DRM_DEBUG("ucode_array_offset_bytes: %u\n",
42 		  le32_to_cpu(hdr->ucode_array_offset_bytes));
43 	DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));
44 }
45 
amdgpu_ucode_print_mc_hdr(const struct common_firmware_header * hdr)46 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr)
47 {
48 	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
49 	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
50 
51 	DRM_DEBUG("MC\n");
52 	amdgpu_ucode_print_common_hdr(hdr);
53 
54 	if (version_major == 1) {
55 		const struct mc_firmware_header_v1_0 *mc_hdr =
56 			container_of(hdr, struct mc_firmware_header_v1_0, header);
57 
58 		DRM_DEBUG("io_debug_size_bytes: %u\n",
59 			  le32_to_cpu(mc_hdr->io_debug_size_bytes));
60 		DRM_DEBUG("io_debug_array_offset_bytes: %u\n",
61 			  le32_to_cpu(mc_hdr->io_debug_array_offset_bytes));
62 	} else {
63 		DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor);
64 	}
65 }
66 
amdgpu_ucode_print_smc_hdr(const struct common_firmware_header * hdr)67 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr)
68 {
69 	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
70 	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
71 	const struct smc_firmware_header_v1_0 *v1_0_hdr;
72 	const struct smc_firmware_header_v2_0 *v2_0_hdr;
73 	const struct smc_firmware_header_v2_1 *v2_1_hdr;
74 
75 	DRM_DEBUG("SMC\n");
76 	amdgpu_ucode_print_common_hdr(hdr);
77 
78 	if (version_major == 1) {
79 		v1_0_hdr = container_of(hdr, struct smc_firmware_header_v1_0, header);
80 		DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(v1_0_hdr->ucode_start_addr));
81 	} else if (version_major == 2) {
82 		switch (version_minor) {
83 		case 0:
84 			v2_0_hdr = container_of(hdr, struct smc_firmware_header_v2_0, v1_0.header);
85 			DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_offset_bytes));
86 			DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_size_bytes));
87 			break;
88 		case 1:
89 			v2_1_hdr = container_of(hdr, struct smc_firmware_header_v2_1, v1_0.header);
90 			DRM_DEBUG("pptable_count: %u\n", le32_to_cpu(v2_1_hdr->pptable_count));
91 			DRM_DEBUG("pptable_entry_offset: %u\n", le32_to_cpu(v2_1_hdr->pptable_entry_offset));
92 			break;
93 		default:
94 			break;
95 		}
96 
97 	} else {
98 		DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
99 	}
100 }
101 
amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header * hdr)102 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr)
103 {
104 	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
105 	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
106 
107 	DRM_DEBUG("GFX\n");
108 	amdgpu_ucode_print_common_hdr(hdr);
109 
110 	if (version_major == 1) {
111 		const struct gfx_firmware_header_v1_0 *gfx_hdr =
112 			container_of(hdr, struct gfx_firmware_header_v1_0, header);
113 
114 		DRM_DEBUG("ucode_feature_version: %u\n",
115 			  le32_to_cpu(gfx_hdr->ucode_feature_version));
116 		DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset));
117 		DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size));
118 	} else if (version_major == 2) {
119 		const struct gfx_firmware_header_v2_0 *gfx_hdr =
120 			container_of(hdr, struct gfx_firmware_header_v2_0, header);
121 
122 		DRM_DEBUG("ucode_feature_version: %u\n",
123 			  le32_to_cpu(gfx_hdr->ucode_feature_version));
124 	} else {
125 		DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
126 	}
127 }
128 
amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header * hdr)129 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
130 {
131 	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
132 	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
133 
134 	DRM_DEBUG("RLC\n");
135 	amdgpu_ucode_print_common_hdr(hdr);
136 
137 	if (version_major == 1) {
138 		const struct rlc_firmware_header_v1_0 *rlc_hdr =
139 			container_of(hdr, struct rlc_firmware_header_v1_0, header);
140 
141 		DRM_DEBUG("ucode_feature_version: %u\n",
142 			  le32_to_cpu(rlc_hdr->ucode_feature_version));
143 		DRM_DEBUG("save_and_restore_offset: %u\n",
144 			  le32_to_cpu(rlc_hdr->save_and_restore_offset));
145 		DRM_DEBUG("clear_state_descriptor_offset: %u\n",
146 			  le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
147 		DRM_DEBUG("avail_scratch_ram_locations: %u\n",
148 			  le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
149 		DRM_DEBUG("master_pkt_description_offset: %u\n",
150 			  le32_to_cpu(rlc_hdr->master_pkt_description_offset));
151 	} else if (version_major == 2) {
152 		const struct rlc_firmware_header_v2_0 *rlc_hdr =
153 			container_of(hdr, struct rlc_firmware_header_v2_0, header);
154 		const struct rlc_firmware_header_v2_1 *rlc_hdr_v2_1 =
155 			container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0);
156 		const struct rlc_firmware_header_v2_2 *rlc_hdr_v2_2 =
157 			container_of(rlc_hdr_v2_1, struct rlc_firmware_header_v2_2, v2_1);
158 		const struct rlc_firmware_header_v2_3 *rlc_hdr_v2_3 =
159 			container_of(rlc_hdr_v2_2, struct rlc_firmware_header_v2_3, v2_2);
160 		const struct rlc_firmware_header_v2_4 *rlc_hdr_v2_4 =
161 			container_of(rlc_hdr_v2_3, struct rlc_firmware_header_v2_4, v2_3);
162 
163 		switch (version_minor) {
164 		case 0:
165 			/* rlc_hdr v2_0 */
166 			DRM_DEBUG("ucode_feature_version: %u\n",
167 				  le32_to_cpu(rlc_hdr->ucode_feature_version));
168 			DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset));
169 			DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size));
170 			DRM_DEBUG("save_and_restore_offset: %u\n",
171 				  le32_to_cpu(rlc_hdr->save_and_restore_offset));
172 			DRM_DEBUG("clear_state_descriptor_offset: %u\n",
173 				  le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
174 			DRM_DEBUG("avail_scratch_ram_locations: %u\n",
175 				  le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
176 			DRM_DEBUG("reg_restore_list_size: %u\n",
177 				  le32_to_cpu(rlc_hdr->reg_restore_list_size));
178 			DRM_DEBUG("reg_list_format_start: %u\n",
179 				  le32_to_cpu(rlc_hdr->reg_list_format_start));
180 			DRM_DEBUG("reg_list_format_separate_start: %u\n",
181 				  le32_to_cpu(rlc_hdr->reg_list_format_separate_start));
182 			DRM_DEBUG("starting_offsets_start: %u\n",
183 				  le32_to_cpu(rlc_hdr->starting_offsets_start));
184 			DRM_DEBUG("reg_list_format_size_bytes: %u\n",
185 				  le32_to_cpu(rlc_hdr->reg_list_format_size_bytes));
186 			DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n",
187 				  le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
188 			DRM_DEBUG("reg_list_size_bytes: %u\n",
189 				  le32_to_cpu(rlc_hdr->reg_list_size_bytes));
190 			DRM_DEBUG("reg_list_array_offset_bytes: %u\n",
191 				  le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
192 			DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n",
193 				  le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes));
194 			DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n",
195 				  le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
196 			DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
197 				  le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
198 			DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n",
199 				  le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes));
200 			break;
201 		case 1:
202 			/* rlc_hdr v2_1 */
203 			DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n",
204 				  le32_to_cpu(rlc_hdr_v2_1->reg_list_format_direct_reg_list_length));
205 			DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n",
206 				  le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_ucode_ver));
207 			DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n",
208 				  le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_feature_ver));
209 			DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n",
210 				  le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_size_bytes));
211 			DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n",
212 				  le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_offset_bytes));
213 			DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n",
214 				  le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_ucode_ver));
215 			DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n",
216 				  le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_feature_ver));
217 			DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n",
218 				  le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_size_bytes));
219 			DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n",
220 				  le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_offset_bytes));
221 			DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n",
222 				  le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_ucode_ver));
223 			DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n",
224 				  le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_feature_ver));
225 			DRM_DEBUG("save_restore_list_srm_size_bytes %u\n",
226 				  le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_size_bytes));
227 			DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n",
228 				  le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_offset_bytes));
229 			break;
230 		case 2:
231 			/* rlc_hdr v2_2 */
232 			DRM_DEBUG("rlc_iram_ucode_size_bytes: %u\n",
233 				  le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_size_bytes));
234 			DRM_DEBUG("rlc_iram_ucode_offset_bytes: %u\n",
235 				  le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_offset_bytes));
236 			DRM_DEBUG("rlc_dram_ucode_size_bytes: %u\n",
237 				  le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_size_bytes));
238 			DRM_DEBUG("rlc_dram_ucode_offset_bytes: %u\n",
239 				  le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_offset_bytes));
240 			break;
241 		case 3:
242 			/* rlc_hdr v2_3 */
243 			DRM_DEBUG("rlcp_ucode_version: %u\n",
244 				  le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_version));
245 			DRM_DEBUG("rlcp_ucode_feature_version: %u\n",
246 				  le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_feature_version));
247 			DRM_DEBUG("rlcp_ucode_size_bytes: %u\n",
248 				  le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_size_bytes));
249 			DRM_DEBUG("rlcp_ucode_offset_bytes: %u\n",
250 				  le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_offset_bytes));
251 			DRM_DEBUG("rlcv_ucode_version: %u\n",
252 				  le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_version));
253 			DRM_DEBUG("rlcv_ucode_feature_version: %u\n",
254 				  le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_feature_version));
255 			DRM_DEBUG("rlcv_ucode_size_bytes: %u\n",
256 				  le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_size_bytes));
257 			DRM_DEBUG("rlcv_ucode_offset_bytes: %u\n",
258 				  le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_offset_bytes));
259 			break;
260 		case 4:
261 			/* rlc_hdr v2_4 */
262 			DRM_DEBUG("global_tap_delays_ucode_size_bytes :%u\n",
263 				  le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_size_bytes));
264 			DRM_DEBUG("global_tap_delays_ucode_offset_bytes: %u\n",
265 				  le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_offset_bytes));
266 			DRM_DEBUG("se0_tap_delays_ucode_size_bytes :%u\n",
267 				  le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_size_bytes));
268 			DRM_DEBUG("se0_tap_delays_ucode_offset_bytes: %u\n",
269 				  le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_offset_bytes));
270 			DRM_DEBUG("se1_tap_delays_ucode_size_bytes :%u\n",
271 				  le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_size_bytes));
272 			DRM_DEBUG("se1_tap_delays_ucode_offset_bytes: %u\n",
273 				  le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_offset_bytes));
274 			DRM_DEBUG("se2_tap_delays_ucode_size_bytes :%u\n",
275 				  le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_size_bytes));
276 			DRM_DEBUG("se2_tap_delays_ucode_offset_bytes: %u\n",
277 				  le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_offset_bytes));
278 			DRM_DEBUG("se3_tap_delays_ucode_size_bytes :%u\n",
279 				  le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_size_bytes));
280 			DRM_DEBUG("se3_tap_delays_ucode_offset_bytes: %u\n",
281 				  le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_offset_bytes));
282 			break;
283 		default:
284 			DRM_ERROR("Unknown RLC v2 ucode: v2.%u\n", version_minor);
285 			break;
286 		}
287 	} else {
288 		DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
289 	}
290 }
291 
amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header * hdr)292 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
293 {
294 	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
295 	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
296 
297 	DRM_DEBUG("SDMA\n");
298 	amdgpu_ucode_print_common_hdr(hdr);
299 
300 	if (version_major == 1) {
301 		const struct sdma_firmware_header_v1_0 *sdma_hdr =
302 			container_of(hdr, struct sdma_firmware_header_v1_0, header);
303 
304 		DRM_DEBUG("ucode_feature_version: %u\n",
305 			  le32_to_cpu(sdma_hdr->ucode_feature_version));
306 		DRM_DEBUG("ucode_change_version: %u\n",
307 			  le32_to_cpu(sdma_hdr->ucode_change_version));
308 		DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));
309 		DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));
310 		if (version_minor >= 1) {
311 			const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr =
312 				container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0);
313 			DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size));
314 		}
315 	} else if (version_major == 2) {
316 		const struct sdma_firmware_header_v2_0 *sdma_hdr =
317 			container_of(hdr, struct sdma_firmware_header_v2_0, header);
318 
319 		DRM_DEBUG("ucode_feature_version: %u\n",
320 			  le32_to_cpu(sdma_hdr->ucode_feature_version));
321 		DRM_DEBUG("ctx_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_offset));
322 		DRM_DEBUG("ctx_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_size));
323 		DRM_DEBUG("ctl_ucode_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_ucode_offset));
324 		DRM_DEBUG("ctl_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_offset));
325 		DRM_DEBUG("ctl_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_size));
326 	} else {
327 		DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",
328 			  version_major, version_minor);
329 	}
330 }
331 
amdgpu_ucode_print_psp_hdr(const struct common_firmware_header * hdr)332 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr)
333 {
334 	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
335 	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
336 	uint32_t fw_index;
337 	const struct psp_fw_bin_desc *desc;
338 
339 	DRM_DEBUG("PSP\n");
340 	amdgpu_ucode_print_common_hdr(hdr);
341 
342 	if (version_major == 1) {
343 		const struct psp_firmware_header_v1_0 *psp_hdr =
344 			container_of(hdr, struct psp_firmware_header_v1_0, header);
345 
346 		DRM_DEBUG("ucode_feature_version: %u\n",
347 			  le32_to_cpu(psp_hdr->sos.fw_version));
348 		DRM_DEBUG("sos_offset_bytes: %u\n",
349 			  le32_to_cpu(psp_hdr->sos.offset_bytes));
350 		DRM_DEBUG("sos_size_bytes: %u\n",
351 			  le32_to_cpu(psp_hdr->sos.size_bytes));
352 		if (version_minor == 1) {
353 			const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
354 				container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
355 			DRM_DEBUG("toc_header_version: %u\n",
356 				  le32_to_cpu(psp_hdr_v1_1->toc.fw_version));
357 			DRM_DEBUG("toc_offset_bytes: %u\n",
358 				  le32_to_cpu(psp_hdr_v1_1->toc.offset_bytes));
359 			DRM_DEBUG("toc_size_bytes: %u\n",
360 				  le32_to_cpu(psp_hdr_v1_1->toc.size_bytes));
361 			DRM_DEBUG("kdb_header_version: %u\n",
362 				  le32_to_cpu(psp_hdr_v1_1->kdb.fw_version));
363 			DRM_DEBUG("kdb_offset_bytes: %u\n",
364 				  le32_to_cpu(psp_hdr_v1_1->kdb.offset_bytes));
365 			DRM_DEBUG("kdb_size_bytes: %u\n",
366 				  le32_to_cpu(psp_hdr_v1_1->kdb.size_bytes));
367 		}
368 		if (version_minor == 2) {
369 			const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 =
370 				container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0);
371 			DRM_DEBUG("kdb_header_version: %u\n",
372 				  le32_to_cpu(psp_hdr_v1_2->kdb.fw_version));
373 			DRM_DEBUG("kdb_offset_bytes: %u\n",
374 				  le32_to_cpu(psp_hdr_v1_2->kdb.offset_bytes));
375 			DRM_DEBUG("kdb_size_bytes: %u\n",
376 				  le32_to_cpu(psp_hdr_v1_2->kdb.size_bytes));
377 		}
378 		if (version_minor == 3) {
379 			const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
380 				container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
381 			const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 =
382 				container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1);
383 			DRM_DEBUG("toc_header_version: %u\n",
384 				  le32_to_cpu(psp_hdr_v1_3->v1_1.toc.fw_version));
385 			DRM_DEBUG("toc_offset_bytes: %u\n",
386 				  le32_to_cpu(psp_hdr_v1_3->v1_1.toc.offset_bytes));
387 			DRM_DEBUG("toc_size_bytes: %u\n",
388 				  le32_to_cpu(psp_hdr_v1_3->v1_1.toc.size_bytes));
389 			DRM_DEBUG("kdb_header_version: %u\n",
390 				  le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.fw_version));
391 			DRM_DEBUG("kdb_offset_bytes: %u\n",
392 				  le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.offset_bytes));
393 			DRM_DEBUG("kdb_size_bytes: %u\n",
394 				  le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.size_bytes));
395 			DRM_DEBUG("spl_header_version: %u\n",
396 				  le32_to_cpu(psp_hdr_v1_3->spl.fw_version));
397 			DRM_DEBUG("spl_offset_bytes: %u\n",
398 				  le32_to_cpu(psp_hdr_v1_3->spl.offset_bytes));
399 			DRM_DEBUG("spl_size_bytes: %u\n",
400 				  le32_to_cpu(psp_hdr_v1_3->spl.size_bytes));
401 		}
402 	} else if (version_major == 2) {
403 		const struct psp_firmware_header_v2_0 *psp_hdr_v2_0 =
404 			 container_of(hdr, struct psp_firmware_header_v2_0, header);
405 		for (fw_index = 0; fw_index < le32_to_cpu(psp_hdr_v2_0->psp_fw_bin_count); fw_index++) {
406 			desc = &(psp_hdr_v2_0->psp_fw_bin[fw_index]);
407 			switch (desc->fw_type) {
408 			case PSP_FW_TYPE_PSP_SOS:
409 				DRM_DEBUG("psp_sos_version: %u\n",
410 					  le32_to_cpu(desc->fw_version));
411 				DRM_DEBUG("psp_sos_size_bytes: %u\n",
412 					  le32_to_cpu(desc->size_bytes));
413 				break;
414 			case PSP_FW_TYPE_PSP_SYS_DRV:
415 				DRM_DEBUG("psp_sys_drv_version: %u\n",
416 					  le32_to_cpu(desc->fw_version));
417 				DRM_DEBUG("psp_sys_drv_size_bytes: %u\n",
418 					  le32_to_cpu(desc->size_bytes));
419 				break;
420 			case PSP_FW_TYPE_PSP_KDB:
421 				DRM_DEBUG("psp_kdb_version: %u\n",
422 					  le32_to_cpu(desc->fw_version));
423 				DRM_DEBUG("psp_kdb_size_bytes: %u\n",
424 					  le32_to_cpu(desc->size_bytes));
425 				break;
426 			case PSP_FW_TYPE_PSP_TOC:
427 				DRM_DEBUG("psp_toc_version: %u\n",
428 					  le32_to_cpu(desc->fw_version));
429 				DRM_DEBUG("psp_toc_size_bytes: %u\n",
430 					  le32_to_cpu(desc->size_bytes));
431 				break;
432 			case PSP_FW_TYPE_PSP_SPL:
433 				DRM_DEBUG("psp_spl_version: %u\n",
434 					  le32_to_cpu(desc->fw_version));
435 				DRM_DEBUG("psp_spl_size_bytes: %u\n",
436 					  le32_to_cpu(desc->size_bytes));
437 				break;
438 			case PSP_FW_TYPE_PSP_RL:
439 				DRM_DEBUG("psp_rl_version: %u\n",
440 					  le32_to_cpu(desc->fw_version));
441 				DRM_DEBUG("psp_rl_size_bytes: %u\n",
442 					  le32_to_cpu(desc->size_bytes));
443 				break;
444 			case PSP_FW_TYPE_PSP_SOC_DRV:
445 				DRM_DEBUG("psp_soc_drv_version: %u\n",
446 					  le32_to_cpu(desc->fw_version));
447 				DRM_DEBUG("psp_soc_drv_size_bytes: %u\n",
448 					  le32_to_cpu(desc->size_bytes));
449 				break;
450 			case PSP_FW_TYPE_PSP_INTF_DRV:
451 				DRM_DEBUG("psp_intf_drv_version: %u\n",
452 					  le32_to_cpu(desc->fw_version));
453 				DRM_DEBUG("psp_intf_drv_size_bytes: %u\n",
454 					  le32_to_cpu(desc->size_bytes));
455 				break;
456 			case PSP_FW_TYPE_PSP_DBG_DRV:
457 				DRM_DEBUG("psp_dbg_drv_version: %u\n",
458 					  le32_to_cpu(desc->fw_version));
459 				DRM_DEBUG("psp_dbg_drv_size_bytes: %u\n",
460 					  le32_to_cpu(desc->size_bytes));
461 				break;
462 			case PSP_FW_TYPE_PSP_RAS_DRV:
463 				DRM_DEBUG("psp_ras_drv_version: %u\n",
464 					  le32_to_cpu(desc->fw_version));
465 				DRM_DEBUG("psp_ras_drv_size_bytes: %u\n",
466 					  le32_to_cpu(desc->size_bytes));
467 				break;
468 			default:
469 				DRM_DEBUG("Unsupported PSP fw type: %d\n", desc->fw_type);
470 				break;
471 			}
472 		}
473 	} else {
474 		DRM_ERROR("Unknown PSP ucode version: %u.%u\n",
475 			  version_major, version_minor);
476 	}
477 }
478 
amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header * hdr)479 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr)
480 {
481 	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
482 	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
483 
484 	DRM_DEBUG("GPU_INFO\n");
485 	amdgpu_ucode_print_common_hdr(hdr);
486 
487 	if (version_major == 1) {
488 		const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr =
489 			container_of(hdr, struct gpu_info_firmware_header_v1_0, header);
490 
491 		DRM_DEBUG("version_major: %u\n",
492 			  le16_to_cpu(gpu_info_hdr->version_major));
493 		DRM_DEBUG("version_minor: %u\n",
494 			  le16_to_cpu(gpu_info_hdr->version_minor));
495 	} else {
496 		DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor);
497 	}
498 }
499 
amdgpu_ucode_validate(const struct firmware * fw)500 static int amdgpu_ucode_validate(const struct firmware *fw)
501 {
502 	const struct common_firmware_header *hdr =
503 		(const struct common_firmware_header *)fw->data;
504 
505 	if (fw->size == le32_to_cpu(hdr->size_bytes))
506 		return 0;
507 
508 	return -EINVAL;
509 }
510 
amdgpu_ucode_hdr_version(union amdgpu_firmware_header * hdr,uint16_t hdr_major,uint16_t hdr_minor)511 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
512 				uint16_t hdr_major, uint16_t hdr_minor)
513 {
514 	if ((hdr->common.header_version_major == hdr_major) &&
515 		(hdr->common.header_version_minor == hdr_minor))
516 		return true;
517 	return false;
518 }
519 
520 enum amdgpu_firmware_load_type
amdgpu_ucode_get_load_type(struct amdgpu_device * adev,int load_type)521 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
522 {
523 	switch (adev->asic_type) {
524 #ifdef CONFIG_DRM_AMDGPU_SI
525 	case CHIP_TAHITI:
526 	case CHIP_PITCAIRN:
527 	case CHIP_VERDE:
528 	case CHIP_OLAND:
529 	case CHIP_HAINAN:
530 		return AMDGPU_FW_LOAD_DIRECT;
531 #endif
532 #ifdef CONFIG_DRM_AMDGPU_CIK
533 	case CHIP_BONAIRE:
534 	case CHIP_KAVERI:
535 	case CHIP_KABINI:
536 	case CHIP_HAWAII:
537 	case CHIP_MULLINS:
538 		return AMDGPU_FW_LOAD_DIRECT;
539 #endif
540 	case CHIP_TOPAZ:
541 	case CHIP_TONGA:
542 	case CHIP_FIJI:
543 	case CHIP_CARRIZO:
544 	case CHIP_STONEY:
545 	case CHIP_POLARIS10:
546 	case CHIP_POLARIS11:
547 	case CHIP_POLARIS12:
548 	case CHIP_VEGAM:
549 		return AMDGPU_FW_LOAD_SMU;
550 	case CHIP_CYAN_SKILLFISH:
551 		if (!(load_type &&
552 		      adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2))
553 			return AMDGPU_FW_LOAD_DIRECT;
554 		else
555 			return AMDGPU_FW_LOAD_PSP;
556 	default:
557 		if (!load_type)
558 			return AMDGPU_FW_LOAD_DIRECT;
559 		else
560 			return AMDGPU_FW_LOAD_PSP;
561 	}
562 }
563 
amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id)564 const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id)
565 {
566 	switch (ucode_id) {
567 	case AMDGPU_UCODE_ID_SDMA0:
568 		return "SDMA0";
569 	case AMDGPU_UCODE_ID_SDMA1:
570 		return "SDMA1";
571 	case AMDGPU_UCODE_ID_SDMA2:
572 		return "SDMA2";
573 	case AMDGPU_UCODE_ID_SDMA3:
574 		return "SDMA3";
575 	case AMDGPU_UCODE_ID_SDMA4:
576 		return "SDMA4";
577 	case AMDGPU_UCODE_ID_SDMA5:
578 		return "SDMA5";
579 	case AMDGPU_UCODE_ID_SDMA6:
580 		return "SDMA6";
581 	case AMDGPU_UCODE_ID_SDMA7:
582 		return "SDMA7";
583 	case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
584 		return "SDMA_CTX";
585 	case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
586 		return "SDMA_CTL";
587 	case AMDGPU_UCODE_ID_CP_CE:
588 		return "CP_CE";
589 	case AMDGPU_UCODE_ID_CP_PFP:
590 		return "CP_PFP";
591 	case AMDGPU_UCODE_ID_CP_ME:
592 		return "CP_ME";
593 	case AMDGPU_UCODE_ID_CP_MEC1:
594 		return "CP_MEC1";
595 	case AMDGPU_UCODE_ID_CP_MEC1_JT:
596 		return "CP_MEC1_JT";
597 	case AMDGPU_UCODE_ID_CP_MEC2:
598 		return "CP_MEC2";
599 	case AMDGPU_UCODE_ID_CP_MEC2_JT:
600 		return "CP_MEC2_JT";
601 	case AMDGPU_UCODE_ID_CP_MES:
602 		return "CP_MES";
603 	case AMDGPU_UCODE_ID_CP_MES_DATA:
604 		return "CP_MES_DATA";
605 	case AMDGPU_UCODE_ID_CP_MES1:
606 		return "CP_MES_KIQ";
607 	case AMDGPU_UCODE_ID_CP_MES1_DATA:
608 		return "CP_MES_KIQ_DATA";
609 	case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
610 		return "RLC_RESTORE_LIST_CNTL";
611 	case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
612 		return "RLC_RESTORE_LIST_GPM_MEM";
613 	case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
614 		return "RLC_RESTORE_LIST_SRM_MEM";
615 	case AMDGPU_UCODE_ID_RLC_IRAM:
616 		return "RLC_IRAM";
617 	case AMDGPU_UCODE_ID_RLC_DRAM:
618 		return "RLC_DRAM";
619 	case AMDGPU_UCODE_ID_RLC_G:
620 		return "RLC_G";
621 	case AMDGPU_UCODE_ID_RLC_P:
622 		return "RLC_P";
623 	case AMDGPU_UCODE_ID_RLC_V:
624 		return "RLC_V";
625 	case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
626 		return "GLOBAL_TAP_DELAYS";
627 	case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
628 		return "SE0_TAP_DELAYS";
629 	case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
630 		return "SE1_TAP_DELAYS";
631 	case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
632 		return "SE2_TAP_DELAYS";
633 	case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
634 		return "SE3_TAP_DELAYS";
635 	case AMDGPU_UCODE_ID_IMU_I:
636 		return "IMU_I";
637 	case AMDGPU_UCODE_ID_IMU_D:
638 		return "IMU_D";
639 	case AMDGPU_UCODE_ID_STORAGE:
640 		return "STORAGE";
641 	case AMDGPU_UCODE_ID_SMC:
642 		return "SMC";
643 	case AMDGPU_UCODE_ID_PPTABLE:
644 		return "PPTABLE";
645 	case AMDGPU_UCODE_ID_UVD:
646 		return "UVD";
647 	case AMDGPU_UCODE_ID_UVD1:
648 		return "UVD1";
649 	case AMDGPU_UCODE_ID_VCE:
650 		return "VCE";
651 	case AMDGPU_UCODE_ID_VCN:
652 		return "VCN";
653 	case AMDGPU_UCODE_ID_VCN1:
654 		return "VCN1";
655 	case AMDGPU_UCODE_ID_DMCU_ERAM:
656 		return "DMCU_ERAM";
657 	case AMDGPU_UCODE_ID_DMCU_INTV:
658 		return "DMCU_INTV";
659 	case AMDGPU_UCODE_ID_VCN0_RAM:
660 		return "VCN0_RAM";
661 	case AMDGPU_UCODE_ID_VCN1_RAM:
662 		return "VCN1_RAM";
663 	case AMDGPU_UCODE_ID_DMCUB:
664 		return "DMCUB";
665 	case AMDGPU_UCODE_ID_CAP:
666 		return "CAP";
667 	default:
668 		return "UNKNOWN UCODE";
669 	}
670 }
671 
672 #define FW_VERSION_ATTR(name, mode, field)				\
673 static ssize_t show_##name(struct device *dev,				\
674 			  struct device_attribute *attr,		\
675 			  char *buf)					\
676 {									\
677 	struct drm_device *ddev = dev_get_drvdata(dev);			\
678 	struct amdgpu_device *adev = drm_to_adev(ddev);			\
679 									\
680 	return sysfs_emit(buf, "0x%08x\n", adev->field);	\
681 }									\
682 static DEVICE_ATTR(name, mode, show_##name, NULL)
683 
684 FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version);
685 FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version);
686 FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version);
687 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
688 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
689 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
690 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
691 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
692 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
693 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
694 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
695 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version);
696 FW_VERSION_ATTR(imu_fw_version, 0444, gfx.imu_fw_version);
697 FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos.fw_version);
698 FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_context.bin_desc.fw_version);
699 FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ras_context.context.bin_desc.fw_version);
700 FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.xgmi_context.context.bin_desc.fw_version);
701 FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version);
702 FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version);
703 FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version);
704 FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version);
705 FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version);
706 FW_VERSION_ATTR(mes_fw_version, 0444, mes.sched_version & AMDGPU_MES_VERSION_MASK);
707 FW_VERSION_ATTR(mes_kiq_fw_version, 0444, mes.kiq_version & AMDGPU_MES_VERSION_MASK);
708 
709 static struct attribute *fw_attrs[] = {
710 	&dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr,
711 	&dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr,
712 	&dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr,
713 	&dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr,
714 	&dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr,
715 	&dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr,
716 	&dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr,
717 	&dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr,
718 	&dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr,
719 	&dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr,
720 	&dev_attr_dmcu_fw_version.attr, &dev_attr_imu_fw_version.attr,
721 	&dev_attr_mes_fw_version.attr, &dev_attr_mes_kiq_fw_version.attr,
722 	NULL
723 };
724 
725 static const struct attribute_group fw_attr_group = {
726 	.name = "fw_version",
727 	.attrs = fw_attrs
728 };
729 
amdgpu_ucode_sysfs_init(struct amdgpu_device * adev)730 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev)
731 {
732 	return sysfs_create_group(&adev->dev->kobj, &fw_attr_group);
733 }
734 
amdgpu_ucode_sysfs_fini(struct amdgpu_device * adev)735 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev)
736 {
737 	sysfs_remove_group(&adev->dev->kobj, &fw_attr_group);
738 }
739 
amdgpu_ucode_init_single_fw(struct amdgpu_device * adev,struct amdgpu_firmware_info * ucode,uint64_t mc_addr,void * kptr)740 static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
741 				       struct amdgpu_firmware_info *ucode,
742 				       uint64_t mc_addr, void *kptr)
743 {
744 	const struct common_firmware_header *header = NULL;
745 	const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
746 	const struct gfx_firmware_header_v2_0 *cpv2_hdr = NULL;
747 	const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL;
748 	const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL;
749 	const struct mes_firmware_header_v1_0 *mes_hdr = NULL;
750 	const struct sdma_firmware_header_v2_0 *sdma_hdr = NULL;
751 	const struct imu_firmware_header_v1_0 *imu_hdr = NULL;
752 	u8 *ucode_addr;
753 
754 	if (!ucode->fw)
755 		return 0;
756 
757 	ucode->mc_addr = mc_addr;
758 	ucode->kaddr = kptr;
759 
760 	if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE)
761 		return 0;
762 
763 	header = (const struct common_firmware_header *)ucode->fw->data;
764 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
765 	cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)ucode->fw->data;
766 	dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data;
767 	dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data;
768 	mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data;
769 	sdma_hdr = (const struct sdma_firmware_header_v2_0 *)ucode->fw->data;
770 	imu_hdr = (const struct imu_firmware_header_v1_0 *)ucode->fw->data;
771 
772 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
773 		switch (ucode->ucode_id) {
774 		case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
775 			ucode->ucode_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes);
776 			ucode_addr = (u8 *)ucode->fw->data +
777 				le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes);
778 			break;
779 		case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
780 			ucode->ucode_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes);
781 			ucode_addr = (u8 *)ucode->fw->data +
782 				le32_to_cpu(sdma_hdr->ctl_ucode_offset);
783 			break;
784 		case AMDGPU_UCODE_ID_CP_MEC1:
785 		case AMDGPU_UCODE_ID_CP_MEC2:
786 			ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
787 				le32_to_cpu(cp_hdr->jt_size) * 4;
788 			ucode_addr = (u8 *)ucode->fw->data +
789 				le32_to_cpu(header->ucode_array_offset_bytes);
790 			break;
791 		case AMDGPU_UCODE_ID_CP_MEC1_JT:
792 		case AMDGPU_UCODE_ID_CP_MEC2_JT:
793 			ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4;
794 			ucode_addr = (u8 *)ucode->fw->data +
795 				le32_to_cpu(header->ucode_array_offset_bytes) +
796 				le32_to_cpu(cp_hdr->jt_offset) * 4;
797 			break;
798 		case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
799 			ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;
800 			ucode_addr = adev->gfx.rlc.save_restore_list_cntl;
801 			break;
802 		case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
803 			ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes;
804 			ucode_addr = adev->gfx.rlc.save_restore_list_gpm;
805 			break;
806 		case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
807 			ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;
808 			ucode_addr = adev->gfx.rlc.save_restore_list_srm;
809 			break;
810 		case AMDGPU_UCODE_ID_RLC_IRAM:
811 			ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes;
812 			ucode_addr = adev->gfx.rlc.rlc_iram_ucode;
813 			break;
814 		case AMDGPU_UCODE_ID_RLC_DRAM:
815 			ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes;
816 			ucode_addr = adev->gfx.rlc.rlc_dram_ucode;
817 			break;
818 		case AMDGPU_UCODE_ID_RLC_P:
819 			ucode->ucode_size = adev->gfx.rlc.rlcp_ucode_size_bytes;
820 			ucode_addr = adev->gfx.rlc.rlcp_ucode;
821 			break;
822 		case AMDGPU_UCODE_ID_RLC_V:
823 			ucode->ucode_size = adev->gfx.rlc.rlcv_ucode_size_bytes;
824 			ucode_addr = adev->gfx.rlc.rlcv_ucode;
825 			break;
826 		case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
827 			ucode->ucode_size = adev->gfx.rlc.global_tap_delays_ucode_size_bytes;
828 			ucode_addr = adev->gfx.rlc.global_tap_delays_ucode;
829 			break;
830 		case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
831 			ucode->ucode_size = adev->gfx.rlc.se0_tap_delays_ucode_size_bytes;
832 			ucode_addr = adev->gfx.rlc.se0_tap_delays_ucode;
833 			break;
834 		case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
835 			ucode->ucode_size = adev->gfx.rlc.se1_tap_delays_ucode_size_bytes;
836 			ucode_addr = adev->gfx.rlc.se1_tap_delays_ucode;
837 			break;
838 		case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
839 			ucode->ucode_size = adev->gfx.rlc.se2_tap_delays_ucode_size_bytes;
840 			ucode_addr = adev->gfx.rlc.se2_tap_delays_ucode;
841 			break;
842 		case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
843 			ucode->ucode_size = adev->gfx.rlc.se3_tap_delays_ucode_size_bytes;
844 			ucode_addr = adev->gfx.rlc.se3_tap_delays_ucode;
845 			break;
846 		case AMDGPU_UCODE_ID_CP_MES:
847 			ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
848 			ucode_addr = (u8 *)ucode->fw->data +
849 				le32_to_cpu(mes_hdr->mes_ucode_offset_bytes);
850 			break;
851 		case AMDGPU_UCODE_ID_CP_MES_DATA:
852 			ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
853 			ucode_addr = (u8 *)ucode->fw->data +
854 				le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes);
855 			break;
856 		case AMDGPU_UCODE_ID_CP_MES1:
857 			ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
858 			ucode_addr = (u8 *)ucode->fw->data +
859 				le32_to_cpu(mes_hdr->mes_ucode_offset_bytes);
860 			break;
861 		case AMDGPU_UCODE_ID_CP_MES1_DATA:
862 			ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
863 			ucode_addr = (u8 *)ucode->fw->data +
864 				le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes);
865 			break;
866 		case AMDGPU_UCODE_ID_DMCU_ERAM:
867 			ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
868 				le32_to_cpu(dmcu_hdr->intv_size_bytes);
869 			ucode_addr = (u8 *)ucode->fw->data +
870 				le32_to_cpu(header->ucode_array_offset_bytes);
871 			break;
872 		case AMDGPU_UCODE_ID_DMCU_INTV:
873 			ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes);
874 			ucode_addr = (u8 *)ucode->fw->data +
875 				le32_to_cpu(header->ucode_array_offset_bytes) +
876 				le32_to_cpu(dmcu_hdr->intv_offset_bytes);
877 			break;
878 		case AMDGPU_UCODE_ID_DMCUB:
879 			ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes);
880 			ucode_addr = (u8 *)ucode->fw->data +
881 				le32_to_cpu(header->ucode_array_offset_bytes);
882 			break;
883 		case AMDGPU_UCODE_ID_PPTABLE:
884 			ucode->ucode_size = ucode->fw->size;
885 			ucode_addr = (u8 *)ucode->fw->data;
886 			break;
887 		case AMDGPU_UCODE_ID_IMU_I:
888 			ucode->ucode_size = le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes);
889 			ucode_addr = (u8 *)ucode->fw->data +
890 				le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes);
891 			break;
892 		case AMDGPU_UCODE_ID_IMU_D:
893 			ucode->ucode_size = le32_to_cpu(imu_hdr->imu_dram_ucode_size_bytes);
894 			ucode_addr = (u8 *)ucode->fw->data +
895 				le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes) +
896 				le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes);
897 			break;
898 		case AMDGPU_UCODE_ID_CP_RS64_PFP:
899 			ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
900 			ucode_addr = (u8 *)ucode->fw->data +
901 				le32_to_cpu(header->ucode_array_offset_bytes);
902 			break;
903 		case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
904 			ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
905 			ucode_addr = (u8 *)ucode->fw->data +
906 				le32_to_cpu(cpv2_hdr->data_offset_bytes);
907 			break;
908 		case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
909 			ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
910 			ucode_addr = (u8 *)ucode->fw->data +
911 				le32_to_cpu(cpv2_hdr->data_offset_bytes);
912 			break;
913 		case AMDGPU_UCODE_ID_CP_RS64_ME:
914 			ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
915 			ucode_addr = (u8 *)ucode->fw->data +
916 				le32_to_cpu(header->ucode_array_offset_bytes);
917 			break;
918 		case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
919 			ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
920 			ucode_addr = (u8 *)ucode->fw->data +
921 				le32_to_cpu(cpv2_hdr->data_offset_bytes);
922 			break;
923 		case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
924 			ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
925 			ucode_addr = (u8 *)ucode->fw->data +
926 				le32_to_cpu(cpv2_hdr->data_offset_bytes);
927 			break;
928 		case AMDGPU_UCODE_ID_CP_RS64_MEC:
929 			ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
930 			ucode_addr = (u8 *)ucode->fw->data +
931 				le32_to_cpu(header->ucode_array_offset_bytes);
932 			break;
933 		case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
934 			ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
935 			ucode_addr = (u8 *)ucode->fw->data +
936 				le32_to_cpu(cpv2_hdr->data_offset_bytes);
937 			break;
938 		case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
939 			ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
940 			ucode_addr = (u8 *)ucode->fw->data +
941 				le32_to_cpu(cpv2_hdr->data_offset_bytes);
942 			break;
943 		case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
944 			ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
945 			ucode_addr = (u8 *)ucode->fw->data +
946 				le32_to_cpu(cpv2_hdr->data_offset_bytes);
947 			break;
948 		case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
949 			ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
950 			ucode_addr = (u8 *)ucode->fw->data +
951 				le32_to_cpu(cpv2_hdr->data_offset_bytes);
952 			break;
953 		default:
954 			ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
955 			ucode_addr = (u8 *)ucode->fw->data +
956 				le32_to_cpu(header->ucode_array_offset_bytes);
957 			break;
958 		}
959 	} else {
960 		ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
961 		ucode_addr = (u8 *)ucode->fw->data +
962 			le32_to_cpu(header->ucode_array_offset_bytes);
963 	}
964 
965 	memcpy(ucode->kaddr, ucode_addr, ucode->ucode_size);
966 
967 	return 0;
968 }
969 
amdgpu_ucode_patch_jt(struct amdgpu_firmware_info * ucode,uint64_t mc_addr,void * kptr)970 static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
971 				uint64_t mc_addr, void *kptr)
972 {
973 	const struct gfx_firmware_header_v1_0 *header = NULL;
974 	const struct common_firmware_header *comm_hdr = NULL;
975 	uint8_t *src_addr = NULL;
976 	uint8_t *dst_addr = NULL;
977 
978 	if (!ucode->fw)
979 		return 0;
980 
981 	comm_hdr = (const struct common_firmware_header *)ucode->fw->data;
982 	header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
983 	dst_addr = ucode->kaddr +
984 			   ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes),
985 			   PAGE_SIZE);
986 	src_addr = (uint8_t *)ucode->fw->data +
987 			   le32_to_cpu(comm_hdr->ucode_array_offset_bytes) +
988 			   (le32_to_cpu(header->jt_offset) * 4);
989 	memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4);
990 
991 	return 0;
992 }
993 
amdgpu_ucode_create_bo(struct amdgpu_device * adev)994 int amdgpu_ucode_create_bo(struct amdgpu_device *adev)
995 {
996 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) {
997 		amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
998 			amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
999 			&adev->firmware.fw_buf,
1000 			&adev->firmware.fw_buf_mc,
1001 			&adev->firmware.fw_buf_ptr);
1002 		if (!adev->firmware.fw_buf) {
1003 			dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n");
1004 			return -ENOMEM;
1005 		} else if (amdgpu_sriov_vf(adev)) {
1006 			memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
1007 		}
1008 	}
1009 	return 0;
1010 }
1011 
amdgpu_ucode_free_bo(struct amdgpu_device * adev)1012 void amdgpu_ucode_free_bo(struct amdgpu_device *adev)
1013 {
1014 	amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
1015 		&adev->firmware.fw_buf_mc,
1016 		&adev->firmware.fw_buf_ptr);
1017 }
1018 
amdgpu_ucode_init_bo(struct amdgpu_device * adev)1019 int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
1020 {
1021 	uint64_t fw_offset = 0;
1022 	int i;
1023 	struct amdgpu_firmware_info *ucode = NULL;
1024 
1025  /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */
1026 	if (!amdgpu_sriov_vf(adev) && (amdgpu_in_reset(adev) || adev->in_suspend))
1027 		return 0;
1028 	/*
1029 	 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
1030 	 * ucode info here
1031 	 */
1032 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1033 		if (amdgpu_sriov_vf(adev))
1034 			adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3;
1035 		else
1036 			adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4;
1037 	} else {
1038 		adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM;
1039 	}
1040 
1041 	for (i = 0; i < adev->firmware.max_ucodes; i++) {
1042 		ucode = &adev->firmware.ucode[i];
1043 		if (ucode->fw) {
1044 			amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset,
1045 						    adev->firmware.fw_buf_ptr + fw_offset);
1046 			if (i == AMDGPU_UCODE_ID_CP_MEC1 &&
1047 			    adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1048 				const struct gfx_firmware_header_v1_0 *cp_hdr;
1049 
1050 				cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
1051 				amdgpu_ucode_patch_jt(ucode,  adev->firmware.fw_buf_mc + fw_offset,
1052 						    adev->firmware.fw_buf_ptr + fw_offset);
1053 				fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
1054 			}
1055 			fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);
1056 		}
1057 	}
1058 	return 0;
1059 }
1060 
amdgpu_ucode_legacy_naming(struct amdgpu_device * adev,int block_type)1061 static const char *amdgpu_ucode_legacy_naming(struct amdgpu_device *adev, int block_type)
1062 {
1063 	if (block_type == MP0_HWIP) {
1064 		switch (adev->ip_versions[MP0_HWIP][0]) {
1065 		case IP_VERSION(9, 0, 0):
1066 			switch (adev->asic_type) {
1067 			case CHIP_VEGA10:
1068 				return "vega10";
1069 			case CHIP_VEGA12:
1070 				return "vega12";
1071 			default:
1072 				return NULL;
1073 			}
1074 		case IP_VERSION(10, 0, 0):
1075 		case IP_VERSION(10, 0, 1):
1076 			if (adev->asic_type == CHIP_RAVEN) {
1077 				if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1078 					return "raven2";
1079 				else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1080 					return "picasso";
1081 				return "raven";
1082 			}
1083 			break;
1084 		case IP_VERSION(11, 0, 0):
1085 			return "navi10";
1086 		case IP_VERSION(11, 0, 2):
1087 			return "vega20";
1088 		case IP_VERSION(11, 0, 3):
1089 			return "renoir";
1090 		case IP_VERSION(11, 0, 4):
1091 			return "arcturus";
1092 		case IP_VERSION(11, 0, 5):
1093 			return "navi14";
1094 		case IP_VERSION(11, 0, 7):
1095 			return "sienna_cichlid";
1096 		case IP_VERSION(11, 0, 9):
1097 			return "navi12";
1098 		case IP_VERSION(11, 0, 11):
1099 			return "navy_flounder";
1100 		case IP_VERSION(11, 0, 12):
1101 			return "dimgrey_cavefish";
1102 		case IP_VERSION(11, 0, 13):
1103 			return "beige_goby";
1104 		case IP_VERSION(11, 5, 0):
1105 			return "vangogh";
1106 		case IP_VERSION(12, 0, 1):
1107 			return "green_sardine";
1108 		case IP_VERSION(13, 0, 2):
1109 			return "aldebaran";
1110 		case IP_VERSION(13, 0, 1):
1111 		case IP_VERSION(13, 0, 3):
1112 			return "yellow_carp";
1113 		}
1114 	} else if (block_type == MP1_HWIP) {
1115 		switch (adev->ip_versions[MP1_HWIP][0]) {
1116 		case IP_VERSION(9, 0, 0):
1117 		case IP_VERSION(10, 0, 0):
1118 		case IP_VERSION(10, 0, 1):
1119 		case IP_VERSION(11, 0, 2):
1120 			if (adev->asic_type == CHIP_ARCTURUS)
1121 				return "arcturus_smc";
1122 			return NULL;
1123 		case IP_VERSION(11, 0, 0):
1124 			return "navi10_smc";
1125 		case IP_VERSION(11, 0, 5):
1126 			return "navi14_smc";
1127 		case IP_VERSION(11, 0, 9):
1128 			return "navi12_smc";
1129 		case IP_VERSION(11, 0, 7):
1130 			return "sienna_cichlid_smc";
1131 		case IP_VERSION(11, 0, 11):
1132 			return "navy_flounder_smc";
1133 		case IP_VERSION(11, 0, 12):
1134 			return "dimgrey_cavefish_smc";
1135 		case IP_VERSION(11, 0, 13):
1136 			return "beige_goby_smc";
1137 		case IP_VERSION(13, 0, 2):
1138 			return "aldebaran_smc";
1139 		}
1140 	} else if (block_type == SDMA0_HWIP) {
1141 		switch (adev->ip_versions[SDMA0_HWIP][0]) {
1142 		case IP_VERSION(4, 0, 0):
1143 			return "vega10_sdma";
1144 		case IP_VERSION(4, 0, 1):
1145 			return "vega12_sdma";
1146 		case IP_VERSION(4, 1, 0):
1147 		case IP_VERSION(4, 1, 1):
1148 			if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1149 				return "raven2_sdma";
1150 			else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1151 				return "picasso_sdma";
1152 			return "raven_sdma";
1153 		case IP_VERSION(4, 1, 2):
1154 			if (adev->apu_flags & AMD_APU_IS_RENOIR)
1155 				return "renoir_sdma";
1156 			return "green_sardine_sdma";
1157 		case IP_VERSION(4, 2, 0):
1158 			return "vega20_sdma";
1159 		case IP_VERSION(4, 2, 2):
1160 			return "arcturus_sdma";
1161 		case IP_VERSION(4, 4, 0):
1162 			return "aldebaran_sdma";
1163 		case IP_VERSION(5, 0, 0):
1164 			return "navi10_sdma";
1165 		case IP_VERSION(5, 0, 1):
1166 			return "cyan_skillfish2_sdma";
1167 		case IP_VERSION(5, 0, 2):
1168 			return "navi14_sdma";
1169 		case IP_VERSION(5, 0, 5):
1170 			return "navi12_sdma";
1171 		case IP_VERSION(5, 2, 0):
1172 			return "sienna_cichlid_sdma";
1173 		case IP_VERSION(5, 2, 2):
1174 			return "navy_flounder_sdma";
1175 		case IP_VERSION(5, 2, 4):
1176 			return "dimgrey_cavefish_sdma";
1177 		case IP_VERSION(5, 2, 5):
1178 			return "beige_goby_sdma";
1179 		case IP_VERSION(5, 2, 3):
1180 			return "yellow_carp_sdma";
1181 		case IP_VERSION(5, 2, 1):
1182 			return "vangogh_sdma";
1183 		}
1184 	} else if (block_type == UVD_HWIP) {
1185 		switch (adev->ip_versions[UVD_HWIP][0]) {
1186 		case IP_VERSION(1, 0, 0):
1187 		case IP_VERSION(1, 0, 1):
1188 			if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1189 				return "raven2_vcn";
1190 			else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1191 				return "picasso_vcn";
1192 			return "raven_vcn";
1193 		case IP_VERSION(2, 5, 0):
1194 			return "arcturus_vcn";
1195 		case IP_VERSION(2, 2, 0):
1196 			if (adev->apu_flags & AMD_APU_IS_RENOIR)
1197 				return "renoir_vcn";
1198 			return "green_sardine_vcn";
1199 		case IP_VERSION(2, 6, 0):
1200 			return "aldebaran_vcn";
1201 		case IP_VERSION(2, 0, 0):
1202 			return "navi10_vcn";
1203 		case IP_VERSION(2, 0, 2):
1204 			if (adev->asic_type == CHIP_NAVI12)
1205 				return "navi12_vcn";
1206 			return "navi14_vcn";
1207 		case IP_VERSION(3, 0, 0):
1208 		case IP_VERSION(3, 0, 64):
1209 		case IP_VERSION(3, 0, 192):
1210 			if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
1211 				return "sienna_cichlid_vcn";
1212 			return "navy_flounder_vcn";
1213 		case IP_VERSION(3, 0, 2):
1214 			return "vangogh_vcn";
1215 		case IP_VERSION(3, 0, 16):
1216 			return "dimgrey_cavefish_vcn";
1217 		case IP_VERSION(3, 0, 33):
1218 			return "beige_goby_vcn";
1219 		case IP_VERSION(3, 1, 1):
1220 			return "yellow_carp_vcn";
1221 		}
1222 	} else if (block_type == GC_HWIP) {
1223 		switch (adev->ip_versions[GC_HWIP][0]) {
1224 		case IP_VERSION(9, 0, 1):
1225 			return "vega10";
1226 		case IP_VERSION(9, 2, 1):
1227 			return "vega12";
1228 		case IP_VERSION(9, 4, 0):
1229 			return "vega20";
1230 		case IP_VERSION(9, 2, 2):
1231 		case IP_VERSION(9, 1, 0):
1232 			if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1233 				return "raven2";
1234 			else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1235 				return "picasso";
1236 			return "raven";
1237 		case IP_VERSION(9, 4, 1):
1238 			return "arcturus";
1239 		case IP_VERSION(9, 3, 0):
1240 			if (adev->apu_flags & AMD_APU_IS_RENOIR)
1241 				return "renoir";
1242 			return "green_sardine";
1243 		case IP_VERSION(9, 4, 2):
1244 			return "aldebaran";
1245 		case IP_VERSION(10, 1, 10):
1246 			return "navi10";
1247 		case IP_VERSION(10, 1, 1):
1248 			return "navi14";
1249 		case IP_VERSION(10, 1, 2):
1250 			return "navi12";
1251 		case IP_VERSION(10, 3, 0):
1252 			return "sienna_cichlid";
1253 		case IP_VERSION(10, 3, 2):
1254 			return "navy_flounder";
1255 		case IP_VERSION(10, 3, 1):
1256 			return "vangogh";
1257 		case IP_VERSION(10, 3, 4):
1258 			return "dimgrey_cavefish";
1259 		case IP_VERSION(10, 3, 5):
1260 			return "beige_goby";
1261 		case IP_VERSION(10, 3, 3):
1262 			return "yellow_carp";
1263 		case IP_VERSION(10, 1, 3):
1264 		case IP_VERSION(10, 1, 4):
1265 			return "cyan_skillfish2";
1266 		}
1267 	}
1268 	return NULL;
1269 }
1270 
amdgpu_ucode_ip_version_decode(struct amdgpu_device * adev,int block_type,char * ucode_prefix,int len)1271 void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len)
1272 {
1273 	int maj, min, rev;
1274 	char *ip_name;
1275 	const char *legacy;
1276 	uint32_t version = adev->ip_versions[block_type][0];
1277 
1278 	legacy = amdgpu_ucode_legacy_naming(adev, block_type);
1279 	if (legacy) {
1280 		snprintf(ucode_prefix, len, "%s", legacy);
1281 		return;
1282 	}
1283 
1284 	switch (block_type) {
1285 	case GC_HWIP:
1286 		ip_name = "gc";
1287 		break;
1288 	case SDMA0_HWIP:
1289 		ip_name = "sdma";
1290 		break;
1291 	case MP0_HWIP:
1292 		ip_name = "psp";
1293 		break;
1294 	case MP1_HWIP:
1295 		ip_name = "smu";
1296 		break;
1297 	case UVD_HWIP:
1298 		ip_name = "vcn";
1299 		break;
1300 	default:
1301 		BUG();
1302 	}
1303 
1304 	maj = IP_VERSION_MAJ(version);
1305 	min = IP_VERSION_MIN(version);
1306 	rev = IP_VERSION_REV(version);
1307 
1308 	snprintf(ucode_prefix, len, "%s_%d_%d_%d", ip_name, maj, min, rev);
1309 }
1310 
1311 /*
1312  * amdgpu_ucode_request - Fetch and validate amdgpu microcode
1313  *
1314  * @adev: amdgpu device
1315  * @fw: pointer to load firmware to
1316  * @fw_name: firmware to load
1317  *
1318  * This is a helper that will use request_firmware and amdgpu_ucode_validate
1319  * to load and run basic validation on firmware. If the load fails, remap
1320  * the error code to -ENODEV, so that early_init functions will fail to load.
1321  */
amdgpu_ucode_request(struct amdgpu_device * adev,const struct firmware ** fw,const char * fw_name)1322 int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw,
1323 			 const char *fw_name)
1324 {
1325 	int err = request_firmware(fw, fw_name, adev->dev);
1326 
1327 	if (err)
1328 		return -ENODEV;
1329 
1330 	err = amdgpu_ucode_validate(*fw);
1331 	if (err) {
1332 		dev_dbg(adev->dev, "\"%s\" failed to validate\n", fw_name);
1333 		release_firmware(*fw);
1334 		*fw = NULL;
1335 	}
1336 
1337 	return err;
1338 }
1339 
1340 /*
1341  * amdgpu_ucode_release - Release firmware microcode
1342  *
1343  * @fw: pointer to firmware to release
1344  */
amdgpu_ucode_release(const struct firmware ** fw)1345 void amdgpu_ucode_release(const struct firmware **fw)
1346 {
1347 	release_firmware(*fw);
1348 	*fw = NULL;
1349 }
1350