1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29 /**
30 * DOC: Interrupt Handling
31 *
32 * Interrupts generated within GPU hardware raise interrupt requests that are
33 * passed to amdgpu IRQ handler which is responsible for detecting source and
34 * type of the interrupt and dispatching matching handlers. If handling an
35 * interrupt requires calling kernel functions that may sleep processing is
36 * dispatched to work handlers.
37 *
38 * If MSI functionality is not disabled by module parameter then MSI
39 * support will be enabled.
40 *
41 * For GPU interrupt sources that may be driven by another driver, IRQ domain
42 * support is used (with mapping between virtual and hardware IRQs).
43 */
44
45 #include <linux/irq.h>
46 #include <linux/pci.h>
47
48 #include <drm/drm_vblank.h>
49 #include <drm/amdgpu_drm.h>
50 #include <drm/drm_drv.h>
51 #include "amdgpu.h"
52 #include "amdgpu_ih.h"
53 #include "atom.h"
54 #include "amdgpu_connectors.h"
55 #include "amdgpu_trace.h"
56 #include "amdgpu_amdkfd.h"
57 #include "amdgpu_ras.h"
58
59 #include <linux/pm_runtime.h>
60
61 #ifdef CONFIG_DRM_AMD_DC
62 #include "amdgpu_dm_irq.h"
63 #endif
64
65 #define AMDGPU_WAIT_IDLE_TIMEOUT 200
66
67 const char *soc15_ih_clientid_name[] = {
68 "IH",
69 "SDMA2 or ACP",
70 "ATHUB",
71 "BIF",
72 "SDMA3 or DCE",
73 "SDMA4 or ISP",
74 "VMC1 or PCIE0",
75 "RLC",
76 "SDMA0",
77 "SDMA1",
78 "SE0SH",
79 "SE1SH",
80 "SE2SH",
81 "SE3SH",
82 "VCN1 or UVD1",
83 "THM",
84 "VCN or UVD",
85 "SDMA5 or VCE0",
86 "VMC",
87 "SDMA6 or XDMA",
88 "GRBM_CP",
89 "ATS",
90 "ROM_SMUIO",
91 "DF",
92 "SDMA7 or VCE1",
93 "PWR",
94 "reserved",
95 "UTCL2",
96 "EA",
97 "UTCL2LOG",
98 "MP0",
99 "MP1"
100 };
101
102 const int node_id_to_phys_map[NODEID_MAX] = {
103 [AID0_NODEID] = 0,
104 [XCD0_NODEID] = 0,
105 [XCD1_NODEID] = 1,
106 [AID1_NODEID] = 1,
107 [XCD2_NODEID] = 2,
108 [XCD3_NODEID] = 3,
109 [AID2_NODEID] = 2,
110 [XCD4_NODEID] = 4,
111 [XCD5_NODEID] = 5,
112 [AID3_NODEID] = 3,
113 [XCD6_NODEID] = 6,
114 [XCD7_NODEID] = 7,
115 };
116
117 /**
118 * amdgpu_irq_disable_all - disable *all* interrupts
119 *
120 * @adev: amdgpu device pointer
121 *
122 * Disable all types of interrupts from all sources.
123 */
amdgpu_irq_disable_all(struct amdgpu_device * adev)124 void amdgpu_irq_disable_all(struct amdgpu_device *adev)
125 {
126 unsigned long irqflags;
127 unsigned int i, j, k;
128 int r;
129
130 spin_lock_irqsave(&adev->irq.lock, irqflags);
131 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
132 if (!adev->irq.client[i].sources)
133 continue;
134
135 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
136 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
137
138 if (!src || !src->funcs->set || !src->num_types)
139 continue;
140
141 for (k = 0; k < src->num_types; ++k) {
142 r = src->funcs->set(adev, src, k,
143 AMDGPU_IRQ_STATE_DISABLE);
144 if (r)
145 DRM_ERROR("error disabling interrupt (%d)\n",
146 r);
147 }
148 }
149 }
150 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
151 }
152
153 /**
154 * amdgpu_irq_handler - IRQ handler
155 *
156 * @irq: IRQ number (unused)
157 * @arg: pointer to DRM device
158 *
159 * IRQ handler for amdgpu driver (all ASICs).
160 *
161 * Returns:
162 * result of handling the IRQ, as defined by &irqreturn_t
163 */
amdgpu_irq_handler(int irq,void * arg)164 static irqreturn_t amdgpu_irq_handler(int irq, void *arg)
165 {
166 struct drm_device *dev = (struct drm_device *) arg;
167 struct amdgpu_device *adev = drm_to_adev(dev);
168 irqreturn_t ret;
169
170 ret = amdgpu_ih_process(adev, &adev->irq.ih);
171 if (ret == IRQ_HANDLED)
172 pm_runtime_mark_last_busy(dev->dev);
173
174 amdgpu_ras_interrupt_fatal_error_handler(adev);
175
176 return ret;
177 }
178
179 /**
180 * amdgpu_irq_handle_ih1 - kick of processing for IH1
181 *
182 * @work: work structure in struct amdgpu_irq
183 *
184 * Kick of processing IH ring 1.
185 */
amdgpu_irq_handle_ih1(struct work_struct * work)186 static void amdgpu_irq_handle_ih1(struct work_struct *work)
187 {
188 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
189 irq.ih1_work);
190
191 amdgpu_ih_process(adev, &adev->irq.ih1);
192 }
193
194 /**
195 * amdgpu_irq_handle_ih2 - kick of processing for IH2
196 *
197 * @work: work structure in struct amdgpu_irq
198 *
199 * Kick of processing IH ring 2.
200 */
amdgpu_irq_handle_ih2(struct work_struct * work)201 static void amdgpu_irq_handle_ih2(struct work_struct *work)
202 {
203 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
204 irq.ih2_work);
205
206 amdgpu_ih_process(adev, &adev->irq.ih2);
207 }
208
209 /**
210 * amdgpu_irq_handle_ih_soft - kick of processing for ih_soft
211 *
212 * @work: work structure in struct amdgpu_irq
213 *
214 * Kick of processing IH soft ring.
215 */
amdgpu_irq_handle_ih_soft(struct work_struct * work)216 static void amdgpu_irq_handle_ih_soft(struct work_struct *work)
217 {
218 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
219 irq.ih_soft_work);
220
221 amdgpu_ih_process(adev, &adev->irq.ih_soft);
222 }
223
224 /**
225 * amdgpu_msi_ok - check whether MSI functionality is enabled
226 *
227 * @adev: amdgpu device pointer (unused)
228 *
229 * Checks whether MSI functionality has been disabled via module parameter
230 * (all ASICs).
231 *
232 * Returns:
233 * *true* if MSIs are allowed to be enabled or *false* otherwise
234 */
amdgpu_msi_ok(struct amdgpu_device * adev)235 static bool amdgpu_msi_ok(struct amdgpu_device *adev)
236 {
237 if (amdgpu_msi == 1)
238 return true;
239 else if (amdgpu_msi == 0)
240 return false;
241
242 return true;
243 }
244
amdgpu_restore_msix(struct amdgpu_device * adev)245 static void amdgpu_restore_msix(struct amdgpu_device *adev)
246 {
247 u16 ctrl;
248
249 pci_read_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
250 if (!(ctrl & PCI_MSIX_FLAGS_ENABLE))
251 return;
252
253 /* VF FLR */
254 ctrl &= ~PCI_MSIX_FLAGS_ENABLE;
255 pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl);
256 ctrl |= PCI_MSIX_FLAGS_ENABLE;
257 pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl);
258 }
259
260 /**
261 * amdgpu_irq_init - initialize interrupt handling
262 *
263 * @adev: amdgpu device pointer
264 *
265 * Sets up work functions for hotplug and reset interrupts, enables MSI
266 * functionality, initializes vblank, hotplug and reset interrupt handling.
267 *
268 * Returns:
269 * 0 on success or error code on failure
270 */
amdgpu_irq_init(struct amdgpu_device * adev)271 int amdgpu_irq_init(struct amdgpu_device *adev)
272 {
273 int r = 0;
274 unsigned int irq;
275
276 spin_lock_init(&adev->irq.lock);
277
278 /* Enable MSI if not disabled by module parameter */
279 adev->irq.msi_enabled = false;
280
281 if (amdgpu_msi_ok(adev)) {
282 int nvec = pci_msix_vec_count(adev->pdev);
283 unsigned int flags;
284
285 if (nvec <= 0)
286 flags = PCI_IRQ_MSI;
287 else
288 flags = PCI_IRQ_MSI | PCI_IRQ_MSIX;
289
290 /* we only need one vector */
291 nvec = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags);
292 if (nvec > 0) {
293 adev->irq.msi_enabled = true;
294 dev_dbg(adev->dev, "using MSI/MSI-X.\n");
295 }
296 }
297
298 INIT_WORK(&adev->irq.ih1_work, amdgpu_irq_handle_ih1);
299 INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2);
300 INIT_WORK(&adev->irq.ih_soft_work, amdgpu_irq_handle_ih_soft);
301
302 /* Use vector 0 for MSI-X. */
303 r = pci_irq_vector(adev->pdev, 0);
304 if (r < 0)
305 return r;
306 irq = r;
307
308 /* PCI devices require shared interrupts. */
309 r = request_irq(irq, amdgpu_irq_handler, IRQF_SHARED, adev_to_drm(adev)->driver->name,
310 adev_to_drm(adev));
311 if (r)
312 return r;
313 adev->irq.installed = true;
314 adev->irq.irq = irq;
315 adev_to_drm(adev)->max_vblank_count = 0x00ffffff;
316
317 DRM_DEBUG("amdgpu: irq initialized.\n");
318 return 0;
319 }
320
321
amdgpu_irq_fini_hw(struct amdgpu_device * adev)322 void amdgpu_irq_fini_hw(struct amdgpu_device *adev)
323 {
324 if (adev->irq.installed) {
325 free_irq(adev->irq.irq, adev_to_drm(adev));
326 adev->irq.installed = false;
327 if (adev->irq.msi_enabled)
328 pci_free_irq_vectors(adev->pdev);
329 }
330
331 amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft);
332 amdgpu_ih_ring_fini(adev, &adev->irq.ih);
333 amdgpu_ih_ring_fini(adev, &adev->irq.ih1);
334 amdgpu_ih_ring_fini(adev, &adev->irq.ih2);
335 }
336
337 /**
338 * amdgpu_irq_fini_sw - shut down interrupt handling
339 *
340 * @adev: amdgpu device pointer
341 *
342 * Tears down work functions for hotplug and reset interrupts, disables MSI
343 * functionality, shuts down vblank, hotplug and reset interrupt handling,
344 * turns off interrupts from all sources (all ASICs).
345 */
amdgpu_irq_fini_sw(struct amdgpu_device * adev)346 void amdgpu_irq_fini_sw(struct amdgpu_device *adev)
347 {
348 unsigned int i, j;
349
350 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
351 if (!adev->irq.client[i].sources)
352 continue;
353
354 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
355 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
356
357 if (!src)
358 continue;
359
360 kfree(src->enabled_types);
361 src->enabled_types = NULL;
362 }
363 kfree(adev->irq.client[i].sources);
364 adev->irq.client[i].sources = NULL;
365 }
366 }
367
368 /**
369 * amdgpu_irq_add_id - register IRQ source
370 *
371 * @adev: amdgpu device pointer
372 * @client_id: client id
373 * @src_id: source id
374 * @source: IRQ source pointer
375 *
376 * Registers IRQ source on a client.
377 *
378 * Returns:
379 * 0 on success or error code otherwise
380 */
amdgpu_irq_add_id(struct amdgpu_device * adev,unsigned int client_id,unsigned int src_id,struct amdgpu_irq_src * source)381 int amdgpu_irq_add_id(struct amdgpu_device *adev,
382 unsigned int client_id, unsigned int src_id,
383 struct amdgpu_irq_src *source)
384 {
385 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX)
386 return -EINVAL;
387
388 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
389 return -EINVAL;
390
391 if (!source->funcs)
392 return -EINVAL;
393
394 if (!adev->irq.client[client_id].sources) {
395 adev->irq.client[client_id].sources =
396 kcalloc(AMDGPU_MAX_IRQ_SRC_ID,
397 sizeof(struct amdgpu_irq_src *),
398 GFP_KERNEL);
399 if (!adev->irq.client[client_id].sources)
400 return -ENOMEM;
401 }
402
403 if (adev->irq.client[client_id].sources[src_id] != NULL)
404 return -EINVAL;
405
406 if (source->num_types && !source->enabled_types) {
407 atomic_t *types;
408
409 types = kcalloc(source->num_types, sizeof(atomic_t),
410 GFP_KERNEL);
411 if (!types)
412 return -ENOMEM;
413
414 source->enabled_types = types;
415 }
416
417 adev->irq.client[client_id].sources[src_id] = source;
418 return 0;
419 }
420
421 /**
422 * amdgpu_irq_dispatch - dispatch IRQ to IP blocks
423 *
424 * @adev: amdgpu device pointer
425 * @ih: interrupt ring instance
426 *
427 * Dispatches IRQ to IP blocks.
428 */
amdgpu_irq_dispatch(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)429 void amdgpu_irq_dispatch(struct amdgpu_device *adev,
430 struct amdgpu_ih_ring *ih)
431 {
432 u32 ring_index = ih->rptr >> 2;
433 struct amdgpu_iv_entry entry;
434 unsigned int client_id, src_id;
435 struct amdgpu_irq_src *src;
436 bool handled = false;
437 int r;
438
439 entry.ih = ih;
440 entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
441
442 /*
443 * timestamp is not supported on some legacy SOCs (cik, cz, iceland,
444 * si and tonga), so initialize timestamp and timestamp_src to 0
445 */
446 entry.timestamp = 0;
447 entry.timestamp_src = 0;
448
449 amdgpu_ih_decode_iv(adev, &entry);
450
451 trace_amdgpu_iv(ih - &adev->irq.ih, &entry);
452
453 client_id = entry.client_id;
454 src_id = entry.src_id;
455
456 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) {
457 DRM_DEBUG("Invalid client_id in IV: %d\n", client_id);
458
459 } else if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
460 DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
461
462 } else if ((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) &&
463 adev->irq.virq[src_id]) {
464 generic_handle_domain_irq(adev->irq.domain, src_id);
465
466 } else if (!adev->irq.client[client_id].sources) {
467 DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n",
468 client_id, src_id);
469
470 } else if ((src = adev->irq.client[client_id].sources[src_id])) {
471 r = src->funcs->process(adev, src, &entry);
472 if (r < 0)
473 DRM_ERROR("error processing interrupt (%d)\n", r);
474 else if (r)
475 handled = true;
476
477 } else {
478 DRM_DEBUG("Unregistered interrupt src_id: %d of client_id:%d\n",
479 src_id, client_id);
480 }
481
482 /* Send it to amdkfd as well if it isn't already handled */
483 if (!handled)
484 amdgpu_amdkfd_interrupt(adev, entry.iv_entry);
485
486 if (amdgpu_ih_ts_after(ih->processed_timestamp, entry.timestamp))
487 ih->processed_timestamp = entry.timestamp;
488 }
489
490 /**
491 * amdgpu_irq_delegate - delegate IV to soft IH ring
492 *
493 * @adev: amdgpu device pointer
494 * @entry: IV entry
495 * @num_dw: size of IV
496 *
497 * Delegate the IV to the soft IH ring and schedule processing of it. Used
498 * if the hardware delegation to IH1 or IH2 doesn't work for some reason.
499 */
amdgpu_irq_delegate(struct amdgpu_device * adev,struct amdgpu_iv_entry * entry,unsigned int num_dw)500 void amdgpu_irq_delegate(struct amdgpu_device *adev,
501 struct amdgpu_iv_entry *entry,
502 unsigned int num_dw)
503 {
504 amdgpu_ih_ring_write(adev, &adev->irq.ih_soft, entry->iv_entry, num_dw);
505 schedule_work(&adev->irq.ih_soft_work);
506 }
507
508 /**
509 * amdgpu_irq_update - update hardware interrupt state
510 *
511 * @adev: amdgpu device pointer
512 * @src: interrupt source pointer
513 * @type: type of interrupt
514 *
515 * Updates interrupt state for the specific source (all ASICs).
516 */
amdgpu_irq_update(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type)517 int amdgpu_irq_update(struct amdgpu_device *adev,
518 struct amdgpu_irq_src *src, unsigned int type)
519 {
520 unsigned long irqflags;
521 enum amdgpu_interrupt_state state;
522 int r;
523
524 spin_lock_irqsave(&adev->irq.lock, irqflags);
525
526 /* We need to determine after taking the lock, otherwise
527 * we might disable just enabled interrupts again
528 */
529 if (amdgpu_irq_enabled(adev, src, type))
530 state = AMDGPU_IRQ_STATE_ENABLE;
531 else
532 state = AMDGPU_IRQ_STATE_DISABLE;
533
534 r = src->funcs->set(adev, src, type, state);
535 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
536 return r;
537 }
538
539 /**
540 * amdgpu_irq_gpu_reset_resume_helper - update interrupt states on all sources
541 *
542 * @adev: amdgpu device pointer
543 *
544 * Updates state of all types of interrupts on all sources on resume after
545 * reset.
546 */
amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device * adev)547 void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
548 {
549 int i, j, k;
550
551 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
552 amdgpu_restore_msix(adev);
553
554 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
555 if (!adev->irq.client[i].sources)
556 continue;
557
558 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
559 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
560
561 if (!src || !src->funcs || !src->funcs->set)
562 continue;
563 for (k = 0; k < src->num_types; k++)
564 amdgpu_irq_update(adev, src, k);
565 }
566 }
567 }
568
569 /**
570 * amdgpu_irq_get - enable interrupt
571 *
572 * @adev: amdgpu device pointer
573 * @src: interrupt source pointer
574 * @type: type of interrupt
575 *
576 * Enables specified type of interrupt on the specified source (all ASICs).
577 *
578 * Returns:
579 * 0 on success or error code otherwise
580 */
amdgpu_irq_get(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type)581 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
582 unsigned int type)
583 {
584 if (!adev->irq.installed)
585 return -ENOENT;
586
587 if (type >= src->num_types)
588 return -EINVAL;
589
590 if (!src->enabled_types || !src->funcs->set)
591 return -EINVAL;
592
593 if (atomic_inc_return(&src->enabled_types[type]) == 1)
594 return amdgpu_irq_update(adev, src, type);
595
596 return 0;
597 }
598
599 /**
600 * amdgpu_irq_put - disable interrupt
601 *
602 * @adev: amdgpu device pointer
603 * @src: interrupt source pointer
604 * @type: type of interrupt
605 *
606 * Enables specified type of interrupt on the specified source (all ASICs).
607 *
608 * Returns:
609 * 0 on success or error code otherwise
610 */
amdgpu_irq_put(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type)611 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
612 unsigned int type)
613 {
614 if (!adev->irq.installed)
615 return -ENOENT;
616
617 if (type >= src->num_types)
618 return -EINVAL;
619
620 if (!src->enabled_types || !src->funcs->set)
621 return -EINVAL;
622
623 if (WARN_ON(!amdgpu_irq_enabled(adev, src, type)))
624 return -EINVAL;
625
626 if (atomic_dec_and_test(&src->enabled_types[type]))
627 return amdgpu_irq_update(adev, src, type);
628
629 return 0;
630 }
631
632 /**
633 * amdgpu_irq_enabled - check whether interrupt is enabled or not
634 *
635 * @adev: amdgpu device pointer
636 * @src: interrupt source pointer
637 * @type: type of interrupt
638 *
639 * Checks whether the given type of interrupt is enabled on the given source.
640 *
641 * Returns:
642 * *true* if interrupt is enabled, *false* if interrupt is disabled or on
643 * invalid parameters
644 */
amdgpu_irq_enabled(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type)645 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
646 unsigned int type)
647 {
648 if (!adev->irq.installed)
649 return false;
650
651 if (type >= src->num_types)
652 return false;
653
654 if (!src->enabled_types || !src->funcs->set)
655 return false;
656
657 return !!atomic_read(&src->enabled_types[type]);
658 }
659
660 /* XXX: Generic IRQ handling */
amdgpu_irq_mask(struct irq_data * irqd)661 static void amdgpu_irq_mask(struct irq_data *irqd)
662 {
663 /* XXX */
664 }
665
amdgpu_irq_unmask(struct irq_data * irqd)666 static void amdgpu_irq_unmask(struct irq_data *irqd)
667 {
668 /* XXX */
669 }
670
671 /* amdgpu hardware interrupt chip descriptor */
672 static struct irq_chip amdgpu_irq_chip = {
673 .name = "amdgpu-ih",
674 .irq_mask = amdgpu_irq_mask,
675 .irq_unmask = amdgpu_irq_unmask,
676 };
677
678 /**
679 * amdgpu_irqdomain_map - create mapping between virtual and hardware IRQ numbers
680 *
681 * @d: amdgpu IRQ domain pointer (unused)
682 * @irq: virtual IRQ number
683 * @hwirq: hardware irq number
684 *
685 * Current implementation assigns simple interrupt handler to the given virtual
686 * IRQ.
687 *
688 * Returns:
689 * 0 on success or error code otherwise
690 */
amdgpu_irqdomain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)691 static int amdgpu_irqdomain_map(struct irq_domain *d,
692 unsigned int irq, irq_hw_number_t hwirq)
693 {
694 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID)
695 return -EPERM;
696
697 irq_set_chip_and_handler(irq,
698 &amdgpu_irq_chip, handle_simple_irq);
699 return 0;
700 }
701
702 /* Implementation of methods for amdgpu IRQ domain */
703 static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
704 .map = amdgpu_irqdomain_map,
705 };
706
707 /**
708 * amdgpu_irq_add_domain - create a linear IRQ domain
709 *
710 * @adev: amdgpu device pointer
711 *
712 * Creates an IRQ domain for GPU interrupt sources
713 * that may be driven by another driver (e.g., ACP).
714 *
715 * Returns:
716 * 0 on success or error code otherwise
717 */
amdgpu_irq_add_domain(struct amdgpu_device * adev)718 int amdgpu_irq_add_domain(struct amdgpu_device *adev)
719 {
720 adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID,
721 &amdgpu_hw_irqdomain_ops, adev);
722 if (!adev->irq.domain) {
723 DRM_ERROR("GPU irq add domain failed\n");
724 return -ENODEV;
725 }
726
727 return 0;
728 }
729
730 /**
731 * amdgpu_irq_remove_domain - remove the IRQ domain
732 *
733 * @adev: amdgpu device pointer
734 *
735 * Removes the IRQ domain for GPU interrupt sources
736 * that may be driven by another driver (e.g., ACP).
737 */
amdgpu_irq_remove_domain(struct amdgpu_device * adev)738 void amdgpu_irq_remove_domain(struct amdgpu_device *adev)
739 {
740 if (adev->irq.domain) {
741 irq_domain_remove(adev->irq.domain);
742 adev->irq.domain = NULL;
743 }
744 }
745
746 /**
747 * amdgpu_irq_create_mapping - create mapping between domain Linux IRQs
748 *
749 * @adev: amdgpu device pointer
750 * @src_id: IH source id
751 *
752 * Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQ
753 * Use this for components that generate a GPU interrupt, but are driven
754 * by a different driver (e.g., ACP).
755 *
756 * Returns:
757 * Linux IRQ
758 */
amdgpu_irq_create_mapping(struct amdgpu_device * adev,unsigned int src_id)759 unsigned int amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned int src_id)
760 {
761 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id);
762
763 return adev->irq.virq[src_id];
764 }
765