1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * based on nouveau_prime.c
23 *
24 * Authors: Alex Deucher
25 */
26
27 /**
28 * DOC: PRIME Buffer Sharing
29 *
30 * The following callback implementations are used for :ref:`sharing GEM buffer
31 * objects between different devices via PRIME <prime_buffer_sharing>`.
32 */
33
34 #include "amdgpu.h"
35 #include "amdgpu_display.h"
36 #include "amdgpu_gem.h"
37 #include "amdgpu_dma_buf.h"
38 #include "amdgpu_xgmi.h"
39 #include <drm/amdgpu_drm.h>
40 #include <drm/ttm/ttm_tt.h>
41 #include <linux/dma-buf.h>
42 #include <linux/dma-fence-array.h>
43 #include <linux/pci-p2pdma.h>
44 #include <linux/pm_runtime.h>
45
46 static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops;
47
48 /**
49 * dma_buf_attach_adev - Helper to get adev of an attachment
50 *
51 * @attach: attachment
52 *
53 * Returns:
54 * A struct amdgpu_device * if the attaching device is an amdgpu device or
55 * partition, NULL otherwise.
56 */
dma_buf_attach_adev(struct dma_buf_attachment * attach)57 static struct amdgpu_device *dma_buf_attach_adev(struct dma_buf_attachment *attach)
58 {
59 if (attach->importer_ops == &amdgpu_dma_buf_attach_ops) {
60 struct drm_gem_object *obj = attach->importer_priv;
61 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
62
63 return amdgpu_ttm_adev(bo->tbo.bdev);
64 }
65
66 return NULL;
67 }
68
69 /**
70 * amdgpu_dma_buf_attach - &dma_buf_ops.attach implementation
71 *
72 * @dmabuf: DMA-buf where we attach to
73 * @attach: attachment to add
74 *
75 * Add the attachment as user to the exported DMA-buf.
76 */
amdgpu_dma_buf_attach(struct dma_buf * dmabuf,struct dma_buf_attachment * attach)77 static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf,
78 struct dma_buf_attachment *attach)
79 {
80 struct amdgpu_device *attach_adev = dma_buf_attach_adev(attach);
81 struct drm_gem_object *obj = dmabuf->priv;
82 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
83 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
84 int r;
85
86 if (!amdgpu_dmabuf_is_xgmi_accessible(attach_adev, bo) &&
87 pci_p2pdma_distance(adev->pdev, attach->dev, false) < 0)
88 attach->peer2peer = false;
89
90 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
91 if (r < 0)
92 goto out;
93
94 return 0;
95
96 out:
97 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
98 return r;
99 }
100
101 /**
102 * amdgpu_dma_buf_detach - &dma_buf_ops.detach implementation
103 *
104 * @dmabuf: DMA-buf where we remove the attachment from
105 * @attach: the attachment to remove
106 *
107 * Called when an attachment is removed from the DMA-buf.
108 */
amdgpu_dma_buf_detach(struct dma_buf * dmabuf,struct dma_buf_attachment * attach)109 static void amdgpu_dma_buf_detach(struct dma_buf *dmabuf,
110 struct dma_buf_attachment *attach)
111 {
112 struct drm_gem_object *obj = dmabuf->priv;
113 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
114 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
115
116 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
117 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
118 }
119
120 /**
121 * amdgpu_dma_buf_pin - &dma_buf_ops.pin implementation
122 *
123 * @attach: attachment to pin down
124 *
125 * Pin the BO which is backing the DMA-buf so that it can't move any more.
126 */
amdgpu_dma_buf_pin(struct dma_buf_attachment * attach)127 static int amdgpu_dma_buf_pin(struct dma_buf_attachment *attach)
128 {
129 struct drm_gem_object *obj = attach->dmabuf->priv;
130 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
131
132 /* pin buffer into GTT */
133 return amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
134 }
135
136 /**
137 * amdgpu_dma_buf_unpin - &dma_buf_ops.unpin implementation
138 *
139 * @attach: attachment to unpin
140 *
141 * Unpin a previously pinned BO to make it movable again.
142 */
amdgpu_dma_buf_unpin(struct dma_buf_attachment * attach)143 static void amdgpu_dma_buf_unpin(struct dma_buf_attachment *attach)
144 {
145 struct drm_gem_object *obj = attach->dmabuf->priv;
146 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
147
148 amdgpu_bo_unpin(bo);
149 }
150
151 /**
152 * amdgpu_dma_buf_map - &dma_buf_ops.map_dma_buf implementation
153 * @attach: DMA-buf attachment
154 * @dir: DMA direction
155 *
156 * Makes sure that the shared DMA buffer can be accessed by the target device.
157 * For now, simply pins it to the GTT domain, where it should be accessible by
158 * all DMA devices.
159 *
160 * Returns:
161 * sg_table filled with the DMA addresses to use or ERR_PRT with negative error
162 * code.
163 */
amdgpu_dma_buf_map(struct dma_buf_attachment * attach,enum dma_data_direction dir)164 static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach,
165 enum dma_data_direction dir)
166 {
167 struct dma_buf *dma_buf = attach->dmabuf;
168 struct drm_gem_object *obj = dma_buf->priv;
169 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
170 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
171 struct sg_table *sgt;
172 long r;
173
174 if (!bo->tbo.pin_count) {
175 /* move buffer into GTT or VRAM */
176 struct ttm_operation_ctx ctx = { false, false };
177 unsigned int domains = AMDGPU_GEM_DOMAIN_GTT;
178
179 if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM &&
180 attach->peer2peer) {
181 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
182 domains |= AMDGPU_GEM_DOMAIN_VRAM;
183 }
184 amdgpu_bo_placement_from_domain(bo, domains);
185 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
186 if (r)
187 return ERR_PTR(r);
188
189 } else if (!(amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type) &
190 AMDGPU_GEM_DOMAIN_GTT)) {
191 return ERR_PTR(-EBUSY);
192 }
193
194 switch (bo->tbo.resource->mem_type) {
195 case TTM_PL_TT:
196 sgt = drm_prime_pages_to_sg(obj->dev,
197 bo->tbo.ttm->pages,
198 bo->tbo.ttm->num_pages);
199 if (IS_ERR(sgt))
200 return sgt;
201
202 if (dma_map_sgtable(attach->dev, sgt, dir,
203 DMA_ATTR_SKIP_CPU_SYNC))
204 goto error_free;
205 break;
206
207 case TTM_PL_VRAM:
208 r = amdgpu_vram_mgr_alloc_sgt(adev, bo->tbo.resource, 0,
209 bo->tbo.base.size, attach->dev,
210 dir, &sgt);
211 if (r)
212 return ERR_PTR(r);
213 break;
214 default:
215 return ERR_PTR(-EINVAL);
216 }
217
218 return sgt;
219
220 error_free:
221 sg_free_table(sgt);
222 kfree(sgt);
223 return ERR_PTR(-EBUSY);
224 }
225
226 /**
227 * amdgpu_dma_buf_unmap - &dma_buf_ops.unmap_dma_buf implementation
228 * @attach: DMA-buf attachment
229 * @sgt: sg_table to unmap
230 * @dir: DMA direction
231 *
232 * This is called when a shared DMA buffer no longer needs to be accessible by
233 * another device. For now, simply unpins the buffer from GTT.
234 */
amdgpu_dma_buf_unmap(struct dma_buf_attachment * attach,struct sg_table * sgt,enum dma_data_direction dir)235 static void amdgpu_dma_buf_unmap(struct dma_buf_attachment *attach,
236 struct sg_table *sgt,
237 enum dma_data_direction dir)
238 {
239 if (sg_page(sgt->sgl)) {
240 dma_unmap_sgtable(attach->dev, sgt, dir, 0);
241 sg_free_table(sgt);
242 kfree(sgt);
243 } else {
244 amdgpu_vram_mgr_free_sgt(attach->dev, dir, sgt);
245 }
246 }
247
248 /**
249 * amdgpu_dma_buf_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation
250 * @dma_buf: Shared DMA buffer
251 * @direction: Direction of DMA transfer
252 *
253 * This is called before CPU access to the shared DMA buffer's memory. If it's
254 * a read access, the buffer is moved to the GTT domain if possible, for optimal
255 * CPU read performance.
256 *
257 * Returns:
258 * 0 on success or a negative error code on failure.
259 */
amdgpu_dma_buf_begin_cpu_access(struct dma_buf * dma_buf,enum dma_data_direction direction)260 static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf,
261 enum dma_data_direction direction)
262 {
263 struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
264 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
265 struct ttm_operation_ctx ctx = { true, false };
266 u32 domain = amdgpu_display_supported_domains(adev, bo->flags);
267 int ret;
268 bool reads = (direction == DMA_BIDIRECTIONAL ||
269 direction == DMA_FROM_DEVICE);
270
271 if (!reads || !(domain & AMDGPU_GEM_DOMAIN_GTT))
272 return 0;
273
274 /* move to gtt */
275 ret = amdgpu_bo_reserve(bo, false);
276 if (unlikely(ret != 0))
277 return ret;
278
279 if (!bo->tbo.pin_count &&
280 (bo->allowed_domains & AMDGPU_GEM_DOMAIN_GTT)) {
281 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
282 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
283 }
284
285 amdgpu_bo_unreserve(bo);
286 return ret;
287 }
288
289 const struct dma_buf_ops amdgpu_dmabuf_ops = {
290 .attach = amdgpu_dma_buf_attach,
291 .detach = amdgpu_dma_buf_detach,
292 .pin = amdgpu_dma_buf_pin,
293 .unpin = amdgpu_dma_buf_unpin,
294 .map_dma_buf = amdgpu_dma_buf_map,
295 .unmap_dma_buf = amdgpu_dma_buf_unmap,
296 .release = drm_gem_dmabuf_release,
297 .begin_cpu_access = amdgpu_dma_buf_begin_cpu_access,
298 .mmap = drm_gem_dmabuf_mmap,
299 .vmap = drm_gem_dmabuf_vmap,
300 .vunmap = drm_gem_dmabuf_vunmap,
301 };
302
303 /**
304 * amdgpu_gem_prime_export - &drm_driver.gem_prime_export implementation
305 * @gobj: GEM BO
306 * @flags: Flags such as DRM_CLOEXEC and DRM_RDWR.
307 *
308 * The main work is done by the &drm_gem_prime_export helper.
309 *
310 * Returns:
311 * Shared DMA buffer representing the GEM BO from the given device.
312 */
amdgpu_gem_prime_export(struct drm_gem_object * gobj,int flags)313 struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj,
314 int flags)
315 {
316 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
317 struct dma_buf *buf;
318
319 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
320 bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
321 return ERR_PTR(-EPERM);
322
323 buf = drm_gem_prime_export(gobj, flags);
324 if (!IS_ERR(buf))
325 buf->ops = &amdgpu_dmabuf_ops;
326
327 return buf;
328 }
329
330 /**
331 * amdgpu_dma_buf_create_obj - create BO for DMA-buf import
332 *
333 * @dev: DRM device
334 * @dma_buf: DMA-buf
335 *
336 * Creates an empty SG BO for DMA-buf import.
337 *
338 * Returns:
339 * A new GEM BO of the given DRM device, representing the memory
340 * described by the given DMA-buf attachment and scatter/gather table.
341 */
342 static struct drm_gem_object *
amdgpu_dma_buf_create_obj(struct drm_device * dev,struct dma_buf * dma_buf)343 amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf)
344 {
345 struct dma_resv *resv = dma_buf->resv;
346 struct amdgpu_device *adev = drm_to_adev(dev);
347 struct drm_gem_object *gobj;
348 struct amdgpu_bo *bo;
349 uint64_t flags = 0;
350 int ret;
351
352 dma_resv_lock(resv, NULL);
353
354 if (dma_buf->ops == &amdgpu_dmabuf_ops) {
355 struct amdgpu_bo *other = gem_to_amdgpu_bo(dma_buf->priv);
356
357 flags |= other->flags & (AMDGPU_GEM_CREATE_CPU_GTT_USWC |
358 AMDGPU_GEM_CREATE_COHERENT |
359 AMDGPU_GEM_CREATE_UNCACHED);
360 }
361
362 ret = amdgpu_gem_object_create(adev, dma_buf->size, PAGE_SIZE,
363 AMDGPU_GEM_DOMAIN_CPU, flags,
364 ttm_bo_type_sg, resv, &gobj, 0);
365 if (ret)
366 goto error;
367
368 bo = gem_to_amdgpu_bo(gobj);
369 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
370 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
371
372 dma_resv_unlock(resv);
373 return gobj;
374
375 error:
376 dma_resv_unlock(resv);
377 return ERR_PTR(ret);
378 }
379
380 /**
381 * amdgpu_dma_buf_move_notify - &attach.move_notify implementation
382 *
383 * @attach: the DMA-buf attachment
384 *
385 * Invalidate the DMA-buf attachment, making sure that the we re-create the
386 * mapping before the next use.
387 */
388 static void
amdgpu_dma_buf_move_notify(struct dma_buf_attachment * attach)389 amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach)
390 {
391 struct drm_gem_object *obj = attach->importer_priv;
392 struct ww_acquire_ctx *ticket = dma_resv_locking_ctx(obj->resv);
393 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
394 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
395 struct ttm_operation_ctx ctx = { false, false };
396 struct ttm_placement placement = {};
397 struct amdgpu_vm_bo_base *bo_base;
398 int r;
399
400 if (!bo->tbo.resource || bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
401 return;
402
403 r = ttm_bo_validate(&bo->tbo, &placement, &ctx);
404 if (r) {
405 DRM_ERROR("Failed to invalidate DMA-buf import (%d))\n", r);
406 return;
407 }
408
409 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
410 struct amdgpu_vm *vm = bo_base->vm;
411 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
412
413 if (ticket) {
414 /* When we get an error here it means that somebody
415 * else is holding the VM lock and updating page tables
416 * So we can just continue here.
417 */
418 r = dma_resv_lock(resv, ticket);
419 if (r)
420 continue;
421
422 } else {
423 /* TODO: This is more problematic and we actually need
424 * to allow page tables updates without holding the
425 * lock.
426 */
427 if (!dma_resv_trylock(resv))
428 continue;
429 }
430
431 /* Reserve fences for two SDMA page table updates */
432 r = dma_resv_reserve_fences(resv, 2);
433 if (!r)
434 r = amdgpu_vm_clear_freed(adev, vm, NULL);
435 if (!r)
436 r = amdgpu_vm_handle_moved(adev, vm);
437
438 if (r && r != -EBUSY)
439 DRM_ERROR("Failed to invalidate VM page tables (%d))\n",
440 r);
441
442 dma_resv_unlock(resv);
443 }
444 }
445
446 static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops = {
447 .allow_peer2peer = true,
448 .move_notify = amdgpu_dma_buf_move_notify
449 };
450
451 /**
452 * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation
453 * @dev: DRM device
454 * @dma_buf: Shared DMA buffer
455 *
456 * Import a dma_buf into a the driver and potentially create a new GEM object.
457 *
458 * Returns:
459 * GEM BO representing the shared DMA buffer for the given device.
460 */
amdgpu_gem_prime_import(struct drm_device * dev,struct dma_buf * dma_buf)461 struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
462 struct dma_buf *dma_buf)
463 {
464 struct dma_buf_attachment *attach;
465 struct drm_gem_object *obj;
466
467 if (dma_buf->ops == &amdgpu_dmabuf_ops) {
468 obj = dma_buf->priv;
469 if (obj->dev == dev) {
470 /*
471 * Importing dmabuf exported from out own gem increases
472 * refcount on gem itself instead of f_count of dmabuf.
473 */
474 drm_gem_object_get(obj);
475 return obj;
476 }
477 }
478
479 obj = amdgpu_dma_buf_create_obj(dev, dma_buf);
480 if (IS_ERR(obj))
481 return obj;
482
483 attach = dma_buf_dynamic_attach(dma_buf, dev->dev,
484 &amdgpu_dma_buf_attach_ops, obj);
485 if (IS_ERR(attach)) {
486 drm_gem_object_put(obj);
487 return ERR_CAST(attach);
488 }
489
490 get_dma_buf(dma_buf);
491 obj->import_attach = attach;
492 return obj;
493 }
494
495 /**
496 * amdgpu_dmabuf_is_xgmi_accessible - Check if xgmi available for P2P transfer
497 *
498 * @adev: amdgpu_device pointer of the importer
499 * @bo: amdgpu buffer object
500 *
501 * Returns:
502 * True if dmabuf accessible over xgmi, false otherwise.
503 */
amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device * adev,struct amdgpu_bo * bo)504 bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev,
505 struct amdgpu_bo *bo)
506 {
507 struct drm_gem_object *obj = &bo->tbo.base;
508 struct drm_gem_object *gobj;
509
510 if (!adev)
511 return false;
512
513 if (obj->import_attach) {
514 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
515
516 if (dma_buf->ops != &amdgpu_dmabuf_ops)
517 /* No XGMI with non AMD GPUs */
518 return false;
519
520 gobj = dma_buf->priv;
521 bo = gem_to_amdgpu_bo(gobj);
522 }
523
524 if (amdgpu_xgmi_same_hive(adev, amdgpu_ttm_adev(bo->tbo.bdev)) &&
525 (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM))
526 return true;
527
528 return false;
529 }
530