1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27 #include <drm/amdgpu_drm.h>
28 #include "amdgpu.h"
29 #include "amdgpu_i2c.h"
30 #include "atom.h"
31 #include "amdgpu_connectors.h"
32 #include "amdgpu_display.h"
33 #include "soc15_common.h"
34 #include "gc/gc_11_0_0_offset.h"
35 #include "gc/gc_11_0_0_sh_mask.h"
36 #include <asm/div64.h>
37
38 #include <linux/pci.h>
39 #include <linux/pm_runtime.h>
40 #include <drm/drm_crtc_helper.h>
41 #include <drm/drm_damage_helper.h>
42 #include <drm/drm_drv.h>
43 #include <drm/drm_edid.h>
44 #include <drm/drm_fb_helper.h>
45 #include <drm/drm_gem_framebuffer_helper.h>
46 #include <drm/drm_fourcc.h>
47 #include <drm/drm_modeset_helper.h>
48 #include <drm/drm_vblank.h>
49
50 /**
51 * amdgpu_display_hotplug_work_func - work handler for display hotplug event
52 *
53 * @work: work struct pointer
54 *
55 * This is the hotplug event work handler (all ASICs).
56 * The work gets scheduled from the IRQ handler if there
57 * was a hotplug interrupt. It walks through the connector table
58 * and calls hotplug handler for each connector. After this, it sends
59 * a DRM hotplug event to alert userspace.
60 *
61 * This design approach is required in order to defer hotplug event handling
62 * from the IRQ handler to a work handler because hotplug handler has to use
63 * mutexes which cannot be locked in an IRQ handler (since &mutex_lock may
64 * sleep).
65 */
amdgpu_display_hotplug_work_func(struct work_struct * work)66 void amdgpu_display_hotplug_work_func(struct work_struct *work)
67 {
68 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
69 hotplug_work.work);
70 struct drm_device *dev = adev_to_drm(adev);
71 struct drm_mode_config *mode_config = &dev->mode_config;
72 struct drm_connector *connector;
73 struct drm_connector_list_iter iter;
74
75 mutex_lock(&mode_config->mutex);
76 drm_connector_list_iter_begin(dev, &iter);
77 drm_for_each_connector_iter(connector, &iter)
78 amdgpu_connector_hotplug(connector);
79 drm_connector_list_iter_end(&iter);
80 mutex_unlock(&mode_config->mutex);
81 /* Just fire off a uevent and let userspace tell us what to do */
82 drm_helper_hpd_irq_event(dev);
83 }
84
85 static int amdgpu_display_framebuffer_init(struct drm_device *dev,
86 struct amdgpu_framebuffer *rfb,
87 const struct drm_mode_fb_cmd2 *mode_cmd,
88 struct drm_gem_object *obj);
89
amdgpu_display_flip_callback(struct dma_fence * f,struct dma_fence_cb * cb)90 static void amdgpu_display_flip_callback(struct dma_fence *f,
91 struct dma_fence_cb *cb)
92 {
93 struct amdgpu_flip_work *work =
94 container_of(cb, struct amdgpu_flip_work, cb);
95
96 dma_fence_put(f);
97 schedule_work(&work->flip_work.work);
98 }
99
amdgpu_display_flip_handle_fence(struct amdgpu_flip_work * work,struct dma_fence ** f)100 static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work,
101 struct dma_fence **f)
102 {
103 struct dma_fence *fence = *f;
104
105 if (fence == NULL)
106 return false;
107
108 *f = NULL;
109
110 if (!dma_fence_add_callback(fence, &work->cb,
111 amdgpu_display_flip_callback))
112 return true;
113
114 dma_fence_put(fence);
115 return false;
116 }
117
amdgpu_display_flip_work_func(struct work_struct * __work)118 static void amdgpu_display_flip_work_func(struct work_struct *__work)
119 {
120 struct delayed_work *delayed_work =
121 container_of(__work, struct delayed_work, work);
122 struct amdgpu_flip_work *work =
123 container_of(delayed_work, struct amdgpu_flip_work, flip_work);
124 struct amdgpu_device *adev = work->adev;
125 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id];
126
127 struct drm_crtc *crtc = &amdgpu_crtc->base;
128 unsigned long flags;
129 unsigned int i;
130 int vpos, hpos;
131
132 for (i = 0; i < work->shared_count; ++i)
133 if (amdgpu_display_flip_handle_fence(work, &work->shared[i]))
134 return;
135
136 /* Wait until we're out of the vertical blank period before the one
137 * targeted by the flip
138 */
139 if (amdgpu_crtc->enabled &&
140 (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0,
141 &vpos, &hpos, NULL, NULL,
142 &crtc->hwmode)
143 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
144 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
145 (int)(work->target_vblank -
146 amdgpu_get_vblank_counter_kms(crtc)) > 0) {
147 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000));
148 return;
149 }
150
151 /* We borrow the event spin lock for protecting flip_status */
152 spin_lock_irqsave(&crtc->dev->event_lock, flags);
153
154 /* Do the flip (mmio) */
155 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async);
156
157 /* Set the flip status */
158 amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
159 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
160
161
162 drm_dbg_vbl(adev_to_drm(adev),
163 "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n",
164 amdgpu_crtc->crtc_id, amdgpu_crtc, work);
165
166 }
167
168 /*
169 * Handle unpin events outside the interrupt handler proper.
170 */
amdgpu_display_unpin_work_func(struct work_struct * __work)171 static void amdgpu_display_unpin_work_func(struct work_struct *__work)
172 {
173 struct amdgpu_flip_work *work =
174 container_of(__work, struct amdgpu_flip_work, unpin_work);
175 int r;
176
177 /* unpin of the old buffer */
178 r = amdgpu_bo_reserve(work->old_abo, true);
179 if (likely(r == 0)) {
180 amdgpu_bo_unpin(work->old_abo);
181 amdgpu_bo_unreserve(work->old_abo);
182 } else
183 DRM_ERROR("failed to reserve buffer after flip\n");
184
185 amdgpu_bo_unref(&work->old_abo);
186 kfree(work->shared);
187 kfree(work);
188 }
189
amdgpu_display_crtc_page_flip_target(struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_pending_vblank_event * event,uint32_t page_flip_flags,uint32_t target,struct drm_modeset_acquire_ctx * ctx)190 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
191 struct drm_framebuffer *fb,
192 struct drm_pending_vblank_event *event,
193 uint32_t page_flip_flags, uint32_t target,
194 struct drm_modeset_acquire_ctx *ctx)
195 {
196 struct drm_device *dev = crtc->dev;
197 struct amdgpu_device *adev = drm_to_adev(dev);
198 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
199 struct drm_gem_object *obj;
200 struct amdgpu_flip_work *work;
201 struct amdgpu_bo *new_abo;
202 unsigned long flags;
203 u64 tiling_flags;
204 int i, r;
205
206 work = kzalloc(sizeof(*work), GFP_KERNEL);
207 if (work == NULL)
208 return -ENOMEM;
209
210 INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func);
211 INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func);
212
213 work->event = event;
214 work->adev = adev;
215 work->crtc_id = amdgpu_crtc->crtc_id;
216 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
217
218 /* schedule unpin of the old buffer */
219 obj = crtc->primary->fb->obj[0];
220
221 /* take a reference to the old object */
222 work->old_abo = gem_to_amdgpu_bo(obj);
223 amdgpu_bo_ref(work->old_abo);
224
225 obj = fb->obj[0];
226 new_abo = gem_to_amdgpu_bo(obj);
227
228 /* pin the new buffer */
229 r = amdgpu_bo_reserve(new_abo, false);
230 if (unlikely(r != 0)) {
231 DRM_ERROR("failed to reserve new abo buffer before flip\n");
232 goto cleanup;
233 }
234
235 if (!adev->enable_virtual_display) {
236 r = amdgpu_bo_pin(new_abo,
237 amdgpu_display_supported_domains(adev, new_abo->flags));
238 if (unlikely(r != 0)) {
239 DRM_ERROR("failed to pin new abo buffer before flip\n");
240 goto unreserve;
241 }
242 }
243
244 r = amdgpu_ttm_alloc_gart(&new_abo->tbo);
245 if (unlikely(r != 0)) {
246 DRM_ERROR("%p bind failed\n", new_abo);
247 goto unpin;
248 }
249
250 r = dma_resv_get_fences(new_abo->tbo.base.resv, DMA_RESV_USAGE_WRITE,
251 &work->shared_count,
252 &work->shared);
253 if (unlikely(r != 0)) {
254 DRM_ERROR("failed to get fences for buffer\n");
255 goto unpin;
256 }
257
258 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
259 amdgpu_bo_unreserve(new_abo);
260
261 if (!adev->enable_virtual_display)
262 work->base = amdgpu_bo_gpu_offset(new_abo);
263 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
264 amdgpu_get_vblank_counter_kms(crtc);
265
266 /* we borrow the event spin lock for protecting flip_wrok */
267 spin_lock_irqsave(&crtc->dev->event_lock, flags);
268 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
269 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
270 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
271 r = -EBUSY;
272 goto pflip_cleanup;
273 }
274
275 amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
276 amdgpu_crtc->pflip_works = work;
277
278
279 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n",
280 amdgpu_crtc->crtc_id, amdgpu_crtc, work);
281 /* update crtc fb */
282 crtc->primary->fb = fb;
283 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
284 amdgpu_display_flip_work_func(&work->flip_work.work);
285 return 0;
286
287 pflip_cleanup:
288 if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) {
289 DRM_ERROR("failed to reserve new abo in error path\n");
290 goto cleanup;
291 }
292 unpin:
293 if (!adev->enable_virtual_display)
294 amdgpu_bo_unpin(new_abo);
295
296 unreserve:
297 amdgpu_bo_unreserve(new_abo);
298
299 cleanup:
300 amdgpu_bo_unref(&work->old_abo);
301 for (i = 0; i < work->shared_count; ++i)
302 dma_fence_put(work->shared[i]);
303 kfree(work->shared);
304 kfree(work);
305
306 return r;
307 }
308
amdgpu_display_crtc_set_config(struct drm_mode_set * set,struct drm_modeset_acquire_ctx * ctx)309 int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
310 struct drm_modeset_acquire_ctx *ctx)
311 {
312 struct drm_device *dev;
313 struct amdgpu_device *adev;
314 struct drm_crtc *crtc;
315 bool active = false;
316 int ret;
317
318 if (!set || !set->crtc)
319 return -EINVAL;
320
321 dev = set->crtc->dev;
322
323 ret = pm_runtime_get_sync(dev->dev);
324 if (ret < 0)
325 goto out;
326
327 ret = drm_crtc_helper_set_config(set, ctx);
328
329 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
330 if (crtc->enabled)
331 active = true;
332
333 pm_runtime_mark_last_busy(dev->dev);
334
335 adev = drm_to_adev(dev);
336 /* if we have active crtcs and we don't have a power ref,
337 * take the current one
338 */
339 if (active && !adev->have_disp_power_ref) {
340 adev->have_disp_power_ref = true;
341 return ret;
342 }
343 /* if we have no active crtcs, then go to
344 * drop the power ref we got before
345 */
346 if (!active && adev->have_disp_power_ref)
347 adev->have_disp_power_ref = false;
348 out:
349 /* drop the power reference we got coming in here */
350 pm_runtime_put_autosuspend(dev->dev);
351 return ret;
352 }
353
354 static const char *encoder_names[41] = {
355 "NONE",
356 "INTERNAL_LVDS",
357 "INTERNAL_TMDS1",
358 "INTERNAL_TMDS2",
359 "INTERNAL_DAC1",
360 "INTERNAL_DAC2",
361 "INTERNAL_SDVOA",
362 "INTERNAL_SDVOB",
363 "SI170B",
364 "CH7303",
365 "CH7301",
366 "INTERNAL_DVO1",
367 "EXTERNAL_SDVOA",
368 "EXTERNAL_SDVOB",
369 "TITFP513",
370 "INTERNAL_LVTM1",
371 "VT1623",
372 "HDMI_SI1930",
373 "HDMI_INTERNAL",
374 "INTERNAL_KLDSCP_TMDS1",
375 "INTERNAL_KLDSCP_DVO1",
376 "INTERNAL_KLDSCP_DAC1",
377 "INTERNAL_KLDSCP_DAC2",
378 "SI178",
379 "MVPU_FPGA",
380 "INTERNAL_DDI",
381 "VT1625",
382 "HDMI_SI1932",
383 "DP_AN9801",
384 "DP_DP501",
385 "INTERNAL_UNIPHY",
386 "INTERNAL_KLDSCP_LVTMA",
387 "INTERNAL_UNIPHY1",
388 "INTERNAL_UNIPHY2",
389 "NUTMEG",
390 "TRAVIS",
391 "INTERNAL_VCE",
392 "INTERNAL_UNIPHY3",
393 "HDMI_ANX9805",
394 "INTERNAL_AMCLK",
395 "VIRTUAL",
396 };
397
398 static const char *hpd_names[6] = {
399 "HPD1",
400 "HPD2",
401 "HPD3",
402 "HPD4",
403 "HPD5",
404 "HPD6",
405 };
406
amdgpu_display_print_display_setup(struct drm_device * dev)407 void amdgpu_display_print_display_setup(struct drm_device *dev)
408 {
409 struct drm_connector *connector;
410 struct amdgpu_connector *amdgpu_connector;
411 struct drm_encoder *encoder;
412 struct amdgpu_encoder *amdgpu_encoder;
413 struct drm_connector_list_iter iter;
414 uint32_t devices;
415 int i = 0;
416
417 drm_connector_list_iter_begin(dev, &iter);
418 DRM_INFO("AMDGPU Display Connectors\n");
419 drm_for_each_connector_iter(connector, &iter) {
420 amdgpu_connector = to_amdgpu_connector(connector);
421 DRM_INFO("Connector %d:\n", i);
422 DRM_INFO(" %s\n", connector->name);
423 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)
424 DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]);
425 if (amdgpu_connector->ddc_bus) {
426 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
427 amdgpu_connector->ddc_bus->rec.mask_clk_reg,
428 amdgpu_connector->ddc_bus->rec.mask_data_reg,
429 amdgpu_connector->ddc_bus->rec.a_clk_reg,
430 amdgpu_connector->ddc_bus->rec.a_data_reg,
431 amdgpu_connector->ddc_bus->rec.en_clk_reg,
432 amdgpu_connector->ddc_bus->rec.en_data_reg,
433 amdgpu_connector->ddc_bus->rec.y_clk_reg,
434 amdgpu_connector->ddc_bus->rec.y_data_reg);
435 if (amdgpu_connector->router.ddc_valid)
436 DRM_INFO(" DDC Router 0x%x/0x%x\n",
437 amdgpu_connector->router.ddc_mux_control_pin,
438 amdgpu_connector->router.ddc_mux_state);
439 if (amdgpu_connector->router.cd_valid)
440 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
441 amdgpu_connector->router.cd_mux_control_pin,
442 amdgpu_connector->router.cd_mux_state);
443 } else {
444 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
445 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
446 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
447 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
448 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
449 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
450 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
451 }
452 DRM_INFO(" Encoders:\n");
453 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
454 amdgpu_encoder = to_amdgpu_encoder(encoder);
455 devices = amdgpu_encoder->devices & amdgpu_connector->devices;
456 if (devices) {
457 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
458 DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
459 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
460 DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
461 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
462 DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
463 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
464 DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
465 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
466 DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
467 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
468 DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
469 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
470 DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
471 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
472 DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
473 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
474 DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
475 if (devices & ATOM_DEVICE_TV1_SUPPORT)
476 DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
477 if (devices & ATOM_DEVICE_CV_SUPPORT)
478 DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
479 }
480 }
481 i++;
482 }
483 drm_connector_list_iter_end(&iter);
484 }
485
amdgpu_display_ddc_probe(struct amdgpu_connector * amdgpu_connector,bool use_aux)486 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
487 bool use_aux)
488 {
489 u8 out = 0x0;
490 u8 buf[8];
491 int ret;
492 struct i2c_msg msgs[] = {
493 {
494 .addr = DDC_ADDR,
495 .flags = 0,
496 .len = 1,
497 .buf = &out,
498 },
499 {
500 .addr = DDC_ADDR,
501 .flags = I2C_M_RD,
502 .len = 8,
503 .buf = buf,
504 }
505 };
506
507 /* on hw with routers, select right port */
508 if (amdgpu_connector->router.ddc_valid)
509 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
510
511 if (use_aux)
512 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
513 else
514 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
515
516 if (ret != 2)
517 /* Couldn't find an accessible DDC on this connector */
518 return false;
519 /* Probe also for valid EDID header
520 * EDID header starts with:
521 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
522 * Only the first 6 bytes must be valid as
523 * drm_edid_block_valid() can fix the last 2 bytes
524 */
525 if (drm_edid_header_is_valid(buf) < 6) {
526 /* Couldn't find an accessible EDID on this
527 * connector
528 */
529 return false;
530 }
531 return true;
532 }
533
amdgpu_dirtyfb(struct drm_framebuffer * fb,struct drm_file * file,unsigned int flags,unsigned int color,struct drm_clip_rect * clips,unsigned int num_clips)534 static int amdgpu_dirtyfb(struct drm_framebuffer *fb, struct drm_file *file,
535 unsigned int flags, unsigned int color,
536 struct drm_clip_rect *clips, unsigned int num_clips)
537 {
538
539 if (file)
540 return -ENOSYS;
541
542 return drm_atomic_helper_dirtyfb(fb, file, flags, color, clips,
543 num_clips);
544 }
545
546 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
547 .destroy = drm_gem_fb_destroy,
548 .create_handle = drm_gem_fb_create_handle,
549 };
550
551 static const struct drm_framebuffer_funcs amdgpu_fb_funcs_atomic = {
552 .destroy = drm_gem_fb_destroy,
553 .create_handle = drm_gem_fb_create_handle,
554 .dirty = amdgpu_dirtyfb
555 };
556
amdgpu_display_supported_domains(struct amdgpu_device * adev,uint64_t bo_flags)557 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
558 uint64_t bo_flags)
559 {
560 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
561
562 #if defined(CONFIG_DRM_AMD_DC)
563 /*
564 * if amdgpu_bo_support_uswc returns false it means that USWC mappings
565 * is not supported for this board. But this mapping is required
566 * to avoid hang caused by placement of scanout BO in GTT on certain
567 * APUs. So force the BO placement to VRAM in case this architecture
568 * will not allow USWC mappings.
569 * Also, don't allow GTT domain if the BO doesn't have USWC flag set.
570 */
571 if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
572 amdgpu_bo_support_uswc(bo_flags) &&
573 adev->dc_enabled &&
574 adev->mode_info.gpu_vm_support)
575 domain |= AMDGPU_GEM_DOMAIN_GTT;
576 #endif
577
578 return domain;
579 }
580
581 static const struct drm_format_info dcc_formats[] = {
582 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
583 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
584 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
585 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
586 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
587 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
588 .has_alpha = true, },
589 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
590 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
591 .has_alpha = true, },
592 { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 2,
593 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
594 .has_alpha = true, },
595 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2,
596 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
597 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2,
598 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
599 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2,
600 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
601 .has_alpha = true, },
602 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2,
603 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
604 .has_alpha = true, },
605 { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 2,
606 .cpp = { 2, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
607 };
608
609 static const struct drm_format_info dcc_retile_formats[] = {
610 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
611 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
612 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
613 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
614 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
615 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
616 .has_alpha = true, },
617 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
618 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
619 .has_alpha = true, },
620 { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 3,
621 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
622 .has_alpha = true, },
623 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3,
624 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
625 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3,
626 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
627 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3,
628 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
629 .has_alpha = true, },
630 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3,
631 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
632 .has_alpha = true, },
633 { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 3,
634 .cpp = { 2, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
635 };
636
637 static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],int num_formats,u32 format)638 lookup_format_info(const struct drm_format_info formats[],
639 int num_formats, u32 format)
640 {
641 int i;
642
643 for (i = 0; i < num_formats; i++) {
644 if (formats[i].format == format)
645 return &formats[i];
646 }
647
648 return NULL;
649 }
650
651 const struct drm_format_info *
amdgpu_lookup_format_info(u32 format,uint64_t modifier)652 amdgpu_lookup_format_info(u32 format, uint64_t modifier)
653 {
654 if (!IS_AMD_FMT_MOD(modifier))
655 return NULL;
656
657 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier))
658 return lookup_format_info(dcc_retile_formats,
659 ARRAY_SIZE(dcc_retile_formats),
660 format);
661
662 if (AMD_FMT_MOD_GET(DCC, modifier))
663 return lookup_format_info(dcc_formats, ARRAY_SIZE(dcc_formats),
664 format);
665
666 /* returning NULL will cause the default format structs to be used. */
667 return NULL;
668 }
669
670
671 /*
672 * Tries to extract the renderable DCC offset from the opaque metadata attached
673 * to the buffer.
674 */
675 static int
extract_render_dcc_offset(struct amdgpu_device * adev,struct drm_gem_object * obj,uint64_t * offset)676 extract_render_dcc_offset(struct amdgpu_device *adev,
677 struct drm_gem_object *obj,
678 uint64_t *offset)
679 {
680 struct amdgpu_bo *rbo;
681 int r = 0;
682 uint32_t metadata[10]; /* Something that fits a descriptor + header. */
683 uint32_t size;
684
685 rbo = gem_to_amdgpu_bo(obj);
686 r = amdgpu_bo_reserve(rbo, false);
687
688 if (unlikely(r)) {
689 /* Don't show error message when returning -ERESTARTSYS */
690 if (r != -ERESTARTSYS)
691 DRM_ERROR("Unable to reserve buffer: %d\n", r);
692 return r;
693 }
694
695 r = amdgpu_bo_get_metadata(rbo, metadata, sizeof(metadata), &size, NULL);
696 amdgpu_bo_unreserve(rbo);
697
698 if (r)
699 return r;
700
701 /*
702 * The first word is the metadata version, and we need space for at least
703 * the version + pci vendor+device id + 8 words for a descriptor.
704 */
705 if (size < 40 || metadata[0] != 1)
706 return -EINVAL;
707
708 if (adev->family >= AMDGPU_FAMILY_NV) {
709 /* resource word 6/7 META_DATA_ADDRESS{_LO} */
710 *offset = ((u64)metadata[9] << 16u) |
711 ((metadata[8] & 0xFF000000u) >> 16);
712 } else {
713 /* resource word 5/7 META_DATA_ADDRESS */
714 *offset = ((u64)metadata[9] << 8u) |
715 ((u64)(metadata[7] & 0x1FE0000u) << 23);
716 }
717
718 return 0;
719 }
720
convert_tiling_flags_to_modifier(struct amdgpu_framebuffer * afb)721 static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
722 {
723 struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
724 uint64_t modifier = 0;
725 int num_pipes = 0;
726 int num_pkrs = 0;
727
728 num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
729 num_pipes = adev->gfx.config.gb_addr_config_fields.num_pipes;
730
731 if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) {
732 modifier = DRM_FORMAT_MOD_LINEAR;
733 } else {
734 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE);
735 bool has_xor = swizzle >= 16;
736 int block_size_bits;
737 int version;
738 int pipe_xor_bits = 0;
739 int bank_xor_bits = 0;
740 int packers = 0;
741 int rb = 0;
742 int pipes = ilog2(num_pipes);
743 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);
744
745 switch (swizzle >> 2) {
746 case 0: /* 256B */
747 block_size_bits = 8;
748 break;
749 case 1: /* 4KiB */
750 case 5: /* 4KiB _X */
751 block_size_bits = 12;
752 break;
753 case 2: /* 64KiB */
754 case 4: /* 64 KiB _T */
755 case 6: /* 64 KiB _X */
756 block_size_bits = 16;
757 break;
758 case 7: /* 256 KiB */
759 block_size_bits = 18;
760 break;
761 default:
762 /* RESERVED or VAR */
763 return -EINVAL;
764 }
765
766 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0))
767 version = AMD_FMT_MOD_TILE_VER_GFX11;
768 else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
769 version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
770 else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0))
771 version = AMD_FMT_MOD_TILE_VER_GFX10;
772 else
773 version = AMD_FMT_MOD_TILE_VER_GFX9;
774
775 switch (swizzle & 3) {
776 case 0: /* Z microtiling */
777 return -EINVAL;
778 case 1: /* S microtiling */
779 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) {
780 if (!has_xor)
781 version = AMD_FMT_MOD_TILE_VER_GFX9;
782 }
783 break;
784 case 2:
785 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) {
786 if (!has_xor && afb->base.format->cpp[0] != 4)
787 version = AMD_FMT_MOD_TILE_VER_GFX9;
788 }
789 break;
790 case 3:
791 break;
792 }
793
794 if (has_xor) {
795 if (num_pipes == num_pkrs && num_pkrs == 0) {
796 DRM_ERROR("invalid number of pipes and packers\n");
797 return -EINVAL;
798 }
799
800 switch (version) {
801 case AMD_FMT_MOD_TILE_VER_GFX11:
802 pipe_xor_bits = min(block_size_bits - 8, pipes);
803 packers = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs);
804 break;
805 case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
806 pipe_xor_bits = min(block_size_bits - 8, pipes);
807 packers = min(block_size_bits - 8 - pipe_xor_bits,
808 ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs));
809 break;
810 case AMD_FMT_MOD_TILE_VER_GFX10:
811 pipe_xor_bits = min(block_size_bits - 8, pipes);
812 break;
813 case AMD_FMT_MOD_TILE_VER_GFX9:
814 rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) +
815 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se);
816 pipe_xor_bits = min(block_size_bits - 8, pipes +
817 ilog2(adev->gfx.config.gb_addr_config_fields.num_se));
818 bank_xor_bits = min(block_size_bits - 8 - pipe_xor_bits,
819 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));
820 break;
821 }
822 }
823
824 modifier = AMD_FMT_MOD |
825 AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) |
826 AMD_FMT_MOD_SET(TILE_VERSION, version) |
827 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
828 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
829 AMD_FMT_MOD_SET(PACKERS, packers);
830
831 if (dcc_offset != 0) {
832 bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0;
833 bool dcc_i128b = version >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
834 const struct drm_format_info *format_info;
835 u64 render_dcc_offset;
836
837 /* Enable constant encode on RAVEN2 and later. */
838 bool dcc_constant_encode = (adev->asic_type > CHIP_RAVEN ||
839 (adev->asic_type == CHIP_RAVEN &&
840 adev->external_rev_id >= 0x81)) &&
841 adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0);
842
843 int max_cblock_size = dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B :
844 dcc_i128b ? AMD_FMT_MOD_DCC_BLOCK_128B :
845 AMD_FMT_MOD_DCC_BLOCK_256B;
846
847 modifier |= AMD_FMT_MOD_SET(DCC, 1) |
848 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, dcc_constant_encode) |
849 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, dcc_i64b) |
850 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, dcc_i128b) |
851 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_cblock_size);
852
853 afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0];
854 afb->base.pitches[1] =
855 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1;
856
857 /*
858 * If the userspace driver uses retiling the tiling flags do not contain
859 * info on the renderable DCC buffer. Luckily the opaque metadata contains
860 * the info so we can try to extract it. The kernel does not use this info
861 * but we should convert it to a modifier plane for getfb2, so the
862 * userspace driver that gets it doesn't have to juggle around another DCC
863 * plane internally.
864 */
865 if (extract_render_dcc_offset(adev, afb->base.obj[0],
866 &render_dcc_offset) == 0 &&
867 render_dcc_offset != 0 &&
868 render_dcc_offset != afb->base.offsets[1] &&
869 render_dcc_offset < UINT_MAX) {
870 uint32_t dcc_block_bits; /* of base surface data */
871
872 modifier |= AMD_FMT_MOD_SET(DCC_RETILE, 1);
873 afb->base.offsets[2] = render_dcc_offset;
874
875 if (adev->family >= AMDGPU_FAMILY_NV) {
876 int extra_pipe = 0;
877
878 if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) &&
879 pipes == packers && pipes > 1)
880 extra_pipe = 1;
881
882 dcc_block_bits = max(20, 16 + pipes + extra_pipe);
883 } else {
884 modifier |= AMD_FMT_MOD_SET(RB, rb) |
885 AMD_FMT_MOD_SET(PIPE, pipes);
886 dcc_block_bits = max(20, 18 + rb);
887 }
888
889 dcc_block_bits -= ilog2(afb->base.format->cpp[0]);
890 afb->base.pitches[2] = ALIGN(afb->base.width,
891 1u << ((dcc_block_bits + 1) / 2));
892 }
893 format_info = amdgpu_lookup_format_info(afb->base.format->format,
894 modifier);
895 if (!format_info)
896 return -EINVAL;
897
898 afb->base.format = format_info;
899 }
900 }
901
902 afb->base.modifier = modifier;
903 afb->base.flags |= DRM_MODE_FB_MODIFIERS;
904 return 0;
905 }
906
907 /* Mirrors the is_displayable check in radeonsi's gfx6_compute_surface */
check_tiling_flags_gfx6(struct amdgpu_framebuffer * afb)908 static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb)
909 {
910 u64 micro_tile_mode;
911
912 if (AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) == 1) /* LINEAR_ALIGNED */
913 return 0;
914
915 micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE);
916 switch (micro_tile_mode) {
917 case 0: /* DISPLAY */
918 case 3: /* RENDER */
919 return 0;
920 default:
921 drm_dbg_kms(afb->base.dev,
922 "Micro tile mode %llu not supported for scanout\n",
923 micro_tile_mode);
924 return -EINVAL;
925 }
926 }
927
get_block_dimensions(unsigned int block_log2,unsigned int cpp,unsigned int * width,unsigned int * height)928 static void get_block_dimensions(unsigned int block_log2, unsigned int cpp,
929 unsigned int *width, unsigned int *height)
930 {
931 unsigned int cpp_log2 = ilog2(cpp);
932 unsigned int pixel_log2 = block_log2 - cpp_log2;
933 unsigned int width_log2 = (pixel_log2 + 1) / 2;
934 unsigned int height_log2 = pixel_log2 - width_log2;
935
936 *width = 1 << width_log2;
937 *height = 1 << height_log2;
938 }
939
get_dcc_block_size(uint64_t modifier,bool rb_aligned,bool pipe_aligned)940 static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned,
941 bool pipe_aligned)
942 {
943 unsigned int ver = AMD_FMT_MOD_GET(TILE_VERSION, modifier);
944
945 switch (ver) {
946 case AMD_FMT_MOD_TILE_VER_GFX9: {
947 /*
948 * TODO: for pipe aligned we may need to check the alignment of the
949 * total size of the surface, which may need to be bigger than the
950 * natural alignment due to some HW workarounds
951 */
952 return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12);
953 }
954 case AMD_FMT_MOD_TILE_VER_GFX10:
955 case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
956 case AMD_FMT_MOD_TILE_VER_GFX11: {
957 int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
958
959 if (ver >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS && pipes_log2 > 1 &&
960 AMD_FMT_MOD_GET(PACKERS, modifier) == pipes_log2)
961 ++pipes_log2;
962
963 return max(8 + (pipe_aligned ? pipes_log2 : 0), 12);
964 }
965 default:
966 return 0;
967 }
968 }
969
amdgpu_display_verify_plane(struct amdgpu_framebuffer * rfb,int plane,const struct drm_format_info * format,unsigned int block_width,unsigned int block_height,unsigned int block_size_log2)970 static int amdgpu_display_verify_plane(struct amdgpu_framebuffer *rfb, int plane,
971 const struct drm_format_info *format,
972 unsigned int block_width, unsigned int block_height,
973 unsigned int block_size_log2)
974 {
975 unsigned int width = rfb->base.width /
976 ((plane && plane < format->num_planes) ? format->hsub : 1);
977 unsigned int height = rfb->base.height /
978 ((plane && plane < format->num_planes) ? format->vsub : 1);
979 unsigned int cpp = plane < format->num_planes ? format->cpp[plane] : 1;
980 unsigned int block_pitch = block_width * cpp;
981 unsigned int min_pitch = ALIGN(width * cpp, block_pitch);
982 unsigned int block_size = 1 << block_size_log2;
983 uint64_t size;
984
985 if (rfb->base.pitches[plane] % block_pitch) {
986 drm_dbg_kms(rfb->base.dev,
987 "pitch %d for plane %d is not a multiple of block pitch %d\n",
988 rfb->base.pitches[plane], plane, block_pitch);
989 return -EINVAL;
990 }
991 if (rfb->base.pitches[plane] < min_pitch) {
992 drm_dbg_kms(rfb->base.dev,
993 "pitch %d for plane %d is less than minimum pitch %d\n",
994 rfb->base.pitches[plane], plane, min_pitch);
995 return -EINVAL;
996 }
997
998 /* Force at least natural alignment. */
999 if (rfb->base.offsets[plane] % block_size) {
1000 drm_dbg_kms(rfb->base.dev,
1001 "offset 0x%x for plane %d is not a multiple of block pitch 0x%x\n",
1002 rfb->base.offsets[plane], plane, block_size);
1003 return -EINVAL;
1004 }
1005
1006 size = rfb->base.offsets[plane] +
1007 (uint64_t)rfb->base.pitches[plane] / block_pitch *
1008 block_size * DIV_ROUND_UP(height, block_height);
1009
1010 if (rfb->base.obj[0]->size < size) {
1011 drm_dbg_kms(rfb->base.dev,
1012 "BO size 0x%zx is less than 0x%llx required for plane %d\n",
1013 rfb->base.obj[0]->size, size, plane);
1014 return -EINVAL;
1015 }
1016
1017 return 0;
1018 }
1019
1020
amdgpu_display_verify_sizes(struct amdgpu_framebuffer * rfb)1021 static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb)
1022 {
1023 const struct drm_format_info *format_info = drm_format_info(rfb->base.format->format);
1024 uint64_t modifier = rfb->base.modifier;
1025 int ret;
1026 unsigned int i, block_width, block_height, block_size_log2;
1027
1028 if (rfb->base.dev->mode_config.fb_modifiers_not_supported)
1029 return 0;
1030
1031 for (i = 0; i < format_info->num_planes; ++i) {
1032 if (modifier == DRM_FORMAT_MOD_LINEAR) {
1033 block_width = 256 / format_info->cpp[i];
1034 block_height = 1;
1035 block_size_log2 = 8;
1036 } else if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) >= AMD_FMT_MOD_TILE_VER_GFX12) {
1037 int swizzle = AMD_FMT_MOD_GET(TILE, modifier);
1038
1039 switch (swizzle) {
1040 case AMD_FMT_MOD_TILE_GFX12_256B_2D:
1041 block_size_log2 = 8;
1042 break;
1043 case AMD_FMT_MOD_TILE_GFX12_4K_2D:
1044 block_size_log2 = 12;
1045 break;
1046 case AMD_FMT_MOD_TILE_GFX12_64K_2D:
1047 block_size_log2 = 16;
1048 break;
1049 case AMD_FMT_MOD_TILE_GFX12_256K_2D:
1050 block_size_log2 = 18;
1051 break;
1052 default:
1053 drm_dbg_kms(rfb->base.dev,
1054 "Gfx12 swizzle mode with unknown block size: %d\n", swizzle);
1055 return -EINVAL;
1056 }
1057
1058 get_block_dimensions(block_size_log2, format_info->cpp[i],
1059 &block_width, &block_height);
1060 } else {
1061 int swizzle = AMD_FMT_MOD_GET(TILE, modifier);
1062
1063 switch ((swizzle & ~3) + 1) {
1064 case DC_SW_256B_S:
1065 block_size_log2 = 8;
1066 break;
1067 case DC_SW_4KB_S:
1068 case DC_SW_4KB_S_X:
1069 block_size_log2 = 12;
1070 break;
1071 case DC_SW_64KB_S:
1072 case DC_SW_64KB_S_T:
1073 case DC_SW_64KB_S_X:
1074 block_size_log2 = 16;
1075 break;
1076 case DC_SW_VAR_S_X:
1077 block_size_log2 = 18;
1078 break;
1079 default:
1080 drm_dbg_kms(rfb->base.dev,
1081 "Swizzle mode with unknown block size: %d\n", swizzle);
1082 return -EINVAL;
1083 }
1084
1085 get_block_dimensions(block_size_log2, format_info->cpp[i],
1086 &block_width, &block_height);
1087 }
1088
1089 ret = amdgpu_display_verify_plane(rfb, i, format_info,
1090 block_width, block_height, block_size_log2);
1091 if (ret)
1092 return ret;
1093 }
1094
1095 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) <= AMD_FMT_MOD_TILE_VER_GFX11 &&
1096 AMD_FMT_MOD_GET(DCC, modifier)) {
1097 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) {
1098 block_size_log2 = get_dcc_block_size(modifier, false, false);
1099 get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
1100 &block_width, &block_height);
1101 ret = amdgpu_display_verify_plane(rfb, i, format_info,
1102 block_width, block_height,
1103 block_size_log2);
1104 if (ret)
1105 return ret;
1106
1107 ++i;
1108 block_size_log2 = get_dcc_block_size(modifier, true, true);
1109 } else {
1110 bool pipe_aligned = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier);
1111
1112 block_size_log2 = get_dcc_block_size(modifier, true, pipe_aligned);
1113 }
1114 get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
1115 &block_width, &block_height);
1116 ret = amdgpu_display_verify_plane(rfb, i, format_info,
1117 block_width, block_height, block_size_log2);
1118 if (ret)
1119 return ret;
1120 }
1121
1122 return 0;
1123 }
1124
amdgpu_display_get_fb_info(const struct amdgpu_framebuffer * amdgpu_fb,uint64_t * tiling_flags,bool * tmz_surface)1125 static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
1126 uint64_t *tiling_flags, bool *tmz_surface)
1127 {
1128 struct amdgpu_bo *rbo;
1129 int r;
1130
1131 if (!amdgpu_fb) {
1132 *tiling_flags = 0;
1133 *tmz_surface = false;
1134 return 0;
1135 }
1136
1137 rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
1138 r = amdgpu_bo_reserve(rbo, false);
1139
1140 if (unlikely(r)) {
1141 /* Don't show error message when returning -ERESTARTSYS */
1142 if (r != -ERESTARTSYS)
1143 DRM_ERROR("Unable to reserve buffer: %d\n", r);
1144 return r;
1145 }
1146
1147 if (tiling_flags)
1148 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1149
1150 if (tmz_surface)
1151 *tmz_surface = amdgpu_bo_encrypted(rbo);
1152
1153 amdgpu_bo_unreserve(rbo);
1154
1155 return r;
1156 }
1157
amdgpu_display_gem_fb_verify_and_init(struct drm_device * dev,struct amdgpu_framebuffer * rfb,struct drm_file * file_priv,const struct drm_mode_fb_cmd2 * mode_cmd,struct drm_gem_object * obj)1158 static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev,
1159 struct amdgpu_framebuffer *rfb,
1160 struct drm_file *file_priv,
1161 const struct drm_mode_fb_cmd2 *mode_cmd,
1162 struct drm_gem_object *obj)
1163 {
1164 int ret;
1165
1166 rfb->base.obj[0] = obj;
1167 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
1168 /* Verify that the modifier is supported. */
1169 if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format,
1170 mode_cmd->modifier[0])) {
1171 drm_dbg_kms(dev,
1172 "unsupported pixel format %p4cc / modifier 0x%llx\n",
1173 &mode_cmd->pixel_format, mode_cmd->modifier[0]);
1174
1175 ret = -EINVAL;
1176 goto err;
1177 }
1178
1179 ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj);
1180 if (ret)
1181 goto err;
1182
1183 if (drm_drv_uses_atomic_modeset(dev))
1184 ret = drm_framebuffer_init(dev, &rfb->base,
1185 &amdgpu_fb_funcs_atomic);
1186 else
1187 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
1188
1189 if (ret)
1190 goto err;
1191
1192 return 0;
1193 err:
1194 drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret);
1195 rfb->base.obj[0] = NULL;
1196 return ret;
1197 }
1198
amdgpu_display_framebuffer_init(struct drm_device * dev,struct amdgpu_framebuffer * rfb,const struct drm_mode_fb_cmd2 * mode_cmd,struct drm_gem_object * obj)1199 static int amdgpu_display_framebuffer_init(struct drm_device *dev,
1200 struct amdgpu_framebuffer *rfb,
1201 const struct drm_mode_fb_cmd2 *mode_cmd,
1202 struct drm_gem_object *obj)
1203 {
1204 struct amdgpu_device *adev = drm_to_adev(dev);
1205 int ret, i;
1206
1207 /*
1208 * This needs to happen before modifier conversion as that might change
1209 * the number of planes.
1210 */
1211 for (i = 1; i < rfb->base.format->num_planes; ++i) {
1212 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
1213 drm_dbg_kms(dev, "Plane 0 and %d have different BOs: %u vs. %u\n",
1214 i, mode_cmd->handles[0], mode_cmd->handles[i]);
1215 ret = -EINVAL;
1216 return ret;
1217 }
1218 }
1219
1220 ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface);
1221 if (ret)
1222 return ret;
1223
1224 if (dev->mode_config.fb_modifiers_not_supported && !adev->enable_virtual_display) {
1225 drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI,
1226 "GFX9+ requires FB check based on format modifier\n");
1227 ret = check_tiling_flags_gfx6(rfb);
1228 if (ret)
1229 return ret;
1230 }
1231
1232 if (!dev->mode_config.fb_modifiers_not_supported &&
1233 !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) {
1234 ret = convert_tiling_flags_to_modifier(rfb);
1235 if (ret) {
1236 drm_dbg_kms(dev, "Failed to convert tiling flags 0x%llX to a modifier",
1237 rfb->tiling_flags);
1238 return ret;
1239 }
1240 }
1241
1242 ret = amdgpu_display_verify_sizes(rfb);
1243 if (ret)
1244 return ret;
1245
1246 for (i = 0; i < rfb->base.format->num_planes; ++i) {
1247 drm_gem_object_get(rfb->base.obj[0]);
1248 rfb->base.obj[i] = rfb->base.obj[0];
1249 }
1250
1251 return 0;
1252 }
1253
1254 struct drm_framebuffer *
amdgpu_display_user_framebuffer_create(struct drm_device * dev,struct drm_file * file_priv,const struct drm_mode_fb_cmd2 * mode_cmd)1255 amdgpu_display_user_framebuffer_create(struct drm_device *dev,
1256 struct drm_file *file_priv,
1257 const struct drm_mode_fb_cmd2 *mode_cmd)
1258 {
1259 struct amdgpu_framebuffer *amdgpu_fb;
1260 struct drm_gem_object *obj;
1261 struct amdgpu_bo *bo;
1262 uint32_t domains;
1263 int ret;
1264
1265 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1266 if (obj == NULL) {
1267 drm_dbg_kms(dev,
1268 "No GEM object associated to handle 0x%08X, can't create framebuffer\n",
1269 mode_cmd->handles[0]);
1270
1271 return ERR_PTR(-ENOENT);
1272 }
1273
1274 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1275 bo = gem_to_amdgpu_bo(obj);
1276 domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags);
1277 if (obj->import_attach && !(domains & AMDGPU_GEM_DOMAIN_GTT)) {
1278 drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n");
1279 drm_gem_object_put(obj);
1280 return ERR_PTR(-EINVAL);
1281 }
1282
1283 amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
1284 if (amdgpu_fb == NULL) {
1285 drm_gem_object_put(obj);
1286 return ERR_PTR(-ENOMEM);
1287 }
1288
1289 ret = amdgpu_display_gem_fb_verify_and_init(dev, amdgpu_fb, file_priv,
1290 mode_cmd, obj);
1291 if (ret) {
1292 kfree(amdgpu_fb);
1293 drm_gem_object_put(obj);
1294 return ERR_PTR(ret);
1295 }
1296
1297 drm_gem_object_put(obj);
1298 return &amdgpu_fb->base;
1299 }
1300
1301 const struct drm_mode_config_funcs amdgpu_mode_funcs = {
1302 .fb_create = amdgpu_display_user_framebuffer_create,
1303 };
1304
1305 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] = {
1306 { UNDERSCAN_OFF, "off" },
1307 { UNDERSCAN_ON, "on" },
1308 { UNDERSCAN_AUTO, "auto" },
1309 };
1310
1311 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] = {
1312 { AMDGPU_AUDIO_DISABLE, "off" },
1313 { AMDGPU_AUDIO_ENABLE, "on" },
1314 { AMDGPU_AUDIO_AUTO, "auto" },
1315 };
1316
1317 /* XXX support different dither options? spatial, temporal, both, etc. */
1318 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] = {
1319 { AMDGPU_FMT_DITHER_DISABLE, "off" },
1320 { AMDGPU_FMT_DITHER_ENABLE, "on" },
1321 };
1322
amdgpu_display_modeset_create_props(struct amdgpu_device * adev)1323 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev)
1324 {
1325 int sz;
1326
1327 adev->mode_info.coherent_mode_property =
1328 drm_property_create_range(adev_to_drm(adev), 0, "coherent", 0, 1);
1329 if (!adev->mode_info.coherent_mode_property)
1330 return -ENOMEM;
1331
1332 adev->mode_info.load_detect_property =
1333 drm_property_create_range(adev_to_drm(adev), 0, "load detection", 0, 1);
1334 if (!adev->mode_info.load_detect_property)
1335 return -ENOMEM;
1336
1337 drm_mode_create_scaling_mode_property(adev_to_drm(adev));
1338
1339 sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
1340 adev->mode_info.underscan_property =
1341 drm_property_create_enum(adev_to_drm(adev), 0,
1342 "underscan",
1343 amdgpu_underscan_enum_list, sz);
1344
1345 adev->mode_info.underscan_hborder_property =
1346 drm_property_create_range(adev_to_drm(adev), 0,
1347 "underscan hborder", 0, 128);
1348 if (!adev->mode_info.underscan_hborder_property)
1349 return -ENOMEM;
1350
1351 adev->mode_info.underscan_vborder_property =
1352 drm_property_create_range(adev_to_drm(adev), 0,
1353 "underscan vborder", 0, 128);
1354 if (!adev->mode_info.underscan_vborder_property)
1355 return -ENOMEM;
1356
1357 sz = ARRAY_SIZE(amdgpu_audio_enum_list);
1358 adev->mode_info.audio_property =
1359 drm_property_create_enum(adev_to_drm(adev), 0,
1360 "audio",
1361 amdgpu_audio_enum_list, sz);
1362
1363 sz = ARRAY_SIZE(amdgpu_dither_enum_list);
1364 adev->mode_info.dither_property =
1365 drm_property_create_enum(adev_to_drm(adev), 0,
1366 "dither",
1367 amdgpu_dither_enum_list, sz);
1368
1369 if (adev->dc_enabled) {
1370 adev->mode_info.abm_level_property =
1371 drm_property_create_range(adev_to_drm(adev), 0,
1372 "abm level", 0, 4);
1373 if (!adev->mode_info.abm_level_property)
1374 return -ENOMEM;
1375 }
1376
1377 return 0;
1378 }
1379
amdgpu_display_update_priority(struct amdgpu_device * adev)1380 void amdgpu_display_update_priority(struct amdgpu_device *adev)
1381 {
1382 /* adjustment options for the display watermarks */
1383 if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
1384 adev->mode_info.disp_priority = 0;
1385 else
1386 adev->mode_info.disp_priority = amdgpu_disp_priority;
1387
1388 }
1389
amdgpu_display_is_hdtv_mode(const struct drm_display_mode * mode)1390 static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode)
1391 {
1392 /* try and guess if this is a tv or a monitor */
1393 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1394 (mode->vdisplay == 576) || /* 576p */
1395 (mode->vdisplay == 720) || /* 720p */
1396 (mode->vdisplay == 1080)) /* 1080p */
1397 return true;
1398 else
1399 return false;
1400 }
1401
amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)1402 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1403 const struct drm_display_mode *mode,
1404 struct drm_display_mode *adjusted_mode)
1405 {
1406 struct drm_device *dev = crtc->dev;
1407 struct drm_encoder *encoder;
1408 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1409 struct amdgpu_encoder *amdgpu_encoder;
1410 struct drm_connector *connector;
1411 u32 src_v = 1, dst_v = 1;
1412 u32 src_h = 1, dst_h = 1;
1413
1414 amdgpu_crtc->h_border = 0;
1415 amdgpu_crtc->v_border = 0;
1416
1417 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1418 if (encoder->crtc != crtc)
1419 continue;
1420 amdgpu_encoder = to_amdgpu_encoder(encoder);
1421 connector = amdgpu_get_connector_for_encoder(encoder);
1422
1423 /* set scaling */
1424 if (amdgpu_encoder->rmx_type == RMX_OFF)
1425 amdgpu_crtc->rmx_type = RMX_OFF;
1426 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||
1427 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)
1428 amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
1429 else
1430 amdgpu_crtc->rmx_type = RMX_OFF;
1431 /* copy native mode */
1432 memcpy(&amdgpu_crtc->native_mode,
1433 &amdgpu_encoder->native_mode,
1434 sizeof(struct drm_display_mode));
1435 src_v = crtc->mode.vdisplay;
1436 dst_v = amdgpu_crtc->native_mode.vdisplay;
1437 src_h = crtc->mode.hdisplay;
1438 dst_h = amdgpu_crtc->native_mode.hdisplay;
1439
1440 /* fix up for overscan on hdmi */
1441 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1442 ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||
1443 ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&
1444 connector->display_info.is_hdmi &&
1445 amdgpu_display_is_hdtv_mode(mode)))) {
1446 if (amdgpu_encoder->underscan_hborder != 0)
1447 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
1448 else
1449 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
1450 if (amdgpu_encoder->underscan_vborder != 0)
1451 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
1452 else
1453 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
1454 amdgpu_crtc->rmx_type = RMX_FULL;
1455 src_v = crtc->mode.vdisplay;
1456 dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
1457 src_h = crtc->mode.hdisplay;
1458 dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
1459 }
1460 }
1461 if (amdgpu_crtc->rmx_type != RMX_OFF) {
1462 fixed20_12 a, b;
1463
1464 a.full = dfixed_const(src_v);
1465 b.full = dfixed_const(dst_v);
1466 amdgpu_crtc->vsc.full = dfixed_div(a, b);
1467 a.full = dfixed_const(src_h);
1468 b.full = dfixed_const(dst_h);
1469 amdgpu_crtc->hsc.full = dfixed_div(a, b);
1470 } else {
1471 amdgpu_crtc->vsc.full = dfixed_const(1);
1472 amdgpu_crtc->hsc.full = dfixed_const(1);
1473 }
1474 return true;
1475 }
1476
1477 /*
1478 * Retrieve current video scanout position of crtc on a given gpu, and
1479 * an optional accurate timestamp of when query happened.
1480 *
1481 * \param dev Device to query.
1482 * \param pipe Crtc to query.
1483 * \param flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1484 * For driver internal use only also supports these flags:
1485 *
1486 * USE_REAL_VBLANKSTART to use the real start of vblank instead
1487 * of a fudged earlier start of vblank.
1488 *
1489 * GET_DISTANCE_TO_VBLANKSTART to return distance to the
1490 * fudged earlier start of vblank in *vpos and the distance
1491 * to true start of vblank in *hpos.
1492 *
1493 * \param *vpos Location where vertical scanout position should be stored.
1494 * \param *hpos Location where horizontal scanout position should go.
1495 * \param *stime Target location for timestamp taken immediately before
1496 * scanout position query. Can be NULL to skip timestamp.
1497 * \param *etime Target location for timestamp taken immediately after
1498 * scanout position query. Can be NULL to skip timestamp.
1499 *
1500 * Returns vpos as a positive number while in active scanout area.
1501 * Returns vpos as a negative number inside vblank, counting the number
1502 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1503 * until start of active scanout / end of vblank."
1504 *
1505 * \return Flags, or'ed together as follows:
1506 *
1507 * DRM_SCANOUTPOS_VALID = Query successful.
1508 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1509 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1510 * this flag means that returned position may be offset by a constant but
1511 * unknown small number of scanlines wrt. real scanout position.
1512 *
1513 */
amdgpu_display_get_crtc_scanoutpos(struct drm_device * dev,unsigned int pipe,unsigned int flags,int * vpos,int * hpos,ktime_t * stime,ktime_t * etime,const struct drm_display_mode * mode)1514 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
1515 unsigned int pipe, unsigned int flags, int *vpos,
1516 int *hpos, ktime_t *stime, ktime_t *etime,
1517 const struct drm_display_mode *mode)
1518 {
1519 u32 vbl = 0, position = 0;
1520 int vbl_start, vbl_end, vtotal, ret = 0;
1521 bool in_vbl = true;
1522
1523 struct amdgpu_device *adev = drm_to_adev(dev);
1524
1525 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1526
1527 /* Get optional system timestamp before query. */
1528 if (stime)
1529 *stime = ktime_get();
1530
1531 if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0)
1532 ret |= DRM_SCANOUTPOS_VALID;
1533
1534 /* Get optional system timestamp after query. */
1535 if (etime)
1536 *etime = ktime_get();
1537
1538 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1539
1540 /* Decode into vertical and horizontal scanout position. */
1541 *vpos = position & 0x1fff;
1542 *hpos = (position >> 16) & 0x1fff;
1543
1544 /* Valid vblank area boundaries from gpu retrieved? */
1545 if (vbl > 0) {
1546 /* Yes: Decode. */
1547 ret |= DRM_SCANOUTPOS_ACCURATE;
1548 vbl_start = vbl & 0x1fff;
1549 vbl_end = (vbl >> 16) & 0x1fff;
1550 } else {
1551 /* No: Fake something reasonable which gives at least ok results. */
1552 vbl_start = mode->crtc_vdisplay;
1553 vbl_end = 0;
1554 }
1555
1556 /* Called from driver internal vblank counter query code? */
1557 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1558 /* Caller wants distance from real vbl_start in *hpos */
1559 *hpos = *vpos - vbl_start;
1560 }
1561
1562 /* Fudge vblank to start a few scanlines earlier to handle the
1563 * problem that vblank irqs fire a few scanlines before start
1564 * of vblank. Some driver internal callers need the true vblank
1565 * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1566 *
1567 * The cause of the "early" vblank irq is that the irq is triggered
1568 * by the line buffer logic when the line buffer read position enters
1569 * the vblank, whereas our crtc scanout position naturally lags the
1570 * line buffer read position.
1571 */
1572 if (!(flags & USE_REAL_VBLANKSTART))
1573 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1574
1575 /* Test scanout position against vblank region. */
1576 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1577 in_vbl = false;
1578
1579 /* In vblank? */
1580 if (in_vbl)
1581 ret |= DRM_SCANOUTPOS_IN_VBLANK;
1582
1583 /* Called from driver internal vblank counter query code? */
1584 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1585 /* Caller wants distance from fudged earlier vbl_start */
1586 *vpos -= vbl_start;
1587 return ret;
1588 }
1589
1590 /* Check if inside vblank area and apply corrective offsets:
1591 * vpos will then be >=0 in video scanout area, but negative
1592 * within vblank area, counting down the number of lines until
1593 * start of scanout.
1594 */
1595
1596 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1597 if (in_vbl && (*vpos >= vbl_start)) {
1598 vtotal = mode->crtc_vtotal;
1599
1600 /* With variable refresh rate displays the vpos can exceed
1601 * the vtotal value. Clamp to 0 to return -vbl_end instead
1602 * of guessing the remaining number of lines until scanout.
1603 */
1604 *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0;
1605 }
1606
1607 /* Correct for shifted end of vbl at vbl_end. */
1608 *vpos = *vpos - vbl_end;
1609
1610 return ret;
1611 }
1612
amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device * adev,int crtc)1613 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
1614 {
1615 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
1616 return AMDGPU_CRTC_IRQ_NONE;
1617
1618 switch (crtc) {
1619 case 0:
1620 return AMDGPU_CRTC_IRQ_VBLANK1;
1621 case 1:
1622 return AMDGPU_CRTC_IRQ_VBLANK2;
1623 case 2:
1624 return AMDGPU_CRTC_IRQ_VBLANK3;
1625 case 3:
1626 return AMDGPU_CRTC_IRQ_VBLANK4;
1627 case 4:
1628 return AMDGPU_CRTC_IRQ_VBLANK5;
1629 case 5:
1630 return AMDGPU_CRTC_IRQ_VBLANK6;
1631 default:
1632 return AMDGPU_CRTC_IRQ_NONE;
1633 }
1634 }
1635
amdgpu_crtc_get_scanout_position(struct drm_crtc * crtc,bool in_vblank_irq,int * vpos,int * hpos,ktime_t * stime,ktime_t * etime,const struct drm_display_mode * mode)1636 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
1637 bool in_vblank_irq, int *vpos,
1638 int *hpos, ktime_t *stime, ktime_t *etime,
1639 const struct drm_display_mode *mode)
1640 {
1641 struct drm_device *dev = crtc->dev;
1642 unsigned int pipe = crtc->index;
1643
1644 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1645 stime, etime, mode);
1646 }
1647
1648 static bool
amdgpu_display_robj_is_fb(struct amdgpu_device * adev,struct amdgpu_bo * robj)1649 amdgpu_display_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj)
1650 {
1651 struct drm_device *dev = adev_to_drm(adev);
1652 struct drm_fb_helper *fb_helper = dev->fb_helper;
1653
1654 if (!fb_helper || !fb_helper->buffer)
1655 return false;
1656
1657 if (gem_to_amdgpu_bo(fb_helper->buffer->gem) != robj)
1658 return false;
1659
1660 return true;
1661 }
1662
amdgpu_display_suspend_helper(struct amdgpu_device * adev)1663 int amdgpu_display_suspend_helper(struct amdgpu_device *adev)
1664 {
1665 struct drm_device *dev = adev_to_drm(adev);
1666 struct drm_crtc *crtc;
1667 struct drm_connector *connector;
1668 struct drm_connector_list_iter iter;
1669 int r;
1670
1671 drm_kms_helper_poll_disable(dev);
1672
1673 /* turn off display hw */
1674 drm_modeset_lock_all(dev);
1675 drm_connector_list_iter_begin(dev, &iter);
1676 drm_for_each_connector_iter(connector, &iter)
1677 drm_helper_connector_dpms(connector,
1678 DRM_MODE_DPMS_OFF);
1679 drm_connector_list_iter_end(&iter);
1680 drm_modeset_unlock_all(dev);
1681 /* unpin the front buffers and cursors */
1682 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1683 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1684 struct drm_framebuffer *fb = crtc->primary->fb;
1685 struct amdgpu_bo *robj;
1686
1687 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1688 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1689
1690 r = amdgpu_bo_reserve(aobj, true);
1691 if (r == 0) {
1692 amdgpu_bo_unpin(aobj);
1693 amdgpu_bo_unreserve(aobj);
1694 }
1695 }
1696
1697 if (!fb || !fb->obj[0])
1698 continue;
1699
1700 robj = gem_to_amdgpu_bo(fb->obj[0]);
1701 if (!amdgpu_display_robj_is_fb(adev, robj)) {
1702 r = amdgpu_bo_reserve(robj, true);
1703 if (r == 0) {
1704 amdgpu_bo_unpin(robj);
1705 amdgpu_bo_unreserve(robj);
1706 }
1707 }
1708 }
1709 return 0;
1710 }
1711
amdgpu_display_resume_helper(struct amdgpu_device * adev)1712 int amdgpu_display_resume_helper(struct amdgpu_device *adev)
1713 {
1714 struct drm_device *dev = adev_to_drm(adev);
1715 struct drm_connector *connector;
1716 struct drm_connector_list_iter iter;
1717 struct drm_crtc *crtc;
1718 int r;
1719
1720 /* pin cursors */
1721 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1722 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1723
1724 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1725 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1726
1727 r = amdgpu_bo_reserve(aobj, true);
1728 if (r == 0) {
1729 r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
1730 if (r != 0)
1731 dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r);
1732 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
1733 amdgpu_bo_unreserve(aobj);
1734 }
1735 }
1736 }
1737
1738 drm_helper_resume_force_mode(dev);
1739
1740 /* turn on display hw */
1741 drm_modeset_lock_all(dev);
1742
1743 drm_connector_list_iter_begin(dev, &iter);
1744 drm_for_each_connector_iter(connector, &iter)
1745 drm_helper_connector_dpms(connector,
1746 DRM_MODE_DPMS_ON);
1747 drm_connector_list_iter_end(&iter);
1748
1749 drm_modeset_unlock_all(dev);
1750
1751 drm_kms_helper_poll_enable(dev);
1752
1753 return 0;
1754 }
1755
1756