1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26
27 #include <linux/firmware.h>
28 #include <linux/module.h>
29 #include <linux/dmi.h>
30 #include <linux/pci.h>
31 #include <linux/debugfs.h>
32 #include <drm/drm_drv.h>
33
34 #include "amdgpu.h"
35 #include "amdgpu_pm.h"
36 #include "amdgpu_vcn.h"
37 #include "soc15d.h"
38
39 /* Firmware Names */
40 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin"
41 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin"
42 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin"
43 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin"
44 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin"
45 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin"
46 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin"
47 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin"
48 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin"
49 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin"
50 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin"
51 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin"
52 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin"
53 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin"
54 #define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin"
55 #define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin"
56 #define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2.bin"
57 #define FIRMWARE_VCN4_0_0 "amdgpu/vcn_4_0_0.bin"
58 #define FIRMWARE_VCN4_0_2 "amdgpu/vcn_4_0_2.bin"
59 #define FIRMWARE_VCN4_0_3 "amdgpu/vcn_4_0_3.bin"
60 #define FIRMWARE_VCN4_0_4 "amdgpu/vcn_4_0_4.bin"
61
62 MODULE_FIRMWARE(FIRMWARE_RAVEN);
63 MODULE_FIRMWARE(FIRMWARE_PICASSO);
64 MODULE_FIRMWARE(FIRMWARE_RAVEN2);
65 MODULE_FIRMWARE(FIRMWARE_ARCTURUS);
66 MODULE_FIRMWARE(FIRMWARE_RENOIR);
67 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE);
68 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN);
69 MODULE_FIRMWARE(FIRMWARE_NAVI10);
70 MODULE_FIRMWARE(FIRMWARE_NAVI14);
71 MODULE_FIRMWARE(FIRMWARE_NAVI12);
72 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID);
73 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER);
74 MODULE_FIRMWARE(FIRMWARE_VANGOGH);
75 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH);
76 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY);
77 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP);
78 MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2);
79 MODULE_FIRMWARE(FIRMWARE_VCN4_0_0);
80 MODULE_FIRMWARE(FIRMWARE_VCN4_0_2);
81 MODULE_FIRMWARE(FIRMWARE_VCN4_0_3);
82 MODULE_FIRMWARE(FIRMWARE_VCN4_0_4);
83
84 static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
85
amdgpu_vcn_early_init(struct amdgpu_device * adev)86 int amdgpu_vcn_early_init(struct amdgpu_device *adev)
87 {
88 char ucode_prefix[30];
89 char fw_name[40];
90 int r;
91
92 amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix));
93 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix);
94 r = amdgpu_ucode_request(adev, &adev->vcn.fw, fw_name);
95 if (r)
96 amdgpu_ucode_release(&adev->vcn.fw);
97
98 return r;
99 }
100
amdgpu_vcn_sw_init(struct amdgpu_device * adev)101 int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
102 {
103 unsigned long bo_size;
104 const struct common_firmware_header *hdr;
105 unsigned char fw_check;
106 unsigned int fw_shared_size, log_offset;
107 int i, r;
108
109 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
110 mutex_init(&adev->vcn.vcn_pg_lock);
111 mutex_init(&adev->vcn.vcn1_jpeg1_workaround);
112 atomic_set(&adev->vcn.total_submission_cnt, 0);
113 for (i = 0; i < adev->vcn.num_vcn_inst; i++)
114 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);
115
116 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
117 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
118 adev->vcn.indirect_sram = true;
119
120 /*
121 * Some Steam Deck's BIOS versions are incompatible with the
122 * indirect SRAM mode, leading to amdgpu being unable to get
123 * properly probed (and even potentially crashing the kernel).
124 * Hence, check for these versions here - notice this is
125 * restricted to Vangogh (Deck's APU).
126 */
127 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 0, 2)) {
128 const char *bios_ver = dmi_get_system_info(DMI_BIOS_VERSION);
129
130 if (bios_ver && (!strncmp("F7A0113", bios_ver, 7) ||
131 !strncmp("F7A0114", bios_ver, 7))) {
132 adev->vcn.indirect_sram = false;
133 dev_info(adev->dev,
134 "Steam Deck quirk: indirect SRAM disabled on BIOS %s\n", bios_ver);
135 }
136 }
137
138 /* from vcn4 and above, only unified queue is used */
139 adev->vcn.using_unified_queue =
140 adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0);
141
142 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
143 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
144
145 /* Bit 20-23, it is encode major and non-zero for new naming convention.
146 * This field is part of version minor and DRM_DISABLED_FLAG in old naming
147 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG
148 * is zero in old naming convention, this field is always zero so far.
149 * These four bits are used to tell which naming convention is present.
150 */
151 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf;
152 if (fw_check) {
153 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev;
154
155 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff;
156 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff;
157 enc_major = fw_check;
158 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf;
159 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf;
160 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n",
161 enc_major, enc_minor, dec_ver, vep, fw_rev);
162 } else {
163 unsigned int version_major, version_minor, family_id;
164
165 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
166 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
167 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
168 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n",
169 version_major, version_minor, family_id);
170 }
171
172 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
173 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
174 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
175
176 if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0)) {
177 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared));
178 log_offset = offsetof(struct amdgpu_vcn4_fw_shared, fw_log);
179 } else {
180 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared));
181 log_offset = offsetof(struct amdgpu_fw_shared, fw_log);
182 }
183
184 bo_size += fw_shared_size;
185
186 if (amdgpu_vcnfw_log)
187 bo_size += AMDGPU_VCNFW_LOG_SIZE;
188
189 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
190 if (adev->vcn.harvest_config & (1 << i))
191 continue;
192
193 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
194 AMDGPU_GEM_DOMAIN_VRAM |
195 AMDGPU_GEM_DOMAIN_GTT,
196 &adev->vcn.inst[i].vcpu_bo,
197 &adev->vcn.inst[i].gpu_addr,
198 &adev->vcn.inst[i].cpu_addr);
199 if (r) {
200 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
201 return r;
202 }
203
204 adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr +
205 bo_size - fw_shared_size;
206 adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr +
207 bo_size - fw_shared_size;
208
209 adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size;
210
211 if (amdgpu_vcnfw_log) {
212 adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
213 adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
214 adev->vcn.inst[i].fw_shared.log_offset = log_offset;
215 }
216
217 if (adev->vcn.indirect_sram) {
218 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
219 AMDGPU_GEM_DOMAIN_VRAM |
220 AMDGPU_GEM_DOMAIN_GTT,
221 &adev->vcn.inst[i].dpg_sram_bo,
222 &adev->vcn.inst[i].dpg_sram_gpu_addr,
223 &adev->vcn.inst[i].dpg_sram_cpu_addr);
224 if (r) {
225 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r);
226 return r;
227 }
228 }
229 }
230
231 return 0;
232 }
233
amdgpu_vcn_sw_fini(struct amdgpu_device * adev)234 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
235 {
236 int i, j;
237
238 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
239 if (adev->vcn.harvest_config & (1 << j))
240 continue;
241
242 amdgpu_bo_free_kernel(
243 &adev->vcn.inst[j].dpg_sram_bo,
244 &adev->vcn.inst[j].dpg_sram_gpu_addr,
245 (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr);
246
247 kvfree(adev->vcn.inst[j].saved_bo);
248
249 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo,
250 &adev->vcn.inst[j].gpu_addr,
251 (void **)&adev->vcn.inst[j].cpu_addr);
252
253 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec);
254
255 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
256 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
257 }
258
259 amdgpu_ucode_release(&adev->vcn.fw);
260 mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround);
261 mutex_destroy(&adev->vcn.vcn_pg_lock);
262
263 return 0;
264 }
265
amdgpu_vcn_is_disabled_vcn(struct amdgpu_device * adev,enum vcn_ring_type type,uint32_t vcn_instance)266 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance)
267 {
268 bool ret = false;
269 int vcn_config = adev->vcn.vcn_config[vcn_instance];
270
271 if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK))
272 ret = true;
273 else if ((type == VCN_DECODE_RING) && (vcn_config & VCN_BLOCK_DECODE_DISABLE_MASK))
274 ret = true;
275 else if ((type == VCN_UNIFIED_RING) && (vcn_config & VCN_BLOCK_QUEUE_DISABLE_MASK))
276 ret = true;
277
278 return ret;
279 }
280
amdgpu_vcn_suspend(struct amdgpu_device * adev)281 int amdgpu_vcn_suspend(struct amdgpu_device *adev)
282 {
283 unsigned int size;
284 void *ptr;
285 int i, idx;
286
287 bool in_ras_intr = amdgpu_ras_intr_triggered();
288
289 cancel_delayed_work_sync(&adev->vcn.idle_work);
290
291 /* err_event_athub will corrupt VCPU buffer, so we need to
292 * restore fw data and clear buffer in amdgpu_vcn_resume() */
293 if (in_ras_intr)
294 return 0;
295
296 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
297 if (adev->vcn.harvest_config & (1 << i))
298 continue;
299 if (adev->vcn.inst[i].vcpu_bo == NULL)
300 return 0;
301
302 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
303 ptr = adev->vcn.inst[i].cpu_addr;
304
305 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL);
306 if (!adev->vcn.inst[i].saved_bo)
307 return -ENOMEM;
308
309 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
310 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size);
311 drm_dev_exit(idx);
312 }
313 }
314 return 0;
315 }
316
amdgpu_vcn_resume(struct amdgpu_device * adev)317 int amdgpu_vcn_resume(struct amdgpu_device *adev)
318 {
319 unsigned int size;
320 void *ptr;
321 int i, idx;
322
323 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
324 if (adev->vcn.harvest_config & (1 << i))
325 continue;
326 if (adev->vcn.inst[i].vcpu_bo == NULL)
327 return -EINVAL;
328
329 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
330 ptr = adev->vcn.inst[i].cpu_addr;
331
332 if (adev->vcn.inst[i].saved_bo != NULL) {
333 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
334 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size);
335 drm_dev_exit(idx);
336 }
337 kvfree(adev->vcn.inst[i].saved_bo);
338 adev->vcn.inst[i].saved_bo = NULL;
339 } else {
340 const struct common_firmware_header *hdr;
341 unsigned int offset;
342
343 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
344 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
345 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
346 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
347 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset,
348 le32_to_cpu(hdr->ucode_size_bytes));
349 drm_dev_exit(idx);
350 }
351 size -= le32_to_cpu(hdr->ucode_size_bytes);
352 ptr += le32_to_cpu(hdr->ucode_size_bytes);
353 }
354 memset_io(ptr, 0, size);
355 }
356 }
357 return 0;
358 }
359
amdgpu_vcn_idle_work_handler(struct work_struct * work)360 static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
361 {
362 struct amdgpu_device *adev =
363 container_of(work, struct amdgpu_device, vcn.idle_work.work);
364 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};
365 unsigned int i, j;
366 int r = 0;
367
368 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
369 if (adev->vcn.harvest_config & (1 << j))
370 continue;
371
372 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
373 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]);
374
375 /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */
376 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
377 !adev->vcn.using_unified_queue) {
378 struct dpg_pause_state new_state;
379
380 if (fence[j] ||
381 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt)))
382 new_state.fw_based = VCN_DPG_STATE__PAUSE;
383 else
384 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
385
386 adev->vcn.pause_dpg_mode(adev, j, &new_state);
387 }
388
389 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec);
390 fences += fence[j];
391 }
392
393 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) {
394 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
395 AMD_PG_STATE_GATE);
396 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
397 false);
398 if (r)
399 dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r);
400 } else {
401 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
402 }
403 }
404
amdgpu_vcn_ring_begin_use(struct amdgpu_ring * ring)405 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
406 {
407 struct amdgpu_device *adev = ring->adev;
408 int r = 0;
409
410 atomic_inc(&adev->vcn.total_submission_cnt);
411
412 if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) {
413 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
414 true);
415 if (r)
416 dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r);
417 }
418
419 mutex_lock(&adev->vcn.vcn_pg_lock);
420 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
421 AMD_PG_STATE_UNGATE);
422
423 /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */
424 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
425 !adev->vcn.using_unified_queue) {
426 struct dpg_pause_state new_state;
427
428 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) {
429 atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
430 new_state.fw_based = VCN_DPG_STATE__PAUSE;
431 } else {
432 unsigned int fences = 0;
433 unsigned int i;
434
435 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
436 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]);
437
438 if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt))
439 new_state.fw_based = VCN_DPG_STATE__PAUSE;
440 else
441 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
442 }
443
444 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state);
445 }
446 mutex_unlock(&adev->vcn.vcn_pg_lock);
447 }
448
amdgpu_vcn_ring_end_use(struct amdgpu_ring * ring)449 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
450 {
451 struct amdgpu_device *adev = ring->adev;
452
453 /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */
454 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
455 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC &&
456 !adev->vcn.using_unified_queue)
457 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
458
459 atomic_dec(&ring->adev->vcn.total_submission_cnt);
460
461 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
462 }
463
amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring * ring)464 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
465 {
466 struct amdgpu_device *adev = ring->adev;
467 uint32_t tmp = 0;
468 unsigned int i;
469 int r;
470
471 /* VCN in SRIOV does not support direct register read/write */
472 if (amdgpu_sriov_vf(adev))
473 return 0;
474
475 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
476 r = amdgpu_ring_alloc(ring, 3);
477 if (r)
478 return r;
479 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
480 amdgpu_ring_write(ring, 0xDEADBEEF);
481 amdgpu_ring_commit(ring);
482 for (i = 0; i < adev->usec_timeout; i++) {
483 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
484 if (tmp == 0xDEADBEEF)
485 break;
486 udelay(1);
487 }
488
489 if (i >= adev->usec_timeout)
490 r = -ETIMEDOUT;
491
492 return r;
493 }
494
amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring * ring)495 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring)
496 {
497 struct amdgpu_device *adev = ring->adev;
498 uint32_t rptr;
499 unsigned int i;
500 int r;
501
502 if (amdgpu_sriov_vf(adev))
503 return 0;
504
505 r = amdgpu_ring_alloc(ring, 16);
506 if (r)
507 return r;
508
509 rptr = amdgpu_ring_get_rptr(ring);
510
511 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
512 amdgpu_ring_commit(ring);
513
514 for (i = 0; i < adev->usec_timeout; i++) {
515 if (amdgpu_ring_get_rptr(ring) != rptr)
516 break;
517 udelay(1);
518 }
519
520 if (i >= adev->usec_timeout)
521 r = -ETIMEDOUT;
522
523 return r;
524 }
525
amdgpu_vcn_dec_send_msg(struct amdgpu_ring * ring,struct amdgpu_ib * ib_msg,struct dma_fence ** fence)526 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
527 struct amdgpu_ib *ib_msg,
528 struct dma_fence **fence)
529 {
530 u64 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
531 struct amdgpu_device *adev = ring->adev;
532 struct dma_fence *f = NULL;
533 struct amdgpu_job *job;
534 struct amdgpu_ib *ib;
535 int i, r;
536
537 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
538 64, AMDGPU_IB_POOL_DIRECT,
539 &job);
540 if (r)
541 goto err;
542
543 ib = &job->ibs[0];
544 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0);
545 ib->ptr[1] = addr;
546 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0);
547 ib->ptr[3] = addr >> 32;
548 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0);
549 ib->ptr[5] = 0;
550 for (i = 6; i < 16; i += 2) {
551 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0);
552 ib->ptr[i+1] = 0;
553 }
554 ib->length_dw = 16;
555
556 r = amdgpu_job_submit_direct(job, ring, &f);
557 if (r)
558 goto err_free;
559
560 amdgpu_ib_free(adev, ib_msg, f);
561
562 if (fence)
563 *fence = dma_fence_get(f);
564 dma_fence_put(f);
565
566 return 0;
567
568 err_free:
569 amdgpu_job_free(job);
570 err:
571 amdgpu_ib_free(adev, ib_msg, f);
572 return r;
573 }
574
amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring * ring,uint32_t handle,struct amdgpu_ib * ib)575 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
576 struct amdgpu_ib *ib)
577 {
578 struct amdgpu_device *adev = ring->adev;
579 uint32_t *msg;
580 int r, i;
581
582 memset(ib, 0, sizeof(*ib));
583 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,
584 AMDGPU_IB_POOL_DIRECT,
585 ib);
586 if (r)
587 return r;
588
589 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);
590 msg[0] = cpu_to_le32(0x00000028);
591 msg[1] = cpu_to_le32(0x00000038);
592 msg[2] = cpu_to_le32(0x00000001);
593 msg[3] = cpu_to_le32(0x00000000);
594 msg[4] = cpu_to_le32(handle);
595 msg[5] = cpu_to_le32(0x00000000);
596 msg[6] = cpu_to_le32(0x00000001);
597 msg[7] = cpu_to_le32(0x00000028);
598 msg[8] = cpu_to_le32(0x00000010);
599 msg[9] = cpu_to_le32(0x00000000);
600 msg[10] = cpu_to_le32(0x00000007);
601 msg[11] = cpu_to_le32(0x00000000);
602 msg[12] = cpu_to_le32(0x00000780);
603 msg[13] = cpu_to_le32(0x00000440);
604 for (i = 14; i < 1024; ++i)
605 msg[i] = cpu_to_le32(0x0);
606
607 return 0;
608 }
609
amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring * ring,uint32_t handle,struct amdgpu_ib * ib)610 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
611 struct amdgpu_ib *ib)
612 {
613 struct amdgpu_device *adev = ring->adev;
614 uint32_t *msg;
615 int r, i;
616
617 memset(ib, 0, sizeof(*ib));
618 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,
619 AMDGPU_IB_POOL_DIRECT,
620 ib);
621 if (r)
622 return r;
623
624 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);
625 msg[0] = cpu_to_le32(0x00000028);
626 msg[1] = cpu_to_le32(0x00000018);
627 msg[2] = cpu_to_le32(0x00000000);
628 msg[3] = cpu_to_le32(0x00000002);
629 msg[4] = cpu_to_le32(handle);
630 msg[5] = cpu_to_le32(0x00000000);
631 for (i = 6; i < 1024; ++i)
632 msg[i] = cpu_to_le32(0x0);
633
634 return 0;
635 }
636
amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring * ring,long timeout)637 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
638 {
639 struct dma_fence *fence = NULL;
640 struct amdgpu_ib ib;
641 long r;
642
643 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib);
644 if (r)
645 goto error;
646
647 r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL);
648 if (r)
649 goto error;
650 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib);
651 if (r)
652 goto error;
653
654 r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence);
655 if (r)
656 goto error;
657
658 r = dma_fence_wait_timeout(fence, false, timeout);
659 if (r == 0)
660 r = -ETIMEDOUT;
661 else if (r > 0)
662 r = 0;
663
664 dma_fence_put(fence);
665 error:
666 return r;
667 }
668
amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib * ib,uint32_t ib_pack_in_dw,bool enc)669 static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib,
670 uint32_t ib_pack_in_dw, bool enc)
671 {
672 uint32_t *ib_checksum;
673
674 ib->ptr[ib->length_dw++] = 0x00000010; /* single queue checksum */
675 ib->ptr[ib->length_dw++] = 0x30000002;
676 ib_checksum = &ib->ptr[ib->length_dw++];
677 ib->ptr[ib->length_dw++] = ib_pack_in_dw;
678
679 ib->ptr[ib->length_dw++] = 0x00000010; /* engine info */
680 ib->ptr[ib->length_dw++] = 0x30000001;
681 ib->ptr[ib->length_dw++] = enc ? 0x2 : 0x3;
682 ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t);
683
684 return ib_checksum;
685 }
686
amdgpu_vcn_unified_ring_ib_checksum(uint32_t ** ib_checksum,uint32_t ib_pack_in_dw)687 static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum,
688 uint32_t ib_pack_in_dw)
689 {
690 uint32_t i;
691 uint32_t checksum = 0;
692
693 for (i = 0; i < ib_pack_in_dw; i++)
694 checksum += *(*ib_checksum + 2 + i);
695
696 **ib_checksum = checksum;
697 }
698
amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring * ring,struct amdgpu_ib * ib_msg,struct dma_fence ** fence)699 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
700 struct amdgpu_ib *ib_msg,
701 struct dma_fence **fence)
702 {
703 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL;
704 unsigned int ib_size_dw = 64;
705 struct amdgpu_device *adev = ring->adev;
706 struct dma_fence *f = NULL;
707 struct amdgpu_job *job;
708 struct amdgpu_ib *ib;
709 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
710 uint32_t *ib_checksum;
711 uint32_t ib_pack_in_dw;
712 int i, r;
713
714 if (adev->vcn.using_unified_queue)
715 ib_size_dw += 8;
716
717 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
718 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
719 &job);
720 if (r)
721 goto err;
722
723 ib = &job->ibs[0];
724 ib->length_dw = 0;
725
726 /* single queue headers */
727 if (adev->vcn.using_unified_queue) {
728 ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t)
729 + 4 + 2; /* engine info + decoding ib in dw */
730 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false);
731 }
732
733 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8;
734 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER);
735 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]);
736 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4;
737 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer));
738
739 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER);
740 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32);
741 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr);
742
743 for (i = ib->length_dw; i < ib_size_dw; ++i)
744 ib->ptr[i] = 0x0;
745
746 if (adev->vcn.using_unified_queue)
747 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, ib_pack_in_dw);
748
749 r = amdgpu_job_submit_direct(job, ring, &f);
750 if (r)
751 goto err_free;
752
753 amdgpu_ib_free(adev, ib_msg, f);
754
755 if (fence)
756 *fence = dma_fence_get(f);
757 dma_fence_put(f);
758
759 return 0;
760
761 err_free:
762 amdgpu_job_free(job);
763 err:
764 amdgpu_ib_free(adev, ib_msg, f);
765 return r;
766 }
767
amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring * ring,long timeout)768 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout)
769 {
770 struct dma_fence *fence = NULL;
771 struct amdgpu_ib ib;
772 long r;
773
774 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib);
775 if (r)
776 goto error;
777
778 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL);
779 if (r)
780 goto error;
781 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib);
782 if (r)
783 goto error;
784
785 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence);
786 if (r)
787 goto error;
788
789 r = dma_fence_wait_timeout(fence, false, timeout);
790 if (r == 0)
791 r = -ETIMEDOUT;
792 else if (r > 0)
793 r = 0;
794
795 dma_fence_put(fence);
796 error:
797 return r;
798 }
799
amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring * ring)800 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
801 {
802 struct amdgpu_device *adev = ring->adev;
803 uint32_t rptr;
804 unsigned int i;
805 int r;
806
807 if (amdgpu_sriov_vf(adev))
808 return 0;
809
810 r = amdgpu_ring_alloc(ring, 16);
811 if (r)
812 return r;
813
814 rptr = amdgpu_ring_get_rptr(ring);
815
816 amdgpu_ring_write(ring, VCN_ENC_CMD_END);
817 amdgpu_ring_commit(ring);
818
819 for (i = 0; i < adev->usec_timeout; i++) {
820 if (amdgpu_ring_get_rptr(ring) != rptr)
821 break;
822 udelay(1);
823 }
824
825 if (i >= adev->usec_timeout)
826 r = -ETIMEDOUT;
827
828 return r;
829 }
830
amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring * ring,uint32_t handle,struct amdgpu_ib * ib_msg,struct dma_fence ** fence)831 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
832 struct amdgpu_ib *ib_msg,
833 struct dma_fence **fence)
834 {
835 unsigned int ib_size_dw = 16;
836 struct amdgpu_device *adev = ring->adev;
837 struct amdgpu_job *job;
838 struct amdgpu_ib *ib;
839 struct dma_fence *f = NULL;
840 uint32_t *ib_checksum = NULL;
841 uint64_t addr;
842 int i, r;
843
844 if (adev->vcn.using_unified_queue)
845 ib_size_dw += 8;
846
847 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
848 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
849 &job);
850 if (r)
851 return r;
852
853 ib = &job->ibs[0];
854 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
855
856 ib->length_dw = 0;
857
858 if (adev->vcn.using_unified_queue)
859 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true);
860
861 ib->ptr[ib->length_dw++] = 0x00000018;
862 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
863 ib->ptr[ib->length_dw++] = handle;
864 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
865 ib->ptr[ib->length_dw++] = addr;
866 ib->ptr[ib->length_dw++] = 0x0000000b;
867
868 ib->ptr[ib->length_dw++] = 0x00000014;
869 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
870 ib->ptr[ib->length_dw++] = 0x0000001c;
871 ib->ptr[ib->length_dw++] = 0x00000000;
872 ib->ptr[ib->length_dw++] = 0x00000000;
873
874 ib->ptr[ib->length_dw++] = 0x00000008;
875 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
876
877 for (i = ib->length_dw; i < ib_size_dw; ++i)
878 ib->ptr[i] = 0x0;
879
880 if (adev->vcn.using_unified_queue)
881 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11);
882
883 r = amdgpu_job_submit_direct(job, ring, &f);
884 if (r)
885 goto err;
886
887 if (fence)
888 *fence = dma_fence_get(f);
889 dma_fence_put(f);
890
891 return 0;
892
893 err:
894 amdgpu_job_free(job);
895 return r;
896 }
897
amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring * ring,uint32_t handle,struct amdgpu_ib * ib_msg,struct dma_fence ** fence)898 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
899 struct amdgpu_ib *ib_msg,
900 struct dma_fence **fence)
901 {
902 unsigned int ib_size_dw = 16;
903 struct amdgpu_device *adev = ring->adev;
904 struct amdgpu_job *job;
905 struct amdgpu_ib *ib;
906 struct dma_fence *f = NULL;
907 uint32_t *ib_checksum = NULL;
908 uint64_t addr;
909 int i, r;
910
911 if (adev->vcn.using_unified_queue)
912 ib_size_dw += 8;
913
914 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
915 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
916 &job);
917 if (r)
918 return r;
919
920 ib = &job->ibs[0];
921 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
922
923 ib->length_dw = 0;
924
925 if (adev->vcn.using_unified_queue)
926 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true);
927
928 ib->ptr[ib->length_dw++] = 0x00000018;
929 ib->ptr[ib->length_dw++] = 0x00000001;
930 ib->ptr[ib->length_dw++] = handle;
931 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
932 ib->ptr[ib->length_dw++] = addr;
933 ib->ptr[ib->length_dw++] = 0x0000000b;
934
935 ib->ptr[ib->length_dw++] = 0x00000014;
936 ib->ptr[ib->length_dw++] = 0x00000002;
937 ib->ptr[ib->length_dw++] = 0x0000001c;
938 ib->ptr[ib->length_dw++] = 0x00000000;
939 ib->ptr[ib->length_dw++] = 0x00000000;
940
941 ib->ptr[ib->length_dw++] = 0x00000008;
942 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
943
944 for (i = ib->length_dw; i < ib_size_dw; ++i)
945 ib->ptr[i] = 0x0;
946
947 if (adev->vcn.using_unified_queue)
948 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11);
949
950 r = amdgpu_job_submit_direct(job, ring, &f);
951 if (r)
952 goto err;
953
954 if (fence)
955 *fence = dma_fence_get(f);
956 dma_fence_put(f);
957
958 return 0;
959
960 err:
961 amdgpu_job_free(job);
962 return r;
963 }
964
amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring * ring,long timeout)965 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
966 {
967 struct amdgpu_device *adev = ring->adev;
968 struct dma_fence *fence = NULL;
969 struct amdgpu_ib ib;
970 long r;
971
972 memset(&ib, 0, sizeof(ib));
973 r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE,
974 AMDGPU_IB_POOL_DIRECT,
975 &ib);
976 if (r)
977 return r;
978
979 r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL);
980 if (r)
981 goto error;
982
983 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence);
984 if (r)
985 goto error;
986
987 r = dma_fence_wait_timeout(fence, false, timeout);
988 if (r == 0)
989 r = -ETIMEDOUT;
990 else if (r > 0)
991 r = 0;
992
993 error:
994 amdgpu_ib_free(adev, &ib, fence);
995 dma_fence_put(fence);
996
997 return r;
998 }
999
amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring * ring,long timeout)1000 int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1001 {
1002 struct amdgpu_device *adev = ring->adev;
1003 long r;
1004
1005 if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(4, 0, 3)) {
1006 r = amdgpu_vcn_enc_ring_test_ib(ring, timeout);
1007 if (r)
1008 goto error;
1009 }
1010
1011 r = amdgpu_vcn_dec_sw_ring_test_ib(ring, timeout);
1012
1013 error:
1014 return r;
1015 }
1016
amdgpu_vcn_get_enc_ring_prio(int ring)1017 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring)
1018 {
1019 switch (ring) {
1020 case 0:
1021 return AMDGPU_RING_PRIO_0;
1022 case 1:
1023 return AMDGPU_RING_PRIO_1;
1024 case 2:
1025 return AMDGPU_RING_PRIO_2;
1026 default:
1027 return AMDGPU_RING_PRIO_0;
1028 }
1029 }
1030
amdgpu_vcn_setup_ucode(struct amdgpu_device * adev)1031 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev)
1032 {
1033 int i;
1034 unsigned int idx;
1035
1036 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1037 const struct common_firmware_header *hdr;
1038
1039 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
1040
1041 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1042 if (adev->vcn.harvest_config & (1 << i))
1043 continue;
1044 /* currently only support 2 FW instances */
1045 if (i >= 2) {
1046 dev_info(adev->dev, "More then 2 VCN FW instances!\n");
1047 break;
1048 }
1049 idx = AMDGPU_UCODE_ID_VCN + i;
1050 adev->firmware.ucode[idx].ucode_id = idx;
1051 adev->firmware.ucode[idx].fw = adev->vcn.fw;
1052 adev->firmware.fw_size +=
1053 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
1054
1055 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(4, 0, 3))
1056 break;
1057 }
1058 dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
1059 }
1060 }
1061
1062 /*
1063 * debugfs for mapping vcn firmware log buffer.
1064 */
1065 #if defined(CONFIG_DEBUG_FS)
amdgpu_debugfs_vcn_fwlog_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1066 static ssize_t amdgpu_debugfs_vcn_fwlog_read(struct file *f, char __user *buf,
1067 size_t size, loff_t *pos)
1068 {
1069 struct amdgpu_vcn_inst *vcn;
1070 void *log_buf;
1071 volatile struct amdgpu_vcn_fwlog *plog;
1072 unsigned int read_pos, write_pos, available, i, read_bytes = 0;
1073 unsigned int read_num[2] = {0};
1074
1075 vcn = file_inode(f)->i_private;
1076 if (!vcn)
1077 return -ENODEV;
1078
1079 if (!vcn->fw_shared.cpu_addr || !amdgpu_vcnfw_log)
1080 return -EFAULT;
1081
1082 log_buf = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size;
1083
1084 plog = (volatile struct amdgpu_vcn_fwlog *)log_buf;
1085 read_pos = plog->rptr;
1086 write_pos = plog->wptr;
1087
1088 if (read_pos > AMDGPU_VCNFW_LOG_SIZE || write_pos > AMDGPU_VCNFW_LOG_SIZE)
1089 return -EFAULT;
1090
1091 if (!size || (read_pos == write_pos))
1092 return 0;
1093
1094 if (write_pos > read_pos) {
1095 available = write_pos - read_pos;
1096 read_num[0] = min(size, (size_t)available);
1097 } else {
1098 read_num[0] = AMDGPU_VCNFW_LOG_SIZE - read_pos;
1099 available = read_num[0] + write_pos - plog->header_size;
1100 if (size > available)
1101 read_num[1] = write_pos - plog->header_size;
1102 else if (size > read_num[0])
1103 read_num[1] = size - read_num[0];
1104 else
1105 read_num[0] = size;
1106 }
1107
1108 for (i = 0; i < 2; i++) {
1109 if (read_num[i]) {
1110 if (read_pos == AMDGPU_VCNFW_LOG_SIZE)
1111 read_pos = plog->header_size;
1112 if (read_num[i] == copy_to_user((buf + read_bytes),
1113 (log_buf + read_pos), read_num[i]))
1114 return -EFAULT;
1115
1116 read_bytes += read_num[i];
1117 read_pos += read_num[i];
1118 }
1119 }
1120
1121 plog->rptr = read_pos;
1122 *pos += read_bytes;
1123 return read_bytes;
1124 }
1125
1126 static const struct file_operations amdgpu_debugfs_vcnfwlog_fops = {
1127 .owner = THIS_MODULE,
1128 .read = amdgpu_debugfs_vcn_fwlog_read,
1129 .llseek = default_llseek
1130 };
1131 #endif
1132
amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device * adev,uint8_t i,struct amdgpu_vcn_inst * vcn)1133 void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, uint8_t i,
1134 struct amdgpu_vcn_inst *vcn)
1135 {
1136 #if defined(CONFIG_DEBUG_FS)
1137 struct drm_minor *minor = adev_to_drm(adev)->primary;
1138 struct dentry *root = minor->debugfs_root;
1139 char name[32];
1140
1141 sprintf(name, "amdgpu_vcn_%d_fwlog", i);
1142 debugfs_create_file_size(name, S_IFREG | 0444, root, vcn,
1143 &amdgpu_debugfs_vcnfwlog_fops,
1144 AMDGPU_VCNFW_LOG_SIZE);
1145 #endif
1146 }
1147
amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst * vcn)1148 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn)
1149 {
1150 #if defined(CONFIG_DEBUG_FS)
1151 volatile uint32_t *flag = vcn->fw_shared.cpu_addr;
1152 void *fw_log_cpu_addr = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size;
1153 uint64_t fw_log_gpu_addr = vcn->fw_shared.gpu_addr + vcn->fw_shared.mem_size;
1154 volatile struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr;
1155 volatile struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr
1156 + vcn->fw_shared.log_offset;
1157 *flag |= cpu_to_le32(AMDGPU_VCN_FW_LOGGING_FLAG);
1158 fw_log->is_enabled = 1;
1159 fw_log->addr_lo = cpu_to_le32(fw_log_gpu_addr & 0xFFFFFFFF);
1160 fw_log->addr_hi = cpu_to_le32(fw_log_gpu_addr >> 32);
1161 fw_log->size = cpu_to_le32(AMDGPU_VCNFW_LOG_SIZE);
1162
1163 log_buf->header_size = sizeof(struct amdgpu_vcn_fwlog);
1164 log_buf->buffer_size = AMDGPU_VCNFW_LOG_SIZE;
1165 log_buf->rptr = log_buf->header_size;
1166 log_buf->wptr = log_buf->header_size;
1167 log_buf->wrapped = 0;
1168 #endif
1169 }
1170
amdgpu_vcn_process_poison_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1171 int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev,
1172 struct amdgpu_irq_src *source,
1173 struct amdgpu_iv_entry *entry)
1174 {
1175 struct ras_common_if *ras_if = adev->vcn.ras_if;
1176 struct ras_dispatch_if ih_data = {
1177 .entry = entry,
1178 };
1179
1180 if (!ras_if)
1181 return 0;
1182
1183 if (!amdgpu_sriov_vf(adev)) {
1184 ih_data.head = *ras_if;
1185 amdgpu_ras_interrupt_dispatch(adev, &ih_data);
1186 } else {
1187 if (adev->virt.ops && adev->virt.ops->ras_poison_handler)
1188 adev->virt.ops->ras_poison_handler(adev);
1189 else
1190 dev_warn(adev->dev,
1191 "No ras_poison_handler interface in SRIOV for VCN!\n");
1192 }
1193
1194 return 0;
1195 }
1196
amdgpu_vcn_ras_late_init(struct amdgpu_device * adev,struct ras_common_if * ras_block)1197 int amdgpu_vcn_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
1198 {
1199 int r, i;
1200
1201 r = amdgpu_ras_block_late_init(adev, ras_block);
1202 if (r)
1203 return r;
1204
1205 if (amdgpu_ras_is_supported(adev, ras_block->block)) {
1206 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1207 if (adev->vcn.harvest_config & (1 << i) ||
1208 !adev->vcn.inst[i].ras_poison_irq.funcs)
1209 continue;
1210
1211 r = amdgpu_irq_get(adev, &adev->vcn.inst[i].ras_poison_irq, 0);
1212 if (r)
1213 goto late_fini;
1214 }
1215 }
1216 return 0;
1217
1218 late_fini:
1219 amdgpu_ras_block_late_fini(adev, ras_block);
1220 return r;
1221 }
1222
amdgpu_vcn_ras_sw_init(struct amdgpu_device * adev)1223 int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev)
1224 {
1225 int err;
1226 struct amdgpu_vcn_ras *ras;
1227
1228 if (!adev->vcn.ras)
1229 return 0;
1230
1231 ras = adev->vcn.ras;
1232 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
1233 if (err) {
1234 dev_err(adev->dev, "Failed to register vcn ras block!\n");
1235 return err;
1236 }
1237
1238 strcpy(ras->ras_block.ras_comm.name, "vcn");
1239 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN;
1240 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON;
1241 adev->vcn.ras_if = &ras->ras_block.ras_comm;
1242
1243 if (!ras->ras_block.ras_late_init)
1244 ras->ras_block.ras_late_init = amdgpu_vcn_ras_late_init;
1245
1246 return 0;
1247 }
1248
amdgpu_vcn_psp_update_sram(struct amdgpu_device * adev,int inst_idx,enum AMDGPU_UCODE_ID ucode_id)1249 int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx,
1250 enum AMDGPU_UCODE_ID ucode_id)
1251 {
1252 struct amdgpu_firmware_info ucode = {
1253 .ucode_id = (ucode_id ? ucode_id :
1254 (inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
1255 AMDGPU_UCODE_ID_VCN0_RAM)),
1256 .mc_addr = adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
1257 .ucode_size = ((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
1258 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr),
1259 };
1260
1261 return psp_execute_ip_fw_load(&adev->psp, &ucode);
1262 }
1263