1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * AMD SoC Power Management Controller Driver
4 *
5 * Copyright (c) 2020, Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
9 */
10
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
13 #include <asm/amd_nb.h>
14 #include <linux/acpi.h>
15 #include <linux/bitfield.h>
16 #include <linux/bits.h>
17 #include <linux/debugfs.h>
18 #include <linux/delay.h>
19 #include <linux/io.h>
20 #include <linux/iopoll.h>
21 #include <linux/limits.h>
22 #include <linux/module.h>
23 #include <linux/pci.h>
24 #include <linux/platform_device.h>
25 #include <linux/rtc.h>
26 #include <linux/serio.h>
27 #include <linux/suspend.h>
28 #include <linux/seq_file.h>
29 #include <linux/uaccess.h>
30
31 #include "pmc.h"
32
33 /* SMU communication registers */
34 #define AMD_PMC_REGISTER_MESSAGE 0x538
35 #define AMD_PMC_REGISTER_RESPONSE 0x980
36 #define AMD_PMC_REGISTER_ARGUMENT 0x9BC
37
38 /* PMC Scratch Registers */
39 #define AMD_PMC_SCRATCH_REG_CZN 0x94
40 #define AMD_PMC_SCRATCH_REG_YC 0xD14
41
42 /* STB Registers */
43 #define AMD_PMC_STB_PMI_0 0x03E30600
44 #define AMD_PMC_STB_S2IDLE_PREPARE 0xC6000001
45 #define AMD_PMC_STB_S2IDLE_RESTORE 0xC6000002
46 #define AMD_PMC_STB_S2IDLE_CHECK 0xC6000003
47 #define AMD_PMC_STB_DUMMY_PC 0xC6000007
48
49 /* STB S2D(Spill to DRAM) has different message port offset */
50 #define AMD_S2D_REGISTER_MESSAGE 0xA20
51 #define AMD_S2D_REGISTER_RESPONSE 0xA80
52 #define AMD_S2D_REGISTER_ARGUMENT 0xA88
53
54 /* STB Spill to DRAM Parameters */
55 #define S2D_TELEMETRY_BYTES_MAX 0x100000
56 #define S2D_TELEMETRY_DRAMBYTES_MAX 0x1000000
57
58 /* Base address of SMU for mapping physical address to virtual address */
59 #define AMD_PMC_MAPPING_SIZE 0x01000
60 #define AMD_PMC_BASE_ADDR_OFFSET 0x10000
61 #define AMD_PMC_BASE_ADDR_LO 0x13B102E8
62 #define AMD_PMC_BASE_ADDR_HI 0x13B102EC
63 #define AMD_PMC_BASE_ADDR_LO_MASK GENMASK(15, 0)
64 #define AMD_PMC_BASE_ADDR_HI_MASK GENMASK(31, 20)
65
66 /* SMU Response Codes */
67 #define AMD_PMC_RESULT_OK 0x01
68 #define AMD_PMC_RESULT_CMD_REJECT_BUSY 0xFC
69 #define AMD_PMC_RESULT_CMD_REJECT_PREREQ 0xFD
70 #define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE
71 #define AMD_PMC_RESULT_FAILED 0xFF
72
73 /* FCH SSC Registers */
74 #define FCH_S0I3_ENTRY_TIME_L_OFFSET 0x30
75 #define FCH_S0I3_ENTRY_TIME_H_OFFSET 0x34
76 #define FCH_S0I3_EXIT_TIME_L_OFFSET 0x38
77 #define FCH_S0I3_EXIT_TIME_H_OFFSET 0x3C
78 #define FCH_SSC_MAPPING_SIZE 0x800
79 #define FCH_BASE_PHY_ADDR_LOW 0xFED81100
80 #define FCH_BASE_PHY_ADDR_HIGH 0x00000000
81
82 /* SMU Message Definations */
83 #define SMU_MSG_GETSMUVERSION 0x02
84 #define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04
85 #define SMU_MSG_LOG_GETDRAM_ADDR_LO 0x05
86 #define SMU_MSG_LOG_START 0x06
87 #define SMU_MSG_LOG_RESET 0x07
88 #define SMU_MSG_LOG_DUMP_DATA 0x08
89 #define SMU_MSG_GET_SUP_CONSTRAINTS 0x09
90
91 #define PMC_MSG_DELAY_MIN_US 50
92 #define RESPONSE_REGISTER_LOOP_MAX 20000
93
94 #define DELAY_MIN_US 2000
95 #define DELAY_MAX_US 3000
96 #define FIFO_SIZE 4096
97
98 enum amd_pmc_def {
99 MSG_TEST = 0x01,
100 MSG_OS_HINT_PCO,
101 MSG_OS_HINT_RN,
102 };
103
104 enum s2d_arg {
105 S2D_TELEMETRY_SIZE = 0x01,
106 S2D_PHYS_ADDR_LOW,
107 S2D_PHYS_ADDR_HIGH,
108 S2D_NUM_SAMPLES,
109 S2D_DRAM_SIZE,
110 };
111
112 struct amd_pmc_bit_map {
113 const char *name;
114 u32 bit_mask;
115 };
116
117 static const struct amd_pmc_bit_map soc15_ip_blk[] = {
118 {"DISPLAY", BIT(0)},
119 {"CPU", BIT(1)},
120 {"GFX", BIT(2)},
121 {"VDD", BIT(3)},
122 {"ACP", BIT(4)},
123 {"VCN", BIT(5)},
124 {"ISP", BIT(6)},
125 {"NBIO", BIT(7)},
126 {"DF", BIT(8)},
127 {"USB3_0", BIT(9)},
128 {"USB3_1", BIT(10)},
129 {"LAPIC", BIT(11)},
130 {"USB3_2", BIT(12)},
131 {"USB3_3", BIT(13)},
132 {"USB3_4", BIT(14)},
133 {"USB4_0", BIT(15)},
134 {"USB4_1", BIT(16)},
135 {"MPM", BIT(17)},
136 {"JPEG", BIT(18)},
137 {"IPU", BIT(19)},
138 {"UMSCH", BIT(20)},
139 {}
140 };
141
142 static bool enable_stb;
143 module_param(enable_stb, bool, 0644);
144 MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism");
145
146 static bool disable_workarounds;
147 module_param(disable_workarounds, bool, 0644);
148 MODULE_PARM_DESC(disable_workarounds, "Disable workarounds for platform bugs");
149
150 static struct amd_pmc_dev pmc;
151 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret);
152 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf);
153 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data);
154
amd_pmc_reg_read(struct amd_pmc_dev * dev,int reg_offset)155 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
156 {
157 return ioread32(dev->regbase + reg_offset);
158 }
159
amd_pmc_reg_write(struct amd_pmc_dev * dev,int reg_offset,u32 val)160 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
161 {
162 iowrite32(val, dev->regbase + reg_offset);
163 }
164
165 struct smu_metrics {
166 u32 table_version;
167 u32 hint_count;
168 u32 s0i3_last_entry_status;
169 u32 timein_s0i2;
170 u64 timeentering_s0i3_lastcapture;
171 u64 timeentering_s0i3_totaltime;
172 u64 timeto_resume_to_os_lastcapture;
173 u64 timeto_resume_to_os_totaltime;
174 u64 timein_s0i3_lastcapture;
175 u64 timein_s0i3_totaltime;
176 u64 timein_swdrips_lastcapture;
177 u64 timein_swdrips_totaltime;
178 u64 timecondition_notmet_lastcapture[32];
179 u64 timecondition_notmet_totaltime[32];
180 } __packed;
181
amd_pmc_stb_debugfs_open(struct inode * inode,struct file * filp)182 static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp)
183 {
184 struct amd_pmc_dev *dev = filp->f_inode->i_private;
185 u32 size = FIFO_SIZE * sizeof(u32);
186 u32 *buf;
187 int rc;
188
189 buf = kzalloc(size, GFP_KERNEL);
190 if (!buf)
191 return -ENOMEM;
192
193 rc = amd_pmc_read_stb(dev, buf);
194 if (rc) {
195 kfree(buf);
196 return rc;
197 }
198
199 filp->private_data = buf;
200 return rc;
201 }
202
amd_pmc_stb_debugfs_read(struct file * filp,char __user * buf,size_t size,loff_t * pos)203 static ssize_t amd_pmc_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
204 loff_t *pos)
205 {
206 if (!filp->private_data)
207 return -EINVAL;
208
209 return simple_read_from_buffer(buf, size, pos, filp->private_data,
210 FIFO_SIZE * sizeof(u32));
211 }
212
amd_pmc_stb_debugfs_release(struct inode * inode,struct file * filp)213 static int amd_pmc_stb_debugfs_release(struct inode *inode, struct file *filp)
214 {
215 kfree(filp->private_data);
216 return 0;
217 }
218
219 static const struct file_operations amd_pmc_stb_debugfs_fops = {
220 .owner = THIS_MODULE,
221 .open = amd_pmc_stb_debugfs_open,
222 .read = amd_pmc_stb_debugfs_read,
223 .release = amd_pmc_stb_debugfs_release,
224 };
225
amd_pmc_stb_debugfs_open_v2(struct inode * inode,struct file * filp)226 static int amd_pmc_stb_debugfs_open_v2(struct inode *inode, struct file *filp)
227 {
228 struct amd_pmc_dev *dev = filp->f_inode->i_private;
229 u32 *buf, fsize, num_samples, stb_rdptr_offset = 0;
230 int ret;
231
232 /* Write dummy postcode while reading the STB buffer */
233 ret = amd_pmc_write_stb(dev, AMD_PMC_STB_DUMMY_PC);
234 if (ret)
235 dev_err(dev->dev, "error writing to STB: %d\n", ret);
236
237 buf = kzalloc(S2D_TELEMETRY_BYTES_MAX, GFP_KERNEL);
238 if (!buf)
239 return -ENOMEM;
240
241 /* Spill to DRAM num_samples uses separate SMU message port */
242 dev->msg_port = 1;
243
244 /* Get the num_samples to calculate the last push location */
245 ret = amd_pmc_send_cmd(dev, S2D_NUM_SAMPLES, &num_samples, dev->s2d_msg_id, true);
246 /* Clear msg_port for other SMU operation */
247 dev->msg_port = 0;
248 if (ret) {
249 dev_err(dev->dev, "error: S2D_NUM_SAMPLES not supported : %d\n", ret);
250 kfree(buf);
251 return ret;
252 }
253
254 /* Start capturing data from the last push location */
255 if (num_samples > S2D_TELEMETRY_BYTES_MAX) {
256 fsize = S2D_TELEMETRY_BYTES_MAX;
257 stb_rdptr_offset = num_samples - fsize;
258 } else {
259 fsize = num_samples;
260 stb_rdptr_offset = 0;
261 }
262
263 memcpy_fromio(buf, dev->stb_virt_addr + stb_rdptr_offset, fsize);
264 filp->private_data = buf;
265
266 return 0;
267 }
268
amd_pmc_stb_debugfs_read_v2(struct file * filp,char __user * buf,size_t size,loff_t * pos)269 static ssize_t amd_pmc_stb_debugfs_read_v2(struct file *filp, char __user *buf, size_t size,
270 loff_t *pos)
271 {
272 if (!filp->private_data)
273 return -EINVAL;
274
275 return simple_read_from_buffer(buf, size, pos, filp->private_data,
276 S2D_TELEMETRY_BYTES_MAX);
277 }
278
amd_pmc_stb_debugfs_release_v2(struct inode * inode,struct file * filp)279 static int amd_pmc_stb_debugfs_release_v2(struct inode *inode, struct file *filp)
280 {
281 kfree(filp->private_data);
282 return 0;
283 }
284
285 static const struct file_operations amd_pmc_stb_debugfs_fops_v2 = {
286 .owner = THIS_MODULE,
287 .open = amd_pmc_stb_debugfs_open_v2,
288 .read = amd_pmc_stb_debugfs_read_v2,
289 .release = amd_pmc_stb_debugfs_release_v2,
290 };
291
amd_pmc_get_ip_info(struct amd_pmc_dev * dev)292 static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
293 {
294 switch (dev->cpu_id) {
295 case AMD_CPU_ID_PCO:
296 case AMD_CPU_ID_RN:
297 case AMD_CPU_ID_YC:
298 case AMD_CPU_ID_CB:
299 dev->num_ips = 12;
300 dev->s2d_msg_id = 0xBE;
301 break;
302 case AMD_CPU_ID_PS:
303 dev->num_ips = 21;
304 dev->s2d_msg_id = 0x85;
305 break;
306 }
307 }
308
amd_pmc_setup_smu_logging(struct amd_pmc_dev * dev)309 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
310 {
311 if (dev->cpu_id == AMD_CPU_ID_PCO) {
312 dev_warn_once(dev->dev, "SMU debugging info not supported on this platform\n");
313 return -EINVAL;
314 }
315
316 /* Get Active devices list from SMU */
317 if (!dev->active_ips)
318 amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, true);
319
320 /* Get dram address */
321 if (!dev->smu_virt_addr) {
322 u32 phys_addr_low, phys_addr_hi;
323 u64 smu_phys_addr;
324
325 amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, true);
326 amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, true);
327 smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
328
329 dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr,
330 sizeof(struct smu_metrics));
331 if (!dev->smu_virt_addr)
332 return -ENOMEM;
333 }
334
335 memset_io(dev->smu_virt_addr, 0, sizeof(struct smu_metrics));
336
337 /* Start the logging */
338 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_RESET, false);
339 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, false);
340
341 return 0;
342 }
343
get_metrics_table(struct amd_pmc_dev * pdev,struct smu_metrics * table)344 static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table)
345 {
346 if (!pdev->smu_virt_addr) {
347 int ret = amd_pmc_setup_smu_logging(pdev);
348
349 if (ret)
350 return ret;
351 }
352
353 if (pdev->cpu_id == AMD_CPU_ID_PCO)
354 return -ENODEV;
355 memcpy_fromio(table, pdev->smu_virt_addr, sizeof(struct smu_metrics));
356 return 0;
357 }
358
amd_pmc_validate_deepest(struct amd_pmc_dev * pdev)359 static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev)
360 {
361 struct smu_metrics table;
362
363 if (get_metrics_table(pdev, &table))
364 return;
365
366 if (!table.s0i3_last_entry_status)
367 dev_warn(pdev->dev, "Last suspend didn't reach deepest state\n");
368 pm_report_hw_sleep_time(table.s0i3_last_entry_status ?
369 table.timein_s0i3_lastcapture : 0);
370 }
371
amd_pmc_get_smu_version(struct amd_pmc_dev * dev)372 static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev)
373 {
374 int rc;
375 u32 val;
376
377 if (dev->cpu_id == AMD_CPU_ID_PCO)
378 return -ENODEV;
379
380 rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, true);
381 if (rc)
382 return rc;
383
384 dev->smu_program = (val >> 24) & GENMASK(7, 0);
385 dev->major = (val >> 16) & GENMASK(7, 0);
386 dev->minor = (val >> 8) & GENMASK(7, 0);
387 dev->rev = (val >> 0) & GENMASK(7, 0);
388
389 dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n",
390 dev->smu_program, dev->major, dev->minor, dev->rev);
391
392 return 0;
393 }
394
smu_fw_version_show(struct device * d,struct device_attribute * attr,char * buf)395 static ssize_t smu_fw_version_show(struct device *d, struct device_attribute *attr,
396 char *buf)
397 {
398 struct amd_pmc_dev *dev = dev_get_drvdata(d);
399
400 if (!dev->major) {
401 int rc = amd_pmc_get_smu_version(dev);
402
403 if (rc)
404 return rc;
405 }
406 return sysfs_emit(buf, "%u.%u.%u\n", dev->major, dev->minor, dev->rev);
407 }
408
smu_program_show(struct device * d,struct device_attribute * attr,char * buf)409 static ssize_t smu_program_show(struct device *d, struct device_attribute *attr,
410 char *buf)
411 {
412 struct amd_pmc_dev *dev = dev_get_drvdata(d);
413
414 if (!dev->major) {
415 int rc = amd_pmc_get_smu_version(dev);
416
417 if (rc)
418 return rc;
419 }
420 return sysfs_emit(buf, "%u\n", dev->smu_program);
421 }
422
423 static DEVICE_ATTR_RO(smu_fw_version);
424 static DEVICE_ATTR_RO(smu_program);
425
pmc_attr_is_visible(struct kobject * kobj,struct attribute * attr,int idx)426 static umode_t pmc_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
427 {
428 struct device *dev = kobj_to_dev(kobj);
429 struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
430
431 if (pdev->cpu_id == AMD_CPU_ID_PCO)
432 return 0;
433 return 0444;
434 }
435
436 static struct attribute *pmc_attrs[] = {
437 &dev_attr_smu_fw_version.attr,
438 &dev_attr_smu_program.attr,
439 NULL,
440 };
441
442 static struct attribute_group pmc_attr_group = {
443 .attrs = pmc_attrs,
444 .is_visible = pmc_attr_is_visible,
445 };
446
447 static const struct attribute_group *pmc_groups[] = {
448 &pmc_attr_group,
449 NULL,
450 };
451
smu_fw_info_show(struct seq_file * s,void * unused)452 static int smu_fw_info_show(struct seq_file *s, void *unused)
453 {
454 struct amd_pmc_dev *dev = s->private;
455 struct smu_metrics table;
456 int idx;
457
458 if (get_metrics_table(dev, &table))
459 return -EINVAL;
460
461 seq_puts(s, "\n=== SMU Statistics ===\n");
462 seq_printf(s, "Table Version: %d\n", table.table_version);
463 seq_printf(s, "Hint Count: %d\n", table.hint_count);
464 seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" :
465 "Unknown/Fail");
466 seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
467 seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
468 seq_printf(s, "Time (in us) to resume from S0i3: %lld\n",
469 table.timeto_resume_to_os_lastcapture);
470
471 seq_puts(s, "\n=== Active time (in us) ===\n");
472 for (idx = 0 ; idx < dev->num_ips ; idx++) {
473 if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
474 seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
475 table.timecondition_notmet_lastcapture[idx]);
476 }
477
478 return 0;
479 }
480 DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
481
s0ix_stats_show(struct seq_file * s,void * unused)482 static int s0ix_stats_show(struct seq_file *s, void *unused)
483 {
484 struct amd_pmc_dev *dev = s->private;
485 u64 entry_time, exit_time, residency;
486
487 /* Use FCH registers to get the S0ix stats */
488 if (!dev->fch_virt_addr) {
489 u32 base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
490 u32 base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
491 u64 fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
492
493 dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE);
494 if (!dev->fch_virt_addr)
495 return -ENOMEM;
496 }
497
498 entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
499 entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
500
501 exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
502 exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
503
504 /* It's in 48MHz. We need to convert it */
505 residency = exit_time - entry_time;
506 do_div(residency, 48);
507
508 seq_puts(s, "=== S0ix statistics ===\n");
509 seq_printf(s, "S0ix Entry Time: %lld\n", entry_time);
510 seq_printf(s, "S0ix Exit Time: %lld\n", exit_time);
511 seq_printf(s, "Residency Time: %lld\n", residency);
512
513 return 0;
514 }
515 DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
516
amd_pmc_idlemask_read(struct amd_pmc_dev * pdev,struct device * dev,struct seq_file * s)517 static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
518 struct seq_file *s)
519 {
520 u32 val;
521 int rc;
522
523 switch (pdev->cpu_id) {
524 case AMD_CPU_ID_CZN:
525 /* we haven't yet read SMU version */
526 if (!pdev->major) {
527 rc = amd_pmc_get_smu_version(pdev);
528 if (rc)
529 return rc;
530 }
531 if (pdev->major > 56 || (pdev->major >= 55 && pdev->minor >= 37))
532 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN);
533 else
534 return -EINVAL;
535 break;
536 case AMD_CPU_ID_YC:
537 case AMD_CPU_ID_CB:
538 case AMD_CPU_ID_PS:
539 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC);
540 break;
541 default:
542 return -EINVAL;
543 }
544
545 if (dev)
546 pm_pr_dbg("SMU idlemask s0i3: 0x%x\n", val);
547
548 if (s)
549 seq_printf(s, "SMU idlemask : 0x%x\n", val);
550
551 return 0;
552 }
553
amd_pmc_idlemask_show(struct seq_file * s,void * unused)554 static int amd_pmc_idlemask_show(struct seq_file *s, void *unused)
555 {
556 return amd_pmc_idlemask_read(s->private, NULL, s);
557 }
558 DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask);
559
amd_pmc_dbgfs_unregister(struct amd_pmc_dev * dev)560 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
561 {
562 debugfs_remove_recursive(dev->dbgfs_dir);
563 }
564
amd_pmc_is_stb_supported(struct amd_pmc_dev * dev)565 static bool amd_pmc_is_stb_supported(struct amd_pmc_dev *dev)
566 {
567 switch (dev->cpu_id) {
568 case AMD_CPU_ID_YC:
569 case AMD_CPU_ID_CB:
570 case AMD_CPU_ID_PS:
571 return true;
572 default:
573 return false;
574 }
575 }
576
amd_pmc_dbgfs_register(struct amd_pmc_dev * dev)577 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
578 {
579 dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
580 debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
581 &smu_fw_info_fops);
582 debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
583 &s0ix_stats_fops);
584 debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev,
585 &amd_pmc_idlemask_fops);
586 /* Enable STB only when the module_param is set */
587 if (enable_stb) {
588 if (amd_pmc_is_stb_supported(dev))
589 debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
590 &amd_pmc_stb_debugfs_fops_v2);
591 else
592 debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
593 &amd_pmc_stb_debugfs_fops);
594 }
595 }
596
amd_pmc_dump_registers(struct amd_pmc_dev * dev)597 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
598 {
599 u32 value, message, argument, response;
600
601 if (dev->msg_port) {
602 message = AMD_S2D_REGISTER_MESSAGE;
603 argument = AMD_S2D_REGISTER_ARGUMENT;
604 response = AMD_S2D_REGISTER_RESPONSE;
605 } else {
606 message = AMD_PMC_REGISTER_MESSAGE;
607 argument = AMD_PMC_REGISTER_ARGUMENT;
608 response = AMD_PMC_REGISTER_RESPONSE;
609 }
610
611 value = amd_pmc_reg_read(dev, response);
612 dev_dbg(dev->dev, "AMD_%s_REGISTER_RESPONSE:%x\n", dev->msg_port ? "S2D" : "PMC", value);
613
614 value = amd_pmc_reg_read(dev, argument);
615 dev_dbg(dev->dev, "AMD_%s_REGISTER_ARGUMENT:%x\n", dev->msg_port ? "S2D" : "PMC", value);
616
617 value = amd_pmc_reg_read(dev, message);
618 dev_dbg(dev->dev, "AMD_%s_REGISTER_MESSAGE:%x\n", dev->msg_port ? "S2D" : "PMC", value);
619 }
620
amd_pmc_send_cmd(struct amd_pmc_dev * dev,u32 arg,u32 * data,u8 msg,bool ret)621 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret)
622 {
623 int rc;
624 u32 val, message, argument, response;
625
626 mutex_lock(&dev->lock);
627
628 if (dev->msg_port) {
629 message = AMD_S2D_REGISTER_MESSAGE;
630 argument = AMD_S2D_REGISTER_ARGUMENT;
631 response = AMD_S2D_REGISTER_RESPONSE;
632 } else {
633 message = AMD_PMC_REGISTER_MESSAGE;
634 argument = AMD_PMC_REGISTER_ARGUMENT;
635 response = AMD_PMC_REGISTER_RESPONSE;
636 }
637
638 /* Wait until we get a valid response */
639 rc = readx_poll_timeout(ioread32, dev->regbase + response,
640 val, val != 0, PMC_MSG_DELAY_MIN_US,
641 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
642 if (rc) {
643 dev_err(dev->dev, "failed to talk to SMU\n");
644 goto out_unlock;
645 }
646
647 /* Write zero to response register */
648 amd_pmc_reg_write(dev, response, 0);
649
650 /* Write argument into response register */
651 amd_pmc_reg_write(dev, argument, arg);
652
653 /* Write message ID to message ID register */
654 amd_pmc_reg_write(dev, message, msg);
655
656 /* Wait until we get a valid response */
657 rc = readx_poll_timeout(ioread32, dev->regbase + response,
658 val, val != 0, PMC_MSG_DELAY_MIN_US,
659 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
660 if (rc) {
661 dev_err(dev->dev, "SMU response timed out\n");
662 goto out_unlock;
663 }
664
665 switch (val) {
666 case AMD_PMC_RESULT_OK:
667 if (ret) {
668 /* PMFW may take longer time to return back the data */
669 usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
670 *data = amd_pmc_reg_read(dev, argument);
671 }
672 break;
673 case AMD_PMC_RESULT_CMD_REJECT_BUSY:
674 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
675 rc = -EBUSY;
676 goto out_unlock;
677 case AMD_PMC_RESULT_CMD_UNKNOWN:
678 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
679 rc = -EINVAL;
680 goto out_unlock;
681 case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
682 case AMD_PMC_RESULT_FAILED:
683 default:
684 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
685 rc = -EIO;
686 goto out_unlock;
687 }
688
689 out_unlock:
690 mutex_unlock(&dev->lock);
691 amd_pmc_dump_registers(dev);
692 return rc;
693 }
694
amd_pmc_get_os_hint(struct amd_pmc_dev * dev)695 static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
696 {
697 switch (dev->cpu_id) {
698 case AMD_CPU_ID_PCO:
699 return MSG_OS_HINT_PCO;
700 case AMD_CPU_ID_RN:
701 case AMD_CPU_ID_YC:
702 case AMD_CPU_ID_CB:
703 case AMD_CPU_ID_PS:
704 return MSG_OS_HINT_RN;
705 }
706 return -EINVAL;
707 }
708
amd_pmc_wa_irq1(struct amd_pmc_dev * pdev)709 static int amd_pmc_wa_irq1(struct amd_pmc_dev *pdev)
710 {
711 struct device *d;
712 int rc;
713
714 /* cezanne platform firmware has a fix in 64.66.0 */
715 if (pdev->cpu_id == AMD_CPU_ID_CZN) {
716 if (!pdev->major) {
717 rc = amd_pmc_get_smu_version(pdev);
718 if (rc)
719 return rc;
720 }
721
722 if (pdev->major > 64 || (pdev->major == 64 && pdev->minor > 65))
723 return 0;
724 }
725
726 d = bus_find_device_by_name(&serio_bus, NULL, "serio0");
727 if (!d)
728 return 0;
729 if (device_may_wakeup(d)) {
730 dev_info_once(d, "Disabling IRQ1 wakeup source to avoid platform firmware bug\n");
731 disable_irq_wake(1);
732 device_set_wakeup_enable(d, false);
733 }
734 put_device(d);
735
736 return 0;
737 }
738
amd_pmc_verify_czn_rtc(struct amd_pmc_dev * pdev,u32 * arg)739 static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg)
740 {
741 struct rtc_device *rtc_device;
742 time64_t then, now, duration;
743 struct rtc_wkalrm alarm;
744 struct rtc_time tm;
745 int rc;
746
747 /* we haven't yet read SMU version */
748 if (!pdev->major) {
749 rc = amd_pmc_get_smu_version(pdev);
750 if (rc)
751 return rc;
752 }
753
754 if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53))
755 return 0;
756
757 rtc_device = rtc_class_open("rtc0");
758 if (!rtc_device)
759 return 0;
760 rc = rtc_read_alarm(rtc_device, &alarm);
761 if (rc)
762 return rc;
763 if (!alarm.enabled) {
764 dev_dbg(pdev->dev, "alarm not enabled\n");
765 return 0;
766 }
767 rc = rtc_read_time(rtc_device, &tm);
768 if (rc)
769 return rc;
770 then = rtc_tm_to_time64(&alarm.time);
771 now = rtc_tm_to_time64(&tm);
772 duration = then-now;
773
774 /* in the past */
775 if (then < now)
776 return 0;
777
778 /* will be stored in upper 16 bits of s0i3 hint argument,
779 * so timer wakeup from s0i3 is limited to ~18 hours or less
780 */
781 if (duration <= 4 || duration > U16_MAX)
782 return -EINVAL;
783
784 *arg |= (duration << 16);
785 rc = rtc_alarm_irq_enable(rtc_device, 0);
786 pm_pr_dbg("wakeup timer programmed for %lld seconds\n", duration);
787
788 return rc;
789 }
790
amd_pmc_s2idle_prepare(void)791 static void amd_pmc_s2idle_prepare(void)
792 {
793 struct amd_pmc_dev *pdev = &pmc;
794 int rc;
795 u8 msg;
796 u32 arg = 1;
797
798 /* Reset and Start SMU logging - to monitor the s0i3 stats */
799 amd_pmc_setup_smu_logging(pdev);
800
801 /* Activate CZN specific platform bug workarounds */
802 if (pdev->cpu_id == AMD_CPU_ID_CZN && !disable_workarounds) {
803 rc = amd_pmc_verify_czn_rtc(pdev, &arg);
804 if (rc) {
805 dev_err(pdev->dev, "failed to set RTC: %d\n", rc);
806 return;
807 }
808 }
809
810 msg = amd_pmc_get_os_hint(pdev);
811 rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, false);
812 if (rc) {
813 dev_err(pdev->dev, "suspend failed: %d\n", rc);
814 return;
815 }
816
817 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_PREPARE);
818 if (rc)
819 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
820 }
821
amd_pmc_s2idle_check(void)822 static void amd_pmc_s2idle_check(void)
823 {
824 struct amd_pmc_dev *pdev = &pmc;
825 struct smu_metrics table;
826 int rc;
827
828 /* Avoid triggering OVP */
829 if (!get_metrics_table(pdev, &table) && table.s0i3_last_entry_status)
830 msleep(2500);
831
832 /* Dump the IdleMask before we add to the STB */
833 amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
834
835 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_CHECK);
836 if (rc)
837 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
838 }
839
amd_pmc_dump_data(struct amd_pmc_dev * pdev)840 static int amd_pmc_dump_data(struct amd_pmc_dev *pdev)
841 {
842 if (pdev->cpu_id == AMD_CPU_ID_PCO)
843 return -ENODEV;
844
845 return amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, false);
846 }
847
amd_pmc_s2idle_restore(void)848 static void amd_pmc_s2idle_restore(void)
849 {
850 struct amd_pmc_dev *pdev = &pmc;
851 int rc;
852 u8 msg;
853
854 msg = amd_pmc_get_os_hint(pdev);
855 rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, false);
856 if (rc)
857 dev_err(pdev->dev, "resume failed: %d\n", rc);
858
859 /* Let SMU know that we are looking for stats */
860 amd_pmc_dump_data(pdev);
861
862 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_RESTORE);
863 if (rc)
864 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
865
866 /* Notify on failed entry */
867 amd_pmc_validate_deepest(pdev);
868
869 amd_pmc_process_restore_quirks(pdev);
870 }
871
872 static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = {
873 .prepare = amd_pmc_s2idle_prepare,
874 .check = amd_pmc_s2idle_check,
875 .restore = amd_pmc_s2idle_restore,
876 };
877
amd_pmc_suspend_handler(struct device * dev)878 static int amd_pmc_suspend_handler(struct device *dev)
879 {
880 struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
881
882 /*
883 * Must be called only from the same set of dev_pm_ops handlers
884 * as i8042_pm_suspend() is called: currently just from .suspend.
885 */
886 if (pdev->disable_8042_wakeup && !disable_workarounds) {
887 int rc = amd_pmc_wa_irq1(pdev);
888
889 if (rc) {
890 dev_err(pdev->dev, "failed to adjust keyboard wakeup: %d\n", rc);
891 return rc;
892 }
893 }
894
895 return 0;
896 }
897
898 static const struct dev_pm_ops amd_pmc_pm = {
899 .suspend = amd_pmc_suspend_handler,
900 };
901
902 static const struct pci_device_id pmc_pci_ids[] = {
903 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PS) },
904 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CB) },
905 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
906 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
907 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
908 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
909 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
910 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) },
911 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) },
912 { }
913 };
914
amd_pmc_s2d_init(struct amd_pmc_dev * dev)915 static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
916 {
917 u32 phys_addr_low, phys_addr_hi;
918 u64 stb_phys_addr;
919 u32 size = 0;
920 int ret;
921
922 /* Spill to DRAM feature uses separate SMU message port */
923 dev->msg_port = 1;
924
925 /* Get num of IP blocks within the SoC */
926 amd_pmc_get_ip_info(dev);
927
928 amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, dev->s2d_msg_id, true);
929 if (size != S2D_TELEMETRY_BYTES_MAX)
930 return -EIO;
931
932 /* Get DRAM size */
933 ret = amd_pmc_send_cmd(dev, S2D_DRAM_SIZE, &dev->dram_size, dev->s2d_msg_id, true);
934 if (ret || !dev->dram_size)
935 dev->dram_size = S2D_TELEMETRY_DRAMBYTES_MAX;
936
937 /* Get STB DRAM address */
938 amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, dev->s2d_msg_id, true);
939 amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, dev->s2d_msg_id, true);
940
941 if (!phys_addr_hi && !phys_addr_low) {
942 dev_err(dev->dev, "STB is not enabled on the system; disable enable_stb or contact system vendor\n");
943 return -EINVAL;
944 }
945
946 stb_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
947
948 /* Clear msg_port for other SMU operation */
949 dev->msg_port = 0;
950
951 dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, dev->dram_size);
952 if (!dev->stb_virt_addr)
953 return -ENOMEM;
954
955 return 0;
956 }
957
amd_pmc_write_stb(struct amd_pmc_dev * dev,u32 data)958 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data)
959 {
960 int err;
961
962 err = amd_smn_write(0, AMD_PMC_STB_PMI_0, data);
963 if (err) {
964 dev_err(dev->dev, "failed to write data in stb: 0x%X\n", AMD_PMC_STB_PMI_0);
965 return pcibios_err_to_errno(err);
966 }
967
968 return 0;
969 }
970
amd_pmc_read_stb(struct amd_pmc_dev * dev,u32 * buf)971 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf)
972 {
973 int i, err;
974
975 for (i = 0; i < FIFO_SIZE; i++) {
976 err = amd_smn_read(0, AMD_PMC_STB_PMI_0, buf++);
977 if (err) {
978 dev_err(dev->dev, "error reading data from stb: 0x%X\n", AMD_PMC_STB_PMI_0);
979 return pcibios_err_to_errno(err);
980 }
981 }
982
983 return 0;
984 }
985
amd_pmc_probe(struct platform_device * pdev)986 static int amd_pmc_probe(struct platform_device *pdev)
987 {
988 struct amd_pmc_dev *dev = &pmc;
989 struct pci_dev *rdev;
990 u32 base_addr_lo, base_addr_hi;
991 u64 base_addr;
992 int err;
993 u32 val;
994
995 dev->dev = &pdev->dev;
996
997 rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
998 if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
999 err = -ENODEV;
1000 goto err_pci_dev_put;
1001 }
1002
1003 dev->cpu_id = rdev->device;
1004
1005 if (dev->cpu_id == AMD_CPU_ID_SP) {
1006 dev_warn_once(dev->dev, "S0i3 is not supported on this hardware\n");
1007 err = -ENODEV;
1008 goto err_pci_dev_put;
1009 }
1010
1011 dev->rdev = rdev;
1012 err = amd_smn_read(0, AMD_PMC_BASE_ADDR_LO, &val);
1013 if (err) {
1014 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_LO);
1015 err = pcibios_err_to_errno(err);
1016 goto err_pci_dev_put;
1017 }
1018
1019 base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
1020
1021 err = amd_smn_read(0, AMD_PMC_BASE_ADDR_HI, &val);
1022 if (err) {
1023 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_HI);
1024 err = pcibios_err_to_errno(err);
1025 goto err_pci_dev_put;
1026 }
1027
1028 base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
1029 base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
1030
1031 dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
1032 AMD_PMC_MAPPING_SIZE);
1033 if (!dev->regbase) {
1034 err = -ENOMEM;
1035 goto err_pci_dev_put;
1036 }
1037
1038 mutex_init(&dev->lock);
1039
1040 if (enable_stb && amd_pmc_is_stb_supported(dev)) {
1041 err = amd_pmc_s2d_init(dev);
1042 if (err)
1043 goto err_pci_dev_put;
1044 }
1045
1046 platform_set_drvdata(pdev, dev);
1047 if (IS_ENABLED(CONFIG_SUSPEND)) {
1048 err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops);
1049 if (err)
1050 dev_warn(dev->dev, "failed to register LPS0 sleep handler, expect increased power consumption\n");
1051 if (!disable_workarounds)
1052 amd_pmc_quirks_init(dev);
1053 }
1054
1055 amd_pmc_dbgfs_register(dev);
1056 pm_report_max_hw_sleep(U64_MAX);
1057 return 0;
1058
1059 err_pci_dev_put:
1060 pci_dev_put(rdev);
1061 return err;
1062 }
1063
amd_pmc_remove(struct platform_device * pdev)1064 static void amd_pmc_remove(struct platform_device *pdev)
1065 {
1066 struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
1067
1068 if (IS_ENABLED(CONFIG_SUSPEND))
1069 acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops);
1070 amd_pmc_dbgfs_unregister(dev);
1071 pci_dev_put(dev->rdev);
1072 mutex_destroy(&dev->lock);
1073 }
1074
1075 static const struct acpi_device_id amd_pmc_acpi_ids[] = {
1076 {"AMDI0005", 0},
1077 {"AMDI0006", 0},
1078 {"AMDI0007", 0},
1079 {"AMDI0008", 0},
1080 {"AMDI0009", 0},
1081 {"AMDI000A", 0},
1082 {"AMD0004", 0},
1083 {"AMD0005", 0},
1084 { }
1085 };
1086 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
1087
1088 static struct platform_driver amd_pmc_driver = {
1089 .driver = {
1090 .name = "amd_pmc",
1091 .acpi_match_table = amd_pmc_acpi_ids,
1092 .dev_groups = pmc_groups,
1093 .pm = pm_sleep_ptr(&amd_pmc_pm),
1094 },
1095 .probe = amd_pmc_probe,
1096 .remove_new = amd_pmc_remove,
1097 };
1098 module_platform_driver(amd_pmc_driver);
1099
1100 MODULE_LICENSE("GPL v2");
1101 MODULE_DESCRIPTION("AMD PMC Driver");
1102