1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
6 */
7
8 #define pr_fmt(fmt) "AMD-Vi: " fmt
9 #define dev_fmt(fmt) pr_fmt(fmt)
10
11 #include <linux/ratelimit.h>
12 #include <linux/pci.h>
13 #include <linux/acpi.h>
14 #include <linux/pci-ats.h>
15 #include <linux/bitmap.h>
16 #include <linux/slab.h>
17 #include <linux/debugfs.h>
18 #include <linux/scatterlist.h>
19 #include <linux/dma-map-ops.h>
20 #include <linux/dma-direct.h>
21 #include <linux/iommu-helper.h>
22 #include <linux/delay.h>
23 #include <linux/amd-iommu.h>
24 #include <linux/notifier.h>
25 #include <linux/export.h>
26 #include <linux/irq.h>
27 #include <linux/msi.h>
28 #include <linux/irqdomain.h>
29 #include <linux/percpu.h>
30 #include <linux/io-pgtable.h>
31 #include <linux/cc_platform.h>
32 #include <asm/irq_remapping.h>
33 #include <asm/io_apic.h>
34 #include <asm/apic.h>
35 #include <asm/hw_irq.h>
36 #include <asm/proto.h>
37 #include <asm/iommu.h>
38 #include <asm/gart.h>
39 #include <asm/dma.h>
40
41 #include "amd_iommu.h"
42 #include "../dma-iommu.h"
43 #include "../irq_remapping.h"
44
45 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
46
47 #define LOOP_TIMEOUT 100000
48
49 /* IO virtual address start page frame number */
50 #define IOVA_START_PFN (1)
51 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
52
53 /* Reserved IOVA ranges */
54 #define MSI_RANGE_START (0xfee00000)
55 #define MSI_RANGE_END (0xfeefffff)
56 #define HT_RANGE_START (0xfd00000000ULL)
57 #define HT_RANGE_END (0xffffffffffULL)
58
59 #define DEFAULT_PGTABLE_LEVEL PAGE_MODE_3_LEVEL
60
61 static DEFINE_SPINLOCK(pd_bitmap_lock);
62
63 LIST_HEAD(ioapic_map);
64 LIST_HEAD(hpet_map);
65 LIST_HEAD(acpihid_map);
66
67 const struct iommu_ops amd_iommu_ops;
68
69 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
70 int amd_iommu_max_glx_val = -1;
71
72 /*
73 * general struct to manage commands send to an IOMMU
74 */
75 struct iommu_cmd {
76 u32 data[4];
77 };
78
79 struct kmem_cache *amd_iommu_irq_cache;
80
81 static void detach_device(struct device *dev);
82 static int domain_enable_v2(struct protection_domain *domain, int pasids);
83
84 /****************************************************************************
85 *
86 * Helper functions
87 *
88 ****************************************************************************/
89
get_acpihid_device_id(struct device * dev,struct acpihid_map_entry ** entry)90 static inline int get_acpihid_device_id(struct device *dev,
91 struct acpihid_map_entry **entry)
92 {
93 struct acpi_device *adev = ACPI_COMPANION(dev);
94 struct acpihid_map_entry *p;
95
96 if (!adev)
97 return -ENODEV;
98
99 list_for_each_entry(p, &acpihid_map, list) {
100 if (acpi_dev_hid_uid_match(adev, p->hid,
101 p->uid[0] ? p->uid : NULL)) {
102 if (entry)
103 *entry = p;
104 return p->devid;
105 }
106 }
107 return -EINVAL;
108 }
109
get_device_sbdf_id(struct device * dev)110 static inline int get_device_sbdf_id(struct device *dev)
111 {
112 int sbdf;
113
114 if (dev_is_pci(dev))
115 sbdf = get_pci_sbdf_id(to_pci_dev(dev));
116 else
117 sbdf = get_acpihid_device_id(dev, NULL);
118
119 return sbdf;
120 }
121
get_dev_table(struct amd_iommu * iommu)122 struct dev_table_entry *get_dev_table(struct amd_iommu *iommu)
123 {
124 struct dev_table_entry *dev_table;
125 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg;
126
127 BUG_ON(pci_seg == NULL);
128 dev_table = pci_seg->dev_table;
129 BUG_ON(dev_table == NULL);
130
131 return dev_table;
132 }
133
get_device_segment(struct device * dev)134 static inline u16 get_device_segment(struct device *dev)
135 {
136 u16 seg;
137
138 if (dev_is_pci(dev)) {
139 struct pci_dev *pdev = to_pci_dev(dev);
140
141 seg = pci_domain_nr(pdev->bus);
142 } else {
143 u32 devid = get_acpihid_device_id(dev, NULL);
144
145 seg = PCI_SBDF_TO_SEGID(devid);
146 }
147
148 return seg;
149 }
150
151 /* Writes the specific IOMMU for a device into the PCI segment rlookup table */
amd_iommu_set_rlookup_table(struct amd_iommu * iommu,u16 devid)152 void amd_iommu_set_rlookup_table(struct amd_iommu *iommu, u16 devid)
153 {
154 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg;
155
156 pci_seg->rlookup_table[devid] = iommu;
157 }
158
__rlookup_amd_iommu(u16 seg,u16 devid)159 static struct amd_iommu *__rlookup_amd_iommu(u16 seg, u16 devid)
160 {
161 struct amd_iommu_pci_seg *pci_seg;
162
163 for_each_pci_segment(pci_seg) {
164 if (pci_seg->id == seg)
165 return pci_seg->rlookup_table[devid];
166 }
167 return NULL;
168 }
169
rlookup_amd_iommu(struct device * dev)170 static struct amd_iommu *rlookup_amd_iommu(struct device *dev)
171 {
172 u16 seg = get_device_segment(dev);
173 int devid = get_device_sbdf_id(dev);
174
175 if (devid < 0)
176 return NULL;
177 return __rlookup_amd_iommu(seg, PCI_SBDF_TO_DEVID(devid));
178 }
179
to_pdomain(struct iommu_domain * dom)180 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
181 {
182 return container_of(dom, struct protection_domain, domain);
183 }
184
alloc_dev_data(struct amd_iommu * iommu,u16 devid)185 static struct iommu_dev_data *alloc_dev_data(struct amd_iommu *iommu, u16 devid)
186 {
187 struct iommu_dev_data *dev_data;
188 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg;
189
190 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
191 if (!dev_data)
192 return NULL;
193
194 spin_lock_init(&dev_data->lock);
195 dev_data->devid = devid;
196 ratelimit_default_init(&dev_data->rs);
197
198 llist_add(&dev_data->dev_data_list, &pci_seg->dev_data_list);
199 return dev_data;
200 }
201
search_dev_data(struct amd_iommu * iommu,u16 devid)202 static struct iommu_dev_data *search_dev_data(struct amd_iommu *iommu, u16 devid)
203 {
204 struct iommu_dev_data *dev_data;
205 struct llist_node *node;
206 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg;
207
208 if (llist_empty(&pci_seg->dev_data_list))
209 return NULL;
210
211 node = pci_seg->dev_data_list.first;
212 llist_for_each_entry(dev_data, node, dev_data_list) {
213 if (dev_data->devid == devid)
214 return dev_data;
215 }
216
217 return NULL;
218 }
219
clone_alias(struct pci_dev * pdev,u16 alias,void * data)220 static int clone_alias(struct pci_dev *pdev, u16 alias, void *data)
221 {
222 struct amd_iommu *iommu;
223 struct dev_table_entry *dev_table;
224 u16 devid = pci_dev_id(pdev);
225
226 if (devid == alias)
227 return 0;
228
229 iommu = rlookup_amd_iommu(&pdev->dev);
230 if (!iommu)
231 return 0;
232
233 amd_iommu_set_rlookup_table(iommu, alias);
234 dev_table = get_dev_table(iommu);
235 memcpy(dev_table[alias].data,
236 dev_table[devid].data,
237 sizeof(dev_table[alias].data));
238
239 return 0;
240 }
241
clone_aliases(struct amd_iommu * iommu,struct device * dev)242 static void clone_aliases(struct amd_iommu *iommu, struct device *dev)
243 {
244 struct pci_dev *pdev;
245
246 if (!dev_is_pci(dev))
247 return;
248 pdev = to_pci_dev(dev);
249
250 /*
251 * The IVRS alias stored in the alias table may not be
252 * part of the PCI DMA aliases if it's bus differs
253 * from the original device.
254 */
255 clone_alias(pdev, iommu->pci_seg->alias_table[pci_dev_id(pdev)], NULL);
256
257 pci_for_each_dma_alias(pdev, clone_alias, NULL);
258 }
259
setup_aliases(struct amd_iommu * iommu,struct device * dev)260 static void setup_aliases(struct amd_iommu *iommu, struct device *dev)
261 {
262 struct pci_dev *pdev = to_pci_dev(dev);
263 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg;
264 u16 ivrs_alias;
265
266 /* For ACPI HID devices, there are no aliases */
267 if (!dev_is_pci(dev))
268 return;
269
270 /*
271 * Add the IVRS alias to the pci aliases if it is on the same
272 * bus. The IVRS table may know about a quirk that we don't.
273 */
274 ivrs_alias = pci_seg->alias_table[pci_dev_id(pdev)];
275 if (ivrs_alias != pci_dev_id(pdev) &&
276 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number)
277 pci_add_dma_alias(pdev, ivrs_alias & 0xff, 1);
278
279 clone_aliases(iommu, dev);
280 }
281
find_dev_data(struct amd_iommu * iommu,u16 devid)282 static struct iommu_dev_data *find_dev_data(struct amd_iommu *iommu, u16 devid)
283 {
284 struct iommu_dev_data *dev_data;
285
286 dev_data = search_dev_data(iommu, devid);
287
288 if (dev_data == NULL) {
289 dev_data = alloc_dev_data(iommu, devid);
290 if (!dev_data)
291 return NULL;
292
293 if (translation_pre_enabled(iommu))
294 dev_data->defer_attach = true;
295 }
296
297 return dev_data;
298 }
299
300 /*
301 * Find or create an IOMMU group for a acpihid device.
302 */
acpihid_device_group(struct device * dev)303 static struct iommu_group *acpihid_device_group(struct device *dev)
304 {
305 struct acpihid_map_entry *p, *entry = NULL;
306 int devid;
307
308 devid = get_acpihid_device_id(dev, &entry);
309 if (devid < 0)
310 return ERR_PTR(devid);
311
312 list_for_each_entry(p, &acpihid_map, list) {
313 if ((devid == p->devid) && p->group)
314 entry->group = p->group;
315 }
316
317 if (!entry->group)
318 entry->group = generic_device_group(dev);
319 else
320 iommu_group_ref_get(entry->group);
321
322 return entry->group;
323 }
324
pci_iommuv2_capable(struct pci_dev * pdev)325 static bool pci_iommuv2_capable(struct pci_dev *pdev)
326 {
327 static const int caps[] = {
328 PCI_EXT_CAP_ID_PRI,
329 PCI_EXT_CAP_ID_PASID,
330 };
331 int i, pos;
332
333 if (!pci_ats_supported(pdev))
334 return false;
335
336 for (i = 0; i < 2; ++i) {
337 pos = pci_find_ext_capability(pdev, caps[i]);
338 if (pos == 0)
339 return false;
340 }
341
342 return true;
343 }
344
345 /*
346 * This function checks if the driver got a valid device from the caller to
347 * avoid dereferencing invalid pointers.
348 */
check_device(struct device * dev)349 static bool check_device(struct device *dev)
350 {
351 struct amd_iommu_pci_seg *pci_seg;
352 struct amd_iommu *iommu;
353 int devid, sbdf;
354
355 if (!dev)
356 return false;
357
358 sbdf = get_device_sbdf_id(dev);
359 if (sbdf < 0)
360 return false;
361 devid = PCI_SBDF_TO_DEVID(sbdf);
362
363 iommu = rlookup_amd_iommu(dev);
364 if (!iommu)
365 return false;
366
367 /* Out of our scope? */
368 pci_seg = iommu->pci_seg;
369 if (devid > pci_seg->last_bdf)
370 return false;
371
372 return true;
373 }
374
iommu_init_device(struct amd_iommu * iommu,struct device * dev)375 static int iommu_init_device(struct amd_iommu *iommu, struct device *dev)
376 {
377 struct iommu_dev_data *dev_data;
378 int devid, sbdf;
379
380 if (dev_iommu_priv_get(dev))
381 return 0;
382
383 sbdf = get_device_sbdf_id(dev);
384 if (sbdf < 0)
385 return sbdf;
386
387 devid = PCI_SBDF_TO_DEVID(sbdf);
388 dev_data = find_dev_data(iommu, devid);
389 if (!dev_data)
390 return -ENOMEM;
391
392 dev_data->dev = dev;
393 setup_aliases(iommu, dev);
394
395 /*
396 * By default we use passthrough mode for IOMMUv2 capable device.
397 * But if amd_iommu=force_isolation is set (e.g. to debug DMA to
398 * invalid address), we ignore the capability for the device so
399 * it'll be forced to go into translation mode.
400 */
401 if ((iommu_default_passthrough() || !amd_iommu_force_isolation) &&
402 dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
403 dev_data->iommu_v2 = iommu->is_iommu_v2;
404 }
405
406 dev_iommu_priv_set(dev, dev_data);
407
408 return 0;
409 }
410
iommu_ignore_device(struct amd_iommu * iommu,struct device * dev)411 static void iommu_ignore_device(struct amd_iommu *iommu, struct device *dev)
412 {
413 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg;
414 struct dev_table_entry *dev_table = get_dev_table(iommu);
415 int devid, sbdf;
416
417 sbdf = get_device_sbdf_id(dev);
418 if (sbdf < 0)
419 return;
420
421 devid = PCI_SBDF_TO_DEVID(sbdf);
422 pci_seg->rlookup_table[devid] = NULL;
423 memset(&dev_table[devid], 0, sizeof(struct dev_table_entry));
424
425 setup_aliases(iommu, dev);
426 }
427
amd_iommu_uninit_device(struct device * dev)428 static void amd_iommu_uninit_device(struct device *dev)
429 {
430 struct iommu_dev_data *dev_data;
431
432 dev_data = dev_iommu_priv_get(dev);
433 if (!dev_data)
434 return;
435
436 if (dev_data->domain)
437 detach_device(dev);
438
439 dev_iommu_priv_set(dev, NULL);
440
441 /*
442 * We keep dev_data around for unplugged devices and reuse it when the
443 * device is re-plugged - not doing so would introduce a ton of races.
444 */
445 }
446
447 /****************************************************************************
448 *
449 * Interrupt handling functions
450 *
451 ****************************************************************************/
452
dump_dte_entry(struct amd_iommu * iommu,u16 devid)453 static void dump_dte_entry(struct amd_iommu *iommu, u16 devid)
454 {
455 int i;
456 struct dev_table_entry *dev_table = get_dev_table(iommu);
457
458 for (i = 0; i < 4; ++i)
459 pr_err("DTE[%d]: %016llx\n", i, dev_table[devid].data[i]);
460 }
461
dump_command(unsigned long phys_addr)462 static void dump_command(unsigned long phys_addr)
463 {
464 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
465 int i;
466
467 for (i = 0; i < 4; ++i)
468 pr_err("CMD[%d]: %08x\n", i, cmd->data[i]);
469 }
470
amd_iommu_report_rmp_hw_error(struct amd_iommu * iommu,volatile u32 * event)471 static void amd_iommu_report_rmp_hw_error(struct amd_iommu *iommu, volatile u32 *event)
472 {
473 struct iommu_dev_data *dev_data = NULL;
474 int devid, vmg_tag, flags;
475 struct pci_dev *pdev;
476 u64 spa;
477
478 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
479 vmg_tag = (event[1]) & 0xFFFF;
480 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
481 spa = ((u64)event[3] << 32) | (event[2] & 0xFFFFFFF8);
482
483 pdev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, PCI_BUS_NUM(devid),
484 devid & 0xff);
485 if (pdev)
486 dev_data = dev_iommu_priv_get(&pdev->dev);
487
488 if (dev_data) {
489 if (__ratelimit(&dev_data->rs)) {
490 pci_err(pdev, "Event logged [RMP_HW_ERROR vmg_tag=0x%04x, spa=0x%llx, flags=0x%04x]\n",
491 vmg_tag, spa, flags);
492 }
493 } else {
494 pr_err_ratelimited("Event logged [RMP_HW_ERROR device=%04x:%02x:%02x.%x, vmg_tag=0x%04x, spa=0x%llx, flags=0x%04x]\n",
495 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
496 vmg_tag, spa, flags);
497 }
498
499 if (pdev)
500 pci_dev_put(pdev);
501 }
502
amd_iommu_report_rmp_fault(struct amd_iommu * iommu,volatile u32 * event)503 static void amd_iommu_report_rmp_fault(struct amd_iommu *iommu, volatile u32 *event)
504 {
505 struct iommu_dev_data *dev_data = NULL;
506 int devid, flags_rmp, vmg_tag, flags;
507 struct pci_dev *pdev;
508 u64 gpa;
509
510 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
511 flags_rmp = (event[0] >> EVENT_FLAGS_SHIFT) & 0xFF;
512 vmg_tag = (event[1]) & 0xFFFF;
513 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
514 gpa = ((u64)event[3] << 32) | event[2];
515
516 pdev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, PCI_BUS_NUM(devid),
517 devid & 0xff);
518 if (pdev)
519 dev_data = dev_iommu_priv_get(&pdev->dev);
520
521 if (dev_data) {
522 if (__ratelimit(&dev_data->rs)) {
523 pci_err(pdev, "Event logged [RMP_PAGE_FAULT vmg_tag=0x%04x, gpa=0x%llx, flags_rmp=0x%04x, flags=0x%04x]\n",
524 vmg_tag, gpa, flags_rmp, flags);
525 }
526 } else {
527 pr_err_ratelimited("Event logged [RMP_PAGE_FAULT device=%04x:%02x:%02x.%x, vmg_tag=0x%04x, gpa=0x%llx, flags_rmp=0x%04x, flags=0x%04x]\n",
528 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
529 vmg_tag, gpa, flags_rmp, flags);
530 }
531
532 if (pdev)
533 pci_dev_put(pdev);
534 }
535
536 #define IS_IOMMU_MEM_TRANSACTION(flags) \
537 (((flags) & EVENT_FLAG_I) == 0)
538
539 #define IS_WRITE_REQUEST(flags) \
540 ((flags) & EVENT_FLAG_RW)
541
amd_iommu_report_page_fault(struct amd_iommu * iommu,u16 devid,u16 domain_id,u64 address,int flags)542 static void amd_iommu_report_page_fault(struct amd_iommu *iommu,
543 u16 devid, u16 domain_id,
544 u64 address, int flags)
545 {
546 struct iommu_dev_data *dev_data = NULL;
547 struct pci_dev *pdev;
548
549 pdev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, PCI_BUS_NUM(devid),
550 devid & 0xff);
551 if (pdev)
552 dev_data = dev_iommu_priv_get(&pdev->dev);
553
554 if (dev_data) {
555 /*
556 * If this is a DMA fault (for which the I(nterrupt)
557 * bit will be unset), allow report_iommu_fault() to
558 * prevent logging it.
559 */
560 if (IS_IOMMU_MEM_TRANSACTION(flags)) {
561 /* Device not attached to domain properly */
562 if (dev_data->domain == NULL) {
563 pr_err_ratelimited("Event logged [Device not attached to domain properly]\n");
564 pr_err_ratelimited(" device=%04x:%02x:%02x.%x domain=0x%04x\n",
565 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid),
566 PCI_FUNC(devid), domain_id);
567 goto out;
568 }
569
570 if (!report_iommu_fault(&dev_data->domain->domain,
571 &pdev->dev, address,
572 IS_WRITE_REQUEST(flags) ?
573 IOMMU_FAULT_WRITE :
574 IOMMU_FAULT_READ))
575 goto out;
576 }
577
578 if (__ratelimit(&dev_data->rs)) {
579 pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%llx flags=0x%04x]\n",
580 domain_id, address, flags);
581 }
582 } else {
583 pr_err_ratelimited("Event logged [IO_PAGE_FAULT device=%04x:%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
584 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
585 domain_id, address, flags);
586 }
587
588 out:
589 if (pdev)
590 pci_dev_put(pdev);
591 }
592
iommu_print_event(struct amd_iommu * iommu,void * __evt)593 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
594 {
595 struct device *dev = iommu->iommu.dev;
596 int type, devid, flags, tag;
597 volatile u32 *event = __evt;
598 int count = 0;
599 u64 address;
600 u32 pasid;
601
602 retry:
603 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
604 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
605 pasid = (event[0] & EVENT_DOMID_MASK_HI) |
606 (event[1] & EVENT_DOMID_MASK_LO);
607 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
608 address = (u64)(((u64)event[3]) << 32) | event[2];
609
610 if (type == 0) {
611 /* Did we hit the erratum? */
612 if (++count == LOOP_TIMEOUT) {
613 pr_err("No event written to event log\n");
614 return;
615 }
616 udelay(1);
617 goto retry;
618 }
619
620 if (type == EVENT_TYPE_IO_FAULT) {
621 amd_iommu_report_page_fault(iommu, devid, pasid, address, flags);
622 return;
623 }
624
625 switch (type) {
626 case EVENT_TYPE_ILL_DEV:
627 dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%04x:%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
628 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
629 pasid, address, flags);
630 dump_dte_entry(iommu, devid);
631 break;
632 case EVENT_TYPE_DEV_TAB_ERR:
633 dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=%04x:%02x:%02x.%x "
634 "address=0x%llx flags=0x%04x]\n",
635 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
636 address, flags);
637 break;
638 case EVENT_TYPE_PAGE_TAB_ERR:
639 dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%04x:%02x:%02x.%x pasid=0x%04x address=0x%llx flags=0x%04x]\n",
640 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
641 pasid, address, flags);
642 break;
643 case EVENT_TYPE_ILL_CMD:
644 dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%llx]\n", address);
645 dump_command(address);
646 break;
647 case EVENT_TYPE_CMD_HARD_ERR:
648 dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%llx flags=0x%04x]\n",
649 address, flags);
650 break;
651 case EVENT_TYPE_IOTLB_INV_TO:
652 dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%04x:%02x:%02x.%x address=0x%llx]\n",
653 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
654 address);
655 break;
656 case EVENT_TYPE_INV_DEV_REQ:
657 dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%04x:%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
658 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
659 pasid, address, flags);
660 break;
661 case EVENT_TYPE_RMP_FAULT:
662 amd_iommu_report_rmp_fault(iommu, event);
663 break;
664 case EVENT_TYPE_RMP_HW_ERR:
665 amd_iommu_report_rmp_hw_error(iommu, event);
666 break;
667 case EVENT_TYPE_INV_PPR_REQ:
668 pasid = PPR_PASID(*((u64 *)__evt));
669 tag = event[1] & 0x03FF;
670 dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%04x:%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x tag=0x%03x]\n",
671 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
672 pasid, address, flags, tag);
673 break;
674 default:
675 dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
676 event[0], event[1], event[2], event[3]);
677 }
678
679 /*
680 * To detect the hardware errata 732 we need to clear the
681 * entry back to zero. This issue does not exist on SNP
682 * enabled system. Also this buffer is not writeable on
683 * SNP enabled system.
684 */
685 if (!amd_iommu_snp_en)
686 memset(__evt, 0, 4 * sizeof(u32));
687 }
688
iommu_poll_events(struct amd_iommu * iommu)689 static void iommu_poll_events(struct amd_iommu *iommu)
690 {
691 u32 head, tail;
692
693 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
694 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
695
696 while (head != tail) {
697 iommu_print_event(iommu, iommu->evt_buf + head);
698 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
699 }
700
701 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
702 }
703
iommu_handle_ppr_entry(struct amd_iommu * iommu,u64 * raw)704 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
705 {
706 struct amd_iommu_fault fault;
707
708 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
709 pr_err_ratelimited("Unknown PPR request received\n");
710 return;
711 }
712
713 fault.address = raw[1];
714 fault.pasid = PPR_PASID(raw[0]);
715 fault.sbdf = PCI_SEG_DEVID_TO_SBDF(iommu->pci_seg->id, PPR_DEVID(raw[0]));
716 fault.tag = PPR_TAG(raw[0]);
717 fault.flags = PPR_FLAGS(raw[0]);
718
719 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
720 }
721
iommu_poll_ppr_log(struct amd_iommu * iommu)722 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
723 {
724 u32 head, tail;
725
726 if (iommu->ppr_log == NULL)
727 return;
728
729 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
730 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
731
732 while (head != tail) {
733 volatile u64 *raw;
734 u64 entry[2];
735 int i;
736
737 raw = (u64 *)(iommu->ppr_log + head);
738
739 /*
740 * Hardware bug: Interrupt may arrive before the entry is
741 * written to memory. If this happens we need to wait for the
742 * entry to arrive.
743 */
744 for (i = 0; i < LOOP_TIMEOUT; ++i) {
745 if (PPR_REQ_TYPE(raw[0]) != 0)
746 break;
747 udelay(1);
748 }
749
750 /* Avoid memcpy function-call overhead */
751 entry[0] = raw[0];
752 entry[1] = raw[1];
753
754 /*
755 * To detect the hardware errata 733 we need to clear the
756 * entry back to zero. This issue does not exist on SNP
757 * enabled system. Also this buffer is not writeable on
758 * SNP enabled system.
759 */
760 if (!amd_iommu_snp_en)
761 raw[0] = raw[1] = 0UL;
762
763 /* Update head pointer of hardware ring-buffer */
764 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
765 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
766
767 /* Handle PPR entry */
768 iommu_handle_ppr_entry(iommu, entry);
769
770 /* Refresh ring-buffer information */
771 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
772 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
773 }
774 }
775
776 #ifdef CONFIG_IRQ_REMAP
777 static int (*iommu_ga_log_notifier)(u32);
778
amd_iommu_register_ga_log_notifier(int (* notifier)(u32))779 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
780 {
781 iommu_ga_log_notifier = notifier;
782
783 /*
784 * Ensure all in-flight IRQ handlers run to completion before returning
785 * to the caller, e.g. to ensure module code isn't unloaded while it's
786 * being executed in the IRQ handler.
787 */
788 if (!notifier)
789 synchronize_rcu();
790
791 return 0;
792 }
793 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
794
iommu_poll_ga_log(struct amd_iommu * iommu)795 static void iommu_poll_ga_log(struct amd_iommu *iommu)
796 {
797 u32 head, tail;
798
799 if (iommu->ga_log == NULL)
800 return;
801
802 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
803 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
804
805 while (head != tail) {
806 volatile u64 *raw;
807 u64 log_entry;
808
809 raw = (u64 *)(iommu->ga_log + head);
810
811 /* Avoid memcpy function-call overhead */
812 log_entry = *raw;
813
814 /* Update head pointer of hardware ring-buffer */
815 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
816 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
817
818 /* Handle GA entry */
819 switch (GA_REQ_TYPE(log_entry)) {
820 case GA_GUEST_NR:
821 if (!iommu_ga_log_notifier)
822 break;
823
824 pr_debug("%s: devid=%#x, ga_tag=%#x\n",
825 __func__, GA_DEVID(log_entry),
826 GA_TAG(log_entry));
827
828 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
829 pr_err("GA log notifier failed.\n");
830 break;
831 default:
832 break;
833 }
834 }
835 }
836
837 static void
amd_iommu_set_pci_msi_domain(struct device * dev,struct amd_iommu * iommu)838 amd_iommu_set_pci_msi_domain(struct device *dev, struct amd_iommu *iommu)
839 {
840 if (!irq_remapping_enabled || !dev_is_pci(dev) ||
841 !pci_dev_has_default_msi_parent_domain(to_pci_dev(dev)))
842 return;
843
844 dev_set_msi_domain(dev, iommu->ir_domain);
845 }
846
847 #else /* CONFIG_IRQ_REMAP */
848 static inline void
amd_iommu_set_pci_msi_domain(struct device * dev,struct amd_iommu * iommu)849 amd_iommu_set_pci_msi_domain(struct device *dev, struct amd_iommu *iommu) { }
850 #endif /* !CONFIG_IRQ_REMAP */
851
amd_iommu_handle_irq(void * data,const char * evt_type,u32 int_mask,u32 overflow_mask,void (* int_handler)(struct amd_iommu *),void (* overflow_handler)(struct amd_iommu *))852 static void amd_iommu_handle_irq(void *data, const char *evt_type,
853 u32 int_mask, u32 overflow_mask,
854 void (*int_handler)(struct amd_iommu *),
855 void (*overflow_handler)(struct amd_iommu *))
856 {
857 struct amd_iommu *iommu = (struct amd_iommu *) data;
858 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
859 u32 mask = int_mask | overflow_mask;
860
861 while (status & mask) {
862 /* Enable interrupt sources again */
863 writel(mask, iommu->mmio_base + MMIO_STATUS_OFFSET);
864
865 if (int_handler) {
866 pr_devel("Processing IOMMU (ivhd%d) %s Log\n",
867 iommu->index, evt_type);
868 int_handler(iommu);
869 }
870
871 if ((status & overflow_mask) && overflow_handler)
872 overflow_handler(iommu);
873
874 /*
875 * Hardware bug: ERBT1312
876 * When re-enabling interrupt (by writing 1
877 * to clear the bit), the hardware might also try to set
878 * the interrupt bit in the event status register.
879 * In this scenario, the bit will be set, and disable
880 * subsequent interrupts.
881 *
882 * Workaround: The IOMMU driver should read back the
883 * status register and check if the interrupt bits are cleared.
884 * If not, driver will need to go through the interrupt handler
885 * again and re-clear the bits
886 */
887 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
888 }
889 }
890
amd_iommu_int_thread_evtlog(int irq,void * data)891 irqreturn_t amd_iommu_int_thread_evtlog(int irq, void *data)
892 {
893 amd_iommu_handle_irq(data, "Evt", MMIO_STATUS_EVT_INT_MASK,
894 MMIO_STATUS_EVT_OVERFLOW_MASK,
895 iommu_poll_events, amd_iommu_restart_event_logging);
896
897 return IRQ_HANDLED;
898 }
899
amd_iommu_int_thread_pprlog(int irq,void * data)900 irqreturn_t amd_iommu_int_thread_pprlog(int irq, void *data)
901 {
902 amd_iommu_handle_irq(data, "PPR", MMIO_STATUS_PPR_INT_MASK,
903 MMIO_STATUS_PPR_OVERFLOW_MASK,
904 iommu_poll_ppr_log, amd_iommu_restart_ppr_log);
905
906 return IRQ_HANDLED;
907 }
908
amd_iommu_int_thread_galog(int irq,void * data)909 irqreturn_t amd_iommu_int_thread_galog(int irq, void *data)
910 {
911 #ifdef CONFIG_IRQ_REMAP
912 amd_iommu_handle_irq(data, "GA", MMIO_STATUS_GALOG_INT_MASK,
913 MMIO_STATUS_GALOG_OVERFLOW_MASK,
914 iommu_poll_ga_log, amd_iommu_restart_ga_log);
915 #endif
916
917 return IRQ_HANDLED;
918 }
919
amd_iommu_int_thread(int irq,void * data)920 irqreturn_t amd_iommu_int_thread(int irq, void *data)
921 {
922 amd_iommu_int_thread_evtlog(irq, data);
923 amd_iommu_int_thread_pprlog(irq, data);
924 amd_iommu_int_thread_galog(irq, data);
925
926 return IRQ_HANDLED;
927 }
928
amd_iommu_int_handler(int irq,void * data)929 irqreturn_t amd_iommu_int_handler(int irq, void *data)
930 {
931 return IRQ_WAKE_THREAD;
932 }
933
934 /****************************************************************************
935 *
936 * IOMMU command queuing functions
937 *
938 ****************************************************************************/
939
wait_on_sem(struct amd_iommu * iommu,u64 data)940 static int wait_on_sem(struct amd_iommu *iommu, u64 data)
941 {
942 int i = 0;
943
944 while (*iommu->cmd_sem != data && i < LOOP_TIMEOUT) {
945 udelay(1);
946 i += 1;
947 }
948
949 if (i == LOOP_TIMEOUT) {
950 pr_alert("Completion-Wait loop timed out\n");
951 return -EIO;
952 }
953
954 return 0;
955 }
956
copy_cmd_to_buffer(struct amd_iommu * iommu,struct iommu_cmd * cmd)957 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
958 struct iommu_cmd *cmd)
959 {
960 u8 *target;
961 u32 tail;
962
963 /* Copy command to buffer */
964 tail = iommu->cmd_buf_tail;
965 target = iommu->cmd_buf + tail;
966 memcpy(target, cmd, sizeof(*cmd));
967
968 tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
969 iommu->cmd_buf_tail = tail;
970
971 /* Tell the IOMMU about it */
972 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
973 }
974
build_completion_wait(struct iommu_cmd * cmd,struct amd_iommu * iommu,u64 data)975 static void build_completion_wait(struct iommu_cmd *cmd,
976 struct amd_iommu *iommu,
977 u64 data)
978 {
979 u64 paddr = iommu_virt_to_phys((void *)iommu->cmd_sem);
980
981 memset(cmd, 0, sizeof(*cmd));
982 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
983 cmd->data[1] = upper_32_bits(paddr);
984 cmd->data[2] = lower_32_bits(data);
985 cmd->data[3] = upper_32_bits(data);
986 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
987 }
988
build_inv_dte(struct iommu_cmd * cmd,u16 devid)989 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
990 {
991 memset(cmd, 0, sizeof(*cmd));
992 cmd->data[0] = devid;
993 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
994 }
995
996 /*
997 * Builds an invalidation address which is suitable for one page or multiple
998 * pages. Sets the size bit (S) as needed is more than one page is flushed.
999 */
build_inv_address(u64 address,size_t size)1000 static inline u64 build_inv_address(u64 address, size_t size)
1001 {
1002 u64 pages, end, msb_diff;
1003
1004 pages = iommu_num_pages(address, size, PAGE_SIZE);
1005
1006 if (pages == 1)
1007 return address & PAGE_MASK;
1008
1009 end = address + size - 1;
1010
1011 /*
1012 * msb_diff would hold the index of the most significant bit that
1013 * flipped between the start and end.
1014 */
1015 msb_diff = fls64(end ^ address) - 1;
1016
1017 /*
1018 * Bits 63:52 are sign extended. If for some reason bit 51 is different
1019 * between the start and the end, invalidate everything.
1020 */
1021 if (unlikely(msb_diff > 51)) {
1022 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
1023 } else {
1024 /*
1025 * The msb-bit must be clear on the address. Just set all the
1026 * lower bits.
1027 */
1028 address |= (1ull << msb_diff) - 1;
1029 }
1030
1031 /* Clear bits 11:0 */
1032 address &= PAGE_MASK;
1033
1034 /* Set the size bit - we flush more than one 4kb page */
1035 return address | CMD_INV_IOMMU_PAGES_SIZE_MASK;
1036 }
1037
build_inv_iommu_pages(struct iommu_cmd * cmd,u64 address,size_t size,u16 domid,int pde)1038 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
1039 size_t size, u16 domid, int pde)
1040 {
1041 u64 inv_address = build_inv_address(address, size);
1042
1043 memset(cmd, 0, sizeof(*cmd));
1044 cmd->data[1] |= domid;
1045 cmd->data[2] = lower_32_bits(inv_address);
1046 cmd->data[3] = upper_32_bits(inv_address);
1047 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
1048 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
1049 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
1050 }
1051
build_inv_iotlb_pages(struct iommu_cmd * cmd,u16 devid,int qdep,u64 address,size_t size)1052 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
1053 u64 address, size_t size)
1054 {
1055 u64 inv_address = build_inv_address(address, size);
1056
1057 memset(cmd, 0, sizeof(*cmd));
1058 cmd->data[0] = devid;
1059 cmd->data[0] |= (qdep & 0xff) << 24;
1060 cmd->data[1] = devid;
1061 cmd->data[2] = lower_32_bits(inv_address);
1062 cmd->data[3] = upper_32_bits(inv_address);
1063 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
1064 }
1065
build_inv_iommu_pasid(struct iommu_cmd * cmd,u16 domid,u32 pasid,u64 address,bool size)1066 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, u32 pasid,
1067 u64 address, bool size)
1068 {
1069 memset(cmd, 0, sizeof(*cmd));
1070
1071 address &= ~(0xfffULL);
1072
1073 cmd->data[0] = pasid;
1074 cmd->data[1] = domid;
1075 cmd->data[2] = lower_32_bits(address);
1076 cmd->data[3] = upper_32_bits(address);
1077 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
1078 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
1079 if (size)
1080 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
1081 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
1082 }
1083
build_inv_iotlb_pasid(struct iommu_cmd * cmd,u16 devid,u32 pasid,int qdep,u64 address,bool size)1084 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, u32 pasid,
1085 int qdep, u64 address, bool size)
1086 {
1087 memset(cmd, 0, sizeof(*cmd));
1088
1089 address &= ~(0xfffULL);
1090
1091 cmd->data[0] = devid;
1092 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
1093 cmd->data[0] |= (qdep & 0xff) << 24;
1094 cmd->data[1] = devid;
1095 cmd->data[1] |= (pasid & 0xff) << 16;
1096 cmd->data[2] = lower_32_bits(address);
1097 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
1098 cmd->data[3] = upper_32_bits(address);
1099 if (size)
1100 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
1101 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
1102 }
1103
build_complete_ppr(struct iommu_cmd * cmd,u16 devid,u32 pasid,int status,int tag,bool gn)1104 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, u32 pasid,
1105 int status, int tag, bool gn)
1106 {
1107 memset(cmd, 0, sizeof(*cmd));
1108
1109 cmd->data[0] = devid;
1110 if (gn) {
1111 cmd->data[1] = pasid;
1112 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
1113 }
1114 cmd->data[3] = tag & 0x1ff;
1115 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
1116
1117 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1118 }
1119
build_inv_all(struct iommu_cmd * cmd)1120 static void build_inv_all(struct iommu_cmd *cmd)
1121 {
1122 memset(cmd, 0, sizeof(*cmd));
1123 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1124 }
1125
build_inv_irt(struct iommu_cmd * cmd,u16 devid)1126 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1127 {
1128 memset(cmd, 0, sizeof(*cmd));
1129 cmd->data[0] = devid;
1130 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1131 }
1132
1133 /*
1134 * Writes the command to the IOMMUs command buffer and informs the
1135 * hardware about the new command.
1136 */
__iommu_queue_command_sync(struct amd_iommu * iommu,struct iommu_cmd * cmd,bool sync)1137 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1138 struct iommu_cmd *cmd,
1139 bool sync)
1140 {
1141 unsigned int count = 0;
1142 u32 left, next_tail;
1143
1144 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1145 again:
1146 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1147
1148 if (left <= 0x20) {
1149 /* Skip udelay() the first time around */
1150 if (count++) {
1151 if (count == LOOP_TIMEOUT) {
1152 pr_err("Command buffer timeout\n");
1153 return -EIO;
1154 }
1155
1156 udelay(1);
1157 }
1158
1159 /* Update head and recheck remaining space */
1160 iommu->cmd_buf_head = readl(iommu->mmio_base +
1161 MMIO_CMD_HEAD_OFFSET);
1162
1163 goto again;
1164 }
1165
1166 copy_cmd_to_buffer(iommu, cmd);
1167
1168 /* Do we need to make sure all commands are processed? */
1169 iommu->need_sync = sync;
1170
1171 return 0;
1172 }
1173
iommu_queue_command_sync(struct amd_iommu * iommu,struct iommu_cmd * cmd,bool sync)1174 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1175 struct iommu_cmd *cmd,
1176 bool sync)
1177 {
1178 unsigned long flags;
1179 int ret;
1180
1181 raw_spin_lock_irqsave(&iommu->lock, flags);
1182 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1183 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1184
1185 return ret;
1186 }
1187
iommu_queue_command(struct amd_iommu * iommu,struct iommu_cmd * cmd)1188 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1189 {
1190 return iommu_queue_command_sync(iommu, cmd, true);
1191 }
1192
1193 /*
1194 * This function queues a completion wait command into the command
1195 * buffer of an IOMMU
1196 */
iommu_completion_wait(struct amd_iommu * iommu)1197 static int iommu_completion_wait(struct amd_iommu *iommu)
1198 {
1199 struct iommu_cmd cmd;
1200 unsigned long flags;
1201 int ret;
1202 u64 data;
1203
1204 if (!iommu->need_sync)
1205 return 0;
1206
1207 data = atomic64_add_return(1, &iommu->cmd_sem_val);
1208 build_completion_wait(&cmd, iommu, data);
1209
1210 raw_spin_lock_irqsave(&iommu->lock, flags);
1211
1212 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1213 if (ret)
1214 goto out_unlock;
1215
1216 ret = wait_on_sem(iommu, data);
1217
1218 out_unlock:
1219 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1220
1221 return ret;
1222 }
1223
iommu_flush_dte(struct amd_iommu * iommu,u16 devid)1224 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1225 {
1226 struct iommu_cmd cmd;
1227
1228 build_inv_dte(&cmd, devid);
1229
1230 return iommu_queue_command(iommu, &cmd);
1231 }
1232
amd_iommu_flush_dte_all(struct amd_iommu * iommu)1233 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1234 {
1235 u32 devid;
1236 u16 last_bdf = iommu->pci_seg->last_bdf;
1237
1238 for (devid = 0; devid <= last_bdf; ++devid)
1239 iommu_flush_dte(iommu, devid);
1240
1241 iommu_completion_wait(iommu);
1242 }
1243
1244 /*
1245 * This function uses heavy locking and may disable irqs for some time. But
1246 * this is no issue because it is only called during resume.
1247 */
amd_iommu_flush_tlb_all(struct amd_iommu * iommu)1248 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1249 {
1250 u32 dom_id;
1251 u16 last_bdf = iommu->pci_seg->last_bdf;
1252
1253 for (dom_id = 0; dom_id <= last_bdf; ++dom_id) {
1254 struct iommu_cmd cmd;
1255 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1256 dom_id, 1);
1257 iommu_queue_command(iommu, &cmd);
1258 }
1259
1260 iommu_completion_wait(iommu);
1261 }
1262
amd_iommu_flush_tlb_domid(struct amd_iommu * iommu,u32 dom_id)1263 static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id)
1264 {
1265 struct iommu_cmd cmd;
1266
1267 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1268 dom_id, 1);
1269 iommu_queue_command(iommu, &cmd);
1270
1271 iommu_completion_wait(iommu);
1272 }
1273
amd_iommu_flush_all(struct amd_iommu * iommu)1274 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1275 {
1276 struct iommu_cmd cmd;
1277
1278 build_inv_all(&cmd);
1279
1280 iommu_queue_command(iommu, &cmd);
1281 iommu_completion_wait(iommu);
1282 }
1283
iommu_flush_irt(struct amd_iommu * iommu,u16 devid)1284 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1285 {
1286 struct iommu_cmd cmd;
1287
1288 build_inv_irt(&cmd, devid);
1289
1290 iommu_queue_command(iommu, &cmd);
1291 }
1292
amd_iommu_flush_irt_all(struct amd_iommu * iommu)1293 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1294 {
1295 u32 devid;
1296 u16 last_bdf = iommu->pci_seg->last_bdf;
1297
1298 if (iommu->irtcachedis_enabled)
1299 return;
1300
1301 for (devid = 0; devid <= last_bdf; devid++)
1302 iommu_flush_irt(iommu, devid);
1303
1304 iommu_completion_wait(iommu);
1305 }
1306
iommu_flush_all_caches(struct amd_iommu * iommu)1307 void iommu_flush_all_caches(struct amd_iommu *iommu)
1308 {
1309 if (iommu_feature(iommu, FEATURE_IA)) {
1310 amd_iommu_flush_all(iommu);
1311 } else {
1312 amd_iommu_flush_dte_all(iommu);
1313 amd_iommu_flush_irt_all(iommu);
1314 amd_iommu_flush_tlb_all(iommu);
1315 }
1316 }
1317
1318 /*
1319 * Command send function for flushing on-device TLB
1320 */
device_flush_iotlb(struct iommu_dev_data * dev_data,u64 address,size_t size)1321 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1322 u64 address, size_t size)
1323 {
1324 struct amd_iommu *iommu;
1325 struct iommu_cmd cmd;
1326 int qdep;
1327
1328 qdep = dev_data->ats.qdep;
1329 iommu = rlookup_amd_iommu(dev_data->dev);
1330 if (!iommu)
1331 return -EINVAL;
1332
1333 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1334
1335 return iommu_queue_command(iommu, &cmd);
1336 }
1337
device_flush_dte_alias(struct pci_dev * pdev,u16 alias,void * data)1338 static int device_flush_dte_alias(struct pci_dev *pdev, u16 alias, void *data)
1339 {
1340 struct amd_iommu *iommu = data;
1341
1342 return iommu_flush_dte(iommu, alias);
1343 }
1344
1345 /*
1346 * Command send function for invalidating a device table entry
1347 */
device_flush_dte(struct iommu_dev_data * dev_data)1348 static int device_flush_dte(struct iommu_dev_data *dev_data)
1349 {
1350 struct amd_iommu *iommu;
1351 struct pci_dev *pdev = NULL;
1352 struct amd_iommu_pci_seg *pci_seg;
1353 u16 alias;
1354 int ret;
1355
1356 iommu = rlookup_amd_iommu(dev_data->dev);
1357 if (!iommu)
1358 return -EINVAL;
1359
1360 if (dev_is_pci(dev_data->dev))
1361 pdev = to_pci_dev(dev_data->dev);
1362
1363 if (pdev)
1364 ret = pci_for_each_dma_alias(pdev,
1365 device_flush_dte_alias, iommu);
1366 else
1367 ret = iommu_flush_dte(iommu, dev_data->devid);
1368 if (ret)
1369 return ret;
1370
1371 pci_seg = iommu->pci_seg;
1372 alias = pci_seg->alias_table[dev_data->devid];
1373 if (alias != dev_data->devid) {
1374 ret = iommu_flush_dte(iommu, alias);
1375 if (ret)
1376 return ret;
1377 }
1378
1379 if (dev_data->ats.enabled)
1380 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1381
1382 return ret;
1383 }
1384
1385 /*
1386 * TLB invalidation function which is called from the mapping functions.
1387 * It invalidates a single PTE if the range to flush is within a single
1388 * page. Otherwise it flushes the whole TLB of the IOMMU.
1389 */
__domain_flush_pages(struct protection_domain * domain,u64 address,size_t size,int pde)1390 static void __domain_flush_pages(struct protection_domain *domain,
1391 u64 address, size_t size, int pde)
1392 {
1393 struct iommu_dev_data *dev_data;
1394 struct iommu_cmd cmd;
1395 int ret = 0, i;
1396
1397 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1398
1399 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1400 if (!domain->dev_iommu[i])
1401 continue;
1402
1403 /*
1404 * Devices of this domain are behind this IOMMU
1405 * We need a TLB flush
1406 */
1407 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1408 }
1409
1410 list_for_each_entry(dev_data, &domain->dev_list, list) {
1411
1412 if (!dev_data->ats.enabled)
1413 continue;
1414
1415 ret |= device_flush_iotlb(dev_data, address, size);
1416 }
1417
1418 WARN_ON(ret);
1419 }
1420
domain_flush_pages(struct protection_domain * domain,u64 address,size_t size,int pde)1421 static void domain_flush_pages(struct protection_domain *domain,
1422 u64 address, size_t size, int pde)
1423 {
1424 if (likely(!amd_iommu_np_cache)) {
1425 __domain_flush_pages(domain, address, size, pde);
1426 return;
1427 }
1428
1429 /*
1430 * When NpCache is on, we infer that we run in a VM and use a vIOMMU.
1431 * In such setups it is best to avoid flushes of ranges which are not
1432 * naturally aligned, since it would lead to flushes of unmodified
1433 * PTEs. Such flushes would require the hypervisor to do more work than
1434 * necessary. Therefore, perform repeated flushes of aligned ranges
1435 * until you cover the range. Each iteration flushes the smaller
1436 * between the natural alignment of the address that we flush and the
1437 * greatest naturally aligned region that fits in the range.
1438 */
1439 while (size != 0) {
1440 int addr_alignment = __ffs(address);
1441 int size_alignment = __fls(size);
1442 int min_alignment;
1443 size_t flush_size;
1444
1445 /*
1446 * size is always non-zero, but address might be zero, causing
1447 * addr_alignment to be negative. As the casting of the
1448 * argument in __ffs(address) to long might trim the high bits
1449 * of the address on x86-32, cast to long when doing the check.
1450 */
1451 if (likely((unsigned long)address != 0))
1452 min_alignment = min(addr_alignment, size_alignment);
1453 else
1454 min_alignment = size_alignment;
1455
1456 flush_size = 1ul << min_alignment;
1457
1458 __domain_flush_pages(domain, address, flush_size, pde);
1459 address += flush_size;
1460 size -= flush_size;
1461 }
1462 }
1463
1464 /* Flush the whole IO/TLB for a given protection domain - including PDE */
amd_iommu_domain_flush_tlb_pde(struct protection_domain * domain)1465 void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain)
1466 {
1467 domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1468 }
1469
amd_iommu_domain_flush_complete(struct protection_domain * domain)1470 void amd_iommu_domain_flush_complete(struct protection_domain *domain)
1471 {
1472 int i;
1473
1474 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1475 if (domain && !domain->dev_iommu[i])
1476 continue;
1477
1478 /*
1479 * Devices of this domain are behind this IOMMU
1480 * We need to wait for completion of all commands.
1481 */
1482 iommu_completion_wait(amd_iommus[i]);
1483 }
1484 }
1485
1486 /* Flush the not present cache if it exists */
domain_flush_np_cache(struct protection_domain * domain,dma_addr_t iova,size_t size)1487 static void domain_flush_np_cache(struct protection_domain *domain,
1488 dma_addr_t iova, size_t size)
1489 {
1490 if (unlikely(amd_iommu_np_cache)) {
1491 unsigned long flags;
1492
1493 spin_lock_irqsave(&domain->lock, flags);
1494 domain_flush_pages(domain, iova, size, 1);
1495 amd_iommu_domain_flush_complete(domain);
1496 spin_unlock_irqrestore(&domain->lock, flags);
1497 }
1498 }
1499
1500
1501 /*
1502 * This function flushes the DTEs for all devices in domain
1503 */
domain_flush_devices(struct protection_domain * domain)1504 static void domain_flush_devices(struct protection_domain *domain)
1505 {
1506 struct iommu_dev_data *dev_data;
1507
1508 list_for_each_entry(dev_data, &domain->dev_list, list)
1509 device_flush_dte(dev_data);
1510 }
1511
1512 /****************************************************************************
1513 *
1514 * The next functions belong to the domain allocation. A domain is
1515 * allocated for every IOMMU as the default domain. If device isolation
1516 * is enabled, every device get its own domain. The most important thing
1517 * about domains is the page table mapping the DMA address space they
1518 * contain.
1519 *
1520 ****************************************************************************/
1521
domain_id_alloc(void)1522 static u16 domain_id_alloc(void)
1523 {
1524 int id;
1525
1526 spin_lock(&pd_bitmap_lock);
1527 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1528 BUG_ON(id == 0);
1529 if (id > 0 && id < MAX_DOMAIN_ID)
1530 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1531 else
1532 id = 0;
1533 spin_unlock(&pd_bitmap_lock);
1534
1535 return id;
1536 }
1537
domain_id_free(int id)1538 static void domain_id_free(int id)
1539 {
1540 spin_lock(&pd_bitmap_lock);
1541 if (id > 0 && id < MAX_DOMAIN_ID)
1542 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1543 spin_unlock(&pd_bitmap_lock);
1544 }
1545
free_gcr3_tbl_level1(u64 * tbl)1546 static void free_gcr3_tbl_level1(u64 *tbl)
1547 {
1548 u64 *ptr;
1549 int i;
1550
1551 for (i = 0; i < 512; ++i) {
1552 if (!(tbl[i] & GCR3_VALID))
1553 continue;
1554
1555 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1556
1557 free_page((unsigned long)ptr);
1558 }
1559 }
1560
free_gcr3_tbl_level2(u64 * tbl)1561 static void free_gcr3_tbl_level2(u64 *tbl)
1562 {
1563 u64 *ptr;
1564 int i;
1565
1566 for (i = 0; i < 512; ++i) {
1567 if (!(tbl[i] & GCR3_VALID))
1568 continue;
1569
1570 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1571
1572 free_gcr3_tbl_level1(ptr);
1573 }
1574 }
1575
free_gcr3_table(struct protection_domain * domain)1576 static void free_gcr3_table(struct protection_domain *domain)
1577 {
1578 if (domain->glx == 2)
1579 free_gcr3_tbl_level2(domain->gcr3_tbl);
1580 else if (domain->glx == 1)
1581 free_gcr3_tbl_level1(domain->gcr3_tbl);
1582 else
1583 BUG_ON(domain->glx != 0);
1584
1585 free_page((unsigned long)domain->gcr3_tbl);
1586 }
1587
set_dte_entry(struct amd_iommu * iommu,u16 devid,struct protection_domain * domain,bool ats,bool ppr)1588 static void set_dte_entry(struct amd_iommu *iommu, u16 devid,
1589 struct protection_domain *domain, bool ats, bool ppr)
1590 {
1591 u64 pte_root = 0;
1592 u64 flags = 0;
1593 u32 old_domid;
1594 struct dev_table_entry *dev_table = get_dev_table(iommu);
1595
1596 if (domain->iop.mode != PAGE_MODE_NONE)
1597 pte_root = iommu_virt_to_phys(domain->iop.root);
1598
1599 pte_root |= (domain->iop.mode & DEV_ENTRY_MODE_MASK)
1600 << DEV_ENTRY_MODE_SHIFT;
1601
1602 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V;
1603
1604 /*
1605 * When SNP is enabled, Only set TV bit when IOMMU
1606 * page translation is in use.
1607 */
1608 if (!amd_iommu_snp_en || (domain->id != 0))
1609 pte_root |= DTE_FLAG_TV;
1610
1611 flags = dev_table[devid].data[1];
1612
1613 if (ats)
1614 flags |= DTE_FLAG_IOTLB;
1615
1616 if (ppr) {
1617 if (iommu_feature(iommu, FEATURE_EPHSUP))
1618 pte_root |= 1ULL << DEV_ENTRY_PPR;
1619 }
1620
1621 if (domain->flags & PD_IOMMUV2_MASK) {
1622 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1623 u64 glx = domain->glx;
1624 u64 tmp;
1625
1626 pte_root |= DTE_FLAG_GV;
1627 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1628
1629 /* First mask out possible old values for GCR3 table */
1630 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1631 flags &= ~tmp;
1632
1633 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1634 flags &= ~tmp;
1635
1636 /* Encode GCR3 table into DTE */
1637 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1638 pte_root |= tmp;
1639
1640 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1641 flags |= tmp;
1642
1643 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1644 flags |= tmp;
1645
1646 if (amd_iommu_gpt_level == PAGE_MODE_5_LEVEL) {
1647 dev_table[devid].data[2] |=
1648 ((u64)GUEST_PGTABLE_5_LEVEL << DTE_GPT_LEVEL_SHIFT);
1649 }
1650
1651 if (domain->flags & PD_GIOV_MASK)
1652 pte_root |= DTE_FLAG_GIOV;
1653 }
1654
1655 flags &= ~DEV_DOMID_MASK;
1656 flags |= domain->id;
1657
1658 old_domid = dev_table[devid].data[1] & DEV_DOMID_MASK;
1659 dev_table[devid].data[1] = flags;
1660 dev_table[devid].data[0] = pte_root;
1661
1662 /*
1663 * A kdump kernel might be replacing a domain ID that was copied from
1664 * the previous kernel--if so, it needs to flush the translation cache
1665 * entries for the old domain ID that is being overwritten
1666 */
1667 if (old_domid) {
1668 amd_iommu_flush_tlb_domid(iommu, old_domid);
1669 }
1670 }
1671
clear_dte_entry(struct amd_iommu * iommu,u16 devid)1672 static void clear_dte_entry(struct amd_iommu *iommu, u16 devid)
1673 {
1674 struct dev_table_entry *dev_table = get_dev_table(iommu);
1675
1676 /* remove entry from the device table seen by the hardware */
1677 dev_table[devid].data[0] = DTE_FLAG_V;
1678
1679 if (!amd_iommu_snp_en)
1680 dev_table[devid].data[0] |= DTE_FLAG_TV;
1681
1682 dev_table[devid].data[1] &= DTE_FLAG_MASK;
1683
1684 amd_iommu_apply_erratum_63(iommu, devid);
1685 }
1686
do_attach(struct iommu_dev_data * dev_data,struct protection_domain * domain)1687 static void do_attach(struct iommu_dev_data *dev_data,
1688 struct protection_domain *domain)
1689 {
1690 struct amd_iommu *iommu;
1691 bool ats;
1692
1693 iommu = rlookup_amd_iommu(dev_data->dev);
1694 if (!iommu)
1695 return;
1696 ats = dev_data->ats.enabled;
1697
1698 /* Update data structures */
1699 dev_data->domain = domain;
1700 list_add(&dev_data->list, &domain->dev_list);
1701
1702 /* Update NUMA Node ID */
1703 if (domain->nid == NUMA_NO_NODE)
1704 domain->nid = dev_to_node(dev_data->dev);
1705
1706 /* Do reference counting */
1707 domain->dev_iommu[iommu->index] += 1;
1708 domain->dev_cnt += 1;
1709
1710 /* Update device table */
1711 set_dte_entry(iommu, dev_data->devid, domain,
1712 ats, dev_data->iommu_v2);
1713 clone_aliases(iommu, dev_data->dev);
1714
1715 device_flush_dte(dev_data);
1716 }
1717
do_detach(struct iommu_dev_data * dev_data)1718 static void do_detach(struct iommu_dev_data *dev_data)
1719 {
1720 struct protection_domain *domain = dev_data->domain;
1721 struct amd_iommu *iommu;
1722
1723 iommu = rlookup_amd_iommu(dev_data->dev);
1724 if (!iommu)
1725 return;
1726
1727 /* Update data structures */
1728 dev_data->domain = NULL;
1729 list_del(&dev_data->list);
1730 clear_dte_entry(iommu, dev_data->devid);
1731 clone_aliases(iommu, dev_data->dev);
1732
1733 /* Flush the DTE entry */
1734 device_flush_dte(dev_data);
1735
1736 /* Flush IOTLB */
1737 amd_iommu_domain_flush_tlb_pde(domain);
1738
1739 /* Wait for the flushes to finish */
1740 amd_iommu_domain_flush_complete(domain);
1741
1742 /* decrease reference counters - needs to happen after the flushes */
1743 domain->dev_iommu[iommu->index] -= 1;
1744 domain->dev_cnt -= 1;
1745 }
1746
pdev_iommuv2_disable(struct pci_dev * pdev)1747 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1748 {
1749 pci_disable_ats(pdev);
1750 pci_disable_pri(pdev);
1751 pci_disable_pasid(pdev);
1752 }
1753
pdev_pri_ats_enable(struct pci_dev * pdev)1754 static int pdev_pri_ats_enable(struct pci_dev *pdev)
1755 {
1756 int ret;
1757
1758 /* Only allow access to user-accessible pages */
1759 ret = pci_enable_pasid(pdev, 0);
1760 if (ret)
1761 return ret;
1762
1763 /* First reset the PRI state of the device */
1764 ret = pci_reset_pri(pdev);
1765 if (ret)
1766 goto out_err_pasid;
1767
1768 /* Enable PRI */
1769 /* FIXME: Hardcode number of outstanding requests for now */
1770 ret = pci_enable_pri(pdev, 32);
1771 if (ret)
1772 goto out_err_pasid;
1773
1774 ret = pci_enable_ats(pdev, PAGE_SHIFT);
1775 if (ret)
1776 goto out_err_pri;
1777
1778 return 0;
1779
1780 out_err_pri:
1781 pci_disable_pri(pdev);
1782
1783 out_err_pasid:
1784 pci_disable_pasid(pdev);
1785
1786 return ret;
1787 }
1788
1789 /*
1790 * If a device is not yet associated with a domain, this function makes the
1791 * device visible in the domain
1792 */
attach_device(struct device * dev,struct protection_domain * domain)1793 static int attach_device(struct device *dev,
1794 struct protection_domain *domain)
1795 {
1796 struct iommu_dev_data *dev_data;
1797 struct pci_dev *pdev;
1798 unsigned long flags;
1799 int ret;
1800
1801 spin_lock_irqsave(&domain->lock, flags);
1802
1803 dev_data = dev_iommu_priv_get(dev);
1804
1805 spin_lock(&dev_data->lock);
1806
1807 ret = -EBUSY;
1808 if (dev_data->domain != NULL)
1809 goto out;
1810
1811 if (!dev_is_pci(dev))
1812 goto skip_ats_check;
1813
1814 pdev = to_pci_dev(dev);
1815 if (domain->flags & PD_IOMMUV2_MASK) {
1816 struct iommu_domain *def_domain = iommu_get_dma_domain(dev);
1817
1818 ret = -EINVAL;
1819
1820 /*
1821 * In case of using AMD_IOMMU_V1 page table mode and the device
1822 * is enabling for PPR/ATS support (using v2 table),
1823 * we need to make sure that the domain type is identity map.
1824 */
1825 if ((amd_iommu_pgtable == AMD_IOMMU_V1) &&
1826 def_domain->type != IOMMU_DOMAIN_IDENTITY) {
1827 goto out;
1828 }
1829
1830 if (dev_data->iommu_v2) {
1831 if (pdev_pri_ats_enable(pdev) != 0)
1832 goto out;
1833
1834 dev_data->ats.enabled = true;
1835 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
1836 dev_data->pri_tlp = pci_prg_resp_pasid_required(pdev);
1837 }
1838 } else if (amd_iommu_iotlb_sup &&
1839 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
1840 dev_data->ats.enabled = true;
1841 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
1842 }
1843
1844 skip_ats_check:
1845 ret = 0;
1846
1847 do_attach(dev_data, domain);
1848
1849 /*
1850 * We might boot into a crash-kernel here. The crashed kernel
1851 * left the caches in the IOMMU dirty. So we have to flush
1852 * here to evict all dirty stuff.
1853 */
1854 amd_iommu_domain_flush_tlb_pde(domain);
1855
1856 amd_iommu_domain_flush_complete(domain);
1857
1858 out:
1859 spin_unlock(&dev_data->lock);
1860
1861 spin_unlock_irqrestore(&domain->lock, flags);
1862
1863 return ret;
1864 }
1865
1866 /*
1867 * Removes a device from a protection domain (with devtable_lock held)
1868 */
detach_device(struct device * dev)1869 static void detach_device(struct device *dev)
1870 {
1871 struct protection_domain *domain;
1872 struct iommu_dev_data *dev_data;
1873 unsigned long flags;
1874
1875 dev_data = dev_iommu_priv_get(dev);
1876 domain = dev_data->domain;
1877
1878 spin_lock_irqsave(&domain->lock, flags);
1879
1880 spin_lock(&dev_data->lock);
1881
1882 /*
1883 * First check if the device is still attached. It might already
1884 * be detached from its domain because the generic
1885 * iommu_detach_group code detached it and we try again here in
1886 * our alias handling.
1887 */
1888 if (WARN_ON(!dev_data->domain))
1889 goto out;
1890
1891 do_detach(dev_data);
1892
1893 if (!dev_is_pci(dev))
1894 goto out;
1895
1896 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
1897 pdev_iommuv2_disable(to_pci_dev(dev));
1898 else if (dev_data->ats.enabled)
1899 pci_disable_ats(to_pci_dev(dev));
1900
1901 dev_data->ats.enabled = false;
1902
1903 out:
1904 spin_unlock(&dev_data->lock);
1905
1906 spin_unlock_irqrestore(&domain->lock, flags);
1907 }
1908
amd_iommu_probe_device(struct device * dev)1909 static struct iommu_device *amd_iommu_probe_device(struct device *dev)
1910 {
1911 struct iommu_device *iommu_dev;
1912 struct amd_iommu *iommu;
1913 int ret;
1914
1915 if (!check_device(dev))
1916 return ERR_PTR(-ENODEV);
1917
1918 iommu = rlookup_amd_iommu(dev);
1919 if (!iommu)
1920 return ERR_PTR(-ENODEV);
1921
1922 /* Not registered yet? */
1923 if (!iommu->iommu.ops)
1924 return ERR_PTR(-ENODEV);
1925
1926 if (dev_iommu_priv_get(dev))
1927 return &iommu->iommu;
1928
1929 ret = iommu_init_device(iommu, dev);
1930 if (ret) {
1931 if (ret != -ENOTSUPP)
1932 dev_err(dev, "Failed to initialize - trying to proceed anyway\n");
1933 iommu_dev = ERR_PTR(ret);
1934 iommu_ignore_device(iommu, dev);
1935 } else {
1936 amd_iommu_set_pci_msi_domain(dev, iommu);
1937 iommu_dev = &iommu->iommu;
1938 }
1939
1940 iommu_completion_wait(iommu);
1941
1942 return iommu_dev;
1943 }
1944
amd_iommu_probe_finalize(struct device * dev)1945 static void amd_iommu_probe_finalize(struct device *dev)
1946 {
1947 /* Domains are initialized for this device - have a look what we ended up with */
1948 set_dma_ops(dev, NULL);
1949 iommu_setup_dma_ops(dev, 0, U64_MAX);
1950 }
1951
amd_iommu_release_device(struct device * dev)1952 static void amd_iommu_release_device(struct device *dev)
1953 {
1954 struct amd_iommu *iommu;
1955
1956 if (!check_device(dev))
1957 return;
1958
1959 iommu = rlookup_amd_iommu(dev);
1960 if (!iommu)
1961 return;
1962
1963 amd_iommu_uninit_device(dev);
1964 iommu_completion_wait(iommu);
1965 }
1966
amd_iommu_device_group(struct device * dev)1967 static struct iommu_group *amd_iommu_device_group(struct device *dev)
1968 {
1969 if (dev_is_pci(dev))
1970 return pci_device_group(dev);
1971
1972 return acpihid_device_group(dev);
1973 }
1974
1975 /*****************************************************************************
1976 *
1977 * The next functions belong to the dma_ops mapping/unmapping code.
1978 *
1979 *****************************************************************************/
1980
update_device_table(struct protection_domain * domain)1981 static void update_device_table(struct protection_domain *domain)
1982 {
1983 struct iommu_dev_data *dev_data;
1984
1985 list_for_each_entry(dev_data, &domain->dev_list, list) {
1986 struct amd_iommu *iommu = rlookup_amd_iommu(dev_data->dev);
1987
1988 if (!iommu)
1989 continue;
1990 set_dte_entry(iommu, dev_data->devid, domain,
1991 dev_data->ats.enabled, dev_data->iommu_v2);
1992 clone_aliases(iommu, dev_data->dev);
1993 }
1994 }
1995
amd_iommu_update_and_flush_device_table(struct protection_domain * domain)1996 void amd_iommu_update_and_flush_device_table(struct protection_domain *domain)
1997 {
1998 update_device_table(domain);
1999 domain_flush_devices(domain);
2000 }
2001
amd_iommu_domain_update(struct protection_domain * domain)2002 void amd_iommu_domain_update(struct protection_domain *domain)
2003 {
2004 /* Update device table */
2005 amd_iommu_update_and_flush_device_table(domain);
2006
2007 /* Flush domain TLB(s) and wait for completion */
2008 amd_iommu_domain_flush_tlb_pde(domain);
2009 amd_iommu_domain_flush_complete(domain);
2010 }
2011
2012 /*****************************************************************************
2013 *
2014 * The following functions belong to the exported interface of AMD IOMMU
2015 *
2016 * This interface allows access to lower level functions of the IOMMU
2017 * like protection domain handling and assignement of devices to domains
2018 * which is not possible with the dma_ops interface.
2019 *
2020 *****************************************************************************/
2021
cleanup_domain(struct protection_domain * domain)2022 static void cleanup_domain(struct protection_domain *domain)
2023 {
2024 struct iommu_dev_data *entry;
2025 unsigned long flags;
2026
2027 spin_lock_irqsave(&domain->lock, flags);
2028
2029 while (!list_empty(&domain->dev_list)) {
2030 entry = list_first_entry(&domain->dev_list,
2031 struct iommu_dev_data, list);
2032 BUG_ON(!entry->domain);
2033 do_detach(entry);
2034 }
2035
2036 spin_unlock_irqrestore(&domain->lock, flags);
2037 }
2038
protection_domain_free(struct protection_domain * domain)2039 static void protection_domain_free(struct protection_domain *domain)
2040 {
2041 if (!domain)
2042 return;
2043
2044 if (domain->iop.pgtbl_cfg.tlb)
2045 free_io_pgtable_ops(&domain->iop.iop.ops);
2046
2047 if (domain->id)
2048 domain_id_free(domain->id);
2049
2050 kfree(domain);
2051 }
2052
protection_domain_init_v1(struct protection_domain * domain,int mode)2053 static int protection_domain_init_v1(struct protection_domain *domain, int mode)
2054 {
2055 u64 *pt_root = NULL;
2056
2057 BUG_ON(mode < PAGE_MODE_NONE || mode > PAGE_MODE_6_LEVEL);
2058
2059 spin_lock_init(&domain->lock);
2060 domain->id = domain_id_alloc();
2061 if (!domain->id)
2062 return -ENOMEM;
2063 INIT_LIST_HEAD(&domain->dev_list);
2064
2065 if (mode != PAGE_MODE_NONE) {
2066 pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2067 if (!pt_root) {
2068 domain_id_free(domain->id);
2069 return -ENOMEM;
2070 }
2071 }
2072
2073 amd_iommu_domain_set_pgtable(domain, pt_root, mode);
2074
2075 return 0;
2076 }
2077
protection_domain_init_v2(struct protection_domain * domain)2078 static int protection_domain_init_v2(struct protection_domain *domain)
2079 {
2080 spin_lock_init(&domain->lock);
2081 domain->id = domain_id_alloc();
2082 if (!domain->id)
2083 return -ENOMEM;
2084 INIT_LIST_HEAD(&domain->dev_list);
2085
2086 domain->flags |= PD_GIOV_MASK;
2087
2088 domain->domain.pgsize_bitmap = AMD_IOMMU_PGSIZES_V2;
2089
2090 if (domain_enable_v2(domain, 1)) {
2091 domain_id_free(domain->id);
2092 return -ENOMEM;
2093 }
2094
2095 return 0;
2096 }
2097
protection_domain_alloc(unsigned int type)2098 static struct protection_domain *protection_domain_alloc(unsigned int type)
2099 {
2100 struct io_pgtable_ops *pgtbl_ops;
2101 struct protection_domain *domain;
2102 int pgtable;
2103 int mode = DEFAULT_PGTABLE_LEVEL;
2104 int ret;
2105
2106 /*
2107 * Force IOMMU v1 page table when iommu=pt and
2108 * when allocating domain for pass-through devices.
2109 */
2110 if (type == IOMMU_DOMAIN_IDENTITY) {
2111 pgtable = AMD_IOMMU_V1;
2112 mode = PAGE_MODE_NONE;
2113 } else if (type == IOMMU_DOMAIN_UNMANAGED) {
2114 pgtable = AMD_IOMMU_V1;
2115 } else if (type == IOMMU_DOMAIN_DMA || type == IOMMU_DOMAIN_DMA_FQ) {
2116 pgtable = amd_iommu_pgtable;
2117 } else {
2118 return NULL;
2119 }
2120
2121 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2122 if (!domain)
2123 return NULL;
2124
2125 switch (pgtable) {
2126 case AMD_IOMMU_V1:
2127 ret = protection_domain_init_v1(domain, mode);
2128 break;
2129 case AMD_IOMMU_V2:
2130 ret = protection_domain_init_v2(domain);
2131 break;
2132 default:
2133 ret = -EINVAL;
2134 }
2135
2136 if (ret)
2137 goto out_err;
2138
2139 /* No need to allocate io pgtable ops in passthrough mode */
2140 if (type == IOMMU_DOMAIN_IDENTITY)
2141 return domain;
2142
2143 domain->nid = NUMA_NO_NODE;
2144
2145 pgtbl_ops = alloc_io_pgtable_ops(pgtable, &domain->iop.pgtbl_cfg, domain);
2146 if (!pgtbl_ops) {
2147 domain_id_free(domain->id);
2148 goto out_err;
2149 }
2150
2151 return domain;
2152 out_err:
2153 kfree(domain);
2154 return NULL;
2155 }
2156
dma_max_address(void)2157 static inline u64 dma_max_address(void)
2158 {
2159 if (amd_iommu_pgtable == AMD_IOMMU_V1)
2160 return ~0ULL;
2161
2162 /* V2 with 4/5 level page table */
2163 return ((1ULL << PM_LEVEL_SHIFT(amd_iommu_gpt_level)) - 1);
2164 }
2165
amd_iommu_domain_alloc(unsigned type)2166 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2167 {
2168 struct protection_domain *domain;
2169
2170 /*
2171 * Since DTE[Mode]=0 is prohibited on SNP-enabled system,
2172 * default to use IOMMU_DOMAIN_DMA[_FQ].
2173 */
2174 if (amd_iommu_snp_en && (type == IOMMU_DOMAIN_IDENTITY))
2175 return NULL;
2176
2177 domain = protection_domain_alloc(type);
2178 if (!domain)
2179 return NULL;
2180
2181 domain->domain.geometry.aperture_start = 0;
2182 domain->domain.geometry.aperture_end = dma_max_address();
2183 domain->domain.geometry.force_aperture = true;
2184
2185 return &domain->domain;
2186 }
2187
amd_iommu_domain_free(struct iommu_domain * dom)2188 static void amd_iommu_domain_free(struct iommu_domain *dom)
2189 {
2190 struct protection_domain *domain;
2191
2192 domain = to_pdomain(dom);
2193
2194 if (domain->dev_cnt > 0)
2195 cleanup_domain(domain);
2196
2197 BUG_ON(domain->dev_cnt != 0);
2198
2199 if (!dom)
2200 return;
2201
2202 if (domain->flags & PD_IOMMUV2_MASK)
2203 free_gcr3_table(domain);
2204
2205 protection_domain_free(domain);
2206 }
2207
amd_iommu_attach_device(struct iommu_domain * dom,struct device * dev)2208 static int amd_iommu_attach_device(struct iommu_domain *dom,
2209 struct device *dev)
2210 {
2211 struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev);
2212 struct protection_domain *domain = to_pdomain(dom);
2213 struct amd_iommu *iommu = rlookup_amd_iommu(dev);
2214 int ret;
2215
2216 /*
2217 * Skip attach device to domain if new domain is same as
2218 * devices current domain
2219 */
2220 if (dev_data->domain == domain)
2221 return 0;
2222
2223 dev_data->defer_attach = false;
2224
2225 if (dev_data->domain)
2226 detach_device(dev);
2227
2228 ret = attach_device(dev, domain);
2229
2230 #ifdef CONFIG_IRQ_REMAP
2231 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
2232 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
2233 dev_data->use_vapic = 1;
2234 else
2235 dev_data->use_vapic = 0;
2236 }
2237 #endif
2238
2239 iommu_completion_wait(iommu);
2240
2241 return ret;
2242 }
2243
amd_iommu_iotlb_sync_map(struct iommu_domain * dom,unsigned long iova,size_t size)2244 static void amd_iommu_iotlb_sync_map(struct iommu_domain *dom,
2245 unsigned long iova, size_t size)
2246 {
2247 struct protection_domain *domain = to_pdomain(dom);
2248 struct io_pgtable_ops *ops = &domain->iop.iop.ops;
2249
2250 if (ops->map_pages)
2251 domain_flush_np_cache(domain, iova, size);
2252 }
2253
amd_iommu_map_pages(struct iommu_domain * dom,unsigned long iova,phys_addr_t paddr,size_t pgsize,size_t pgcount,int iommu_prot,gfp_t gfp,size_t * mapped)2254 static int amd_iommu_map_pages(struct iommu_domain *dom, unsigned long iova,
2255 phys_addr_t paddr, size_t pgsize, size_t pgcount,
2256 int iommu_prot, gfp_t gfp, size_t *mapped)
2257 {
2258 struct protection_domain *domain = to_pdomain(dom);
2259 struct io_pgtable_ops *ops = &domain->iop.iop.ops;
2260 int prot = 0;
2261 int ret = -EINVAL;
2262
2263 if ((amd_iommu_pgtable == AMD_IOMMU_V1) &&
2264 (domain->iop.mode == PAGE_MODE_NONE))
2265 return -EINVAL;
2266
2267 if (iommu_prot & IOMMU_READ)
2268 prot |= IOMMU_PROT_IR;
2269 if (iommu_prot & IOMMU_WRITE)
2270 prot |= IOMMU_PROT_IW;
2271
2272 if (ops->map_pages) {
2273 ret = ops->map_pages(ops, iova, paddr, pgsize,
2274 pgcount, prot, gfp, mapped);
2275 }
2276
2277 return ret;
2278 }
2279
amd_iommu_iotlb_gather_add_page(struct iommu_domain * domain,struct iommu_iotlb_gather * gather,unsigned long iova,size_t size)2280 static void amd_iommu_iotlb_gather_add_page(struct iommu_domain *domain,
2281 struct iommu_iotlb_gather *gather,
2282 unsigned long iova, size_t size)
2283 {
2284 /*
2285 * AMD's IOMMU can flush as many pages as necessary in a single flush.
2286 * Unless we run in a virtual machine, which can be inferred according
2287 * to whether "non-present cache" is on, it is probably best to prefer
2288 * (potentially) too extensive TLB flushing (i.e., more misses) over
2289 * mutliple TLB flushes (i.e., more flushes). For virtual machines the
2290 * hypervisor needs to synchronize the host IOMMU PTEs with those of
2291 * the guest, and the trade-off is different: unnecessary TLB flushes
2292 * should be avoided.
2293 */
2294 if (amd_iommu_np_cache &&
2295 iommu_iotlb_gather_is_disjoint(gather, iova, size))
2296 iommu_iotlb_sync(domain, gather);
2297
2298 iommu_iotlb_gather_add_range(gather, iova, size);
2299 }
2300
amd_iommu_unmap_pages(struct iommu_domain * dom,unsigned long iova,size_t pgsize,size_t pgcount,struct iommu_iotlb_gather * gather)2301 static size_t amd_iommu_unmap_pages(struct iommu_domain *dom, unsigned long iova,
2302 size_t pgsize, size_t pgcount,
2303 struct iommu_iotlb_gather *gather)
2304 {
2305 struct protection_domain *domain = to_pdomain(dom);
2306 struct io_pgtable_ops *ops = &domain->iop.iop.ops;
2307 size_t r;
2308
2309 if ((amd_iommu_pgtable == AMD_IOMMU_V1) &&
2310 (domain->iop.mode == PAGE_MODE_NONE))
2311 return 0;
2312
2313 r = (ops->unmap_pages) ? ops->unmap_pages(ops, iova, pgsize, pgcount, NULL) : 0;
2314
2315 if (r)
2316 amd_iommu_iotlb_gather_add_page(dom, gather, iova, r);
2317
2318 return r;
2319 }
2320
amd_iommu_iova_to_phys(struct iommu_domain * dom,dma_addr_t iova)2321 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2322 dma_addr_t iova)
2323 {
2324 struct protection_domain *domain = to_pdomain(dom);
2325 struct io_pgtable_ops *ops = &domain->iop.iop.ops;
2326
2327 return ops->iova_to_phys(ops, iova);
2328 }
2329
amd_iommu_capable(struct device * dev,enum iommu_cap cap)2330 static bool amd_iommu_capable(struct device *dev, enum iommu_cap cap)
2331 {
2332 switch (cap) {
2333 case IOMMU_CAP_CACHE_COHERENCY:
2334 return true;
2335 case IOMMU_CAP_NOEXEC:
2336 return false;
2337 case IOMMU_CAP_PRE_BOOT_PROTECTION:
2338 return amdr_ivrs_remap_support;
2339 case IOMMU_CAP_ENFORCE_CACHE_COHERENCY:
2340 return true;
2341 case IOMMU_CAP_DEFERRED_FLUSH:
2342 return true;
2343 default:
2344 break;
2345 }
2346
2347 return false;
2348 }
2349
amd_iommu_get_resv_regions(struct device * dev,struct list_head * head)2350 static void amd_iommu_get_resv_regions(struct device *dev,
2351 struct list_head *head)
2352 {
2353 struct iommu_resv_region *region;
2354 struct unity_map_entry *entry;
2355 struct amd_iommu *iommu;
2356 struct amd_iommu_pci_seg *pci_seg;
2357 int devid, sbdf;
2358
2359 sbdf = get_device_sbdf_id(dev);
2360 if (sbdf < 0)
2361 return;
2362
2363 devid = PCI_SBDF_TO_DEVID(sbdf);
2364 iommu = rlookup_amd_iommu(dev);
2365 if (!iommu)
2366 return;
2367 pci_seg = iommu->pci_seg;
2368
2369 list_for_each_entry(entry, &pci_seg->unity_map, list) {
2370 int type, prot = 0;
2371 size_t length;
2372
2373 if (devid < entry->devid_start || devid > entry->devid_end)
2374 continue;
2375
2376 type = IOMMU_RESV_DIRECT;
2377 length = entry->address_end - entry->address_start;
2378 if (entry->prot & IOMMU_PROT_IR)
2379 prot |= IOMMU_READ;
2380 if (entry->prot & IOMMU_PROT_IW)
2381 prot |= IOMMU_WRITE;
2382 if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE)
2383 /* Exclusion range */
2384 type = IOMMU_RESV_RESERVED;
2385
2386 region = iommu_alloc_resv_region(entry->address_start,
2387 length, prot, type,
2388 GFP_KERNEL);
2389 if (!region) {
2390 dev_err(dev, "Out of memory allocating dm-regions\n");
2391 return;
2392 }
2393 list_add_tail(®ion->list, head);
2394 }
2395
2396 region = iommu_alloc_resv_region(MSI_RANGE_START,
2397 MSI_RANGE_END - MSI_RANGE_START + 1,
2398 0, IOMMU_RESV_MSI, GFP_KERNEL);
2399 if (!region)
2400 return;
2401 list_add_tail(®ion->list, head);
2402
2403 region = iommu_alloc_resv_region(HT_RANGE_START,
2404 HT_RANGE_END - HT_RANGE_START + 1,
2405 0, IOMMU_RESV_RESERVED, GFP_KERNEL);
2406 if (!region)
2407 return;
2408 list_add_tail(®ion->list, head);
2409 }
2410
amd_iommu_is_attach_deferred(struct device * dev)2411 bool amd_iommu_is_attach_deferred(struct device *dev)
2412 {
2413 struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev);
2414
2415 return dev_data->defer_attach;
2416 }
2417 EXPORT_SYMBOL_GPL(amd_iommu_is_attach_deferred);
2418
amd_iommu_flush_iotlb_all(struct iommu_domain * domain)2419 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
2420 {
2421 struct protection_domain *dom = to_pdomain(domain);
2422 unsigned long flags;
2423
2424 spin_lock_irqsave(&dom->lock, flags);
2425 amd_iommu_domain_flush_tlb_pde(dom);
2426 amd_iommu_domain_flush_complete(dom);
2427 spin_unlock_irqrestore(&dom->lock, flags);
2428 }
2429
amd_iommu_iotlb_sync(struct iommu_domain * domain,struct iommu_iotlb_gather * gather)2430 static void amd_iommu_iotlb_sync(struct iommu_domain *domain,
2431 struct iommu_iotlb_gather *gather)
2432 {
2433 struct protection_domain *dom = to_pdomain(domain);
2434 unsigned long flags;
2435
2436 spin_lock_irqsave(&dom->lock, flags);
2437 domain_flush_pages(dom, gather->start, gather->end - gather->start + 1, 1);
2438 amd_iommu_domain_flush_complete(dom);
2439 spin_unlock_irqrestore(&dom->lock, flags);
2440 }
2441
amd_iommu_def_domain_type(struct device * dev)2442 static int amd_iommu_def_domain_type(struct device *dev)
2443 {
2444 struct iommu_dev_data *dev_data;
2445
2446 dev_data = dev_iommu_priv_get(dev);
2447 if (!dev_data)
2448 return 0;
2449
2450 /*
2451 * Do not identity map IOMMUv2 capable devices when:
2452 * - memory encryption is active, because some of those devices
2453 * (AMD GPUs) don't have the encryption bit in their DMA-mask
2454 * and require remapping.
2455 * - SNP is enabled, because it prohibits DTE[Mode]=0.
2456 */
2457 if (dev_data->iommu_v2 &&
2458 !cc_platform_has(CC_ATTR_MEM_ENCRYPT) &&
2459 !amd_iommu_snp_en) {
2460 return IOMMU_DOMAIN_IDENTITY;
2461 }
2462
2463 return 0;
2464 }
2465
amd_iommu_enforce_cache_coherency(struct iommu_domain * domain)2466 static bool amd_iommu_enforce_cache_coherency(struct iommu_domain *domain)
2467 {
2468 /* IOMMU_PTE_FC is always set */
2469 return true;
2470 }
2471
2472 const struct iommu_ops amd_iommu_ops = {
2473 .capable = amd_iommu_capable,
2474 .domain_alloc = amd_iommu_domain_alloc,
2475 .probe_device = amd_iommu_probe_device,
2476 .release_device = amd_iommu_release_device,
2477 .probe_finalize = amd_iommu_probe_finalize,
2478 .device_group = amd_iommu_device_group,
2479 .get_resv_regions = amd_iommu_get_resv_regions,
2480 .is_attach_deferred = amd_iommu_is_attach_deferred,
2481 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
2482 .def_domain_type = amd_iommu_def_domain_type,
2483 .default_domain_ops = &(const struct iommu_domain_ops) {
2484 .attach_dev = amd_iommu_attach_device,
2485 .map_pages = amd_iommu_map_pages,
2486 .unmap_pages = amd_iommu_unmap_pages,
2487 .iotlb_sync_map = amd_iommu_iotlb_sync_map,
2488 .iova_to_phys = amd_iommu_iova_to_phys,
2489 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
2490 .iotlb_sync = amd_iommu_iotlb_sync,
2491 .free = amd_iommu_domain_free,
2492 .enforce_cache_coherency = amd_iommu_enforce_cache_coherency,
2493 }
2494 };
2495
2496 /*****************************************************************************
2497 *
2498 * The next functions do a basic initialization of IOMMU for pass through
2499 * mode
2500 *
2501 * In passthrough mode the IOMMU is initialized and enabled but not used for
2502 * DMA-API translation.
2503 *
2504 *****************************************************************************/
2505
2506 /* IOMMUv2 specific functions */
amd_iommu_register_ppr_notifier(struct notifier_block * nb)2507 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
2508 {
2509 return atomic_notifier_chain_register(&ppr_notifier, nb);
2510 }
2511 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
2512
amd_iommu_unregister_ppr_notifier(struct notifier_block * nb)2513 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
2514 {
2515 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
2516 }
2517 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
2518
amd_iommu_domain_direct_map(struct iommu_domain * dom)2519 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
2520 {
2521 struct protection_domain *domain = to_pdomain(dom);
2522 unsigned long flags;
2523
2524 spin_lock_irqsave(&domain->lock, flags);
2525
2526 if (domain->iop.pgtbl_cfg.tlb)
2527 free_io_pgtable_ops(&domain->iop.iop.ops);
2528
2529 spin_unlock_irqrestore(&domain->lock, flags);
2530 }
2531 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
2532
2533 /* Note: This function expects iommu_domain->lock to be held prior calling the function. */
domain_enable_v2(struct protection_domain * domain,int pasids)2534 static int domain_enable_v2(struct protection_domain *domain, int pasids)
2535 {
2536 int levels;
2537
2538 /* Number of GCR3 table levels required */
2539 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
2540 levels += 1;
2541
2542 if (levels > amd_iommu_max_glx_val)
2543 return -EINVAL;
2544
2545 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
2546 if (domain->gcr3_tbl == NULL)
2547 return -ENOMEM;
2548
2549 domain->glx = levels;
2550 domain->flags |= PD_IOMMUV2_MASK;
2551
2552 amd_iommu_domain_update(domain);
2553
2554 return 0;
2555 }
2556
amd_iommu_domain_enable_v2(struct iommu_domain * dom,int pasids)2557 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
2558 {
2559 struct protection_domain *pdom = to_pdomain(dom);
2560 unsigned long flags;
2561 int ret;
2562
2563 spin_lock_irqsave(&pdom->lock, flags);
2564
2565 /*
2566 * Save us all sanity checks whether devices already in the
2567 * domain support IOMMUv2. Just force that the domain has no
2568 * devices attached when it is switched into IOMMUv2 mode.
2569 */
2570 ret = -EBUSY;
2571 if (pdom->dev_cnt > 0 || pdom->flags & PD_IOMMUV2_MASK)
2572 goto out;
2573
2574 if (!pdom->gcr3_tbl)
2575 ret = domain_enable_v2(pdom, pasids);
2576
2577 out:
2578 spin_unlock_irqrestore(&pdom->lock, flags);
2579 return ret;
2580 }
2581 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
2582
__flush_pasid(struct protection_domain * domain,u32 pasid,u64 address,bool size)2583 static int __flush_pasid(struct protection_domain *domain, u32 pasid,
2584 u64 address, bool size)
2585 {
2586 struct iommu_dev_data *dev_data;
2587 struct iommu_cmd cmd;
2588 int i, ret;
2589
2590 if (!(domain->flags & PD_IOMMUV2_MASK))
2591 return -EINVAL;
2592
2593 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
2594
2595 /*
2596 * IOMMU TLB needs to be flushed before Device TLB to
2597 * prevent device TLB refill from IOMMU TLB
2598 */
2599 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
2600 if (domain->dev_iommu[i] == 0)
2601 continue;
2602
2603 ret = iommu_queue_command(amd_iommus[i], &cmd);
2604 if (ret != 0)
2605 goto out;
2606 }
2607
2608 /* Wait until IOMMU TLB flushes are complete */
2609 amd_iommu_domain_flush_complete(domain);
2610
2611 /* Now flush device TLBs */
2612 list_for_each_entry(dev_data, &domain->dev_list, list) {
2613 struct amd_iommu *iommu;
2614 int qdep;
2615
2616 /*
2617 There might be non-IOMMUv2 capable devices in an IOMMUv2
2618 * domain.
2619 */
2620 if (!dev_data->ats.enabled)
2621 continue;
2622
2623 qdep = dev_data->ats.qdep;
2624 iommu = rlookup_amd_iommu(dev_data->dev);
2625 if (!iommu)
2626 continue;
2627 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
2628 qdep, address, size);
2629
2630 ret = iommu_queue_command(iommu, &cmd);
2631 if (ret != 0)
2632 goto out;
2633 }
2634
2635 /* Wait until all device TLBs are flushed */
2636 amd_iommu_domain_flush_complete(domain);
2637
2638 ret = 0;
2639
2640 out:
2641
2642 return ret;
2643 }
2644
__amd_iommu_flush_page(struct protection_domain * domain,u32 pasid,u64 address)2645 static int __amd_iommu_flush_page(struct protection_domain *domain, u32 pasid,
2646 u64 address)
2647 {
2648 return __flush_pasid(domain, pasid, address, false);
2649 }
2650
amd_iommu_flush_page(struct iommu_domain * dom,u32 pasid,u64 address)2651 int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid,
2652 u64 address)
2653 {
2654 struct protection_domain *domain = to_pdomain(dom);
2655 unsigned long flags;
2656 int ret;
2657
2658 spin_lock_irqsave(&domain->lock, flags);
2659 ret = __amd_iommu_flush_page(domain, pasid, address);
2660 spin_unlock_irqrestore(&domain->lock, flags);
2661
2662 return ret;
2663 }
2664 EXPORT_SYMBOL(amd_iommu_flush_page);
2665
__amd_iommu_flush_tlb(struct protection_domain * domain,u32 pasid)2666 static int __amd_iommu_flush_tlb(struct protection_domain *domain, u32 pasid)
2667 {
2668 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
2669 true);
2670 }
2671
amd_iommu_flush_tlb(struct iommu_domain * dom,u32 pasid)2672 int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid)
2673 {
2674 struct protection_domain *domain = to_pdomain(dom);
2675 unsigned long flags;
2676 int ret;
2677
2678 spin_lock_irqsave(&domain->lock, flags);
2679 ret = __amd_iommu_flush_tlb(domain, pasid);
2680 spin_unlock_irqrestore(&domain->lock, flags);
2681
2682 return ret;
2683 }
2684 EXPORT_SYMBOL(amd_iommu_flush_tlb);
2685
__get_gcr3_pte(u64 * root,int level,u32 pasid,bool alloc)2686 static u64 *__get_gcr3_pte(u64 *root, int level, u32 pasid, bool alloc)
2687 {
2688 int index;
2689 u64 *pte;
2690
2691 while (true) {
2692
2693 index = (pasid >> (9 * level)) & 0x1ff;
2694 pte = &root[index];
2695
2696 if (level == 0)
2697 break;
2698
2699 if (!(*pte & GCR3_VALID)) {
2700 if (!alloc)
2701 return NULL;
2702
2703 root = (void *)get_zeroed_page(GFP_ATOMIC);
2704 if (root == NULL)
2705 return NULL;
2706
2707 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
2708 }
2709
2710 root = iommu_phys_to_virt(*pte & PAGE_MASK);
2711
2712 level -= 1;
2713 }
2714
2715 return pte;
2716 }
2717
__set_gcr3(struct protection_domain * domain,u32 pasid,unsigned long cr3)2718 static int __set_gcr3(struct protection_domain *domain, u32 pasid,
2719 unsigned long cr3)
2720 {
2721 u64 *pte;
2722
2723 if (domain->iop.mode != PAGE_MODE_NONE)
2724 return -EINVAL;
2725
2726 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
2727 if (pte == NULL)
2728 return -ENOMEM;
2729
2730 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
2731
2732 return __amd_iommu_flush_tlb(domain, pasid);
2733 }
2734
__clear_gcr3(struct protection_domain * domain,u32 pasid)2735 static int __clear_gcr3(struct protection_domain *domain, u32 pasid)
2736 {
2737 u64 *pte;
2738
2739 if (domain->iop.mode != PAGE_MODE_NONE)
2740 return -EINVAL;
2741
2742 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
2743 if (pte == NULL)
2744 return 0;
2745
2746 *pte = 0;
2747
2748 return __amd_iommu_flush_tlb(domain, pasid);
2749 }
2750
amd_iommu_domain_set_gcr3(struct iommu_domain * dom,u32 pasid,unsigned long cr3)2751 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,
2752 unsigned long cr3)
2753 {
2754 struct protection_domain *domain = to_pdomain(dom);
2755 unsigned long flags;
2756 int ret;
2757
2758 spin_lock_irqsave(&domain->lock, flags);
2759 ret = __set_gcr3(domain, pasid, cr3);
2760 spin_unlock_irqrestore(&domain->lock, flags);
2761
2762 return ret;
2763 }
2764 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
2765
amd_iommu_domain_clear_gcr3(struct iommu_domain * dom,u32 pasid)2766 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid)
2767 {
2768 struct protection_domain *domain = to_pdomain(dom);
2769 unsigned long flags;
2770 int ret;
2771
2772 spin_lock_irqsave(&domain->lock, flags);
2773 ret = __clear_gcr3(domain, pasid);
2774 spin_unlock_irqrestore(&domain->lock, flags);
2775
2776 return ret;
2777 }
2778 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
2779
amd_iommu_complete_ppr(struct pci_dev * pdev,u32 pasid,int status,int tag)2780 int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,
2781 int status, int tag)
2782 {
2783 struct iommu_dev_data *dev_data;
2784 struct amd_iommu *iommu;
2785 struct iommu_cmd cmd;
2786
2787 dev_data = dev_iommu_priv_get(&pdev->dev);
2788 iommu = rlookup_amd_iommu(&pdev->dev);
2789 if (!iommu)
2790 return -ENODEV;
2791
2792 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
2793 tag, dev_data->pri_tlp);
2794
2795 return iommu_queue_command(iommu, &cmd);
2796 }
2797 EXPORT_SYMBOL(amd_iommu_complete_ppr);
2798
amd_iommu_device_info(struct pci_dev * pdev,struct amd_iommu_device_info * info)2799 int amd_iommu_device_info(struct pci_dev *pdev,
2800 struct amd_iommu_device_info *info)
2801 {
2802 int max_pasids;
2803 int pos;
2804
2805 if (pdev == NULL || info == NULL)
2806 return -EINVAL;
2807
2808 if (!amd_iommu_v2_supported())
2809 return -EINVAL;
2810
2811 memset(info, 0, sizeof(*info));
2812
2813 if (pci_ats_supported(pdev))
2814 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
2815
2816 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2817 if (pos)
2818 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
2819
2820 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
2821 if (pos) {
2822 int features;
2823
2824 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
2825 max_pasids = min(max_pasids, (1 << 20));
2826
2827 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
2828 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
2829
2830 features = pci_pasid_features(pdev);
2831 if (features & PCI_PASID_CAP_EXEC)
2832 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
2833 if (features & PCI_PASID_CAP_PRIV)
2834 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
2835 }
2836
2837 return 0;
2838 }
2839 EXPORT_SYMBOL(amd_iommu_device_info);
2840
2841 #ifdef CONFIG_IRQ_REMAP
2842
2843 /*****************************************************************************
2844 *
2845 * Interrupt Remapping Implementation
2846 *
2847 *****************************************************************************/
2848
2849 static struct irq_chip amd_ir_chip;
2850 static DEFINE_SPINLOCK(iommu_table_lock);
2851
iommu_flush_irt_and_complete(struct amd_iommu * iommu,u16 devid)2852 static void iommu_flush_irt_and_complete(struct amd_iommu *iommu, u16 devid)
2853 {
2854 int ret;
2855 u64 data;
2856 unsigned long flags;
2857 struct iommu_cmd cmd, cmd2;
2858
2859 if (iommu->irtcachedis_enabled)
2860 return;
2861
2862 build_inv_irt(&cmd, devid);
2863 data = atomic64_add_return(1, &iommu->cmd_sem_val);
2864 build_completion_wait(&cmd2, iommu, data);
2865
2866 raw_spin_lock_irqsave(&iommu->lock, flags);
2867 ret = __iommu_queue_command_sync(iommu, &cmd, true);
2868 if (ret)
2869 goto out;
2870 ret = __iommu_queue_command_sync(iommu, &cmd2, false);
2871 if (ret)
2872 goto out;
2873 wait_on_sem(iommu, data);
2874 out:
2875 raw_spin_unlock_irqrestore(&iommu->lock, flags);
2876 }
2877
set_dte_irq_entry(struct amd_iommu * iommu,u16 devid,struct irq_remap_table * table)2878 static void set_dte_irq_entry(struct amd_iommu *iommu, u16 devid,
2879 struct irq_remap_table *table)
2880 {
2881 u64 dte;
2882 struct dev_table_entry *dev_table = get_dev_table(iommu);
2883
2884 dte = dev_table[devid].data[2];
2885 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
2886 dte |= iommu_virt_to_phys(table->table);
2887 dte |= DTE_IRQ_REMAP_INTCTL;
2888 dte |= DTE_INTTABLEN;
2889 dte |= DTE_IRQ_REMAP_ENABLE;
2890
2891 dev_table[devid].data[2] = dte;
2892 }
2893
get_irq_table(struct amd_iommu * iommu,u16 devid)2894 static struct irq_remap_table *get_irq_table(struct amd_iommu *iommu, u16 devid)
2895 {
2896 struct irq_remap_table *table;
2897 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg;
2898
2899 if (WARN_ONCE(!pci_seg->rlookup_table[devid],
2900 "%s: no iommu for devid %x:%x\n",
2901 __func__, pci_seg->id, devid))
2902 return NULL;
2903
2904 table = pci_seg->irq_lookup_table[devid];
2905 if (WARN_ONCE(!table, "%s: no table for devid %x:%x\n",
2906 __func__, pci_seg->id, devid))
2907 return NULL;
2908
2909 return table;
2910 }
2911
__alloc_irq_table(void)2912 static struct irq_remap_table *__alloc_irq_table(void)
2913 {
2914 struct irq_remap_table *table;
2915
2916 table = kzalloc(sizeof(*table), GFP_KERNEL);
2917 if (!table)
2918 return NULL;
2919
2920 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
2921 if (!table->table) {
2922 kfree(table);
2923 return NULL;
2924 }
2925 raw_spin_lock_init(&table->lock);
2926
2927 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
2928 memset(table->table, 0,
2929 MAX_IRQS_PER_TABLE * sizeof(u32));
2930 else
2931 memset(table->table, 0,
2932 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
2933 return table;
2934 }
2935
set_remap_table_entry(struct amd_iommu * iommu,u16 devid,struct irq_remap_table * table)2936 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
2937 struct irq_remap_table *table)
2938 {
2939 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg;
2940
2941 pci_seg->irq_lookup_table[devid] = table;
2942 set_dte_irq_entry(iommu, devid, table);
2943 iommu_flush_dte(iommu, devid);
2944 }
2945
set_remap_table_entry_alias(struct pci_dev * pdev,u16 alias,void * data)2946 static int set_remap_table_entry_alias(struct pci_dev *pdev, u16 alias,
2947 void *data)
2948 {
2949 struct irq_remap_table *table = data;
2950 struct amd_iommu_pci_seg *pci_seg;
2951 struct amd_iommu *iommu = rlookup_amd_iommu(&pdev->dev);
2952
2953 if (!iommu)
2954 return -EINVAL;
2955
2956 pci_seg = iommu->pci_seg;
2957 pci_seg->irq_lookup_table[alias] = table;
2958 set_dte_irq_entry(iommu, alias, table);
2959 iommu_flush_dte(pci_seg->rlookup_table[alias], alias);
2960
2961 return 0;
2962 }
2963
alloc_irq_table(struct amd_iommu * iommu,u16 devid,struct pci_dev * pdev)2964 static struct irq_remap_table *alloc_irq_table(struct amd_iommu *iommu,
2965 u16 devid, struct pci_dev *pdev)
2966 {
2967 struct irq_remap_table *table = NULL;
2968 struct irq_remap_table *new_table = NULL;
2969 struct amd_iommu_pci_seg *pci_seg;
2970 unsigned long flags;
2971 u16 alias;
2972
2973 spin_lock_irqsave(&iommu_table_lock, flags);
2974
2975 pci_seg = iommu->pci_seg;
2976 table = pci_seg->irq_lookup_table[devid];
2977 if (table)
2978 goto out_unlock;
2979
2980 alias = pci_seg->alias_table[devid];
2981 table = pci_seg->irq_lookup_table[alias];
2982 if (table) {
2983 set_remap_table_entry(iommu, devid, table);
2984 goto out_wait;
2985 }
2986 spin_unlock_irqrestore(&iommu_table_lock, flags);
2987
2988 /* Nothing there yet, allocate new irq remapping table */
2989 new_table = __alloc_irq_table();
2990 if (!new_table)
2991 return NULL;
2992
2993 spin_lock_irqsave(&iommu_table_lock, flags);
2994
2995 table = pci_seg->irq_lookup_table[devid];
2996 if (table)
2997 goto out_unlock;
2998
2999 table = pci_seg->irq_lookup_table[alias];
3000 if (table) {
3001 set_remap_table_entry(iommu, devid, table);
3002 goto out_wait;
3003 }
3004
3005 table = new_table;
3006 new_table = NULL;
3007
3008 if (pdev)
3009 pci_for_each_dma_alias(pdev, set_remap_table_entry_alias,
3010 table);
3011 else
3012 set_remap_table_entry(iommu, devid, table);
3013
3014 if (devid != alias)
3015 set_remap_table_entry(iommu, alias, table);
3016
3017 out_wait:
3018 iommu_completion_wait(iommu);
3019
3020 out_unlock:
3021 spin_unlock_irqrestore(&iommu_table_lock, flags);
3022
3023 if (new_table) {
3024 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3025 kfree(new_table);
3026 }
3027 return table;
3028 }
3029
alloc_irq_index(struct amd_iommu * iommu,u16 devid,int count,bool align,struct pci_dev * pdev)3030 static int alloc_irq_index(struct amd_iommu *iommu, u16 devid, int count,
3031 bool align, struct pci_dev *pdev)
3032 {
3033 struct irq_remap_table *table;
3034 int index, c, alignment = 1;
3035 unsigned long flags;
3036
3037 table = alloc_irq_table(iommu, devid, pdev);
3038 if (!table)
3039 return -ENODEV;
3040
3041 if (align)
3042 alignment = roundup_pow_of_two(count);
3043
3044 raw_spin_lock_irqsave(&table->lock, flags);
3045
3046 /* Scan table for free entries */
3047 for (index = ALIGN(table->min_index, alignment), c = 0;
3048 index < MAX_IRQS_PER_TABLE;) {
3049 if (!iommu->irte_ops->is_allocated(table, index)) {
3050 c += 1;
3051 } else {
3052 c = 0;
3053 index = ALIGN(index + 1, alignment);
3054 continue;
3055 }
3056
3057 if (c == count) {
3058 for (; c != 0; --c)
3059 iommu->irte_ops->set_allocated(table, index - c + 1);
3060
3061 index -= count - 1;
3062 goto out;
3063 }
3064
3065 index++;
3066 }
3067
3068 index = -ENOSPC;
3069
3070 out:
3071 raw_spin_unlock_irqrestore(&table->lock, flags);
3072
3073 return index;
3074 }
3075
modify_irte_ga(struct amd_iommu * iommu,u16 devid,int index,struct irte_ga * irte)3076 static int modify_irte_ga(struct amd_iommu *iommu, u16 devid, int index,
3077 struct irte_ga *irte)
3078 {
3079 struct irq_remap_table *table;
3080 struct irte_ga *entry;
3081 unsigned long flags;
3082 u128 old;
3083
3084 table = get_irq_table(iommu, devid);
3085 if (!table)
3086 return -ENOMEM;
3087
3088 raw_spin_lock_irqsave(&table->lock, flags);
3089
3090 entry = (struct irte_ga *)table->table;
3091 entry = &entry[index];
3092
3093 /*
3094 * We use cmpxchg16 to atomically update the 128-bit IRTE,
3095 * and it cannot be updated by the hardware or other processors
3096 * behind us, so the return value of cmpxchg16 should be the
3097 * same as the old value.
3098 */
3099 old = entry->irte;
3100 WARN_ON(!try_cmpxchg128(&entry->irte, &old, irte->irte));
3101
3102 raw_spin_unlock_irqrestore(&table->lock, flags);
3103
3104 iommu_flush_irt_and_complete(iommu, devid);
3105
3106 return 0;
3107 }
3108
modify_irte(struct amd_iommu * iommu,u16 devid,int index,union irte * irte)3109 static int modify_irte(struct amd_iommu *iommu,
3110 u16 devid, int index, union irte *irte)
3111 {
3112 struct irq_remap_table *table;
3113 unsigned long flags;
3114
3115 table = get_irq_table(iommu, devid);
3116 if (!table)
3117 return -ENOMEM;
3118
3119 raw_spin_lock_irqsave(&table->lock, flags);
3120 table->table[index] = irte->val;
3121 raw_spin_unlock_irqrestore(&table->lock, flags);
3122
3123 iommu_flush_irt_and_complete(iommu, devid);
3124
3125 return 0;
3126 }
3127
free_irte(struct amd_iommu * iommu,u16 devid,int index)3128 static void free_irte(struct amd_iommu *iommu, u16 devid, int index)
3129 {
3130 struct irq_remap_table *table;
3131 unsigned long flags;
3132
3133 table = get_irq_table(iommu, devid);
3134 if (!table)
3135 return;
3136
3137 raw_spin_lock_irqsave(&table->lock, flags);
3138 iommu->irte_ops->clear_allocated(table, index);
3139 raw_spin_unlock_irqrestore(&table->lock, flags);
3140
3141 iommu_flush_irt_and_complete(iommu, devid);
3142 }
3143
irte_prepare(void * entry,u32 delivery_mode,bool dest_mode,u8 vector,u32 dest_apicid,int devid)3144 static void irte_prepare(void *entry,
3145 u32 delivery_mode, bool dest_mode,
3146 u8 vector, u32 dest_apicid, int devid)
3147 {
3148 union irte *irte = (union irte *) entry;
3149
3150 irte->val = 0;
3151 irte->fields.vector = vector;
3152 irte->fields.int_type = delivery_mode;
3153 irte->fields.destination = dest_apicid;
3154 irte->fields.dm = dest_mode;
3155 irte->fields.valid = 1;
3156 }
3157
irte_ga_prepare(void * entry,u32 delivery_mode,bool dest_mode,u8 vector,u32 dest_apicid,int devid)3158 static void irte_ga_prepare(void *entry,
3159 u32 delivery_mode, bool dest_mode,
3160 u8 vector, u32 dest_apicid, int devid)
3161 {
3162 struct irte_ga *irte = (struct irte_ga *) entry;
3163
3164 irte->lo.val = 0;
3165 irte->hi.val = 0;
3166 irte->lo.fields_remap.int_type = delivery_mode;
3167 irte->lo.fields_remap.dm = dest_mode;
3168 irte->hi.fields.vector = vector;
3169 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
3170 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
3171 irte->lo.fields_remap.valid = 1;
3172 }
3173
irte_activate(struct amd_iommu * iommu,void * entry,u16 devid,u16 index)3174 static void irte_activate(struct amd_iommu *iommu, void *entry, u16 devid, u16 index)
3175 {
3176 union irte *irte = (union irte *) entry;
3177
3178 irte->fields.valid = 1;
3179 modify_irte(iommu, devid, index, irte);
3180 }
3181
irte_ga_activate(struct amd_iommu * iommu,void * entry,u16 devid,u16 index)3182 static void irte_ga_activate(struct amd_iommu *iommu, void *entry, u16 devid, u16 index)
3183 {
3184 struct irte_ga *irte = (struct irte_ga *) entry;
3185
3186 irte->lo.fields_remap.valid = 1;
3187 modify_irte_ga(iommu, devid, index, irte);
3188 }
3189
irte_deactivate(struct amd_iommu * iommu,void * entry,u16 devid,u16 index)3190 static void irte_deactivate(struct amd_iommu *iommu, void *entry, u16 devid, u16 index)
3191 {
3192 union irte *irte = (union irte *) entry;
3193
3194 irte->fields.valid = 0;
3195 modify_irte(iommu, devid, index, irte);
3196 }
3197
irte_ga_deactivate(struct amd_iommu * iommu,void * entry,u16 devid,u16 index)3198 static void irte_ga_deactivate(struct amd_iommu *iommu, void *entry, u16 devid, u16 index)
3199 {
3200 struct irte_ga *irte = (struct irte_ga *) entry;
3201
3202 irte->lo.fields_remap.valid = 0;
3203 modify_irte_ga(iommu, devid, index, irte);
3204 }
3205
irte_set_affinity(struct amd_iommu * iommu,void * entry,u16 devid,u16 index,u8 vector,u32 dest_apicid)3206 static void irte_set_affinity(struct amd_iommu *iommu, void *entry, u16 devid, u16 index,
3207 u8 vector, u32 dest_apicid)
3208 {
3209 union irte *irte = (union irte *) entry;
3210
3211 irte->fields.vector = vector;
3212 irte->fields.destination = dest_apicid;
3213 modify_irte(iommu, devid, index, irte);
3214 }
3215
irte_ga_set_affinity(struct amd_iommu * iommu,void * entry,u16 devid,u16 index,u8 vector,u32 dest_apicid)3216 static void irte_ga_set_affinity(struct amd_iommu *iommu, void *entry, u16 devid, u16 index,
3217 u8 vector, u32 dest_apicid)
3218 {
3219 struct irte_ga *irte = (struct irte_ga *) entry;
3220
3221 if (!irte->lo.fields_remap.guest_mode) {
3222 irte->hi.fields.vector = vector;
3223 irte->lo.fields_remap.destination =
3224 APICID_TO_IRTE_DEST_LO(dest_apicid);
3225 irte->hi.fields.destination =
3226 APICID_TO_IRTE_DEST_HI(dest_apicid);
3227 modify_irte_ga(iommu, devid, index, irte);
3228 }
3229 }
3230
3231 #define IRTE_ALLOCATED (~1U)
irte_set_allocated(struct irq_remap_table * table,int index)3232 static void irte_set_allocated(struct irq_remap_table *table, int index)
3233 {
3234 table->table[index] = IRTE_ALLOCATED;
3235 }
3236
irte_ga_set_allocated(struct irq_remap_table * table,int index)3237 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3238 {
3239 struct irte_ga *ptr = (struct irte_ga *)table->table;
3240 struct irte_ga *irte = &ptr[index];
3241
3242 memset(&irte->lo.val, 0, sizeof(u64));
3243 memset(&irte->hi.val, 0, sizeof(u64));
3244 irte->hi.fields.vector = 0xff;
3245 }
3246
irte_is_allocated(struct irq_remap_table * table,int index)3247 static bool irte_is_allocated(struct irq_remap_table *table, int index)
3248 {
3249 union irte *ptr = (union irte *)table->table;
3250 union irte *irte = &ptr[index];
3251
3252 return irte->val != 0;
3253 }
3254
irte_ga_is_allocated(struct irq_remap_table * table,int index)3255 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3256 {
3257 struct irte_ga *ptr = (struct irte_ga *)table->table;
3258 struct irte_ga *irte = &ptr[index];
3259
3260 return irte->hi.fields.vector != 0;
3261 }
3262
irte_clear_allocated(struct irq_remap_table * table,int index)3263 static void irte_clear_allocated(struct irq_remap_table *table, int index)
3264 {
3265 table->table[index] = 0;
3266 }
3267
irte_ga_clear_allocated(struct irq_remap_table * table,int index)3268 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3269 {
3270 struct irte_ga *ptr = (struct irte_ga *)table->table;
3271 struct irte_ga *irte = &ptr[index];
3272
3273 memset(&irte->lo.val, 0, sizeof(u64));
3274 memset(&irte->hi.val, 0, sizeof(u64));
3275 }
3276
get_devid(struct irq_alloc_info * info)3277 static int get_devid(struct irq_alloc_info *info)
3278 {
3279 switch (info->type) {
3280 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3281 return get_ioapic_devid(info->devid);
3282 case X86_IRQ_ALLOC_TYPE_HPET:
3283 return get_hpet_devid(info->devid);
3284 case X86_IRQ_ALLOC_TYPE_PCI_MSI:
3285 case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
3286 return get_device_sbdf_id(msi_desc_to_dev(info->desc));
3287 default:
3288 WARN_ON_ONCE(1);
3289 return -1;
3290 }
3291 }
3292
3293 struct irq_remap_ops amd_iommu_irq_ops = {
3294 .prepare = amd_iommu_prepare,
3295 .enable = amd_iommu_enable,
3296 .disable = amd_iommu_disable,
3297 .reenable = amd_iommu_reenable,
3298 .enable_faulting = amd_iommu_enable_faulting,
3299 };
3300
fill_msi_msg(struct msi_msg * msg,u32 index)3301 static void fill_msi_msg(struct msi_msg *msg, u32 index)
3302 {
3303 msg->data = index;
3304 msg->address_lo = 0;
3305 msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW;
3306 msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;
3307 }
3308
irq_remapping_prepare_irte(struct amd_ir_data * data,struct irq_cfg * irq_cfg,struct irq_alloc_info * info,int devid,int index,int sub_handle)3309 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
3310 struct irq_cfg *irq_cfg,
3311 struct irq_alloc_info *info,
3312 int devid, int index, int sub_handle)
3313 {
3314 struct irq_2_irte *irte_info = &data->irq_2_irte;
3315 struct amd_iommu *iommu = data->iommu;
3316
3317 if (!iommu)
3318 return;
3319
3320 data->irq_2_irte.devid = devid;
3321 data->irq_2_irte.index = index + sub_handle;
3322 iommu->irte_ops->prepare(data->entry, apic->delivery_mode,
3323 apic->dest_mode_logical, irq_cfg->vector,
3324 irq_cfg->dest_apicid, devid);
3325
3326 switch (info->type) {
3327 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3328 case X86_IRQ_ALLOC_TYPE_HPET:
3329 case X86_IRQ_ALLOC_TYPE_PCI_MSI:
3330 case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
3331 fill_msi_msg(&data->msi_entry, irte_info->index);
3332 break;
3333
3334 default:
3335 BUG_ON(1);
3336 break;
3337 }
3338 }
3339
3340 struct amd_irte_ops irte_32_ops = {
3341 .prepare = irte_prepare,
3342 .activate = irte_activate,
3343 .deactivate = irte_deactivate,
3344 .set_affinity = irte_set_affinity,
3345 .set_allocated = irte_set_allocated,
3346 .is_allocated = irte_is_allocated,
3347 .clear_allocated = irte_clear_allocated,
3348 };
3349
3350 struct amd_irte_ops irte_128_ops = {
3351 .prepare = irte_ga_prepare,
3352 .activate = irte_ga_activate,
3353 .deactivate = irte_ga_deactivate,
3354 .set_affinity = irte_ga_set_affinity,
3355 .set_allocated = irte_ga_set_allocated,
3356 .is_allocated = irte_ga_is_allocated,
3357 .clear_allocated = irte_ga_clear_allocated,
3358 };
3359
irq_remapping_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)3360 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
3361 unsigned int nr_irqs, void *arg)
3362 {
3363 struct irq_alloc_info *info = arg;
3364 struct irq_data *irq_data;
3365 struct amd_ir_data *data = NULL;
3366 struct amd_iommu *iommu;
3367 struct irq_cfg *cfg;
3368 int i, ret, devid, seg, sbdf;
3369 int index;
3370
3371 if (!info)
3372 return -EINVAL;
3373 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_PCI_MSI)
3374 return -EINVAL;
3375
3376 sbdf = get_devid(info);
3377 if (sbdf < 0)
3378 return -EINVAL;
3379
3380 seg = PCI_SBDF_TO_SEGID(sbdf);
3381 devid = PCI_SBDF_TO_DEVID(sbdf);
3382 iommu = __rlookup_amd_iommu(seg, devid);
3383 if (!iommu)
3384 return -EINVAL;
3385
3386 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
3387 if (ret < 0)
3388 return ret;
3389
3390 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
3391 struct irq_remap_table *table;
3392
3393 table = alloc_irq_table(iommu, devid, NULL);
3394 if (table) {
3395 if (!table->min_index) {
3396 /*
3397 * Keep the first 32 indexes free for IOAPIC
3398 * interrupts.
3399 */
3400 table->min_index = 32;
3401 for (i = 0; i < 32; ++i)
3402 iommu->irte_ops->set_allocated(table, i);
3403 }
3404 WARN_ON(table->min_index != 32);
3405 index = info->ioapic.pin;
3406 } else {
3407 index = -ENOMEM;
3408 }
3409 } else if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI ||
3410 info->type == X86_IRQ_ALLOC_TYPE_PCI_MSIX) {
3411 bool align = (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI);
3412
3413 index = alloc_irq_index(iommu, devid, nr_irqs, align,
3414 msi_desc_to_pci_dev(info->desc));
3415 } else {
3416 index = alloc_irq_index(iommu, devid, nr_irqs, false, NULL);
3417 }
3418
3419 if (index < 0) {
3420 pr_warn("Failed to allocate IRTE\n");
3421 ret = index;
3422 goto out_free_parent;
3423 }
3424
3425 for (i = 0; i < nr_irqs; i++) {
3426 irq_data = irq_domain_get_irq_data(domain, virq + i);
3427 cfg = irq_data ? irqd_cfg(irq_data) : NULL;
3428 if (!cfg) {
3429 ret = -EINVAL;
3430 goto out_free_data;
3431 }
3432
3433 ret = -ENOMEM;
3434 data = kzalloc(sizeof(*data), GFP_KERNEL);
3435 if (!data)
3436 goto out_free_data;
3437
3438 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3439 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
3440 else
3441 data->entry = kzalloc(sizeof(struct irte_ga),
3442 GFP_KERNEL);
3443 if (!data->entry) {
3444 kfree(data);
3445 goto out_free_data;
3446 }
3447
3448 data->iommu = iommu;
3449 irq_data->hwirq = (devid << 16) + i;
3450 irq_data->chip_data = data;
3451 irq_data->chip = &amd_ir_chip;
3452 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
3453 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
3454 }
3455
3456 return 0;
3457
3458 out_free_data:
3459 for (i--; i >= 0; i--) {
3460 irq_data = irq_domain_get_irq_data(domain, virq + i);
3461 if (irq_data)
3462 kfree(irq_data->chip_data);
3463 }
3464 for (i = 0; i < nr_irqs; i++)
3465 free_irte(iommu, devid, index + i);
3466 out_free_parent:
3467 irq_domain_free_irqs_common(domain, virq, nr_irqs);
3468 return ret;
3469 }
3470
irq_remapping_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)3471 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
3472 unsigned int nr_irqs)
3473 {
3474 struct irq_2_irte *irte_info;
3475 struct irq_data *irq_data;
3476 struct amd_ir_data *data;
3477 int i;
3478
3479 for (i = 0; i < nr_irqs; i++) {
3480 irq_data = irq_domain_get_irq_data(domain, virq + i);
3481 if (irq_data && irq_data->chip_data) {
3482 data = irq_data->chip_data;
3483 irte_info = &data->irq_2_irte;
3484 free_irte(data->iommu, irte_info->devid, irte_info->index);
3485 kfree(data->entry);
3486 kfree(data);
3487 }
3488 }
3489 irq_domain_free_irqs_common(domain, virq, nr_irqs);
3490 }
3491
3492 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
3493 struct amd_ir_data *ir_data,
3494 struct irq_2_irte *irte_info,
3495 struct irq_cfg *cfg);
3496
irq_remapping_activate(struct irq_domain * domain,struct irq_data * irq_data,bool reserve)3497 static int irq_remapping_activate(struct irq_domain *domain,
3498 struct irq_data *irq_data, bool reserve)
3499 {
3500 struct amd_ir_data *data = irq_data->chip_data;
3501 struct irq_2_irte *irte_info = &data->irq_2_irte;
3502 struct amd_iommu *iommu = data->iommu;
3503 struct irq_cfg *cfg = irqd_cfg(irq_data);
3504
3505 if (!iommu)
3506 return 0;
3507
3508 iommu->irte_ops->activate(iommu, data->entry, irte_info->devid,
3509 irte_info->index);
3510 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
3511 return 0;
3512 }
3513
irq_remapping_deactivate(struct irq_domain * domain,struct irq_data * irq_data)3514 static void irq_remapping_deactivate(struct irq_domain *domain,
3515 struct irq_data *irq_data)
3516 {
3517 struct amd_ir_data *data = irq_data->chip_data;
3518 struct irq_2_irte *irte_info = &data->irq_2_irte;
3519 struct amd_iommu *iommu = data->iommu;
3520
3521 if (iommu)
3522 iommu->irte_ops->deactivate(iommu, data->entry, irte_info->devid,
3523 irte_info->index);
3524 }
3525
irq_remapping_select(struct irq_domain * d,struct irq_fwspec * fwspec,enum irq_domain_bus_token bus_token)3526 static int irq_remapping_select(struct irq_domain *d, struct irq_fwspec *fwspec,
3527 enum irq_domain_bus_token bus_token)
3528 {
3529 struct amd_iommu *iommu;
3530 int devid = -1;
3531
3532 if (!amd_iommu_irq_remap)
3533 return 0;
3534
3535 if (x86_fwspec_is_ioapic(fwspec))
3536 devid = get_ioapic_devid(fwspec->param[0]);
3537 else if (x86_fwspec_is_hpet(fwspec))
3538 devid = get_hpet_devid(fwspec->param[0]);
3539
3540 if (devid < 0)
3541 return 0;
3542 iommu = __rlookup_amd_iommu((devid >> 16), (devid & 0xffff));
3543
3544 return iommu && iommu->ir_domain == d;
3545 }
3546
3547 static const struct irq_domain_ops amd_ir_domain_ops = {
3548 .select = irq_remapping_select,
3549 .alloc = irq_remapping_alloc,
3550 .free = irq_remapping_free,
3551 .activate = irq_remapping_activate,
3552 .deactivate = irq_remapping_deactivate,
3553 };
3554
amd_iommu_activate_guest_mode(void * data)3555 int amd_iommu_activate_guest_mode(void *data)
3556 {
3557 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3558 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3559 u64 valid;
3560
3561 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) || !entry)
3562 return 0;
3563
3564 valid = entry->lo.fields_vapic.valid;
3565
3566 entry->lo.val = 0;
3567 entry->hi.val = 0;
3568
3569 entry->lo.fields_vapic.valid = valid;
3570 entry->lo.fields_vapic.guest_mode = 1;
3571 entry->lo.fields_vapic.ga_log_intr = 1;
3572 entry->hi.fields.ga_root_ptr = ir_data->ga_root_ptr;
3573 entry->hi.fields.vector = ir_data->ga_vector;
3574 entry->lo.fields_vapic.ga_tag = ir_data->ga_tag;
3575
3576 return modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid,
3577 ir_data->irq_2_irte.index, entry);
3578 }
3579 EXPORT_SYMBOL(amd_iommu_activate_guest_mode);
3580
amd_iommu_deactivate_guest_mode(void * data)3581 int amd_iommu_deactivate_guest_mode(void *data)
3582 {
3583 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3584 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3585 struct irq_cfg *cfg = ir_data->cfg;
3586 u64 valid;
3587
3588 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
3589 !entry || !entry->lo.fields_vapic.guest_mode)
3590 return 0;
3591
3592 valid = entry->lo.fields_remap.valid;
3593
3594 entry->lo.val = 0;
3595 entry->hi.val = 0;
3596
3597 entry->lo.fields_remap.valid = valid;
3598 entry->lo.fields_remap.dm = apic->dest_mode_logical;
3599 entry->lo.fields_remap.int_type = apic->delivery_mode;
3600 entry->hi.fields.vector = cfg->vector;
3601 entry->lo.fields_remap.destination =
3602 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
3603 entry->hi.fields.destination =
3604 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
3605
3606 return modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid,
3607 ir_data->irq_2_irte.index, entry);
3608 }
3609 EXPORT_SYMBOL(amd_iommu_deactivate_guest_mode);
3610
amd_ir_set_vcpu_affinity(struct irq_data * data,void * vcpu_info)3611 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
3612 {
3613 int ret;
3614 struct amd_iommu_pi_data *pi_data = vcpu_info;
3615 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
3616 struct amd_ir_data *ir_data = data->chip_data;
3617 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
3618 struct iommu_dev_data *dev_data;
3619
3620 if (ir_data->iommu == NULL)
3621 return -EINVAL;
3622
3623 dev_data = search_dev_data(ir_data->iommu, irte_info->devid);
3624
3625 /* Note:
3626 * This device has never been set up for guest mode.
3627 * we should not modify the IRTE
3628 */
3629 if (!dev_data || !dev_data->use_vapic)
3630 return -EINVAL;
3631
3632 ir_data->cfg = irqd_cfg(data);
3633 pi_data->ir_data = ir_data;
3634
3635 /* Note:
3636 * SVM tries to set up for VAPIC mode, but we are in
3637 * legacy mode. So, we force legacy mode instead.
3638 */
3639 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3640 pr_debug("%s: Fall back to using intr legacy remap\n",
3641 __func__);
3642 pi_data->is_guest_mode = false;
3643 }
3644
3645 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
3646 if (pi_data->is_guest_mode) {
3647 ir_data->ga_root_ptr = (pi_data->base >> 12);
3648 ir_data->ga_vector = vcpu_pi_info->vector;
3649 ir_data->ga_tag = pi_data->ga_tag;
3650 ret = amd_iommu_activate_guest_mode(ir_data);
3651 if (!ret)
3652 ir_data->cached_ga_tag = pi_data->ga_tag;
3653 } else {
3654 ret = amd_iommu_deactivate_guest_mode(ir_data);
3655
3656 /*
3657 * This communicates the ga_tag back to the caller
3658 * so that it can do all the necessary clean up.
3659 */
3660 if (!ret)
3661 ir_data->cached_ga_tag = 0;
3662 }
3663
3664 return ret;
3665 }
3666
3667
amd_ir_update_irte(struct irq_data * irqd,struct amd_iommu * iommu,struct amd_ir_data * ir_data,struct irq_2_irte * irte_info,struct irq_cfg * cfg)3668 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
3669 struct amd_ir_data *ir_data,
3670 struct irq_2_irte *irte_info,
3671 struct irq_cfg *cfg)
3672 {
3673
3674 /*
3675 * Atomically updates the IRTE with the new destination, vector
3676 * and flushes the interrupt entry cache.
3677 */
3678 iommu->irte_ops->set_affinity(iommu, ir_data->entry, irte_info->devid,
3679 irte_info->index, cfg->vector,
3680 cfg->dest_apicid);
3681 }
3682
amd_ir_set_affinity(struct irq_data * data,const struct cpumask * mask,bool force)3683 static int amd_ir_set_affinity(struct irq_data *data,
3684 const struct cpumask *mask, bool force)
3685 {
3686 struct amd_ir_data *ir_data = data->chip_data;
3687 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
3688 struct irq_cfg *cfg = irqd_cfg(data);
3689 struct irq_data *parent = data->parent_data;
3690 struct amd_iommu *iommu = ir_data->iommu;
3691 int ret;
3692
3693 if (!iommu)
3694 return -ENODEV;
3695
3696 ret = parent->chip->irq_set_affinity(parent, mask, force);
3697 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
3698 return ret;
3699
3700 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
3701 /*
3702 * After this point, all the interrupts will start arriving
3703 * at the new destination. So, time to cleanup the previous
3704 * vector allocation.
3705 */
3706 vector_schedule_cleanup(cfg);
3707
3708 return IRQ_SET_MASK_OK_DONE;
3709 }
3710
ir_compose_msi_msg(struct irq_data * irq_data,struct msi_msg * msg)3711 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
3712 {
3713 struct amd_ir_data *ir_data = irq_data->chip_data;
3714
3715 *msg = ir_data->msi_entry;
3716 }
3717
3718 static struct irq_chip amd_ir_chip = {
3719 .name = "AMD-IR",
3720 .irq_ack = apic_ack_irq,
3721 .irq_set_affinity = amd_ir_set_affinity,
3722 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
3723 .irq_compose_msi_msg = ir_compose_msi_msg,
3724 };
3725
3726 static const struct msi_parent_ops amdvi_msi_parent_ops = {
3727 .supported_flags = X86_VECTOR_MSI_FLAGS_SUPPORTED |
3728 MSI_FLAG_MULTI_PCI_MSI |
3729 MSI_FLAG_PCI_IMS,
3730 .prefix = "IR-",
3731 .init_dev_msi_info = msi_parent_init_dev_msi_info,
3732 };
3733
3734 static const struct msi_parent_ops virt_amdvi_msi_parent_ops = {
3735 .supported_flags = X86_VECTOR_MSI_FLAGS_SUPPORTED |
3736 MSI_FLAG_MULTI_PCI_MSI,
3737 .prefix = "vIR-",
3738 .init_dev_msi_info = msi_parent_init_dev_msi_info,
3739 };
3740
amd_iommu_create_irq_domain(struct amd_iommu * iommu)3741 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
3742 {
3743 struct fwnode_handle *fn;
3744
3745 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
3746 if (!fn)
3747 return -ENOMEM;
3748 iommu->ir_domain = irq_domain_create_hierarchy(arch_get_ir_parent_domain(), 0, 0,
3749 fn, &amd_ir_domain_ops, iommu);
3750 if (!iommu->ir_domain) {
3751 irq_domain_free_fwnode(fn);
3752 return -ENOMEM;
3753 }
3754
3755 irq_domain_update_bus_token(iommu->ir_domain, DOMAIN_BUS_AMDVI);
3756 iommu->ir_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT |
3757 IRQ_DOMAIN_FLAG_ISOLATED_MSI;
3758
3759 if (amd_iommu_np_cache)
3760 iommu->ir_domain->msi_parent_ops = &virt_amdvi_msi_parent_ops;
3761 else
3762 iommu->ir_domain->msi_parent_ops = &amdvi_msi_parent_ops;
3763
3764 return 0;
3765 }
3766
amd_iommu_update_ga(int cpu,bool is_run,void * data)3767 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
3768 {
3769 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3770 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3771
3772 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
3773 !entry || !entry->lo.fields_vapic.guest_mode)
3774 return 0;
3775
3776 if (!ir_data->iommu)
3777 return -ENODEV;
3778
3779 if (cpu >= 0) {
3780 entry->lo.fields_vapic.destination =
3781 APICID_TO_IRTE_DEST_LO(cpu);
3782 entry->hi.fields.destination =
3783 APICID_TO_IRTE_DEST_HI(cpu);
3784 }
3785 entry->lo.fields_vapic.is_run = is_run;
3786
3787 return modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid,
3788 ir_data->irq_2_irte.index, entry);
3789 }
3790 EXPORT_SYMBOL(amd_iommu_update_ga);
3791 #endif
3792