xref: /openbmc/linux/drivers/ata/pata_amd.c (revision 25df73d9)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * pata_amd.c 	- AMD PATA for new ATA layer
4  *			  (C) 2005-2006 Red Hat Inc
5  *
6  *  Based on pata-sil680. Errata information is taken from data sheets
7  *  and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are
8  *  claimed by sata-nv.c.
9  *
10  *  TODO:
11  *	Variable system clock when/if it makes sense
12  *	Power management on ports
13  *
14  *
15  *  Documentation publicly available.
16  */
17 
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/blkdev.h>
22 #include <linux/delay.h>
23 #include <scsi/scsi_host.h>
24 #include <linux/libata.h>
25 
26 #define DRV_NAME "pata_amd"
27 #define DRV_VERSION "0.4.1"
28 
29 /**
30  *	timing_setup		-	shared timing computation and load
31  *	@ap: ATA port being set up
32  *	@adev: drive being configured
33  *	@offset: port offset
34  *	@speed: target speed
35  *	@clock: clock multiplier (number of times 33MHz for this part)
36  *
37  *	Perform the actual timing set up for Nvidia or AMD PATA devices.
38  *	The actual devices vary so they all call into this helper function
39  *	providing the clock multipler and offset (because AMD and Nvidia put
40  *	the ports at different locations).
41  */
42 
timing_setup(struct ata_port * ap,struct ata_device * adev,int offset,int speed,int clock)43 static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offset, int speed, int clock)
44 {
45 	static const unsigned char amd_cyc2udma[] = {
46 		6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7
47 	};
48 
49 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
50 	struct ata_device *peer = ata_dev_pair(adev);
51 	int dn = ap->port_no * 2 + adev->devno;
52 	struct ata_timing at, apeer;
53 	int T, UT;
54 	const int amd_clock = 33333;	/* KHz. */
55 	u8 t;
56 
57 	T = 1000000000 / amd_clock;
58 	UT = T;
59 	if (clock >= 2)
60 		UT = T / 2;
61 
62 	if (ata_timing_compute(adev, speed, &at, T, UT) < 0) {
63 		dev_err(&pdev->dev, "unknown mode %d\n", speed);
64 		return;
65 	}
66 
67 	if (peer) {
68 		/* This may be over conservative */
69 		if (ata_dma_enabled(peer)) {
70 			ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT);
71 			ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
72 		}
73 		ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT);
74 		ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
75 	}
76 
77 	if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1;
78 	if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15;
79 
80 	/*
81 	 *	Now do the setup work
82 	 */
83 
84 	/* Configure the address set up timing */
85 	pci_read_config_byte(pdev, offset + 0x0C, &t);
86 	t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(at.setup, 1, 4) - 1) << ((3 - dn) << 1));
87 	pci_write_config_byte(pdev, offset + 0x0C , t);
88 
89 	/* Configure the 8bit I/O timing */
90 	pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)),
91 		((clamp_val(at.act8b, 1, 16) - 1) << 4) | (clamp_val(at.rec8b, 1, 16) - 1));
92 
93 	/* Drive timing */
94 	pci_write_config_byte(pdev, offset + 0x08 + (3 - dn),
95 		((clamp_val(at.active, 1, 16) - 1) << 4) | (clamp_val(at.recover, 1, 16) - 1));
96 
97 	switch (clock) {
98 		case 1:
99 		t = at.udma ? (0xc0 | (clamp_val(at.udma, 2, 5) - 2)) : 0x03;
100 		break;
101 
102 		case 2:
103 		t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 2, 10)]) : 0x03;
104 		break;
105 
106 		case 3:
107 		t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 10)]) : 0x03;
108 		break;
109 
110 		case 4:
111 		t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 15)]) : 0x03;
112 		break;
113 
114 		default:
115 			return;
116 	}
117 
118 	/* UDMA timing */
119 	if (at.udma)
120 		pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t);
121 }
122 
123 /**
124  *	amd_pre_reset		-	perform reset handling
125  *	@link: ATA link
126  *	@deadline: deadline jiffies for the operation
127  *
128  *	Reset sequence checking enable bits to see which ports are
129  *	active.
130  */
131 
amd_pre_reset(struct ata_link * link,unsigned long deadline)132 static int amd_pre_reset(struct ata_link *link, unsigned long deadline)
133 {
134 	static const struct pci_bits amd_enable_bits[] = {
135 		{ 0x40, 1, 0x02, 0x02 },
136 		{ 0x40, 1, 0x01, 0x01 }
137 	};
138 
139 	struct ata_port *ap = link->ap;
140 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
141 
142 	if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no]))
143 		return -ENOENT;
144 
145 	return ata_sff_prereset(link, deadline);
146 }
147 
148 /**
149  *	amd_cable_detect	-	report cable type
150  *	@ap: port
151  *
152  *	AMD controller/BIOS setups record the cable type in word 0x42
153  */
154 
amd_cable_detect(struct ata_port * ap)155 static int amd_cable_detect(struct ata_port *ap)
156 {
157 	static const u32 bitmask[2] = {0x03, 0x0C};
158 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
159 	u8 ata66;
160 
161 	pci_read_config_byte(pdev, 0x42, &ata66);
162 	if (ata66 & bitmask[ap->port_no])
163 		return ATA_CBL_PATA80;
164 	return ATA_CBL_PATA40;
165 }
166 
167 /**
168  *	amd_fifo_setup		-	set the PIO FIFO for ATA/ATAPI
169  *	@ap: ATA interface
170  *
171  *	Set the PCI fifo for this device according to the devices present
172  *	on the bus at this point in time. We need to turn the post write buffer
173  *	off for ATAPI devices as we may need to issue a word sized write to the
174  *	device as the final I/O
175  */
176 
amd_fifo_setup(struct ata_port * ap)177 static void amd_fifo_setup(struct ata_port *ap)
178 {
179 	struct ata_device *adev;
180 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
181 	static const u8 fifobit[2] = { 0xC0, 0x30};
182 	u8 fifo = fifobit[ap->port_no];
183 	u8 r;
184 
185 
186 	ata_for_each_dev(adev, &ap->link, ENABLED) {
187 		if (adev->class == ATA_DEV_ATAPI)
188 			fifo = 0;
189 	}
190 	if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7411) /* FIFO is broken */
191 		fifo = 0;
192 
193 	/* On the later chips the read prefetch bits become no-op bits */
194 	pci_read_config_byte(pdev, 0x41, &r);
195 	r &= ~fifobit[ap->port_no];
196 	r |= fifo;
197 	pci_write_config_byte(pdev, 0x41, r);
198 }
199 
200 /**
201  *	amd33_set_piomode	-	set initial PIO mode data
202  *	@ap: ATA interface
203  *	@adev: ATA device
204  *
205  *	Program the AMD registers for PIO mode.
206  */
207 
amd33_set_piomode(struct ata_port * ap,struct ata_device * adev)208 static void amd33_set_piomode(struct ata_port *ap, struct ata_device *adev)
209 {
210 	amd_fifo_setup(ap);
211 	timing_setup(ap, adev, 0x40, adev->pio_mode, 1);
212 }
213 
amd66_set_piomode(struct ata_port * ap,struct ata_device * adev)214 static void amd66_set_piomode(struct ata_port *ap, struct ata_device *adev)
215 {
216 	amd_fifo_setup(ap);
217 	timing_setup(ap, adev, 0x40, adev->pio_mode, 2);
218 }
219 
amd100_set_piomode(struct ata_port * ap,struct ata_device * adev)220 static void amd100_set_piomode(struct ata_port *ap, struct ata_device *adev)
221 {
222 	amd_fifo_setup(ap);
223 	timing_setup(ap, adev, 0x40, adev->pio_mode, 3);
224 }
225 
amd133_set_piomode(struct ata_port * ap,struct ata_device * adev)226 static void amd133_set_piomode(struct ata_port *ap, struct ata_device *adev)
227 {
228 	amd_fifo_setup(ap);
229 	timing_setup(ap, adev, 0x40, adev->pio_mode, 4);
230 }
231 
232 /**
233  *	amd33_set_dmamode	-	set initial DMA mode data
234  *	@ap: ATA interface
235  *	@adev: ATA device
236  *
237  *	Program the MWDMA/UDMA modes for the AMD and Nvidia
238  *	chipset.
239  */
240 
amd33_set_dmamode(struct ata_port * ap,struct ata_device * adev)241 static void amd33_set_dmamode(struct ata_port *ap, struct ata_device *adev)
242 {
243 	timing_setup(ap, adev, 0x40, adev->dma_mode, 1);
244 }
245 
amd66_set_dmamode(struct ata_port * ap,struct ata_device * adev)246 static void amd66_set_dmamode(struct ata_port *ap, struct ata_device *adev)
247 {
248 	timing_setup(ap, adev, 0x40, adev->dma_mode, 2);
249 }
250 
amd100_set_dmamode(struct ata_port * ap,struct ata_device * adev)251 static void amd100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
252 {
253 	timing_setup(ap, adev, 0x40, adev->dma_mode, 3);
254 }
255 
amd133_set_dmamode(struct ata_port * ap,struct ata_device * adev)256 static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
257 {
258 	timing_setup(ap, adev, 0x40, adev->dma_mode, 4);
259 }
260 
261 /* Both host-side and drive-side detection results are worthless on NV
262  * PATAs.  Ignore them and just follow what BIOS configured.  Both the
263  * current configuration in PCI config reg and ACPI GTM result are
264  * cached during driver attach and are consulted to select transfer
265  * mode.
266  */
nv_mode_filter(struct ata_device * dev,unsigned int xfer_mask)267 static unsigned int nv_mode_filter(struct ata_device *dev,
268 				   unsigned int xfer_mask)
269 {
270 	static const unsigned int udma_mask_map[] =
271 		{ ATA_UDMA2, ATA_UDMA1, ATA_UDMA0, 0,
272 		  ATA_UDMA3, ATA_UDMA4, ATA_UDMA5, ATA_UDMA6 };
273 	struct ata_port *ap = dev->link->ap;
274 	char acpi_str[32] = "";
275 	u32 saved_udma, udma;
276 	const struct ata_acpi_gtm *gtm;
277 	unsigned int bios_limit = 0, acpi_limit = 0, limit;
278 
279 	/* find out what BIOS configured */
280 	udma = saved_udma = (unsigned long)ap->host->private_data;
281 
282 	if (ap->port_no == 0)
283 		udma >>= 16;
284 	if (dev->devno == 0)
285 		udma >>= 8;
286 
287 	if ((udma & 0xc0) == 0xc0)
288 		bios_limit = ata_pack_xfermask(0, 0, udma_mask_map[udma & 0x7]);
289 
290 	/* consult ACPI GTM too */
291 	gtm = ata_acpi_init_gtm(ap);
292 	if (gtm) {
293 		acpi_limit = ata_acpi_gtm_xfermask(dev, gtm);
294 
295 		snprintf(acpi_str, sizeof(acpi_str), " (%u:%u:0x%x)",
296 			 gtm->drive[0].dma, gtm->drive[1].dma, gtm->flags);
297 	}
298 
299 	/* be optimistic, EH can take care of things if something goes wrong */
300 	limit = bios_limit | acpi_limit;
301 
302 	/* If PIO or DMA isn't configured at all, don't limit.  Let EH
303 	 * handle it.
304 	 */
305 	if (!(limit & ATA_MASK_PIO))
306 		limit |= ATA_MASK_PIO;
307 	if (!(limit & (ATA_MASK_MWDMA | ATA_MASK_UDMA)))
308 		limit |= ATA_MASK_MWDMA | ATA_MASK_UDMA;
309 	/* PIO4, MWDMA2, UDMA2 should always be supported regardless of
310 	   cable detection result */
311 	limit |= ata_pack_xfermask(ATA_PIO4, ATA_MWDMA2, ATA_UDMA2);
312 
313 	ata_port_dbg(ap,
314 		     "nv_mode_filter: 0x%x&0x%x->0x%x, BIOS=0x%x (0x%x) ACPI=0x%x%s\n",
315 		     xfer_mask, limit, xfer_mask & limit, bios_limit,
316 		     saved_udma, acpi_limit, acpi_str);
317 
318 	return xfer_mask & limit;
319 }
320 
321 /**
322  *	nv_pre_reset	-	cable detection
323  *	@link: ATA link
324  *	@deadline: deadline jiffies for the operation
325  *
326  *	Perform cable detection. The BIOS stores this in PCI config
327  *	space for us.
328  */
329 
nv_pre_reset(struct ata_link * link,unsigned long deadline)330 static int nv_pre_reset(struct ata_link *link, unsigned long deadline)
331 {
332 	static const struct pci_bits nv_enable_bits[] = {
333 		{ 0x50, 1, 0x02, 0x02 },
334 		{ 0x50, 1, 0x01, 0x01 }
335 	};
336 
337 	struct ata_port *ap = link->ap;
338 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
339 
340 	if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no]))
341 		return -ENOENT;
342 
343 	return ata_sff_prereset(link, deadline);
344 }
345 
346 /**
347  *	nv100_set_piomode	-	set initial PIO mode data
348  *	@ap: ATA interface
349  *	@adev: ATA device
350  *
351  *	Program the AMD registers for PIO mode.
352  */
353 
nv100_set_piomode(struct ata_port * ap,struct ata_device * adev)354 static void nv100_set_piomode(struct ata_port *ap, struct ata_device *adev)
355 {
356 	timing_setup(ap, adev, 0x50, adev->pio_mode, 3);
357 }
358 
nv133_set_piomode(struct ata_port * ap,struct ata_device * adev)359 static void nv133_set_piomode(struct ata_port *ap, struct ata_device *adev)
360 {
361 	timing_setup(ap, adev, 0x50, adev->pio_mode, 4);
362 }
363 
364 /**
365  *	nv100_set_dmamode	-	set initial DMA mode data
366  *	@ap: ATA interface
367  *	@adev: ATA device
368  *
369  *	Program the MWDMA/UDMA modes for the AMD and Nvidia
370  *	chipset.
371  */
372 
nv100_set_dmamode(struct ata_port * ap,struct ata_device * adev)373 static void nv100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
374 {
375 	timing_setup(ap, adev, 0x50, adev->dma_mode, 3);
376 }
377 
nv133_set_dmamode(struct ata_port * ap,struct ata_device * adev)378 static void nv133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
379 {
380 	timing_setup(ap, adev, 0x50, adev->dma_mode, 4);
381 }
382 
nv_host_stop(struct ata_host * host)383 static void nv_host_stop(struct ata_host *host)
384 {
385 	u32 udma = (unsigned long)host->private_data;
386 
387 	/* restore PCI config register 0x60 */
388 	pci_write_config_dword(to_pci_dev(host->dev), 0x60, udma);
389 }
390 
391 static const struct scsi_host_template amd_sht = {
392 	ATA_BMDMA_SHT(DRV_NAME),
393 };
394 
395 static const struct ata_port_operations amd_base_port_ops = {
396 	.inherits	= &ata_bmdma32_port_ops,
397 	.prereset	= amd_pre_reset,
398 };
399 
400 static struct ata_port_operations amd33_port_ops = {
401 	.inherits	= &amd_base_port_ops,
402 	.cable_detect	= ata_cable_40wire,
403 	.set_piomode	= amd33_set_piomode,
404 	.set_dmamode	= amd33_set_dmamode,
405 };
406 
407 static struct ata_port_operations amd66_port_ops = {
408 	.inherits	= &amd_base_port_ops,
409 	.cable_detect	= ata_cable_unknown,
410 	.set_piomode	= amd66_set_piomode,
411 	.set_dmamode	= amd66_set_dmamode,
412 };
413 
414 static struct ata_port_operations amd100_port_ops = {
415 	.inherits	= &amd_base_port_ops,
416 	.cable_detect	= ata_cable_unknown,
417 	.set_piomode	= amd100_set_piomode,
418 	.set_dmamode	= amd100_set_dmamode,
419 };
420 
421 static struct ata_port_operations amd133_port_ops = {
422 	.inherits	= &amd_base_port_ops,
423 	.cable_detect	= amd_cable_detect,
424 	.set_piomode	= amd133_set_piomode,
425 	.set_dmamode	= amd133_set_dmamode,
426 };
427 
428 static const struct ata_port_operations nv_base_port_ops = {
429 	.inherits	= &ata_bmdma_port_ops,
430 	.cable_detect	= ata_cable_ignore,
431 	.mode_filter	= nv_mode_filter,
432 	.prereset	= nv_pre_reset,
433 	.host_stop	= nv_host_stop,
434 };
435 
436 static struct ata_port_operations nv100_port_ops = {
437 	.inherits	= &nv_base_port_ops,
438 	.set_piomode	= nv100_set_piomode,
439 	.set_dmamode	= nv100_set_dmamode,
440 };
441 
442 static struct ata_port_operations nv133_port_ops = {
443 	.inherits	= &nv_base_port_ops,
444 	.set_piomode	= nv133_set_piomode,
445 	.set_dmamode	= nv133_set_dmamode,
446 };
447 
amd_clear_fifo(struct pci_dev * pdev)448 static void amd_clear_fifo(struct pci_dev *pdev)
449 {
450 	u8 fifo;
451 	/* Disable the FIFO, the FIFO logic will re-enable it as
452 	   appropriate */
453 	pci_read_config_byte(pdev, 0x41, &fifo);
454 	fifo &= 0x0F;
455 	pci_write_config_byte(pdev, 0x41, fifo);
456 }
457 
amd_init_one(struct pci_dev * pdev,const struct pci_device_id * id)458 static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
459 {
460 	static const struct ata_port_info info[10] = {
461 		{	/* 0: AMD 7401 - no swdma */
462 			.flags = ATA_FLAG_SLAVE_POSS,
463 			.pio_mask = ATA_PIO4,
464 			.mwdma_mask = ATA_MWDMA2,
465 			.udma_mask = ATA_UDMA2,
466 			.port_ops = &amd33_port_ops
467 		},
468 		{	/* 1: Early AMD7409 - no swdma */
469 			.flags = ATA_FLAG_SLAVE_POSS,
470 			.pio_mask = ATA_PIO4,
471 			.mwdma_mask = ATA_MWDMA2,
472 			.udma_mask = ATA_UDMA4,
473 			.port_ops = &amd66_port_ops
474 		},
475 		{	/* 2: AMD 7409 */
476 			.flags = ATA_FLAG_SLAVE_POSS,
477 			.pio_mask = ATA_PIO4,
478 			.mwdma_mask = ATA_MWDMA2,
479 			.udma_mask = ATA_UDMA4,
480 			.port_ops = &amd66_port_ops
481 		},
482 		{	/* 3: AMD 7411 */
483 			.flags = ATA_FLAG_SLAVE_POSS,
484 			.pio_mask = ATA_PIO4,
485 			.mwdma_mask = ATA_MWDMA2,
486 			.udma_mask = ATA_UDMA5,
487 			.port_ops = &amd100_port_ops
488 		},
489 		{	/* 4: AMD 7441 */
490 			.flags = ATA_FLAG_SLAVE_POSS,
491 			.pio_mask = ATA_PIO4,
492 			.mwdma_mask = ATA_MWDMA2,
493 			.udma_mask = ATA_UDMA5,
494 			.port_ops = &amd100_port_ops
495 		},
496 		{	/* 5: AMD 8111 - no swdma */
497 			.flags = ATA_FLAG_SLAVE_POSS,
498 			.pio_mask = ATA_PIO4,
499 			.mwdma_mask = ATA_MWDMA2,
500 			.udma_mask = ATA_UDMA6,
501 			.port_ops = &amd133_port_ops
502 		},
503 		{	/* 6: AMD 8111 UDMA 100 (Serenade) - no swdma */
504 			.flags = ATA_FLAG_SLAVE_POSS,
505 			.pio_mask = ATA_PIO4,
506 			.mwdma_mask = ATA_MWDMA2,
507 			.udma_mask = ATA_UDMA5,
508 			.port_ops = &amd133_port_ops
509 		},
510 		{	/* 7: Nvidia Nforce */
511 			.flags = ATA_FLAG_SLAVE_POSS,
512 			.pio_mask = ATA_PIO4,
513 			.mwdma_mask = ATA_MWDMA2,
514 			.udma_mask = ATA_UDMA5,
515 			.port_ops = &nv100_port_ops
516 		},
517 		{	/* 8: Nvidia Nforce2 and later - no swdma */
518 			.flags = ATA_FLAG_SLAVE_POSS,
519 			.pio_mask = ATA_PIO4,
520 			.mwdma_mask = ATA_MWDMA2,
521 			.udma_mask = ATA_UDMA6,
522 			.port_ops = &nv133_port_ops
523 		},
524 		{	/* 9: AMD CS5536 (Geode companion) */
525 			.flags = ATA_FLAG_SLAVE_POSS,
526 			.pio_mask = ATA_PIO4,
527 			.mwdma_mask = ATA_MWDMA2,
528 			.udma_mask = ATA_UDMA5,
529 			.port_ops = &amd100_port_ops
530 		}
531 	};
532 	const struct ata_port_info *ppi[] = { NULL, NULL };
533 	int type = id->driver_data;
534 	void *hpriv = NULL;
535 	u8 fifo;
536 	int rc;
537 
538 	ata_print_version_once(&pdev->dev, DRV_VERSION);
539 
540 	rc = pcim_enable_device(pdev);
541 	if (rc)
542 		return rc;
543 
544 	pci_read_config_byte(pdev, 0x41, &fifo);
545 
546 	/* Check for AMD7409 without swdma errata and if found adjust type */
547 	if (type == 1 && pdev->revision > 0x7)
548 		type = 2;
549 
550 	/* Serenade ? */
551 	if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
552 			 pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
553 		type = 6;	/* UDMA 100 only */
554 
555 	/*
556 	 * Okay, type is determined now.  Apply type-specific workarounds.
557 	 */
558 	ppi[0] = &info[type];
559 
560 	if (type < 3)
561 		ata_pci_bmdma_clear_simplex(pdev);
562 	if (pdev->vendor == PCI_VENDOR_ID_AMD)
563 		amd_clear_fifo(pdev);
564 	/* Cable detection on Nvidia chips doesn't work too well,
565 	 * cache BIOS programmed UDMA mode.
566 	 */
567 	if (type == 7 || type == 8) {
568 		u32 udma;
569 
570 		pci_read_config_dword(pdev, 0x60, &udma);
571 		hpriv = (void *)(unsigned long)udma;
572 	}
573 
574 	/* And fire it up */
575 	return ata_pci_bmdma_init_one(pdev, ppi, &amd_sht, hpriv, 0);
576 }
577 
578 #ifdef CONFIG_PM_SLEEP
amd_reinit_one(struct pci_dev * pdev)579 static int amd_reinit_one(struct pci_dev *pdev)
580 {
581 	struct ata_host *host = pci_get_drvdata(pdev);
582 	int rc;
583 
584 	rc = ata_pci_device_do_resume(pdev);
585 	if (rc)
586 		return rc;
587 
588 	if (pdev->vendor == PCI_VENDOR_ID_AMD) {
589 		amd_clear_fifo(pdev);
590 		if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7409 ||
591 		    pdev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
592 			ata_pci_bmdma_clear_simplex(pdev);
593 	}
594 	ata_host_resume(host);
595 	return 0;
596 }
597 #endif
598 
599 static const struct pci_device_id amd[] = {
600 	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_COBRA_7401),		0 },
601 	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_VIPER_7409),		1 },
602 	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_VIPER_7411),		3 },
603 	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_OPUS_7441),		4 },
604 	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_8111_IDE),		5 },
605 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_IDE),	7 },
606 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE),	8 },
607 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE),	8 },
608 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE),	8 },
609 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE),	8 },
610 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE),	8 },
611 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE),	8 },
612 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE),	8 },
613 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE),	8 },
614 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE),	8 },
615 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE),	8 },
616 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE),	8 },
617 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE),	8 },
618 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE),	8 },
619 	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_CS5536_IDE),		9 },
620 	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_CS5536_DEV_IDE),	9 },
621 
622 	{ },
623 };
624 
625 static struct pci_driver amd_pci_driver = {
626 	.name 		= DRV_NAME,
627 	.id_table	= amd,
628 	.probe 		= amd_init_one,
629 	.remove		= ata_pci_remove_one,
630 #ifdef CONFIG_PM_SLEEP
631 	.suspend	= ata_pci_device_suspend,
632 	.resume		= amd_reinit_one,
633 #endif
634 };
635 
636 module_pci_driver(amd_pci_driver);
637 
638 MODULE_AUTHOR("Alan Cox");
639 MODULE_DESCRIPTION("low-level driver for AMD and Nvidia PATA IDE");
640 MODULE_LICENSE("GPL");
641 MODULE_DEVICE_TABLE(pci, amd);
642 MODULE_VERSION(DRV_VERSION);
643