1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #define SWSMU_CODE_LAYER_L2
25 
26 #include <linux/firmware.h>
27 #include "amdgpu.h"
28 #include "amdgpu_dpm.h"
29 #include "amdgpu_smu.h"
30 #include "atomfirmware.h"
31 #include "amdgpu_atomfirmware.h"
32 #include "amdgpu_atombios.h"
33 #include "smu_v13_0.h"
34 #include "smu13_driver_if_aldebaran.h"
35 #include "soc15_common.h"
36 #include "atom.h"
37 #include "aldebaran_ppt.h"
38 #include "smu_v13_0_pptable.h"
39 #include "aldebaran_ppsmc.h"
40 #include "nbio/nbio_7_4_offset.h"
41 #include "nbio/nbio_7_4_sh_mask.h"
42 #include "thm/thm_11_0_2_offset.h"
43 #include "thm/thm_11_0_2_sh_mask.h"
44 #include "amdgpu_xgmi.h"
45 #include <linux/pci.h>
46 #include "amdgpu_ras.h"
47 #include "smu_cmn.h"
48 #include "mp/mp_13_0_2_offset.h"
49 
50 /*
51  * DO NOT use these for err/warn/info/debug messages.
52  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53  * They are more MGPU friendly.
54  */
55 #undef pr_err
56 #undef pr_warn
57 #undef pr_info
58 #undef pr_debug
59 
60 #define ALDEBARAN_FEA_MAP(smu_feature, aldebaran_feature) \
61 	[smu_feature] = {1, (aldebaran_feature)}
62 
63 #define FEATURE_MASK(feature) (1ULL << feature)
64 #define SMC_DPM_FEATURE ( \
65 			  FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \
66 			  FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)	| \
67 			  FEATURE_MASK(FEATURE_DPM_UCLK_BIT)	| \
68 			  FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)	| \
69 			  FEATURE_MASK(FEATURE_DPM_FCLK_BIT)	| \
70 			  FEATURE_MASK(FEATURE_DPM_LCLK_BIT)	| \
71 			  FEATURE_MASK(FEATURE_DPM_XGMI_BIT)	| \
72 			  FEATURE_MASK(FEATURE_DPM_VCN_BIT))
73 
74 /* possible frequency drift (1Mhz) */
75 #define EPSILON				1
76 
77 #define smnPCIE_ESM_CTRL			0x111003D0
78 
79 /*
80  * SMU support ECCTABLE since version 68.42.0,
81  * use this to check ECCTALE feature whether support
82  */
83 #define SUPPORT_ECCTABLE_SMU_VERSION 0x00442a00
84 
85 /*
86  * SMU support mca_ceumc_addr in ECCTABLE since version 68.55.0,
87  * use this to check mca_ceumc_addr record whether support
88  */
89 #define SUPPORT_ECCTABLE_V2_SMU_VERSION 0x00443700
90 
91 /*
92  * SMU support BAD CHENNEL info MSG since version 68.51.00,
93  * use this to check ECCTALE feature whether support
94  */
95 #define SUPPORT_BAD_CHANNEL_INFO_MSG_VERSION 0x00443300
96 
97 static const struct smu_temperature_range smu13_thermal_policy[] = {
98 	{-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
99 	{ 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
100 };
101 
102 static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT] = {
103 	MSG_MAP(TestMessage,			     PPSMC_MSG_TestMessage,			0),
104 	MSG_MAP(GetSmuVersion,			     PPSMC_MSG_GetSmuVersion,			1),
105 	MSG_MAP(GetDriverIfVersion,		     PPSMC_MSG_GetDriverIfVersion,		1),
106 	MSG_MAP(EnableAllSmuFeatures,		     PPSMC_MSG_EnableAllSmuFeatures,		0),
107 	MSG_MAP(DisableAllSmuFeatures,		     PPSMC_MSG_DisableAllSmuFeatures,		0),
108 	MSG_MAP(GetEnabledSmuFeaturesLow,	     PPSMC_MSG_GetEnabledSmuFeaturesLow,	1),
109 	MSG_MAP(GetEnabledSmuFeaturesHigh,	     PPSMC_MSG_GetEnabledSmuFeaturesHigh,	1),
110 	MSG_MAP(SetDriverDramAddrHigh,		     PPSMC_MSG_SetDriverDramAddrHigh,		1),
111 	MSG_MAP(SetDriverDramAddrLow,		     PPSMC_MSG_SetDriverDramAddrLow,		1),
112 	MSG_MAP(SetToolsDramAddrHigh,		     PPSMC_MSG_SetToolsDramAddrHigh,		0),
113 	MSG_MAP(SetToolsDramAddrLow,		     PPSMC_MSG_SetToolsDramAddrLow,		0),
114 	MSG_MAP(TransferTableSmu2Dram,		     PPSMC_MSG_TransferTableSmu2Dram,		1),
115 	MSG_MAP(TransferTableDram2Smu,		     PPSMC_MSG_TransferTableDram2Smu,		0),
116 	MSG_MAP(UseDefaultPPTable,		     PPSMC_MSG_UseDefaultPPTable,		0),
117 	MSG_MAP(SetSystemVirtualDramAddrHigh,	     PPSMC_MSG_SetSystemVirtualDramAddrHigh,	0),
118 	MSG_MAP(SetSystemVirtualDramAddrLow,	     PPSMC_MSG_SetSystemVirtualDramAddrLow,	0),
119 	MSG_MAP(SetSoftMinByFreq,		     PPSMC_MSG_SetSoftMinByFreq,		0),
120 	MSG_MAP(SetSoftMaxByFreq,		     PPSMC_MSG_SetSoftMaxByFreq,		0),
121 	MSG_MAP(SetHardMinByFreq,		     PPSMC_MSG_SetHardMinByFreq,		0),
122 	MSG_MAP(SetHardMaxByFreq,		     PPSMC_MSG_SetHardMaxByFreq,		0),
123 	MSG_MAP(GetMinDpmFreq,			     PPSMC_MSG_GetMinDpmFreq,			0),
124 	MSG_MAP(GetMaxDpmFreq,			     PPSMC_MSG_GetMaxDpmFreq,			0),
125 	MSG_MAP(GetDpmFreqByIndex,		     PPSMC_MSG_GetDpmFreqByIndex,		1),
126 	MSG_MAP(SetWorkloadMask,		     PPSMC_MSG_SetWorkloadMask,			1),
127 	MSG_MAP(GetVoltageByDpm,		     PPSMC_MSG_GetVoltageByDpm,			0),
128 	MSG_MAP(GetVoltageByDpmOverdrive,	     PPSMC_MSG_GetVoltageByDpmOverdrive,	0),
129 	MSG_MAP(SetPptLimit,			     PPSMC_MSG_SetPptLimit,			0),
130 	MSG_MAP(GetPptLimit,			     PPSMC_MSG_GetPptLimit,			1),
131 	MSG_MAP(PrepareMp1ForUnload,		     PPSMC_MSG_PrepareMp1ForUnload,		0),
132 	MSG_MAP(GfxDeviceDriverReset,		     PPSMC_MSG_GfxDriverReset,			0),
133 	MSG_MAP(RunDcBtc,			     PPSMC_MSG_RunDcBtc,			0),
134 	MSG_MAP(DramLogSetDramAddrHigh,		     PPSMC_MSG_DramLogSetDramAddrHigh,		0),
135 	MSG_MAP(DramLogSetDramAddrLow,		     PPSMC_MSG_DramLogSetDramAddrLow,		0),
136 	MSG_MAP(DramLogSetDramSize,		     PPSMC_MSG_DramLogSetDramSize,		0),
137 	MSG_MAP(GetDebugData,			     PPSMC_MSG_GetDebugData,			0),
138 	MSG_MAP(WaflTest,			     PPSMC_MSG_WaflTest,			0),
139 	MSG_MAP(SetMemoryChannelEnable,		     PPSMC_MSG_SetMemoryChannelEnable,		0),
140 	MSG_MAP(SetNumBadHbmPagesRetired,	     PPSMC_MSG_SetNumBadHbmPagesRetired,	0),
141 	MSG_MAP(DFCstateControl,		     PPSMC_MSG_DFCstateControl,			0),
142 	MSG_MAP(GetGmiPwrDnHyst,		     PPSMC_MSG_GetGmiPwrDnHyst,			0),
143 	MSG_MAP(SetGmiPwrDnHyst,		     PPSMC_MSG_SetGmiPwrDnHyst,			0),
144 	MSG_MAP(GmiPwrDnControl,		     PPSMC_MSG_GmiPwrDnControl,			0),
145 	MSG_MAP(EnterGfxoff,			     PPSMC_MSG_EnterGfxoff,			0),
146 	MSG_MAP(ExitGfxoff,			     PPSMC_MSG_ExitGfxoff,			0),
147 	MSG_MAP(SetExecuteDMATest,		     PPSMC_MSG_SetExecuteDMATest,		0),
148 	MSG_MAP(EnableDeterminism,		     PPSMC_MSG_EnableDeterminism,		0),
149 	MSG_MAP(DisableDeterminism,		     PPSMC_MSG_DisableDeterminism,		0),
150 	MSG_MAP(SetUclkDpmMode,			     PPSMC_MSG_SetUclkDpmMode,			0),
151 	MSG_MAP(GfxDriverResetRecovery,		     PPSMC_MSG_GfxDriverResetRecovery,		0),
152 	MSG_MAP(BoardPowerCalibration,		     PPSMC_MSG_BoardPowerCalibration,		0),
153 	MSG_MAP(HeavySBR,                            PPSMC_MSG_HeavySBR,                        0),
154 	MSG_MAP(SetBadHBMPagesRetiredFlagsPerChannel,	PPSMC_MSG_SetBadHBMPagesRetiredFlagsPerChannel,	0),
155 };
156 
157 static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = {
158 	CLK_MAP(GFXCLK, PPCLK_GFXCLK),
159 	CLK_MAP(SCLK,	PPCLK_GFXCLK),
160 	CLK_MAP(SOCCLK, PPCLK_SOCCLK),
161 	CLK_MAP(FCLK, PPCLK_FCLK),
162 	CLK_MAP(UCLK, PPCLK_UCLK),
163 	CLK_MAP(MCLK, PPCLK_UCLK),
164 	CLK_MAP(DCLK, PPCLK_DCLK),
165 	CLK_MAP(VCLK, PPCLK_VCLK),
166 	CLK_MAP(LCLK, 	PPCLK_LCLK),
167 };
168 
169 static const struct cmn2asic_mapping aldebaran_feature_mask_map[SMU_FEATURE_COUNT] = {
170 	ALDEBARAN_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, 		FEATURE_DATA_CALCULATIONS),
171 	ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, 			FEATURE_DPM_GFXCLK_BIT),
172 	ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT, 			FEATURE_DPM_UCLK_BIT),
173 	ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT, 			FEATURE_DPM_SOCCLK_BIT),
174 	ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, 			FEATURE_DPM_FCLK_BIT),
175 	ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT, 			FEATURE_DPM_LCLK_BIT),
176 	ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_XGMI_BIT, 				FEATURE_DPM_XGMI_BIT),
177 	ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, 			FEATURE_DS_GFXCLK_BIT),
178 	ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, 			FEATURE_DS_SOCCLK_BIT),
179 	ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, 				FEATURE_DS_LCLK_BIT),
180 	ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, 				FEATURE_DS_FCLK_BIT),
181 	ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_UCLK_BIT,				FEATURE_DS_UCLK_BIT),
182 	ALDEBARAN_FEA_MAP(SMU_FEATURE_GFX_SS_BIT, 				FEATURE_GFX_SS_BIT),
183 	ALDEBARAN_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, 				FEATURE_DPM_VCN_BIT),
184 	ALDEBARAN_FEA_MAP(SMU_FEATURE_RSMU_SMN_CG_BIT, 			FEATURE_RSMU_SMN_CG_BIT),
185 	ALDEBARAN_FEA_MAP(SMU_FEATURE_WAFL_CG_BIT, 				FEATURE_WAFL_CG_BIT),
186 	ALDEBARAN_FEA_MAP(SMU_FEATURE_PPT_BIT, 					FEATURE_PPT_BIT),
187 	ALDEBARAN_FEA_MAP(SMU_FEATURE_TDC_BIT, 					FEATURE_TDC_BIT),
188 	ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_PLUS_BIT, 			FEATURE_APCC_PLUS_BIT),
189 	ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, 			FEATURE_APCC_DFLL_BIT),
190 	ALDEBARAN_FEA_MAP(SMU_FEATURE_FUSE_CG_BIT, 				FEATURE_FUSE_CG_BIT),
191 	ALDEBARAN_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, 				FEATURE_MP1_CG_BIT),
192 	ALDEBARAN_FEA_MAP(SMU_FEATURE_SMUIO_CG_BIT, 			FEATURE_SMUIO_CG_BIT),
193 	ALDEBARAN_FEA_MAP(SMU_FEATURE_THM_CG_BIT, 				FEATURE_THM_CG_BIT),
194 	ALDEBARAN_FEA_MAP(SMU_FEATURE_CLK_CG_BIT, 				FEATURE_CLK_CG_BIT),
195 	ALDEBARAN_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, 				FEATURE_FW_CTF_BIT),
196 	ALDEBARAN_FEA_MAP(SMU_FEATURE_THERMAL_BIT, 				FEATURE_THERMAL_BIT),
197 	ALDEBARAN_FEA_MAP(SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT, 	FEATURE_OUT_OF_BAND_MONITOR_BIT),
198 	ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT, FEATURE_XGMI_PER_LINK_PWR_DWN),
199 	ALDEBARAN_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT, 			FEATURE_DF_CSTATE),
200 };
201 
202 static const struct cmn2asic_mapping aldebaran_table_map[SMU_TABLE_COUNT] = {
203 	TAB_MAP(PPTABLE),
204 	TAB_MAP(AVFS_PSM_DEBUG),
205 	TAB_MAP(AVFS_FUSE_OVERRIDE),
206 	TAB_MAP(PMSTATUSLOG),
207 	TAB_MAP(SMU_METRICS),
208 	TAB_MAP(DRIVER_SMU_CONFIG),
209 	TAB_MAP(I2C_COMMANDS),
210 	TAB_MAP(ECCINFO),
211 };
212 
213 static const uint8_t aldebaran_throttler_map[] = {
214 	[THROTTLER_PPT0_BIT]		= (SMU_THROTTLER_PPT0_BIT),
215 	[THROTTLER_PPT1_BIT]		= (SMU_THROTTLER_PPT1_BIT),
216 	[THROTTLER_TDC_GFX_BIT]		= (SMU_THROTTLER_TDC_GFX_BIT),
217 	[THROTTLER_TDC_SOC_BIT]		= (SMU_THROTTLER_TDC_SOC_BIT),
218 	[THROTTLER_TDC_HBM_BIT]		= (SMU_THROTTLER_TDC_MEM_BIT),
219 	[THROTTLER_TEMP_GPU_BIT]	= (SMU_THROTTLER_TEMP_GPU_BIT),
220 	[THROTTLER_TEMP_MEM_BIT]	= (SMU_THROTTLER_TEMP_MEM_BIT),
221 	[THROTTLER_TEMP_VR_GFX_BIT]	= (SMU_THROTTLER_TEMP_VR_GFX_BIT),
222 	[THROTTLER_TEMP_VR_SOC_BIT]	= (SMU_THROTTLER_TEMP_VR_SOC_BIT),
223 	[THROTTLER_TEMP_VR_MEM_BIT]	= (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
224 	[THROTTLER_APCC_BIT]		= (SMU_THROTTLER_APCC_BIT),
225 };
226 
aldebaran_tables_init(struct smu_context * smu)227 static int aldebaran_tables_init(struct smu_context *smu)
228 {
229 	struct smu_table_context *smu_table = &smu->smu_table;
230 	struct smu_table *tables = smu_table->tables;
231 
232 	SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
233 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
234 
235 	SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
236 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
237 
238 	SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
239 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
240 
241 	SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
242 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
243 
244 	SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
245 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
246 
247 	smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
248 	if (!smu_table->metrics_table)
249 		return -ENOMEM;
250 	smu_table->metrics_time = 0;
251 
252 	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
253 	smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
254 	if (!smu_table->gpu_metrics_table) {
255 		kfree(smu_table->metrics_table);
256 		return -ENOMEM;
257 	}
258 
259 	smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
260 	if (!smu_table->ecc_table) {
261 		kfree(smu_table->metrics_table);
262 		kfree(smu_table->gpu_metrics_table);
263 		return -ENOMEM;
264 	}
265 
266 	return 0;
267 }
268 
aldebaran_allocate_dpm_context(struct smu_context * smu)269 static int aldebaran_allocate_dpm_context(struct smu_context *smu)
270 {
271 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
272 
273 	smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
274 				       GFP_KERNEL);
275 	if (!smu_dpm->dpm_context)
276 		return -ENOMEM;
277 	smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
278 
279 	return 0;
280 }
281 
aldebaran_init_smc_tables(struct smu_context * smu)282 static int aldebaran_init_smc_tables(struct smu_context *smu)
283 {
284 	int ret = 0;
285 
286 	ret = aldebaran_tables_init(smu);
287 	if (ret)
288 		return ret;
289 
290 	ret = aldebaran_allocate_dpm_context(smu);
291 	if (ret)
292 		return ret;
293 
294 	return smu_v13_0_init_smc_tables(smu);
295 }
296 
aldebaran_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)297 static int aldebaran_get_allowed_feature_mask(struct smu_context *smu,
298 					      uint32_t *feature_mask, uint32_t num)
299 {
300 	if (num > 2)
301 		return -EINVAL;
302 
303 	/* pptable will handle the features to enable */
304 	memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
305 
306 	return 0;
307 }
308 
aldebaran_set_default_dpm_table(struct smu_context * smu)309 static int aldebaran_set_default_dpm_table(struct smu_context *smu)
310 {
311 	struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
312 	struct smu_13_0_dpm_table *dpm_table = NULL;
313 	PPTable_t *pptable = smu->smu_table.driver_pptable;
314 	int ret = 0;
315 
316 	/* socclk dpm table setup */
317 	dpm_table = &dpm_context->dpm_tables.soc_table;
318 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
319 		ret = smu_v13_0_set_single_dpm_table(smu,
320 						     SMU_SOCCLK,
321 						     dpm_table);
322 		if (ret)
323 			return ret;
324 	} else {
325 		dpm_table->count = 1;
326 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
327 		dpm_table->dpm_levels[0].enabled = true;
328 		dpm_table->min = dpm_table->dpm_levels[0].value;
329 		dpm_table->max = dpm_table->dpm_levels[0].value;
330 	}
331 
332 	/* gfxclk dpm table setup */
333 	dpm_table = &dpm_context->dpm_tables.gfx_table;
334 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
335 		/* in the case of gfxclk, only fine-grained dpm is honored */
336 		dpm_table->count = 2;
337 		dpm_table->dpm_levels[0].value = pptable->GfxclkFmin;
338 		dpm_table->dpm_levels[0].enabled = true;
339 		dpm_table->dpm_levels[1].value = pptable->GfxclkFmax;
340 		dpm_table->dpm_levels[1].enabled = true;
341 		dpm_table->min = dpm_table->dpm_levels[0].value;
342 		dpm_table->max = dpm_table->dpm_levels[1].value;
343 	} else {
344 		dpm_table->count = 1;
345 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
346 		dpm_table->dpm_levels[0].enabled = true;
347 		dpm_table->min = dpm_table->dpm_levels[0].value;
348 		dpm_table->max = dpm_table->dpm_levels[0].value;
349 	}
350 
351 	/* memclk dpm table setup */
352 	dpm_table = &dpm_context->dpm_tables.uclk_table;
353 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
354 		ret = smu_v13_0_set_single_dpm_table(smu,
355 						     SMU_UCLK,
356 						     dpm_table);
357 		if (ret)
358 			return ret;
359 	} else {
360 		dpm_table->count = 1;
361 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
362 		dpm_table->dpm_levels[0].enabled = true;
363 		dpm_table->min = dpm_table->dpm_levels[0].value;
364 		dpm_table->max = dpm_table->dpm_levels[0].value;
365 	}
366 
367 	/* fclk dpm table setup */
368 	dpm_table = &dpm_context->dpm_tables.fclk_table;
369 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
370 		ret = smu_v13_0_set_single_dpm_table(smu,
371 						     SMU_FCLK,
372 						     dpm_table);
373 		if (ret)
374 			return ret;
375 	} else {
376 		dpm_table->count = 1;
377 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
378 		dpm_table->dpm_levels[0].enabled = true;
379 		dpm_table->min = dpm_table->dpm_levels[0].value;
380 		dpm_table->max = dpm_table->dpm_levels[0].value;
381 	}
382 
383 	return 0;
384 }
385 
aldebaran_check_powerplay_table(struct smu_context * smu)386 static int aldebaran_check_powerplay_table(struct smu_context *smu)
387 {
388 	struct smu_table_context *table_context = &smu->smu_table;
389 	struct smu_13_0_powerplay_table *powerplay_table =
390 		table_context->power_play_table;
391 
392 	table_context->thermal_controller_type =
393 		powerplay_table->thermal_controller_type;
394 
395 	return 0;
396 }
397 
aldebaran_store_powerplay_table(struct smu_context * smu)398 static int aldebaran_store_powerplay_table(struct smu_context *smu)
399 {
400 	struct smu_table_context *table_context = &smu->smu_table;
401 	struct smu_13_0_powerplay_table *powerplay_table =
402 		table_context->power_play_table;
403 	memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
404 	       sizeof(PPTable_t));
405 
406 	return 0;
407 }
408 
aldebaran_append_powerplay_table(struct smu_context * smu)409 static int aldebaran_append_powerplay_table(struct smu_context *smu)
410 {
411 	struct smu_table_context *table_context = &smu->smu_table;
412 	PPTable_t *smc_pptable = table_context->driver_pptable;
413 	struct atom_smc_dpm_info_v4_10 *smc_dpm_table;
414 	int index, ret;
415 
416 	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
417 					   smc_dpm_info);
418 
419 	ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
420 				      (uint8_t **)&smc_dpm_table);
421 	if (ret)
422 		return ret;
423 
424 	dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
425 			smc_dpm_table->table_header.format_revision,
426 			smc_dpm_table->table_header.content_revision);
427 
428 	if ((smc_dpm_table->table_header.format_revision == 4) &&
429 	    (smc_dpm_table->table_header.content_revision == 10))
430 		smu_memcpy_trailing(smc_pptable, GfxMaxCurrent, reserved,
431 				    smc_dpm_table, GfxMaxCurrent);
432 	return 0;
433 }
434 
aldebaran_setup_pptable(struct smu_context * smu)435 static int aldebaran_setup_pptable(struct smu_context *smu)
436 {
437 	int ret = 0;
438 
439 	/* VBIOS pptable is the first choice */
440 	smu->smu_table.boot_values.pp_table_id = 0;
441 
442 	ret = smu_v13_0_setup_pptable(smu);
443 	if (ret)
444 		return ret;
445 
446 	ret = aldebaran_store_powerplay_table(smu);
447 	if (ret)
448 		return ret;
449 
450 	ret = aldebaran_append_powerplay_table(smu);
451 	if (ret)
452 		return ret;
453 
454 	ret = aldebaran_check_powerplay_table(smu);
455 	if (ret)
456 		return ret;
457 
458 	return ret;
459 }
460 
aldebaran_is_primary(struct smu_context * smu)461 static bool aldebaran_is_primary(struct smu_context *smu)
462 {
463 	struct amdgpu_device *adev = smu->adev;
464 
465 	if (adev->smuio.funcs && adev->smuio.funcs->get_die_id)
466 		return adev->smuio.funcs->get_die_id(adev) == 0;
467 
468 	return true;
469 }
470 
aldebaran_run_board_btc(struct smu_context * smu)471 static int aldebaran_run_board_btc(struct smu_context *smu)
472 {
473 	u32 smu_version;
474 	int ret;
475 
476 	if (!aldebaran_is_primary(smu))
477 		return 0;
478 
479 	ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
480 	if (ret) {
481 		dev_err(smu->adev->dev, "Failed to get smu version!\n");
482 		return ret;
483 	}
484 	if (smu_version <= 0x00441d00)
485 		return 0;
486 
487 	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BoardPowerCalibration, NULL);
488 	if (ret)
489 		dev_err(smu->adev->dev, "Board power calibration failed!\n");
490 
491 	return ret;
492 }
493 
aldebaran_run_btc(struct smu_context * smu)494 static int aldebaran_run_btc(struct smu_context *smu)
495 {
496 	int ret;
497 
498 	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
499 	if (ret)
500 		dev_err(smu->adev->dev, "RunDcBtc failed!\n");
501 	else
502 		ret = aldebaran_run_board_btc(smu);
503 
504 	return ret;
505 }
506 
aldebaran_populate_umd_state_clk(struct smu_context * smu)507 static int aldebaran_populate_umd_state_clk(struct smu_context *smu)
508 {
509 	struct smu_13_0_dpm_context *dpm_context =
510 		smu->smu_dpm.dpm_context;
511 	struct smu_13_0_dpm_table *gfx_table =
512 		&dpm_context->dpm_tables.gfx_table;
513 	struct smu_13_0_dpm_table *mem_table =
514 		&dpm_context->dpm_tables.uclk_table;
515 	struct smu_13_0_dpm_table *soc_table =
516 		&dpm_context->dpm_tables.soc_table;
517 	struct smu_umd_pstate_table *pstate_table =
518 		&smu->pstate_table;
519 
520 	pstate_table->gfxclk_pstate.min = gfx_table->min;
521 	pstate_table->gfxclk_pstate.peak = gfx_table->max;
522 	pstate_table->gfxclk_pstate.curr.min = gfx_table->min;
523 	pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
524 
525 	pstate_table->uclk_pstate.min = mem_table->min;
526 	pstate_table->uclk_pstate.peak = mem_table->max;
527 	pstate_table->uclk_pstate.curr.min = mem_table->min;
528 	pstate_table->uclk_pstate.curr.max = mem_table->max;
529 
530 	pstate_table->socclk_pstate.min = soc_table->min;
531 	pstate_table->socclk_pstate.peak = soc_table->max;
532 	pstate_table->socclk_pstate.curr.min = soc_table->min;
533 	pstate_table->socclk_pstate.curr.max = soc_table->max;
534 
535 	if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL &&
536 	    mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL &&
537 	    soc_table->count > ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL) {
538 		pstate_table->gfxclk_pstate.standard =
539 			gfx_table->dpm_levels[ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL].value;
540 		pstate_table->uclk_pstate.standard =
541 			mem_table->dpm_levels[ALDEBARAN_UMD_PSTATE_MCLK_LEVEL].value;
542 		pstate_table->socclk_pstate.standard =
543 			soc_table->dpm_levels[ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL].value;
544 	} else {
545 		pstate_table->gfxclk_pstate.standard =
546 			pstate_table->gfxclk_pstate.min;
547 		pstate_table->uclk_pstate.standard =
548 			pstate_table->uclk_pstate.min;
549 		pstate_table->socclk_pstate.standard =
550 			pstate_table->socclk_pstate.min;
551 	}
552 
553 	return 0;
554 }
555 
aldebaran_get_clk_table(struct smu_context * smu,struct pp_clock_levels_with_latency * clocks,struct smu_13_0_dpm_table * dpm_table)556 static int aldebaran_get_clk_table(struct smu_context *smu,
557 				   struct pp_clock_levels_with_latency *clocks,
558 				   struct smu_13_0_dpm_table *dpm_table)
559 {
560 	uint32_t i;
561 
562 	clocks->num_levels = min_t(uint32_t,
563 				   dpm_table->count,
564 				   (uint32_t)PP_MAX_CLOCK_LEVELS);
565 
566 	for (i = 0; i < clocks->num_levels; i++) {
567 		clocks->data[i].clocks_in_khz =
568 			dpm_table->dpm_levels[i].value * 1000;
569 		clocks->data[i].latency_in_us = 0;
570 	}
571 
572 	return 0;
573 }
574 
aldebaran_freqs_in_same_level(int32_t frequency1,int32_t frequency2)575 static int aldebaran_freqs_in_same_level(int32_t frequency1,
576 					 int32_t frequency2)
577 {
578 	return (abs(frequency1 - frequency2) <= EPSILON);
579 }
580 
aldebaran_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)581 static int aldebaran_get_smu_metrics_data(struct smu_context *smu,
582 					  MetricsMember_t member,
583 					  uint32_t *value)
584 {
585 	struct smu_table_context *smu_table = &smu->smu_table;
586 	SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
587 	int ret = 0;
588 
589 	ret = smu_cmn_get_metrics_table(smu,
590 					NULL,
591 					false);
592 	if (ret)
593 		return ret;
594 
595 	switch (member) {
596 	case METRICS_CURR_GFXCLK:
597 		*value = metrics->CurrClock[PPCLK_GFXCLK];
598 		break;
599 	case METRICS_CURR_SOCCLK:
600 		*value = metrics->CurrClock[PPCLK_SOCCLK];
601 		break;
602 	case METRICS_CURR_UCLK:
603 		*value = metrics->CurrClock[PPCLK_UCLK];
604 		break;
605 	case METRICS_CURR_VCLK:
606 		*value = metrics->CurrClock[PPCLK_VCLK];
607 		break;
608 	case METRICS_CURR_DCLK:
609 		*value = metrics->CurrClock[PPCLK_DCLK];
610 		break;
611 	case METRICS_CURR_FCLK:
612 		*value = metrics->CurrClock[PPCLK_FCLK];
613 		break;
614 	case METRICS_AVERAGE_GFXCLK:
615 		*value = metrics->AverageGfxclkFrequency;
616 		break;
617 	case METRICS_AVERAGE_SOCCLK:
618 		*value = metrics->AverageSocclkFrequency;
619 		break;
620 	case METRICS_AVERAGE_UCLK:
621 		*value = metrics->AverageUclkFrequency;
622 		break;
623 	case METRICS_AVERAGE_GFXACTIVITY:
624 		*value = metrics->AverageGfxActivity;
625 		break;
626 	case METRICS_AVERAGE_MEMACTIVITY:
627 		*value = metrics->AverageUclkActivity;
628 		break;
629 	case METRICS_AVERAGE_SOCKETPOWER:
630 		/* Valid power data is available only from primary die */
631 		if (aldebaran_is_primary(smu))
632 			*value = metrics->AverageSocketPower << 8;
633 		else
634 			ret = -EOPNOTSUPP;
635 		break;
636 	case METRICS_TEMPERATURE_EDGE:
637 		*value = metrics->TemperatureEdge *
638 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
639 		break;
640 	case METRICS_TEMPERATURE_HOTSPOT:
641 		*value = metrics->TemperatureHotspot *
642 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
643 		break;
644 	case METRICS_TEMPERATURE_MEM:
645 		*value = metrics->TemperatureHBM *
646 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
647 		break;
648 	case METRICS_TEMPERATURE_VRGFX:
649 		*value = metrics->TemperatureVrGfx *
650 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
651 		break;
652 	case METRICS_TEMPERATURE_VRSOC:
653 		*value = metrics->TemperatureVrSoc *
654 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
655 		break;
656 	case METRICS_TEMPERATURE_VRMEM:
657 		*value = metrics->TemperatureVrMem *
658 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
659 		break;
660 	case METRICS_THROTTLER_STATUS:
661 		*value = metrics->ThrottlerStatus;
662 		break;
663 	case METRICS_UNIQUE_ID_UPPER32:
664 		*value = metrics->PublicSerialNumUpper32;
665 		break;
666 	case METRICS_UNIQUE_ID_LOWER32:
667 		*value = metrics->PublicSerialNumLower32;
668 		break;
669 	default:
670 		*value = UINT_MAX;
671 		break;
672 	}
673 
674 	return ret;
675 }
676 
aldebaran_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)677 static int aldebaran_get_current_clk_freq_by_table(struct smu_context *smu,
678 						   enum smu_clk_type clk_type,
679 						   uint32_t *value)
680 {
681 	MetricsMember_t member_type;
682 	int clk_id = 0;
683 
684 	if (!value)
685 		return -EINVAL;
686 
687 	clk_id = smu_cmn_to_asic_specific_index(smu,
688 						CMN2ASIC_MAPPING_CLK,
689 						clk_type);
690 	if (clk_id < 0)
691 		return -EINVAL;
692 
693 	switch (clk_id) {
694 	case PPCLK_GFXCLK:
695 		/*
696 		 * CurrClock[clk_id] can provide accurate
697 		 *   output only when the dpm feature is enabled.
698 		 * We can use Average_* for dpm disabled case.
699 		 *   But this is available for gfxclk/uclk/socclk/vclk/dclk.
700 		 */
701 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
702 			member_type = METRICS_CURR_GFXCLK;
703 		else
704 			member_type = METRICS_AVERAGE_GFXCLK;
705 		break;
706 	case PPCLK_UCLK:
707 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
708 			member_type = METRICS_CURR_UCLK;
709 		else
710 			member_type = METRICS_AVERAGE_UCLK;
711 		break;
712 	case PPCLK_SOCCLK:
713 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
714 			member_type = METRICS_CURR_SOCCLK;
715 		else
716 			member_type = METRICS_AVERAGE_SOCCLK;
717 		break;
718 	case PPCLK_VCLK:
719 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
720 			member_type = METRICS_CURR_VCLK;
721 		else
722 			member_type = METRICS_AVERAGE_VCLK;
723 		break;
724 	case PPCLK_DCLK:
725 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
726 			member_type = METRICS_CURR_DCLK;
727 		else
728 			member_type = METRICS_AVERAGE_DCLK;
729 		break;
730 	case PPCLK_FCLK:
731 		member_type = METRICS_CURR_FCLK;
732 		break;
733 	default:
734 		return -EINVAL;
735 	}
736 
737 	return aldebaran_get_smu_metrics_data(smu,
738 					      member_type,
739 					      value);
740 }
741 
aldebaran_print_clk_levels(struct smu_context * smu,enum smu_clk_type type,char * buf)742 static int aldebaran_print_clk_levels(struct smu_context *smu,
743 				      enum smu_clk_type type, char *buf)
744 {
745 	int i, now, size = 0;
746 	int ret = 0;
747 	struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
748 	struct pp_clock_levels_with_latency clocks;
749 	struct smu_13_0_dpm_table *single_dpm_table;
750 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
751 	struct smu_13_0_dpm_context *dpm_context = NULL;
752 	int display_levels;
753 	uint32_t freq_values[3] = {0};
754 	uint32_t min_clk, max_clk;
755 
756 	smu_cmn_get_sysfs_buf(&buf, &size);
757 
758 	if (amdgpu_ras_intr_triggered()) {
759 		size += sysfs_emit_at(buf, size, "unavailable\n");
760 		return size;
761 	}
762 
763 	dpm_context = smu_dpm->dpm_context;
764 
765 	switch (type) {
766 
767 	case SMU_OD_SCLK:
768 		size += sysfs_emit_at(buf, size, "%s:\n", "GFXCLK");
769 		fallthrough;
770 	case SMU_SCLK:
771 		ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now);
772 		if (ret) {
773 			dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!");
774 			return ret;
775 		}
776 
777 		single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
778 		ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
779 		if (ret) {
780 			dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!");
781 			return ret;
782 		}
783 
784 		display_levels = (clocks.num_levels == 1) ? 1 : 2;
785 
786 		min_clk = pstate_table->gfxclk_pstate.curr.min;
787 		max_clk = pstate_table->gfxclk_pstate.curr.max;
788 
789 		freq_values[0] = min_clk;
790 		freq_values[1] = max_clk;
791 
792 		/* fine-grained dpm has only 2 levels */
793 		if (now > min_clk && now < max_clk) {
794 			display_levels++;
795 			freq_values[2] = max_clk;
796 			freq_values[1] = now;
797 		}
798 
799 		for (i = 0; i < display_levels; i++)
800 			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
801 				freq_values[i],
802 				(display_levels == 1) ?
803 					"*" :
804 					(aldebaran_freqs_in_same_level(
805 						 freq_values[i], now) ?
806 						 "*" :
807 						 ""));
808 
809 		break;
810 
811 	case SMU_OD_MCLK:
812 		size += sysfs_emit_at(buf, size, "%s:\n", "MCLK");
813 		fallthrough;
814 	case SMU_MCLK:
815 		ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, &now);
816 		if (ret) {
817 			dev_err(smu->adev->dev, "Attempt to get current mclk Failed!");
818 			return ret;
819 		}
820 
821 		single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
822 		ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
823 		if (ret) {
824 			dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!");
825 			return ret;
826 		}
827 
828 		for (i = 0; i < clocks.num_levels; i++)
829 			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
830 					i, clocks.data[i].clocks_in_khz / 1000,
831 					(clocks.num_levels == 1) ? "*" :
832 					(aldebaran_freqs_in_same_level(
833 								       clocks.data[i].clocks_in_khz / 1000,
834 								       now) ? "*" : ""));
835 		break;
836 
837 	case SMU_SOCCLK:
838 		ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now);
839 		if (ret) {
840 			dev_err(smu->adev->dev, "Attempt to get current socclk Failed!");
841 			return ret;
842 		}
843 
844 		single_dpm_table = &(dpm_context->dpm_tables.soc_table);
845 		ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
846 		if (ret) {
847 			dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!");
848 			return ret;
849 		}
850 
851 		for (i = 0; i < clocks.num_levels; i++)
852 			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
853 					i, clocks.data[i].clocks_in_khz / 1000,
854 					(clocks.num_levels == 1) ? "*" :
855 					(aldebaran_freqs_in_same_level(
856 								       clocks.data[i].clocks_in_khz / 1000,
857 								       now) ? "*" : ""));
858 		break;
859 
860 	case SMU_FCLK:
861 		ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_FCLK, &now);
862 		if (ret) {
863 			dev_err(smu->adev->dev, "Attempt to get current fclk Failed!");
864 			return ret;
865 		}
866 
867 		single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
868 		ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
869 		if (ret) {
870 			dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!");
871 			return ret;
872 		}
873 
874 		for (i = 0; i < single_dpm_table->count; i++)
875 			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
876 					i, single_dpm_table->dpm_levels[i].value,
877 					(clocks.num_levels == 1) ? "*" :
878 					(aldebaran_freqs_in_same_level(
879 								       clocks.data[i].clocks_in_khz / 1000,
880 								       now) ? "*" : ""));
881 		break;
882 
883 	case SMU_VCLK:
884 		ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_VCLK, &now);
885 		if (ret) {
886 			dev_err(smu->adev->dev, "Attempt to get current vclk Failed!");
887 			return ret;
888 		}
889 
890 		single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
891 		ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
892 		if (ret) {
893 			dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!");
894 			return ret;
895 		}
896 
897 		for (i = 0; i < single_dpm_table->count; i++)
898 			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
899 					i, single_dpm_table->dpm_levels[i].value,
900 					(clocks.num_levels == 1) ? "*" :
901 					(aldebaran_freqs_in_same_level(
902 								       clocks.data[i].clocks_in_khz / 1000,
903 								       now) ? "*" : ""));
904 		break;
905 
906 	case SMU_DCLK:
907 		ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_DCLK, &now);
908 		if (ret) {
909 			dev_err(smu->adev->dev, "Attempt to get current dclk Failed!");
910 			return ret;
911 		}
912 
913 		single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
914 		ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
915 		if (ret) {
916 			dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!");
917 			return ret;
918 		}
919 
920 		for (i = 0; i < single_dpm_table->count; i++)
921 			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
922 					i, single_dpm_table->dpm_levels[i].value,
923 					(clocks.num_levels == 1) ? "*" :
924 					(aldebaran_freqs_in_same_level(
925 								       clocks.data[i].clocks_in_khz / 1000,
926 								       now) ? "*" : ""));
927 		break;
928 
929 	default:
930 		break;
931 	}
932 
933 	return size;
934 }
935 
aldebaran_upload_dpm_level(struct smu_context * smu,bool max,uint32_t feature_mask,uint32_t level)936 static int aldebaran_upload_dpm_level(struct smu_context *smu,
937 				      bool max,
938 				      uint32_t feature_mask,
939 				      uint32_t level)
940 {
941 	struct smu_13_0_dpm_context *dpm_context =
942 		smu->smu_dpm.dpm_context;
943 	uint32_t freq;
944 	int ret = 0;
945 
946 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
947 	    (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) {
948 		freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
949 		ret = smu_cmn_send_smc_msg_with_param(smu,
950 						      (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
951 						      (PPCLK_GFXCLK << 16) | (freq & 0xffff),
952 						      NULL);
953 		if (ret) {
954 			dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
955 				max ? "max" : "min");
956 			return ret;
957 		}
958 	}
959 
960 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
961 	    (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) {
962 		freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
963 		ret = smu_cmn_send_smc_msg_with_param(smu,
964 						      (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
965 						      (PPCLK_UCLK << 16) | (freq & 0xffff),
966 						      NULL);
967 		if (ret) {
968 			dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
969 				max ? "max" : "min");
970 			return ret;
971 		}
972 	}
973 
974 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
975 	    (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) {
976 		freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
977 		ret = smu_cmn_send_smc_msg_with_param(smu,
978 						      (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
979 						      (PPCLK_SOCCLK << 16) | (freq & 0xffff),
980 						      NULL);
981 		if (ret) {
982 			dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
983 				max ? "max" : "min");
984 			return ret;
985 		}
986 	}
987 
988 	return ret;
989 }
990 
aldebaran_force_clk_levels(struct smu_context * smu,enum smu_clk_type type,uint32_t mask)991 static int aldebaran_force_clk_levels(struct smu_context *smu,
992 				      enum smu_clk_type type, uint32_t mask)
993 {
994 	struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
995 	struct smu_13_0_dpm_table *single_dpm_table = NULL;
996 	uint32_t soft_min_level, soft_max_level;
997 	int ret = 0;
998 
999 	soft_min_level = mask ? (ffs(mask) - 1) : 0;
1000 	soft_max_level = mask ? (fls(mask) - 1) : 0;
1001 
1002 	switch (type) {
1003 	case SMU_SCLK:
1004 		single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1005 		if (soft_max_level >= single_dpm_table->count) {
1006 			dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
1007 				soft_max_level, single_dpm_table->count - 1);
1008 			ret = -EINVAL;
1009 			break;
1010 		}
1011 
1012 		ret = aldebaran_upload_dpm_level(smu,
1013 						 false,
1014 						 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT),
1015 						 soft_min_level);
1016 		if (ret) {
1017 			dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
1018 			break;
1019 		}
1020 
1021 		ret = aldebaran_upload_dpm_level(smu,
1022 						 true,
1023 						 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT),
1024 						 soft_max_level);
1025 		if (ret)
1026 			dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
1027 
1028 		break;
1029 
1030 	case SMU_MCLK:
1031 	case SMU_SOCCLK:
1032 	case SMU_FCLK:
1033 		/*
1034 		 * Should not arrive here since aldebaran does not
1035 		 * support mclk/socclk/fclk softmin/softmax settings
1036 		 */
1037 		ret = -EINVAL;
1038 		break;
1039 
1040 	default:
1041 		break;
1042 	}
1043 
1044 	return ret;
1045 }
1046 
aldebaran_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)1047 static int aldebaran_get_thermal_temperature_range(struct smu_context *smu,
1048 						   struct smu_temperature_range *range)
1049 {
1050 	struct smu_table_context *table_context = &smu->smu_table;
1051 	struct smu_13_0_powerplay_table *powerplay_table =
1052 		table_context->power_play_table;
1053 	PPTable_t *pptable = smu->smu_table.driver_pptable;
1054 
1055 	if (!range)
1056 		return -EINVAL;
1057 
1058 	memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
1059 
1060 	range->hotspot_crit_max = pptable->ThotspotLimit *
1061 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1062 	range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1063 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1064 	range->mem_crit_max = pptable->TmemLimit *
1065 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1066 	range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
1067 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1068 	range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1069 
1070 	return 0;
1071 }
1072 
aldebaran_get_current_activity_percent(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)1073 static int aldebaran_get_current_activity_percent(struct smu_context *smu,
1074 						  enum amd_pp_sensors sensor,
1075 						  uint32_t *value)
1076 {
1077 	int ret = 0;
1078 
1079 	if (!value)
1080 		return -EINVAL;
1081 
1082 	switch (sensor) {
1083 	case AMDGPU_PP_SENSOR_GPU_LOAD:
1084 		ret = aldebaran_get_smu_metrics_data(smu,
1085 						     METRICS_AVERAGE_GFXACTIVITY,
1086 						     value);
1087 		break;
1088 	case AMDGPU_PP_SENSOR_MEM_LOAD:
1089 		ret = aldebaran_get_smu_metrics_data(smu,
1090 						     METRICS_AVERAGE_MEMACTIVITY,
1091 						     value);
1092 		break;
1093 	default:
1094 		dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
1095 		return -EINVAL;
1096 	}
1097 
1098 	return ret;
1099 }
1100 
aldebaran_thermal_get_temperature(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)1101 static int aldebaran_thermal_get_temperature(struct smu_context *smu,
1102 					     enum amd_pp_sensors sensor,
1103 					     uint32_t *value)
1104 {
1105 	int ret = 0;
1106 
1107 	if (!value)
1108 		return -EINVAL;
1109 
1110 	switch (sensor) {
1111 	case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1112 		ret = aldebaran_get_smu_metrics_data(smu,
1113 						     METRICS_TEMPERATURE_HOTSPOT,
1114 						     value);
1115 		break;
1116 	case AMDGPU_PP_SENSOR_EDGE_TEMP:
1117 		ret = aldebaran_get_smu_metrics_data(smu,
1118 						     METRICS_TEMPERATURE_EDGE,
1119 						     value);
1120 		break;
1121 	case AMDGPU_PP_SENSOR_MEM_TEMP:
1122 		ret = aldebaran_get_smu_metrics_data(smu,
1123 						     METRICS_TEMPERATURE_MEM,
1124 						     value);
1125 		break;
1126 	default:
1127 		dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1128 		return -EINVAL;
1129 	}
1130 
1131 	return ret;
1132 }
1133 
aldebaran_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1134 static int aldebaran_read_sensor(struct smu_context *smu,
1135 				 enum amd_pp_sensors sensor,
1136 				 void *data, uint32_t *size)
1137 {
1138 	int ret = 0;
1139 
1140 	if (amdgpu_ras_intr_triggered())
1141 		return 0;
1142 
1143 	if (!data || !size)
1144 		return -EINVAL;
1145 
1146 	switch (sensor) {
1147 	case AMDGPU_PP_SENSOR_MEM_LOAD:
1148 	case AMDGPU_PP_SENSOR_GPU_LOAD:
1149 		ret = aldebaran_get_current_activity_percent(smu,
1150 							     sensor,
1151 							     (uint32_t *)data);
1152 		*size = 4;
1153 		break;
1154 	case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1155 		ret = aldebaran_get_smu_metrics_data(smu,
1156 						     METRICS_AVERAGE_SOCKETPOWER,
1157 						     (uint32_t *)data);
1158 		*size = 4;
1159 		break;
1160 	case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1161 	case AMDGPU_PP_SENSOR_EDGE_TEMP:
1162 	case AMDGPU_PP_SENSOR_MEM_TEMP:
1163 		ret = aldebaran_thermal_get_temperature(smu, sensor,
1164 							(uint32_t *)data);
1165 		*size = 4;
1166 		break;
1167 	case AMDGPU_PP_SENSOR_GFX_MCLK:
1168 		ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1169 		/* the output clock frequency in 10K unit */
1170 		*(uint32_t *)data *= 100;
1171 		*size = 4;
1172 		break;
1173 	case AMDGPU_PP_SENSOR_GFX_SCLK:
1174 		ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1175 		*(uint32_t *)data *= 100;
1176 		*size = 4;
1177 		break;
1178 	case AMDGPU_PP_SENSOR_VDDGFX:
1179 		ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data);
1180 		*size = 4;
1181 		break;
1182 	case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1183 	default:
1184 		ret = -EOPNOTSUPP;
1185 		break;
1186 	}
1187 
1188 	return ret;
1189 }
1190 
aldebaran_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit)1191 static int aldebaran_get_power_limit(struct smu_context *smu,
1192 				     uint32_t *current_power_limit,
1193 				     uint32_t *default_power_limit,
1194 				     uint32_t *max_power_limit)
1195 {
1196 	PPTable_t *pptable = smu->smu_table.driver_pptable;
1197 	uint32_t power_limit = 0;
1198 	int ret;
1199 
1200 	if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1201 		if (current_power_limit)
1202 			*current_power_limit = 0;
1203 		if (default_power_limit)
1204 			*default_power_limit = 0;
1205 		if (max_power_limit)
1206 			*max_power_limit = 0;
1207 
1208 		dev_warn(smu->adev->dev,
1209 			"PPT feature is not enabled, power values can't be fetched.");
1210 
1211 		return 0;
1212 	}
1213 
1214 	/* Valid power data is available only from primary die.
1215 	 * For secondary die show the value as 0.
1216 	 */
1217 	if (aldebaran_is_primary(smu)) {
1218 		ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit,
1219 					   &power_limit);
1220 
1221 		if (ret) {
1222 			/* the last hope to figure out the ppt limit */
1223 			if (!pptable) {
1224 				dev_err(smu->adev->dev,
1225 					"Cannot get PPT limit due to pptable missing!");
1226 				return -EINVAL;
1227 			}
1228 			power_limit = pptable->PptLimit;
1229 		}
1230 	}
1231 
1232 	if (current_power_limit)
1233 		*current_power_limit = power_limit;
1234 	if (default_power_limit)
1235 		*default_power_limit = power_limit;
1236 
1237 	if (max_power_limit) {
1238 		if (pptable)
1239 			*max_power_limit = pptable->PptLimit;
1240 	}
1241 
1242 	return 0;
1243 }
1244 
aldebaran_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)1245 static int aldebaran_set_power_limit(struct smu_context *smu,
1246 				     enum smu_ppt_limit_type limit_type,
1247 				     uint32_t limit)
1248 {
1249 	/* Power limit can be set only through primary die */
1250 	if (aldebaran_is_primary(smu))
1251 		return smu_v13_0_set_power_limit(smu, limit_type, limit);
1252 
1253 	return -EINVAL;
1254 }
1255 
aldebaran_system_features_control(struct smu_context * smu,bool enable)1256 static int aldebaran_system_features_control(struct  smu_context *smu, bool enable)
1257 {
1258 	int ret;
1259 
1260 	ret = smu_v13_0_system_features_control(smu, enable);
1261 	if (!ret && enable)
1262 		ret = aldebaran_run_btc(smu);
1263 
1264 	return ret;
1265 }
1266 
aldebaran_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1267 static int aldebaran_set_performance_level(struct smu_context *smu,
1268 					   enum amd_dpm_forced_level level)
1269 {
1270 	struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1271 	struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1272 	struct smu_13_0_dpm_table *gfx_table =
1273 		&dpm_context->dpm_tables.gfx_table;
1274 	struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1275 
1276 	/* Disable determinism if switching to another mode */
1277 	if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) &&
1278 	    (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) {
1279 		smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL);
1280 		pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1281 	}
1282 
1283 	switch (level) {
1284 
1285 	case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM:
1286 		return 0;
1287 
1288 	case AMD_DPM_FORCED_LEVEL_HIGH:
1289 	case AMD_DPM_FORCED_LEVEL_LOW:
1290 	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1291 	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1292 	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1293 	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1294 	default:
1295 		break;
1296 	}
1297 
1298 	return smu_v13_0_set_performance_level(smu, level);
1299 }
1300 
aldebaran_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1301 static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu,
1302 					  enum smu_clk_type clk_type,
1303 					  uint32_t min,
1304 					  uint32_t max)
1305 {
1306 	struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1307 	struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1308 	struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1309 	struct amdgpu_device *adev = smu->adev;
1310 	uint32_t min_clk;
1311 	uint32_t max_clk;
1312 	int ret = 0;
1313 
1314 	if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK)
1315 		return -EINVAL;
1316 
1317 	if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1318 			&& (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1319 		return -EINVAL;
1320 
1321 	if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
1322 		if (min >= max) {
1323 			dev_err(smu->adev->dev,
1324 				"Minimum GFX clk should be less than the maximum allowed clock\n");
1325 			return -EINVAL;
1326 		}
1327 
1328 		if ((min == pstate_table->gfxclk_pstate.curr.min) &&
1329 		    (max == pstate_table->gfxclk_pstate.curr.max))
1330 			return 0;
1331 
1332 		ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK,
1333 							    min, max);
1334 		if (!ret) {
1335 			pstate_table->gfxclk_pstate.curr.min = min;
1336 			pstate_table->gfxclk_pstate.curr.max = max;
1337 		}
1338 
1339 		return ret;
1340 	}
1341 
1342 	if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
1343 		if (!max || (max < dpm_context->dpm_tables.gfx_table.min) ||
1344 			(max > dpm_context->dpm_tables.gfx_table.max)) {
1345 			dev_warn(adev->dev,
1346 					"Invalid max frequency %d MHz specified for determinism\n", max);
1347 			return -EINVAL;
1348 		}
1349 
1350 		/* Restore default min/max clocks and enable determinism */
1351 		min_clk = dpm_context->dpm_tables.gfx_table.min;
1352 		max_clk = dpm_context->dpm_tables.gfx_table.max;
1353 		ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1354 		if (!ret) {
1355 			usleep_range(500, 1000);
1356 			ret = smu_cmn_send_smc_msg_with_param(smu,
1357 					SMU_MSG_EnableDeterminism,
1358 					max, NULL);
1359 			if (ret) {
1360 				dev_err(adev->dev,
1361 						"Failed to enable determinism at GFX clock %d MHz\n", max);
1362 			} else {
1363 				pstate_table->gfxclk_pstate.curr.min = min_clk;
1364 				pstate_table->gfxclk_pstate.curr.max = max;
1365 			}
1366 		}
1367 	}
1368 
1369 	return ret;
1370 }
1371 
aldebaran_usr_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)1372 static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
1373 							long input[], uint32_t size)
1374 {
1375 	struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1376 	struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1377 	struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1378 	uint32_t min_clk;
1379 	uint32_t max_clk;
1380 	int ret = 0;
1381 
1382 	/* Only allowed in manual or determinism mode */
1383 	if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1384 			&& (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1385 		return -EINVAL;
1386 
1387 	switch (type) {
1388 	case PP_OD_EDIT_SCLK_VDDC_TABLE:
1389 		if (size != 2) {
1390 			dev_err(smu->adev->dev, "Input parameter number not correct\n");
1391 			return -EINVAL;
1392 		}
1393 
1394 		if (input[0] == 0) {
1395 			if (input[1] < dpm_context->dpm_tables.gfx_table.min) {
1396 				dev_warn(smu->adev->dev, "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n",
1397 					input[1], dpm_context->dpm_tables.gfx_table.min);
1398 				pstate_table->gfxclk_pstate.custom.min =
1399 					pstate_table->gfxclk_pstate.curr.min;
1400 				return -EINVAL;
1401 			}
1402 
1403 			pstate_table->gfxclk_pstate.custom.min = input[1];
1404 		} else if (input[0] == 1) {
1405 			if (input[1] > dpm_context->dpm_tables.gfx_table.max) {
1406 				dev_warn(smu->adev->dev, "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
1407 					input[1], dpm_context->dpm_tables.gfx_table.max);
1408 				pstate_table->gfxclk_pstate.custom.max =
1409 					pstate_table->gfxclk_pstate.curr.max;
1410 				return -EINVAL;
1411 			}
1412 
1413 			pstate_table->gfxclk_pstate.custom.max = input[1];
1414 		} else {
1415 			return -EINVAL;
1416 		}
1417 		break;
1418 	case PP_OD_RESTORE_DEFAULT_TABLE:
1419 		if (size != 0) {
1420 			dev_err(smu->adev->dev, "Input parameter number not correct\n");
1421 			return -EINVAL;
1422 		} else {
1423 			/* Use the default frequencies for manual and determinism mode */
1424 			min_clk = dpm_context->dpm_tables.gfx_table.min;
1425 			max_clk = dpm_context->dpm_tables.gfx_table.max;
1426 
1427 			return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1428 		}
1429 		break;
1430 	case PP_OD_COMMIT_DPM_TABLE:
1431 		if (size != 0) {
1432 			dev_err(smu->adev->dev, "Input parameter number not correct\n");
1433 			return -EINVAL;
1434 		} else {
1435 			if (!pstate_table->gfxclk_pstate.custom.min)
1436 				pstate_table->gfxclk_pstate.custom.min =
1437 					pstate_table->gfxclk_pstate.curr.min;
1438 
1439 			if (!pstate_table->gfxclk_pstate.custom.max)
1440 				pstate_table->gfxclk_pstate.custom.max =
1441 					pstate_table->gfxclk_pstate.curr.max;
1442 
1443 			min_clk = pstate_table->gfxclk_pstate.custom.min;
1444 			max_clk = pstate_table->gfxclk_pstate.custom.max;
1445 
1446 			return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1447 		}
1448 		break;
1449 	default:
1450 		return -ENOSYS;
1451 	}
1452 
1453 	return ret;
1454 }
1455 
aldebaran_is_dpm_running(struct smu_context * smu)1456 static bool aldebaran_is_dpm_running(struct smu_context *smu)
1457 {
1458 	int ret;
1459 	uint64_t feature_enabled;
1460 
1461 	ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
1462 	if (ret)
1463 		return false;
1464 	return !!(feature_enabled & SMC_DPM_FEATURE);
1465 }
1466 
aldebaran_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num_msgs)1467 static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap,
1468 			      struct i2c_msg *msg, int num_msgs)
1469 {
1470 	struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
1471 	struct amdgpu_device *adev = smu_i2c->adev;
1472 	struct smu_context *smu = adev->powerplay.pp_handle;
1473 	struct smu_table_context *smu_table = &smu->smu_table;
1474 	struct smu_table *table = &smu_table->driver_table;
1475 	SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
1476 	int i, j, r, c;
1477 	u16 dir;
1478 
1479 	if (!adev->pm.dpm_enabled)
1480 		return -EBUSY;
1481 
1482 	req = kzalloc(sizeof(*req), GFP_KERNEL);
1483 	if (!req)
1484 		return -ENOMEM;
1485 
1486 	req->I2CcontrollerPort = smu_i2c->port;
1487 	req->I2CSpeed = I2C_SPEED_FAST_400K;
1488 	req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
1489 	dir = msg[0].flags & I2C_M_RD;
1490 
1491 	for (c = i = 0; i < num_msgs; i++) {
1492 		for (j = 0; j < msg[i].len; j++, c++) {
1493 			SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
1494 
1495 			if (!(msg[i].flags & I2C_M_RD)) {
1496 				/* write */
1497 				cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
1498 				cmd->ReadWriteData = msg[i].buf[j];
1499 			}
1500 
1501 			if ((dir ^ msg[i].flags) & I2C_M_RD) {
1502 				/* The direction changes.
1503 				 */
1504 				dir = msg[i].flags & I2C_M_RD;
1505 				cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
1506 			}
1507 
1508 			req->NumCmds++;
1509 
1510 			/*
1511 			 * Insert STOP if we are at the last byte of either last
1512 			 * message for the transaction or the client explicitly
1513 			 * requires a STOP at this particular message.
1514 			 */
1515 			if ((j == msg[i].len - 1) &&
1516 			    ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
1517 				cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
1518 				cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
1519 			}
1520 		}
1521 	}
1522 	mutex_lock(&adev->pm.mutex);
1523 	r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
1524 	if (r)
1525 		goto fail;
1526 
1527 	for (c = i = 0; i < num_msgs; i++) {
1528 		if (!(msg[i].flags & I2C_M_RD)) {
1529 			c += msg[i].len;
1530 			continue;
1531 		}
1532 		for (j = 0; j < msg[i].len; j++, c++) {
1533 			SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
1534 
1535 			msg[i].buf[j] = cmd->ReadWriteData;
1536 		}
1537 	}
1538 	r = num_msgs;
1539 fail:
1540 	mutex_unlock(&adev->pm.mutex);
1541 	kfree(req);
1542 	return r;
1543 }
1544 
aldebaran_i2c_func(struct i2c_adapter * adap)1545 static u32 aldebaran_i2c_func(struct i2c_adapter *adap)
1546 {
1547 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1548 }
1549 
1550 
1551 static const struct i2c_algorithm aldebaran_i2c_algo = {
1552 	.master_xfer = aldebaran_i2c_xfer,
1553 	.functionality = aldebaran_i2c_func,
1554 };
1555 
1556 static const struct i2c_adapter_quirks aldebaran_i2c_control_quirks = {
1557 	.flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
1558 	.max_read_len  = MAX_SW_I2C_COMMANDS,
1559 	.max_write_len = MAX_SW_I2C_COMMANDS,
1560 	.max_comb_1st_msg_len = 2,
1561 	.max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
1562 };
1563 
aldebaran_i2c_control_init(struct smu_context * smu)1564 static int aldebaran_i2c_control_init(struct smu_context *smu)
1565 {
1566 	struct amdgpu_device *adev = smu->adev;
1567 	struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[0];
1568 	struct i2c_adapter *control = &smu_i2c->adapter;
1569 	int res;
1570 
1571 	smu_i2c->adev = adev;
1572 	smu_i2c->port = 0;
1573 	mutex_init(&smu_i2c->mutex);
1574 	control->owner = THIS_MODULE;
1575 	control->class = I2C_CLASS_SPD;
1576 	control->dev.parent = &adev->pdev->dev;
1577 	control->algo = &aldebaran_i2c_algo;
1578 	snprintf(control->name, sizeof(control->name), "AMDGPU SMU 0");
1579 	control->quirks = &aldebaran_i2c_control_quirks;
1580 	i2c_set_adapdata(control, smu_i2c);
1581 
1582 	res = i2c_add_adapter(control);
1583 	if (res) {
1584 		DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
1585 		goto Out_err;
1586 	}
1587 
1588 	adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
1589 	adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
1590 
1591 	return 0;
1592 Out_err:
1593 	i2c_del_adapter(control);
1594 
1595 	return res;
1596 }
1597 
aldebaran_i2c_control_fini(struct smu_context * smu)1598 static void aldebaran_i2c_control_fini(struct smu_context *smu)
1599 {
1600 	struct amdgpu_device *adev = smu->adev;
1601 	int i;
1602 
1603 	for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
1604 		struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
1605 		struct i2c_adapter *control = &smu_i2c->adapter;
1606 
1607 		i2c_del_adapter(control);
1608 	}
1609 	adev->pm.ras_eeprom_i2c_bus = NULL;
1610 	adev->pm.fru_eeprom_i2c_bus = NULL;
1611 }
1612 
aldebaran_get_unique_id(struct smu_context * smu)1613 static void aldebaran_get_unique_id(struct smu_context *smu)
1614 {
1615 	struct amdgpu_device *adev = smu->adev;
1616 	uint32_t upper32 = 0, lower32 = 0;
1617 
1618 	if (aldebaran_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32))
1619 		goto out;
1620 	if (aldebaran_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32))
1621 		goto out;
1622 
1623 out:
1624 	adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1625 	if (adev->serial[0] == '\0')
1626 		sprintf(adev->serial, "%016llx", adev->unique_id);
1627 }
1628 
aldebaran_is_baco_supported(struct smu_context * smu)1629 static bool aldebaran_is_baco_supported(struct smu_context *smu)
1630 {
1631 	/* aldebaran is not support baco */
1632 
1633 	return false;
1634 }
1635 
aldebaran_set_df_cstate(struct smu_context * smu,enum pp_df_cstate state)1636 static int aldebaran_set_df_cstate(struct smu_context *smu,
1637 				   enum pp_df_cstate state)
1638 {
1639 	struct amdgpu_device *adev = smu->adev;
1640 
1641 	/*
1642 	 * Aldebaran does not need the cstate disablement
1643 	 * prerequisite for gpu reset.
1644 	 */
1645 	if (amdgpu_in_reset(adev) || adev->in_suspend)
1646 		return 0;
1647 
1648 	return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
1649 }
1650 
aldebaran_allow_xgmi_power_down(struct smu_context * smu,bool en)1651 static int aldebaran_allow_xgmi_power_down(struct smu_context *smu, bool en)
1652 {
1653 	struct amdgpu_device *adev = smu->adev;
1654 
1655 	/* The message only works on master die and NACK will be sent
1656 	   back for other dies, only send it on master die */
1657 	if (!adev->smuio.funcs->get_socket_id(adev) &&
1658 	    !adev->smuio.funcs->get_die_id(adev))
1659 		return smu_cmn_send_smc_msg_with_param(smu,
1660 				   SMU_MSG_GmiPwrDnControl,
1661 				   en ? 0 : 1,
1662 				   NULL);
1663 	else
1664 		return 0;
1665 }
1666 
1667 static const struct throttling_logging_label {
1668 	uint32_t feature_mask;
1669 	const char *label;
1670 } logging_label[] = {
1671 	{(1U << THROTTLER_TEMP_GPU_BIT), "GPU"},
1672 	{(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
1673 	{(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
1674 	{(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
1675 	{(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
1676 };
aldebaran_log_thermal_throttling_event(struct smu_context * smu)1677 static void aldebaran_log_thermal_throttling_event(struct smu_context *smu)
1678 {
1679 	int ret;
1680 	int throttler_idx, throtting_events = 0, buf_idx = 0;
1681 	struct amdgpu_device *adev = smu->adev;
1682 	uint32_t throttler_status;
1683 	char log_buf[256];
1684 
1685 	ret = aldebaran_get_smu_metrics_data(smu,
1686 					     METRICS_THROTTLER_STATUS,
1687 					     &throttler_status);
1688 	if (ret)
1689 		return;
1690 
1691 	memset(log_buf, 0, sizeof(log_buf));
1692 	for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
1693 	     throttler_idx++) {
1694 		if (throttler_status & logging_label[throttler_idx].feature_mask) {
1695 			throtting_events++;
1696 			buf_idx += snprintf(log_buf + buf_idx,
1697 					    sizeof(log_buf) - buf_idx,
1698 					    "%s%s",
1699 					    throtting_events > 1 ? " and " : "",
1700 					    logging_label[throttler_idx].label);
1701 			if (buf_idx >= sizeof(log_buf)) {
1702 				dev_err(adev->dev, "buffer overflow!\n");
1703 				log_buf[sizeof(log_buf) - 1] = '\0';
1704 				break;
1705 			}
1706 		}
1707 	}
1708 
1709 	dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
1710 		 log_buf);
1711 	kgd2kfd_smi_event_throttle(smu->adev->kfd.dev,
1712 		smu_cmn_get_indep_throttler_status(throttler_status,
1713 						   aldebaran_throttler_map));
1714 }
1715 
aldebaran_get_current_pcie_link_speed(struct smu_context * smu)1716 static int aldebaran_get_current_pcie_link_speed(struct smu_context *smu)
1717 {
1718 	struct amdgpu_device *adev = smu->adev;
1719 	uint32_t esm_ctrl;
1720 
1721 	/* TODO: confirm this on real target */
1722 	esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
1723 	if ((esm_ctrl >> 15) & 0x1)
1724 		return (((esm_ctrl >> 8) & 0x7F) + 128);
1725 
1726 	return smu_v13_0_get_current_pcie_link_speed(smu);
1727 }
1728 
aldebaran_get_gpu_metrics(struct smu_context * smu,void ** table)1729 static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu,
1730 					 void **table)
1731 {
1732 	struct smu_table_context *smu_table = &smu->smu_table;
1733 	struct gpu_metrics_v1_3 *gpu_metrics =
1734 		(struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
1735 	SmuMetrics_t metrics;
1736 	int i, ret = 0;
1737 
1738 	ret = smu_cmn_get_metrics_table(smu,
1739 					&metrics,
1740 					true);
1741 	if (ret)
1742 		return ret;
1743 
1744 	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
1745 
1746 	gpu_metrics->temperature_edge = metrics.TemperatureEdge;
1747 	gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
1748 	gpu_metrics->temperature_mem = metrics.TemperatureHBM;
1749 	gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
1750 	gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
1751 	gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
1752 
1753 	gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
1754 	gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
1755 	gpu_metrics->average_mm_activity = 0;
1756 
1757 	/* Valid power data is available only from primary die */
1758 	if (aldebaran_is_primary(smu)) {
1759 		gpu_metrics->average_socket_power = metrics.AverageSocketPower;
1760 		gpu_metrics->energy_accumulator =
1761 			(uint64_t)metrics.EnergyAcc64bitHigh << 32 |
1762 			metrics.EnergyAcc64bitLow;
1763 	} else {
1764 		gpu_metrics->average_socket_power = 0;
1765 		gpu_metrics->energy_accumulator = 0;
1766 	}
1767 
1768 	gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
1769 	gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
1770 	gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
1771 	gpu_metrics->average_vclk0_frequency = 0;
1772 	gpu_metrics->average_dclk0_frequency = 0;
1773 
1774 	gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
1775 	gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
1776 	gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
1777 	gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
1778 	gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
1779 
1780 	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1781 	gpu_metrics->indep_throttle_status =
1782 			smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1783 							   aldebaran_throttler_map);
1784 
1785 	gpu_metrics->current_fan_speed = 0;
1786 
1787 	gpu_metrics->pcie_link_width =
1788 		smu_v13_0_get_current_pcie_link_width(smu);
1789 	gpu_metrics->pcie_link_speed =
1790 		aldebaran_get_current_pcie_link_speed(smu);
1791 
1792 	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1793 
1794 	gpu_metrics->gfx_activity_acc = metrics.GfxBusyAcc;
1795 	gpu_metrics->mem_activity_acc = metrics.DramBusyAcc;
1796 
1797 	for (i = 0; i < NUM_HBM_INSTANCES; i++)
1798 		gpu_metrics->temperature_hbm[i] = metrics.TemperatureAllHBM[i];
1799 
1800 	gpu_metrics->firmware_timestamp = ((uint64_t)metrics.TimeStampHigh << 32) |
1801 					metrics.TimeStampLow;
1802 
1803 	*table = (void *)gpu_metrics;
1804 
1805 	return sizeof(struct gpu_metrics_v1_3);
1806 }
1807 
aldebaran_check_ecc_table_support(struct smu_context * smu,int * ecctable_version)1808 static int aldebaran_check_ecc_table_support(struct smu_context *smu,
1809 		int *ecctable_version)
1810 {
1811 	uint32_t if_version = 0xff, smu_version = 0xff;
1812 	int ret = 0;
1813 
1814 	ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
1815 	if (ret) {
1816 		/* return not support if failed get smu_version */
1817 		ret = -EOPNOTSUPP;
1818 	}
1819 
1820 	if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION)
1821 		ret = -EOPNOTSUPP;
1822 	else if (smu_version >= SUPPORT_ECCTABLE_SMU_VERSION &&
1823 			smu_version < SUPPORT_ECCTABLE_V2_SMU_VERSION)
1824 		*ecctable_version = 1;
1825 	else
1826 		*ecctable_version = 2;
1827 
1828 	return ret;
1829 }
1830 
aldebaran_get_ecc_info(struct smu_context * smu,void * table)1831 static ssize_t aldebaran_get_ecc_info(struct smu_context *smu,
1832 					 void *table)
1833 {
1834 	struct smu_table_context *smu_table = &smu->smu_table;
1835 	EccInfoTable_t *ecc_table = NULL;
1836 	struct ecc_info_per_ch *ecc_info_per_channel = NULL;
1837 	int i, ret = 0;
1838 	int table_version = 0;
1839 	struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
1840 
1841 	ret = aldebaran_check_ecc_table_support(smu, &table_version);
1842 	if (ret)
1843 		return ret;
1844 
1845 	ret = smu_cmn_update_table(smu,
1846 			       SMU_TABLE_ECCINFO,
1847 			       0,
1848 			       smu_table->ecc_table,
1849 			       false);
1850 	if (ret) {
1851 		dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n");
1852 		return ret;
1853 	}
1854 
1855 	ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
1856 
1857 	if (table_version == 1) {
1858 		for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) {
1859 			ecc_info_per_channel = &(eccinfo->ecc[i]);
1860 			ecc_info_per_channel->ce_count_lo_chip =
1861 				ecc_table->EccInfo[i].ce_count_lo_chip;
1862 			ecc_info_per_channel->ce_count_hi_chip =
1863 				ecc_table->EccInfo[i].ce_count_hi_chip;
1864 			ecc_info_per_channel->mca_umc_status =
1865 				ecc_table->EccInfo[i].mca_umc_status;
1866 			ecc_info_per_channel->mca_umc_addr =
1867 				ecc_table->EccInfo[i].mca_umc_addr;
1868 		}
1869 	} else if (table_version == 2) {
1870 		for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) {
1871 			ecc_info_per_channel = &(eccinfo->ecc[i]);
1872 			ecc_info_per_channel->ce_count_lo_chip =
1873 				ecc_table->EccInfo_V2[i].ce_count_lo_chip;
1874 			ecc_info_per_channel->ce_count_hi_chip =
1875 				ecc_table->EccInfo_V2[i].ce_count_hi_chip;
1876 			ecc_info_per_channel->mca_umc_status =
1877 				ecc_table->EccInfo_V2[i].mca_umc_status;
1878 			ecc_info_per_channel->mca_umc_addr =
1879 				ecc_table->EccInfo_V2[i].mca_umc_addr;
1880 			ecc_info_per_channel->mca_ceumc_addr =
1881 				ecc_table->EccInfo_V2[i].mca_ceumc_addr;
1882 		}
1883 		eccinfo->record_ce_addr_supported = 1;
1884 	}
1885 
1886 	return ret;
1887 }
1888 
aldebaran_mode1_reset(struct smu_context * smu)1889 static int aldebaran_mode1_reset(struct smu_context *smu)
1890 {
1891 	u32 smu_version, fatal_err, param;
1892 	int ret = 0;
1893 	struct amdgpu_device *adev = smu->adev;
1894 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1895 
1896 	fatal_err = 0;
1897 	param = SMU_RESET_MODE_1;
1898 
1899 	/*
1900 	* PM FW support SMU_MSG_GfxDeviceDriverReset from 68.07
1901 	*/
1902 	smu_cmn_get_smc_version(smu, NULL, &smu_version);
1903 	if (smu_version < 0x00440700) {
1904 		ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1905 	} else {
1906 		/* fatal error triggered by ras, PMFW supports the flag
1907 		   from 68.44.0 */
1908 		if ((smu_version >= 0x00442c00) && ras &&
1909 		    atomic_read(&ras->in_recovery))
1910 			fatal_err = 1;
1911 
1912 		param |= (fatal_err << 16);
1913 		ret = smu_cmn_send_smc_msg_with_param(smu,
1914 					SMU_MSG_GfxDeviceDriverReset, param, NULL);
1915 	}
1916 
1917 	if (!ret)
1918 		msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
1919 
1920 	return ret;
1921 }
1922 
aldebaran_mode2_reset(struct smu_context * smu)1923 static int aldebaran_mode2_reset(struct smu_context *smu)
1924 {
1925 	u32 smu_version;
1926 	int ret = 0, index;
1927 	struct amdgpu_device *adev = smu->adev;
1928 	int timeout = 10;
1929 
1930 	smu_cmn_get_smc_version(smu, NULL, &smu_version);
1931 
1932 	index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
1933 						SMU_MSG_GfxDeviceDriverReset);
1934 	if (index < 0 )
1935 		return -EINVAL;
1936 	mutex_lock(&smu->message_lock);
1937 	if (smu_version >= 0x00441400) {
1938 		ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2);
1939 		/* This is similar to FLR, wait till max FLR timeout */
1940 		msleep(100);
1941 		dev_dbg(smu->adev->dev, "restore config space...\n");
1942 		/* Restore the config space saved during init */
1943 		amdgpu_device_load_pci_state(adev->pdev);
1944 
1945 		dev_dbg(smu->adev->dev, "wait for reset ack\n");
1946 		while (ret == -ETIME && timeout)  {
1947 			ret = smu_cmn_wait_for_response(smu);
1948 			/* Wait a bit more time for getting ACK */
1949 			if (ret == -ETIME) {
1950 				--timeout;
1951 				usleep_range(500, 1000);
1952 				continue;
1953 			}
1954 
1955 			if (ret != 1) {
1956 				dev_err(adev->dev, "failed to send mode2 message \tparam: 0x%08x response %#x\n",
1957 						SMU_RESET_MODE_2, ret);
1958 				goto out;
1959 			}
1960 		}
1961 
1962 	} else {
1963 		dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n",
1964 				smu_version);
1965 	}
1966 
1967 	if (ret == 1)
1968 		ret = 0;
1969 out:
1970 	mutex_unlock(&smu->message_lock);
1971 
1972 	return ret;
1973 }
1974 
aldebaran_smu_handle_passthrough_sbr(struct smu_context * smu,bool enable)1975 static int aldebaran_smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)
1976 {
1977 	int ret = 0;
1978 	ret =  smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_HeavySBR, enable ? 1 : 0, NULL);
1979 
1980 	return ret;
1981 }
1982 
aldebaran_is_mode1_reset_supported(struct smu_context * smu)1983 static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu)
1984 {
1985 #if 0
1986 	struct amdgpu_device *adev = smu->adev;
1987 	u32 smu_version;
1988 	uint32_t val;
1989 	/**
1990 	 * PM FW version support mode1 reset from 68.07
1991 	 */
1992 	smu_cmn_get_smc_version(smu, NULL, &smu_version);
1993 	if ((smu_version < 0x00440700))
1994 		return false;
1995 	/**
1996 	 * mode1 reset relies on PSP, so we should check if
1997 	 * PSP is alive.
1998 	 */
1999 	val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
2000 
2001 	return val != 0x0;
2002 #endif
2003 	return true;
2004 }
2005 
aldebaran_is_mode2_reset_supported(struct smu_context * smu)2006 static bool aldebaran_is_mode2_reset_supported(struct smu_context *smu)
2007 {
2008 	return true;
2009 }
2010 
aldebaran_set_mp1_state(struct smu_context * smu,enum pp_mp1_state mp1_state)2011 static int aldebaran_set_mp1_state(struct smu_context *smu,
2012 				   enum pp_mp1_state mp1_state)
2013 {
2014 	switch (mp1_state) {
2015 	case PP_MP1_STATE_UNLOAD:
2016 		return smu_cmn_set_mp1_state(smu, mp1_state);
2017 	default:
2018 		return 0;
2019 	}
2020 }
2021 
aldebaran_smu_send_hbm_bad_page_num(struct smu_context * smu,uint32_t size)2022 static int aldebaran_smu_send_hbm_bad_page_num(struct smu_context *smu,
2023 		uint32_t size)
2024 {
2025 	int ret = 0;
2026 
2027 	/* message SMU to update the bad page number on SMUBUS */
2028 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL);
2029 	if (ret)
2030 		dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad pages number\n",
2031 				__func__);
2032 
2033 	return ret;
2034 }
2035 
aldebaran_check_bad_channel_info_support(struct smu_context * smu)2036 static int aldebaran_check_bad_channel_info_support(struct smu_context *smu)
2037 {
2038 	uint32_t if_version = 0xff, smu_version = 0xff;
2039 	int ret = 0;
2040 
2041 	ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
2042 	if (ret) {
2043 		/* return not support if failed get smu_version */
2044 		ret = -EOPNOTSUPP;
2045 	}
2046 
2047 	if (smu_version < SUPPORT_BAD_CHANNEL_INFO_MSG_VERSION)
2048 		ret = -EOPNOTSUPP;
2049 
2050 	return ret;
2051 }
2052 
aldebaran_send_hbm_bad_channel_flag(struct smu_context * smu,uint32_t size)2053 static int aldebaran_send_hbm_bad_channel_flag(struct smu_context *smu,
2054 		uint32_t size)
2055 {
2056 	int ret = 0;
2057 
2058 	ret = aldebaran_check_bad_channel_info_support(smu);
2059 	if (ret)
2060 		return ret;
2061 
2062 	/* message SMU to update the bad channel info on SMUBUS */
2063 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetBadHBMPagesRetiredFlagsPerChannel, size, NULL);
2064 	if (ret)
2065 		dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad channel info\n",
2066 				__func__);
2067 
2068 	return ret;
2069 }
2070 
2071 static const struct pptable_funcs aldebaran_ppt_funcs = {
2072 	/* init dpm */
2073 	.get_allowed_feature_mask = aldebaran_get_allowed_feature_mask,
2074 	/* dpm/clk tables */
2075 	.set_default_dpm_table = aldebaran_set_default_dpm_table,
2076 	.populate_umd_state_clk = aldebaran_populate_umd_state_clk,
2077 	.get_thermal_temperature_range = aldebaran_get_thermal_temperature_range,
2078 	.print_clk_levels = aldebaran_print_clk_levels,
2079 	.force_clk_levels = aldebaran_force_clk_levels,
2080 	.read_sensor = aldebaran_read_sensor,
2081 	.set_performance_level = aldebaran_set_performance_level,
2082 	.get_power_limit = aldebaran_get_power_limit,
2083 	.is_dpm_running = aldebaran_is_dpm_running,
2084 	.get_unique_id = aldebaran_get_unique_id,
2085 	.init_microcode = smu_v13_0_init_microcode,
2086 	.load_microcode = smu_v13_0_load_microcode,
2087 	.fini_microcode = smu_v13_0_fini_microcode,
2088 	.init_smc_tables = aldebaran_init_smc_tables,
2089 	.fini_smc_tables = smu_v13_0_fini_smc_tables,
2090 	.init_power = smu_v13_0_init_power,
2091 	.fini_power = smu_v13_0_fini_power,
2092 	.check_fw_status = smu_v13_0_check_fw_status,
2093 	/* pptable related */
2094 	.setup_pptable = aldebaran_setup_pptable,
2095 	.get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
2096 	.check_fw_version = smu_v13_0_check_fw_version,
2097 	.write_pptable = smu_cmn_write_pptable,
2098 	.set_driver_table_location = smu_v13_0_set_driver_table_location,
2099 	.set_tool_table_location = smu_v13_0_set_tool_table_location,
2100 	.notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
2101 	.system_features_control = aldebaran_system_features_control,
2102 	.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2103 	.send_smc_msg = smu_cmn_send_smc_msg,
2104 	.get_enabled_mask = smu_cmn_get_enabled_mask,
2105 	.feature_is_enabled = smu_cmn_feature_is_enabled,
2106 	.disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2107 	.set_power_limit = aldebaran_set_power_limit,
2108 	.init_max_sustainable_clocks = smu_v13_0_init_max_sustainable_clocks,
2109 	.enable_thermal_alert = smu_v13_0_enable_thermal_alert,
2110 	.disable_thermal_alert = smu_v13_0_disable_thermal_alert,
2111 	.set_xgmi_pstate = smu_v13_0_set_xgmi_pstate,
2112 	.register_irq_handler = smu_v13_0_register_irq_handler,
2113 	.set_azalia_d3_pme = smu_v13_0_set_azalia_d3_pme,
2114 	.get_max_sustainable_clocks_by_dc = smu_v13_0_get_max_sustainable_clocks_by_dc,
2115 	.baco_is_support = aldebaran_is_baco_supported,
2116 	.get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq,
2117 	.set_soft_freq_limited_range = aldebaran_set_soft_freq_limited_range,
2118 	.od_edit_dpm_table = aldebaran_usr_edit_dpm_table,
2119 	.set_df_cstate = aldebaran_set_df_cstate,
2120 	.allow_xgmi_power_down = aldebaran_allow_xgmi_power_down,
2121 	.log_thermal_throttling_event = aldebaran_log_thermal_throttling_event,
2122 	.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2123 	.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2124 	.get_gpu_metrics = aldebaran_get_gpu_metrics,
2125 	.mode1_reset_is_support = aldebaran_is_mode1_reset_supported,
2126 	.mode2_reset_is_support = aldebaran_is_mode2_reset_supported,
2127 	.smu_handle_passthrough_sbr = aldebaran_smu_handle_passthrough_sbr,
2128 	.mode1_reset = aldebaran_mode1_reset,
2129 	.set_mp1_state = aldebaran_set_mp1_state,
2130 	.mode2_reset = aldebaran_mode2_reset,
2131 	.wait_for_event = smu_v13_0_wait_for_event,
2132 	.i2c_init = aldebaran_i2c_control_init,
2133 	.i2c_fini = aldebaran_i2c_control_fini,
2134 	.send_hbm_bad_pages_num = aldebaran_smu_send_hbm_bad_page_num,
2135 	.get_ecc_info = aldebaran_get_ecc_info,
2136 	.send_hbm_bad_channel_flag = aldebaran_send_hbm_bad_channel_flag,
2137 };
2138 
aldebaran_set_ppt_funcs(struct smu_context * smu)2139 void aldebaran_set_ppt_funcs(struct smu_context *smu)
2140 {
2141 	smu->ppt_funcs = &aldebaran_ppt_funcs;
2142 	smu->message_map = aldebaran_message_map;
2143 	smu->clock_map = aldebaran_clk_map;
2144 	smu->feature_map = aldebaran_feature_mask_map;
2145 	smu->table_map = aldebaran_table_map;
2146 	smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
2147 	smu_v13_0_set_smu_mailbox_registers(smu);
2148 }
2149