1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * ahci.c - AHCI SATA support
4 *
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
13 *
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/dmi.h>
28 #include <linux/gfp.h>
29 #include <scsi/scsi_host.h>
30 #include <scsi/scsi_cmnd.h>
31 #include <linux/libata.h>
32 #include <linux/ahci-remap.h>
33 #include <linux/io-64-nonatomic-lo-hi.h>
34 #include "ahci.h"
35
36 #define DRV_NAME "ahci"
37 #define DRV_VERSION "3.0"
38
39 enum {
40 AHCI_PCI_BAR_STA2X11 = 0,
41 AHCI_PCI_BAR_CAVIUM = 0,
42 AHCI_PCI_BAR_LOONGSON = 0,
43 AHCI_PCI_BAR_ENMOTUS = 2,
44 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
45 AHCI_PCI_BAR_STANDARD = 5,
46 };
47
48 enum board_ids {
49 /* board IDs by feature in alphabetical order */
50 board_ahci,
51 board_ahci_43bit_dma,
52 board_ahci_ign_iferr,
53 board_ahci_low_power,
54 board_ahci_no_debounce_delay,
55 board_ahci_nomsi,
56 board_ahci_noncq,
57 board_ahci_nosntf,
58 board_ahci_yes_fbs,
59
60 /* board IDs for specific chipsets in alphabetical order */
61 board_ahci_al,
62 board_ahci_avn,
63 board_ahci_mcp65,
64 board_ahci_mcp77,
65 board_ahci_mcp89,
66 board_ahci_mv,
67 board_ahci_sb600,
68 board_ahci_sb700, /* for SB700 and SB800 */
69 board_ahci_vt8251,
70
71 /*
72 * board IDs for Intel chipsets that support more than 6 ports
73 * *and* end up needing the PCS quirk.
74 */
75 board_ahci_pcs7,
76
77 /* aliases */
78 board_ahci_mcp_linux = board_ahci_mcp65,
79 board_ahci_mcp67 = board_ahci_mcp65,
80 board_ahci_mcp73 = board_ahci_mcp65,
81 board_ahci_mcp79 = board_ahci_mcp77,
82 };
83
84 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
85 static void ahci_remove_one(struct pci_dev *dev);
86 static void ahci_shutdown_one(struct pci_dev *dev);
87 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv);
88 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
91 unsigned long deadline);
92 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
93 static bool is_mcp89_apple(struct pci_dev *pdev);
94 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
95 unsigned long deadline);
96 #ifdef CONFIG_PM
97 static int ahci_pci_device_runtime_suspend(struct device *dev);
98 static int ahci_pci_device_runtime_resume(struct device *dev);
99 #ifdef CONFIG_PM_SLEEP
100 static int ahci_pci_device_suspend(struct device *dev);
101 static int ahci_pci_device_resume(struct device *dev);
102 #endif
103 #endif /* CONFIG_PM */
104
105 static const struct scsi_host_template ahci_sht = {
106 AHCI_SHT("ahci"),
107 };
108
109 static struct ata_port_operations ahci_vt8251_ops = {
110 .inherits = &ahci_ops,
111 .hardreset = ahci_vt8251_hardreset,
112 };
113
114 static struct ata_port_operations ahci_p5wdh_ops = {
115 .inherits = &ahci_ops,
116 .hardreset = ahci_p5wdh_hardreset,
117 };
118
119 static struct ata_port_operations ahci_avn_ops = {
120 .inherits = &ahci_ops,
121 .hardreset = ahci_avn_hardreset,
122 };
123
124 static const struct ata_port_info ahci_port_info[] = {
125 /* by features */
126 [board_ahci] = {
127 .flags = AHCI_FLAG_COMMON,
128 .pio_mask = ATA_PIO4,
129 .udma_mask = ATA_UDMA6,
130 .port_ops = &ahci_ops,
131 },
132 [board_ahci_43bit_dma] = {
133 AHCI_HFLAGS (AHCI_HFLAG_43BIT_ONLY),
134 .flags = AHCI_FLAG_COMMON,
135 .pio_mask = ATA_PIO4,
136 .udma_mask = ATA_UDMA6,
137 .port_ops = &ahci_ops,
138 },
139 [board_ahci_ign_iferr] = {
140 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
141 .flags = AHCI_FLAG_COMMON,
142 .pio_mask = ATA_PIO4,
143 .udma_mask = ATA_UDMA6,
144 .port_ops = &ahci_ops,
145 },
146 [board_ahci_low_power] = {
147 AHCI_HFLAGS (AHCI_HFLAG_USE_LPM_POLICY),
148 .flags = AHCI_FLAG_COMMON,
149 .pio_mask = ATA_PIO4,
150 .udma_mask = ATA_UDMA6,
151 .port_ops = &ahci_ops,
152 },
153 [board_ahci_no_debounce_delay] = {
154 .flags = AHCI_FLAG_COMMON,
155 .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY,
156 .pio_mask = ATA_PIO4,
157 .udma_mask = ATA_UDMA6,
158 .port_ops = &ahci_ops,
159 },
160 [board_ahci_nomsi] = {
161 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
162 .flags = AHCI_FLAG_COMMON,
163 .pio_mask = ATA_PIO4,
164 .udma_mask = ATA_UDMA6,
165 .port_ops = &ahci_ops,
166 },
167 [board_ahci_noncq] = {
168 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
169 .flags = AHCI_FLAG_COMMON,
170 .pio_mask = ATA_PIO4,
171 .udma_mask = ATA_UDMA6,
172 .port_ops = &ahci_ops,
173 },
174 [board_ahci_nosntf] = {
175 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
176 .flags = AHCI_FLAG_COMMON,
177 .pio_mask = ATA_PIO4,
178 .udma_mask = ATA_UDMA6,
179 .port_ops = &ahci_ops,
180 },
181 [board_ahci_yes_fbs] = {
182 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
183 .flags = AHCI_FLAG_COMMON,
184 .pio_mask = ATA_PIO4,
185 .udma_mask = ATA_UDMA6,
186 .port_ops = &ahci_ops,
187 },
188 /* by chipsets */
189 [board_ahci_al] = {
190 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
191 .flags = AHCI_FLAG_COMMON,
192 .pio_mask = ATA_PIO4,
193 .udma_mask = ATA_UDMA6,
194 .port_ops = &ahci_ops,
195 },
196 [board_ahci_avn] = {
197 .flags = AHCI_FLAG_COMMON,
198 .pio_mask = ATA_PIO4,
199 .udma_mask = ATA_UDMA6,
200 .port_ops = &ahci_avn_ops,
201 },
202 [board_ahci_mcp65] = {
203 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
204 AHCI_HFLAG_YES_NCQ),
205 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
206 .pio_mask = ATA_PIO4,
207 .udma_mask = ATA_UDMA6,
208 .port_ops = &ahci_ops,
209 },
210 [board_ahci_mcp77] = {
211 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
212 .flags = AHCI_FLAG_COMMON,
213 .pio_mask = ATA_PIO4,
214 .udma_mask = ATA_UDMA6,
215 .port_ops = &ahci_ops,
216 },
217 [board_ahci_mcp89] = {
218 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
219 .flags = AHCI_FLAG_COMMON,
220 .pio_mask = ATA_PIO4,
221 .udma_mask = ATA_UDMA6,
222 .port_ops = &ahci_ops,
223 },
224 [board_ahci_mv] = {
225 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
226 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
227 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
228 .pio_mask = ATA_PIO4,
229 .udma_mask = ATA_UDMA6,
230 .port_ops = &ahci_ops,
231 },
232 [board_ahci_sb600] = {
233 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
234 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
235 AHCI_HFLAG_32BIT_ONLY),
236 .flags = AHCI_FLAG_COMMON,
237 .pio_mask = ATA_PIO4,
238 .udma_mask = ATA_UDMA6,
239 .port_ops = &ahci_pmp_retry_srst_ops,
240 },
241 [board_ahci_sb700] = { /* for SB700 and SB800 */
242 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
243 .flags = AHCI_FLAG_COMMON,
244 .pio_mask = ATA_PIO4,
245 .udma_mask = ATA_UDMA6,
246 .port_ops = &ahci_pmp_retry_srst_ops,
247 },
248 [board_ahci_vt8251] = {
249 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
250 .flags = AHCI_FLAG_COMMON,
251 .pio_mask = ATA_PIO4,
252 .udma_mask = ATA_UDMA6,
253 .port_ops = &ahci_vt8251_ops,
254 },
255 [board_ahci_pcs7] = {
256 .flags = AHCI_FLAG_COMMON,
257 .pio_mask = ATA_PIO4,
258 .udma_mask = ATA_UDMA6,
259 .port_ops = &ahci_ops,
260 },
261 };
262
263 static const struct pci_device_id ahci_pci_tbl[] = {
264 /* Intel */
265 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
266 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
267 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
268 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
269 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
270 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
271 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
272 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
273 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
274 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
275 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
276 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
277 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8/Lewisburg RAID*/
278 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
279 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
280 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
281 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
282 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
283 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
284 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
285 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
286 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_low_power }, /* ICH9M */
287 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_low_power }, /* ICH9M */
288 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_low_power }, /* ICH9M */
289 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_low_power }, /* ICH9M */
290 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_low_power }, /* ICH9M */
291 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
292 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_low_power }, /* ICH9M */
293 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
294 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
295 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
296 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
297 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
298 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
299 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
300 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
301 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
302 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_low_power }, /* PCH M AHCI */
303 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
304 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_low_power }, /* PCH M RAID */
305 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
306 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
307 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
308 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
309 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
310 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
311 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
312 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
313 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
314 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
315 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
316 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
317 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
318 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
319 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
320 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
321 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
322 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
323 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
324 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
325 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
326 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
327 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_low_power }, /* CPT M AHCI */
328 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
329 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_low_power }, /* CPT M RAID */
330 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
331 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
332 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
333 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
334 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
335 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
336 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
337 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_low_power }, /* Panther M AHCI */
338 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
339 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
340 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
341 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_low_power }, /* Panther M RAID */
342 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
343 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
344 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_low_power }, /* Lynx M AHCI */
345 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
346 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_low_power }, /* Lynx M RAID */
347 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
348 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_low_power }, /* Lynx M RAID */
349 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
350 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_low_power }, /* Lynx M RAID */
351 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_low_power }, /* Lynx LP AHCI */
352 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_low_power }, /* Lynx LP AHCI */
353 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_low_power }, /* Lynx LP RAID */
354 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_low_power }, /* Lynx LP RAID */
355 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_low_power }, /* Lynx LP RAID */
356 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_low_power }, /* Lynx LP RAID */
357 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_low_power }, /* Lynx LP RAID */
358 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_low_power }, /* Lynx LP RAID */
359 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_low_power }, /* Cannon Lake PCH-LP AHCI */
360 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
361 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
362 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
363 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
364 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
365 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
366 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
367 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
368 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
369 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
370 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
371 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
372 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
373 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
374 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
375 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
376 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg/Lewisburg AHCI*/
377 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* *burg SATA0 'RAID' */
378 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* *burg SATA1 'RAID' */
379 { PCI_VDEVICE(INTEL, 0x282f), board_ahci }, /* *burg SATA2 'RAID' */
380 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */
381 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */
382 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */
383 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */
384 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
385 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
386 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
387 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
388 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
389 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
390 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
391 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
392 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
393 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_low_power }, /* Wildcat LP AHCI */
394 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_low_power }, /* Wildcat LP RAID */
395 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_low_power }, /* Wildcat LP RAID */
396 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_low_power }, /* Wildcat LP RAID */
397 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
398 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_low_power }, /* 9 Series M AHCI */
399 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
400 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_low_power }, /* 9 Series M RAID */
401 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
402 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_low_power }, /* 9 Series M RAID */
403 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
404 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_low_power }, /* 9 Series M RAID */
405 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_low_power }, /* Sunrise LP AHCI */
406 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_low_power }, /* Sunrise LP RAID */
407 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_low_power }, /* Sunrise LP RAID */
408 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
409 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_low_power }, /* Sunrise M AHCI */
410 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
411 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
412 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_low_power }, /* Sunrise M RAID */
413 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
414 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
415 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
416 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
417 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
418 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
419 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
420 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
421 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
422 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
423 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
424 { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
425 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_low_power }, /* Bay Trail AHCI */
426 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_low_power }, /* Bay Trail AHCI */
427 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_low_power }, /* Cherry Tr. AHCI */
428 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_low_power }, /* ApolloLake AHCI */
429 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_low_power }, /* Ice Lake LP AHCI */
430 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_low_power }, /* Comet Lake PCH-U AHCI */
431 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power }, /* Comet Lake PCH RAID */
432 /* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */
433 { PCI_VDEVICE(INTEL, 0x4b63), board_ahci_low_power }, /* Elkhart Lake AHCI */
434
435 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
436 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
437 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
438 /* JMicron 362B and 362C have an AHCI function with IDE class code */
439 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
440 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
441 /* May need to update quirk_jmicron_async_suspend() for additions */
442
443 /* ATI */
444 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
445 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
446 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
447 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
448 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
449 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
450 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
451
452 /* Amazon's Annapurna Labs support */
453 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
454 .class = PCI_CLASS_STORAGE_SATA_AHCI,
455 .class_mask = 0xffffff,
456 board_ahci_al },
457 /* AMD */
458 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
459 { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */
460 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
461 { PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power }, /* AMD Green Sardine */
462 /* AMD is using RAID class only for ahci controllers */
463 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
464 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
465
466 /* Dell S140/S150 */
467 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID,
468 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
469
470 /* VIA */
471 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
472 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
473
474 /* NVIDIA */
475 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
476 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
477 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
478 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
479 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
480 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
481 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
482 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
483 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
484 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
485 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
486 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
487 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
488 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
489 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
490 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
491 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
492 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
493 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
494 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
495 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
496 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
497 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
498 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
499 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
500 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
501 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
502 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
503 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
504 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
505 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
506 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
507 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
508 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
509 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
510 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
511 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
512 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
513 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
514 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
515 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
516 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
517 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
518 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
519 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
520 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
521 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
522 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
523 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
524 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
525 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
526 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
527 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
528 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
529 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
530 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
531 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
532 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
533 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
534 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
535 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
536 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
537 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
538 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
539 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
540 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
541 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
542 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
543 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
544 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
545 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
546 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
547 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
548 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
549 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
550 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
551 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
552 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
553 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
554 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
555 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
556 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
557 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
558 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
559
560 /* SiS */
561 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
562 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
563 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
564
565 /* ST Microelectronics */
566 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
567
568 /* Marvell */
569 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
570 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
571 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
572 .class = PCI_CLASS_STORAGE_SATA_AHCI,
573 .class_mask = 0xffffff,
574 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
575 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
576 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
577 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
578 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
579 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
580 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
581 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
582 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
583 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
584 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
585 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
586 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
587 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
588 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
589 .driver_data = board_ahci_yes_fbs },
590 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
591 .driver_data = board_ahci_yes_fbs },
592 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
593 .driver_data = board_ahci_yes_fbs },
594 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9215),
595 .driver_data = board_ahci_yes_fbs },
596 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
597 .driver_data = board_ahci_yes_fbs },
598 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9235),
599 .driver_data = board_ahci_no_debounce_delay },
600 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
601 .driver_data = board_ahci_yes_fbs },
602 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
603 .driver_data = board_ahci_yes_fbs },
604
605 /* Promise */
606 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
607 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
608
609 /* ASMedia */
610 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci_43bit_dma }, /* ASM1060 */
611 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci_43bit_dma }, /* ASM1060 */
612 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci_43bit_dma }, /* ASM1061 */
613 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci_43bit_dma }, /* ASM1061/1062 */
614 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci_43bit_dma }, /* ASM1061R */
615 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci_43bit_dma }, /* ASM1062R */
616 { PCI_VDEVICE(ASMEDIA, 0x0624), board_ahci_43bit_dma }, /* ASM1062+JMB575 */
617 { PCI_VDEVICE(ASMEDIA, 0x1062), board_ahci }, /* ASM1062A */
618 { PCI_VDEVICE(ASMEDIA, 0x1064), board_ahci }, /* ASM1064 */
619 { PCI_VDEVICE(ASMEDIA, 0x1164), board_ahci }, /* ASM1164 */
620 { PCI_VDEVICE(ASMEDIA, 0x1165), board_ahci }, /* ASM1165 */
621 { PCI_VDEVICE(ASMEDIA, 0x1166), board_ahci }, /* ASM1166 */
622
623 /*
624 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
625 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
626 */
627 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
628 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
629
630 /* Enmotus */
631 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
632
633 /* Loongson */
634 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
635
636 /* Generic, PCI class code for AHCI */
637 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
638 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
639
640 { } /* terminate list */
641 };
642
643 static const struct dev_pm_ops ahci_pci_pm_ops = {
644 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
645 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
646 ahci_pci_device_runtime_resume, NULL)
647 };
648
649 static struct pci_driver ahci_pci_driver = {
650 .name = DRV_NAME,
651 .id_table = ahci_pci_tbl,
652 .probe = ahci_init_one,
653 .remove = ahci_remove_one,
654 .shutdown = ahci_shutdown_one,
655 .driver = {
656 .pm = &ahci_pci_pm_ops,
657 },
658 };
659
660 #if IS_ENABLED(CONFIG_PATA_MARVELL)
661 static int marvell_enable;
662 #else
663 static int marvell_enable = 1;
664 #endif
665 module_param(marvell_enable, int, 0644);
666 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
667
668 static int mobile_lpm_policy = -1;
669 module_param(mobile_lpm_policy, int, 0644);
670 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
671
672 static char *ahci_mask_port_map;
673 module_param_named(mask_port_map, ahci_mask_port_map, charp, 0444);
674 MODULE_PARM_DESC(mask_port_map,
675 "32-bits port map masks to ignore controllers ports. "
676 "Valid values are: "
677 "\"<mask>\" to apply the same mask to all AHCI controller "
678 "devices, and \"<pci_dev>=<mask>,<pci_dev>=<mask>,...\" to "
679 "specify different masks for the controllers specified, "
680 "where <pci_dev> is the PCI ID of an AHCI controller in the "
681 "form \"domain:bus:dev.func\"");
682
ahci_apply_port_map_mask(struct device * dev,struct ahci_host_priv * hpriv,char * mask_s)683 static void ahci_apply_port_map_mask(struct device *dev,
684 struct ahci_host_priv *hpriv, char *mask_s)
685 {
686 unsigned int mask;
687
688 if (kstrtouint(mask_s, 0, &mask)) {
689 dev_err(dev, "Invalid port map mask\n");
690 return;
691 }
692
693 hpriv->mask_port_map = mask;
694 }
695
ahci_get_port_map_mask(struct device * dev,struct ahci_host_priv * hpriv)696 static void ahci_get_port_map_mask(struct device *dev,
697 struct ahci_host_priv *hpriv)
698 {
699 char *param, *end, *str, *mask_s;
700 char *name;
701
702 if (!strlen(ahci_mask_port_map))
703 return;
704
705 str = kstrdup(ahci_mask_port_map, GFP_KERNEL);
706 if (!str)
707 return;
708
709 /* Handle single mask case */
710 if (!strchr(str, '=')) {
711 ahci_apply_port_map_mask(dev, hpriv, str);
712 goto free;
713 }
714
715 /*
716 * Mask list case: parse the parameter to apply the mask only if
717 * the device name matches.
718 */
719 param = str;
720 end = param + strlen(param);
721 while (param && param < end && *param) {
722 name = param;
723 param = strchr(name, '=');
724 if (!param)
725 break;
726
727 *param = '\0';
728 param++;
729 if (param >= end)
730 break;
731
732 if (strcmp(dev_name(dev), name) != 0) {
733 param = strchr(param, ',');
734 if (param)
735 param++;
736 continue;
737 }
738
739 mask_s = param;
740 param = strchr(mask_s, ',');
741 if (param) {
742 *param = '\0';
743 param++;
744 }
745
746 ahci_apply_port_map_mask(dev, hpriv, mask_s);
747 }
748
749 free:
750 kfree(str);
751 }
752
ahci_pci_save_initial_config(struct pci_dev * pdev,struct ahci_host_priv * hpriv)753 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
754 struct ahci_host_priv *hpriv)
755 {
756 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
757 dev_info(&pdev->dev, "JMB361 has only one port\n");
758 hpriv->saved_port_map = 1;
759 }
760
761 /*
762 * Temporary Marvell 6145 hack: PATA port presence
763 * is asserted through the standard AHCI port
764 * presence register, as bit 4 (counting from 0)
765 */
766 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
767 if (pdev->device == 0x6121)
768 hpriv->mask_port_map = 0x3;
769 else
770 hpriv->mask_port_map = 0xf;
771 dev_info(&pdev->dev,
772 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
773 }
774
775 /* Handle port map masks passed as module parameter. */
776 if (ahci_mask_port_map)
777 ahci_get_port_map_mask(&pdev->dev, hpriv);
778
779 ahci_save_initial_config(&pdev->dev, hpriv);
780 }
781
ahci_pci_reset_controller(struct ata_host * host)782 static int ahci_pci_reset_controller(struct ata_host *host)
783 {
784 struct pci_dev *pdev = to_pci_dev(host->dev);
785 struct ahci_host_priv *hpriv = host->private_data;
786 int rc;
787
788 rc = ahci_reset_controller(host);
789 if (rc)
790 return rc;
791
792 /*
793 * If platform firmware failed to enable ports, try to enable
794 * them here.
795 */
796 ahci_intel_pcs_quirk(pdev, hpriv);
797
798 return 0;
799 }
800
ahci_pci_init_controller(struct ata_host * host)801 static void ahci_pci_init_controller(struct ata_host *host)
802 {
803 struct ahci_host_priv *hpriv = host->private_data;
804 struct pci_dev *pdev = to_pci_dev(host->dev);
805 void __iomem *port_mmio;
806 u32 tmp;
807 int mv;
808
809 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
810 if (pdev->device == 0x6121)
811 mv = 2;
812 else
813 mv = 4;
814 port_mmio = __ahci_port_base(hpriv, mv);
815
816 writel(0, port_mmio + PORT_IRQ_MASK);
817
818 /* clear port IRQ */
819 tmp = readl(port_mmio + PORT_IRQ_STAT);
820 dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
821 if (tmp)
822 writel(tmp, port_mmio + PORT_IRQ_STAT);
823 }
824
825 ahci_init_controller(host);
826 }
827
ahci_vt8251_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)828 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
829 unsigned long deadline)
830 {
831 struct ata_port *ap = link->ap;
832 struct ahci_host_priv *hpriv = ap->host->private_data;
833 bool online;
834 int rc;
835
836 hpriv->stop_engine(ap);
837
838 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
839 deadline, &online, NULL);
840
841 hpriv->start_engine(ap);
842
843 /* vt8251 doesn't clear BSY on signature FIS reception,
844 * request follow-up softreset.
845 */
846 return online ? -EAGAIN : rc;
847 }
848
ahci_p5wdh_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)849 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
850 unsigned long deadline)
851 {
852 struct ata_port *ap = link->ap;
853 struct ahci_port_priv *pp = ap->private_data;
854 struct ahci_host_priv *hpriv = ap->host->private_data;
855 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
856 struct ata_taskfile tf;
857 bool online;
858 int rc;
859
860 hpriv->stop_engine(ap);
861
862 /* clear D2H reception area to properly wait for D2H FIS */
863 ata_tf_init(link->device, &tf);
864 tf.status = ATA_BUSY;
865 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
866
867 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
868 deadline, &online, NULL);
869
870 hpriv->start_engine(ap);
871
872 /* The pseudo configuration device on SIMG4726 attached to
873 * ASUS P5W-DH Deluxe doesn't send signature FIS after
874 * hardreset if no device is attached to the first downstream
875 * port && the pseudo device locks up on SRST w/ PMP==0. To
876 * work around this, wait for !BSY only briefly. If BSY isn't
877 * cleared, perform CLO and proceed to IDENTIFY (achieved by
878 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
879 *
880 * Wait for two seconds. Devices attached to downstream port
881 * which can't process the following IDENTIFY after this will
882 * have to be reset again. For most cases, this should
883 * suffice while making probing snappish enough.
884 */
885 if (online) {
886 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
887 ahci_check_ready);
888 if (rc)
889 ahci_kick_engine(ap);
890 }
891 return rc;
892 }
893
894 /*
895 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
896 *
897 * It has been observed with some SSDs that the timing of events in the
898 * link synchronization phase can leave the port in a state that can not
899 * be recovered by a SATA-hard-reset alone. The failing signature is
900 * SStatus.DET stuck at 1 ("Device presence detected but Phy
901 * communication not established"). It was found that unloading and
902 * reloading the driver when this problem occurs allows the drive
903 * connection to be recovered (DET advanced to 0x3). The critical
904 * component of reloading the driver is that the port state machines are
905 * reset by bouncing "port enable" in the AHCI PCS configuration
906 * register. So, reproduce that effect by bouncing a port whenever we
907 * see DET==1 after a reset.
908 */
ahci_avn_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)909 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
910 unsigned long deadline)
911 {
912 const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context);
913 struct ata_port *ap = link->ap;
914 struct ahci_port_priv *pp = ap->private_data;
915 struct ahci_host_priv *hpriv = ap->host->private_data;
916 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
917 unsigned long tmo = deadline - jiffies;
918 struct ata_taskfile tf;
919 bool online;
920 int rc, i;
921
922 hpriv->stop_engine(ap);
923
924 for (i = 0; i < 2; i++) {
925 u16 val;
926 u32 sstatus;
927 int port = ap->port_no;
928 struct ata_host *host = ap->host;
929 struct pci_dev *pdev = to_pci_dev(host->dev);
930
931 /* clear D2H reception area to properly wait for D2H FIS */
932 ata_tf_init(link->device, &tf);
933 tf.status = ATA_BUSY;
934 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
935
936 rc = sata_link_hardreset(link, timing, deadline, &online,
937 ahci_check_ready);
938
939 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
940 (sstatus & 0xf) != 1)
941 break;
942
943 ata_link_info(link, "avn bounce port%d\n", port);
944
945 pci_read_config_word(pdev, 0x92, &val);
946 val &= ~(1 << port);
947 pci_write_config_word(pdev, 0x92, val);
948 ata_msleep(ap, 1000);
949 val |= 1 << port;
950 pci_write_config_word(pdev, 0x92, val);
951 deadline += tmo;
952 }
953
954 hpriv->start_engine(ap);
955
956 if (online)
957 *class = ahci_dev_classify(ap);
958
959 return rc;
960 }
961
962
963 #ifdef CONFIG_PM
ahci_pci_disable_interrupts(struct ata_host * host)964 static void ahci_pci_disable_interrupts(struct ata_host *host)
965 {
966 struct ahci_host_priv *hpriv = host->private_data;
967 void __iomem *mmio = hpriv->mmio;
968 u32 ctl;
969
970 /* AHCI spec rev1.1 section 8.3.3:
971 * Software must disable interrupts prior to requesting a
972 * transition of the HBA to D3 state.
973 */
974 ctl = readl(mmio + HOST_CTL);
975 ctl &= ~HOST_IRQ_EN;
976 writel(ctl, mmio + HOST_CTL);
977 readl(mmio + HOST_CTL); /* flush */
978 }
979
ahci_pci_device_runtime_suspend(struct device * dev)980 static int ahci_pci_device_runtime_suspend(struct device *dev)
981 {
982 struct pci_dev *pdev = to_pci_dev(dev);
983 struct ata_host *host = pci_get_drvdata(pdev);
984
985 ahci_pci_disable_interrupts(host);
986 return 0;
987 }
988
ahci_pci_device_runtime_resume(struct device * dev)989 static int ahci_pci_device_runtime_resume(struct device *dev)
990 {
991 struct pci_dev *pdev = to_pci_dev(dev);
992 struct ata_host *host = pci_get_drvdata(pdev);
993 int rc;
994
995 rc = ahci_pci_reset_controller(host);
996 if (rc)
997 return rc;
998 ahci_pci_init_controller(host);
999 return 0;
1000 }
1001
1002 #ifdef CONFIG_PM_SLEEP
ahci_pci_device_suspend(struct device * dev)1003 static int ahci_pci_device_suspend(struct device *dev)
1004 {
1005 struct pci_dev *pdev = to_pci_dev(dev);
1006 struct ata_host *host = pci_get_drvdata(pdev);
1007 struct ahci_host_priv *hpriv = host->private_data;
1008
1009 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
1010 dev_err(&pdev->dev,
1011 "BIOS update required for suspend/resume\n");
1012 return -EIO;
1013 }
1014
1015 ahci_pci_disable_interrupts(host);
1016 ata_host_suspend(host, PMSG_SUSPEND);
1017 return 0;
1018 }
1019
ahci_pci_device_resume(struct device * dev)1020 static int ahci_pci_device_resume(struct device *dev)
1021 {
1022 struct pci_dev *pdev = to_pci_dev(dev);
1023 struct ata_host *host = pci_get_drvdata(pdev);
1024 int rc;
1025
1026 /* Apple BIOS helpfully mangles the registers on resume */
1027 if (is_mcp89_apple(pdev))
1028 ahci_mcp89_apple_enable(pdev);
1029
1030 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1031 rc = ahci_pci_reset_controller(host);
1032 if (rc)
1033 return rc;
1034
1035 ahci_pci_init_controller(host);
1036 }
1037
1038 ata_host_resume(host);
1039
1040 return 0;
1041 }
1042 #endif
1043
1044 #endif /* CONFIG_PM */
1045
ahci_configure_dma_masks(struct pci_dev * pdev,struct ahci_host_priv * hpriv)1046 static int ahci_configure_dma_masks(struct pci_dev *pdev,
1047 struct ahci_host_priv *hpriv)
1048 {
1049 int dma_bits;
1050 int rc;
1051
1052 if (hpriv->cap & HOST_CAP_64) {
1053 dma_bits = 64;
1054 if (hpriv->flags & AHCI_HFLAG_43BIT_ONLY)
1055 dma_bits = 43;
1056 } else {
1057 dma_bits = 32;
1058 }
1059
1060 /*
1061 * If the device fixup already set the dma_mask to some non-standard
1062 * value, don't extend it here. This happens on STA2X11, for example.
1063 *
1064 * XXX: manipulating the DMA mask from platform code is completely
1065 * bogus, platform code should use dev->bus_dma_limit instead..
1066 */
1067 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
1068 return 0;
1069
1070 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
1071 if (rc)
1072 dev_err(&pdev->dev, "DMA enable failed\n");
1073 return rc;
1074 }
1075
ahci_pci_print_info(struct ata_host * host)1076 static void ahci_pci_print_info(struct ata_host *host)
1077 {
1078 struct pci_dev *pdev = to_pci_dev(host->dev);
1079 u16 cc;
1080 const char *scc_s;
1081
1082 pci_read_config_word(pdev, 0x0a, &cc);
1083 if (cc == PCI_CLASS_STORAGE_IDE)
1084 scc_s = "IDE";
1085 else if (cc == PCI_CLASS_STORAGE_SATA)
1086 scc_s = "SATA";
1087 else if (cc == PCI_CLASS_STORAGE_RAID)
1088 scc_s = "RAID";
1089 else
1090 scc_s = "unknown";
1091
1092 ahci_print_info(host, scc_s);
1093 }
1094
1095 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
1096 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
1097 * support PMP and the 4726 either directly exports the device
1098 * attached to the first downstream port or acts as a hardware storage
1099 * controller and emulate a single ATA device (can be RAID 0/1 or some
1100 * other configuration).
1101 *
1102 * When there's no device attached to the first downstream port of the
1103 * 4726, "Config Disk" appears, which is a pseudo ATA device to
1104 * configure the 4726. However, ATA emulation of the device is very
1105 * lame. It doesn't send signature D2H Reg FIS after the initial
1106 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
1107 *
1108 * The following function works around the problem by always using
1109 * hardreset on the port and not depending on receiving signature FIS
1110 * afterward. If signature FIS isn't received soon, ATA class is
1111 * assumed without follow-up softreset.
1112 */
ahci_p5wdh_workaround(struct ata_host * host)1113 static void ahci_p5wdh_workaround(struct ata_host *host)
1114 {
1115 static const struct dmi_system_id sysids[] = {
1116 {
1117 .ident = "P5W DH Deluxe",
1118 .matches = {
1119 DMI_MATCH(DMI_SYS_VENDOR,
1120 "ASUSTEK COMPUTER INC"),
1121 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
1122 },
1123 },
1124 { }
1125 };
1126 struct pci_dev *pdev = to_pci_dev(host->dev);
1127
1128 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
1129 dmi_check_system(sysids)) {
1130 struct ata_port *ap = host->ports[1];
1131
1132 dev_info(&pdev->dev,
1133 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1134
1135 ap->ops = &ahci_p5wdh_ops;
1136 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1137 }
1138 }
1139
1140 /*
1141 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1142 * booting in BIOS compatibility mode. We restore the registers but not ID.
1143 */
ahci_mcp89_apple_enable(struct pci_dev * pdev)1144 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1145 {
1146 u32 val;
1147
1148 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1149
1150 pci_read_config_dword(pdev, 0xf8, &val);
1151 val |= 1 << 0x1b;
1152 /* the following changes the device ID, but appears not to affect function */
1153 /* val = (val & ~0xf0000000) | 0x80000000; */
1154 pci_write_config_dword(pdev, 0xf8, val);
1155
1156 pci_read_config_dword(pdev, 0x54c, &val);
1157 val |= 1 << 0xc;
1158 pci_write_config_dword(pdev, 0x54c, val);
1159
1160 pci_read_config_dword(pdev, 0x4a4, &val);
1161 val &= 0xff;
1162 val |= 0x01060100;
1163 pci_write_config_dword(pdev, 0x4a4, val);
1164
1165 pci_read_config_dword(pdev, 0x54c, &val);
1166 val &= ~(1 << 0xc);
1167 pci_write_config_dword(pdev, 0x54c, val);
1168
1169 pci_read_config_dword(pdev, 0xf8, &val);
1170 val &= ~(1 << 0x1b);
1171 pci_write_config_dword(pdev, 0xf8, val);
1172 }
1173
is_mcp89_apple(struct pci_dev * pdev)1174 static bool is_mcp89_apple(struct pci_dev *pdev)
1175 {
1176 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1177 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1178 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1179 pdev->subsystem_device == 0xcb89;
1180 }
1181
1182 /* only some SB600 ahci controllers can do 64bit DMA */
ahci_sb600_enable_64bit(struct pci_dev * pdev)1183 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1184 {
1185 static const struct dmi_system_id sysids[] = {
1186 /*
1187 * The oldest version known to be broken is 0901 and
1188 * working is 1501 which was released on 2007-10-26.
1189 * Enable 64bit DMA on 1501 and anything newer.
1190 *
1191 * Please read bko#9412 for more info.
1192 */
1193 {
1194 .ident = "ASUS M2A-VM",
1195 .matches = {
1196 DMI_MATCH(DMI_BOARD_VENDOR,
1197 "ASUSTeK Computer INC."),
1198 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1199 },
1200 .driver_data = "20071026", /* yyyymmdd */
1201 },
1202 /*
1203 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1204 * support 64bit DMA.
1205 *
1206 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1207 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1208 * This spelling mistake was fixed in BIOS version 1.5, so
1209 * 1.5 and later have the Manufacturer as
1210 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1211 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1212 *
1213 * BIOS versions earlier than 1.9 had a Board Product Name
1214 * DMI field of "MS-7376". This was changed to be
1215 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1216 * match on DMI_BOARD_NAME of "MS-7376".
1217 */
1218 {
1219 .ident = "MSI K9A2 Platinum",
1220 .matches = {
1221 DMI_MATCH(DMI_BOARD_VENDOR,
1222 "MICRO-STAR INTER"),
1223 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1224 },
1225 },
1226 /*
1227 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1228 * 64bit DMA.
1229 *
1230 * This board also had the typo mentioned above in the
1231 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1232 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1233 */
1234 {
1235 .ident = "MSI K9AGM2",
1236 .matches = {
1237 DMI_MATCH(DMI_BOARD_VENDOR,
1238 "MICRO-STAR INTER"),
1239 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1240 },
1241 },
1242 /*
1243 * All BIOS versions for the Asus M3A support 64bit DMA.
1244 * (all release versions from 0301 to 1206 were tested)
1245 */
1246 {
1247 .ident = "ASUS M3A",
1248 .matches = {
1249 DMI_MATCH(DMI_BOARD_VENDOR,
1250 "ASUSTeK Computer INC."),
1251 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1252 },
1253 },
1254 { }
1255 };
1256 const struct dmi_system_id *match;
1257 int year, month, date;
1258 char buf[9];
1259
1260 match = dmi_first_match(sysids);
1261 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1262 !match)
1263 return false;
1264
1265 if (!match->driver_data)
1266 goto enable_64bit;
1267
1268 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1269 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1270
1271 if (strcmp(buf, match->driver_data) >= 0)
1272 goto enable_64bit;
1273 else {
1274 dev_warn(&pdev->dev,
1275 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1276 match->ident);
1277 return false;
1278 }
1279
1280 enable_64bit:
1281 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1282 return true;
1283 }
1284
ahci_broken_system_poweroff(struct pci_dev * pdev)1285 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1286 {
1287 static const struct dmi_system_id broken_systems[] = {
1288 {
1289 .ident = "HP Compaq nx6310",
1290 .matches = {
1291 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1292 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1293 },
1294 /* PCI slot number of the controller */
1295 .driver_data = (void *)0x1FUL,
1296 },
1297 {
1298 .ident = "HP Compaq 6720s",
1299 .matches = {
1300 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1301 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1302 },
1303 /* PCI slot number of the controller */
1304 .driver_data = (void *)0x1FUL,
1305 },
1306
1307 { } /* terminate list */
1308 };
1309 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1310
1311 if (dmi) {
1312 unsigned long slot = (unsigned long)dmi->driver_data;
1313 /* apply the quirk only to on-board controllers */
1314 return slot == PCI_SLOT(pdev->devfn);
1315 }
1316
1317 return false;
1318 }
1319
ahci_broken_suspend(struct pci_dev * pdev)1320 static bool ahci_broken_suspend(struct pci_dev *pdev)
1321 {
1322 static const struct dmi_system_id sysids[] = {
1323 /*
1324 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1325 * to the harddisk doesn't become online after
1326 * resuming from STR. Warn and fail suspend.
1327 *
1328 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1329 *
1330 * Use dates instead of versions to match as HP is
1331 * apparently recycling both product and version
1332 * strings.
1333 *
1334 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1335 */
1336 {
1337 .ident = "dv4",
1338 .matches = {
1339 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1340 DMI_MATCH(DMI_PRODUCT_NAME,
1341 "HP Pavilion dv4 Notebook PC"),
1342 },
1343 .driver_data = "20090105", /* F.30 */
1344 },
1345 {
1346 .ident = "dv5",
1347 .matches = {
1348 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1349 DMI_MATCH(DMI_PRODUCT_NAME,
1350 "HP Pavilion dv5 Notebook PC"),
1351 },
1352 .driver_data = "20090506", /* F.16 */
1353 },
1354 {
1355 .ident = "dv6",
1356 .matches = {
1357 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1358 DMI_MATCH(DMI_PRODUCT_NAME,
1359 "HP Pavilion dv6 Notebook PC"),
1360 },
1361 .driver_data = "20090423", /* F.21 */
1362 },
1363 {
1364 .ident = "HDX18",
1365 .matches = {
1366 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1367 DMI_MATCH(DMI_PRODUCT_NAME,
1368 "HP HDX18 Notebook PC"),
1369 },
1370 .driver_data = "20090430", /* F.23 */
1371 },
1372 /*
1373 * Acer eMachines G725 has the same problem. BIOS
1374 * V1.03 is known to be broken. V3.04 is known to
1375 * work. Between, there are V1.06, V2.06 and V3.03
1376 * that we don't have much idea about. For now,
1377 * blacklist anything older than V3.04.
1378 *
1379 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1380 */
1381 {
1382 .ident = "G725",
1383 .matches = {
1384 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1385 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1386 },
1387 .driver_data = "20091216", /* V3.04 */
1388 },
1389 { } /* terminate list */
1390 };
1391 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1392 int year, month, date;
1393 char buf[9];
1394
1395 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1396 return false;
1397
1398 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1399 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1400
1401 return strcmp(buf, dmi->driver_data) < 0;
1402 }
1403
ahci_broken_lpm(struct pci_dev * pdev)1404 static bool ahci_broken_lpm(struct pci_dev *pdev)
1405 {
1406 static const struct dmi_system_id sysids[] = {
1407 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1408 {
1409 .matches = {
1410 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1411 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1412 },
1413 .driver_data = "20180406", /* 1.31 */
1414 },
1415 {
1416 .matches = {
1417 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1418 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1419 },
1420 .driver_data = "20180420", /* 1.28 */
1421 },
1422 {
1423 .matches = {
1424 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1425 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1426 },
1427 .driver_data = "20180315", /* 1.33 */
1428 },
1429 {
1430 .matches = {
1431 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1432 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1433 },
1434 /*
1435 * Note date based on release notes, 2.35 has been
1436 * reported to be good, but I've been unable to get
1437 * a hold of the reporter to get the DMI BIOS date.
1438 * TODO: fix this.
1439 */
1440 .driver_data = "20180310", /* 2.35 */
1441 },
1442 { } /* terminate list */
1443 };
1444 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1445 int year, month, date;
1446 char buf[9];
1447
1448 if (!dmi)
1449 return false;
1450
1451 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1452 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1453
1454 return strcmp(buf, dmi->driver_data) < 0;
1455 }
1456
ahci_broken_online(struct pci_dev * pdev)1457 static bool ahci_broken_online(struct pci_dev *pdev)
1458 {
1459 #define ENCODE_BUSDEVFN(bus, slot, func) \
1460 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1461 static const struct dmi_system_id sysids[] = {
1462 /*
1463 * There are several gigabyte boards which use
1464 * SIMG5723s configured as hardware RAID. Certain
1465 * 5723 firmware revisions shipped there keep the link
1466 * online but fail to answer properly to SRST or
1467 * IDENTIFY when no device is attached downstream
1468 * causing libata to retry quite a few times leading
1469 * to excessive detection delay.
1470 *
1471 * As these firmwares respond to the second reset try
1472 * with invalid device signature, considering unknown
1473 * sig as offline works around the problem acceptably.
1474 */
1475 {
1476 .ident = "EP45-DQ6",
1477 .matches = {
1478 DMI_MATCH(DMI_BOARD_VENDOR,
1479 "Gigabyte Technology Co., Ltd."),
1480 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1481 },
1482 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1483 },
1484 {
1485 .ident = "EP45-DS5",
1486 .matches = {
1487 DMI_MATCH(DMI_BOARD_VENDOR,
1488 "Gigabyte Technology Co., Ltd."),
1489 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1490 },
1491 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1492 },
1493 { } /* terminate list */
1494 };
1495 #undef ENCODE_BUSDEVFN
1496 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1497 unsigned int val;
1498
1499 if (!dmi)
1500 return false;
1501
1502 val = (unsigned long)dmi->driver_data;
1503
1504 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1505 }
1506
ahci_broken_devslp(struct pci_dev * pdev)1507 static bool ahci_broken_devslp(struct pci_dev *pdev)
1508 {
1509 /* device with broken DEVSLP but still showing SDS capability */
1510 static const struct pci_device_id ids[] = {
1511 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1512 {}
1513 };
1514
1515 return pci_match_id(ids, pdev);
1516 }
1517
1518 #ifdef CONFIG_ATA_ACPI
ahci_gtf_filter_workaround(struct ata_host * host)1519 static void ahci_gtf_filter_workaround(struct ata_host *host)
1520 {
1521 static const struct dmi_system_id sysids[] = {
1522 /*
1523 * Aspire 3810T issues a bunch of SATA enable commands
1524 * via _GTF including an invalid one and one which is
1525 * rejected by the device. Among the successful ones
1526 * is FPDMA non-zero offset enable which when enabled
1527 * only on the drive side leads to NCQ command
1528 * failures. Filter it out.
1529 */
1530 {
1531 .ident = "Aspire 3810T",
1532 .matches = {
1533 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1534 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1535 },
1536 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1537 },
1538 { }
1539 };
1540 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1541 unsigned int filter;
1542 int i;
1543
1544 if (!dmi)
1545 return;
1546
1547 filter = (unsigned long)dmi->driver_data;
1548 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1549 filter, dmi->ident);
1550
1551 for (i = 0; i < host->n_ports; i++) {
1552 struct ata_port *ap = host->ports[i];
1553 struct ata_link *link;
1554 struct ata_device *dev;
1555
1556 ata_for_each_link(link, ap, EDGE)
1557 ata_for_each_dev(dev, link, ALL)
1558 dev->gtf_filter |= filter;
1559 }
1560 }
1561 #else
ahci_gtf_filter_workaround(struct ata_host * host)1562 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1563 {}
1564 #endif
1565
1566 /*
1567 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1568 * as DUMMY, or detected but eventually get a "link down" and never get up
1569 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1570 * port_map may hold a value of 0x00.
1571 *
1572 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1573 * and can significantly reduce the occurrence of the problem.
1574 *
1575 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1576 */
acer_sa5_271_workaround(struct ahci_host_priv * hpriv,struct pci_dev * pdev)1577 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1578 struct pci_dev *pdev)
1579 {
1580 static const struct dmi_system_id sysids[] = {
1581 {
1582 .ident = "Acer Switch Alpha 12",
1583 .matches = {
1584 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1585 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1586 },
1587 },
1588 { }
1589 };
1590
1591 if (dmi_check_system(sysids)) {
1592 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1593 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1594 hpriv->port_map = 0x7;
1595 hpriv->cap = 0xC734FF02;
1596 }
1597 }
1598 }
1599
1600 #ifdef CONFIG_ARM64
1601 /*
1602 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1603 * Workaround is to make sure all pending IRQs are served before leaving
1604 * handler.
1605 */
ahci_thunderx_irq_handler(int irq,void * dev_instance)1606 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1607 {
1608 struct ata_host *host = dev_instance;
1609 struct ahci_host_priv *hpriv;
1610 unsigned int rc = 0;
1611 void __iomem *mmio;
1612 u32 irq_stat, irq_masked;
1613 unsigned int handled = 1;
1614
1615 hpriv = host->private_data;
1616 mmio = hpriv->mmio;
1617 irq_stat = readl(mmio + HOST_IRQ_STAT);
1618 if (!irq_stat)
1619 return IRQ_NONE;
1620
1621 do {
1622 irq_masked = irq_stat & hpriv->port_map;
1623 spin_lock(&host->lock);
1624 rc = ahci_handle_port_intr(host, irq_masked);
1625 if (!rc)
1626 handled = 0;
1627 writel(irq_stat, mmio + HOST_IRQ_STAT);
1628 irq_stat = readl(mmio + HOST_IRQ_STAT);
1629 spin_unlock(&host->lock);
1630 } while (irq_stat);
1631
1632 return IRQ_RETVAL(handled);
1633 }
1634 #endif
1635
ahci_remap_check(struct pci_dev * pdev,int bar,struct ahci_host_priv * hpriv)1636 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1637 struct ahci_host_priv *hpriv)
1638 {
1639 int i;
1640 u32 cap;
1641
1642 /*
1643 * Check if this device might have remapped nvme devices.
1644 */
1645 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1646 pci_resource_len(pdev, bar) < SZ_512K ||
1647 bar != AHCI_PCI_BAR_STANDARD ||
1648 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1649 return;
1650
1651 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1652 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1653 if ((cap & (1 << i)) == 0)
1654 continue;
1655 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1656 != PCI_CLASS_STORAGE_EXPRESS)
1657 continue;
1658
1659 /* We've found a remapped device */
1660 hpriv->remapped_nvme++;
1661 }
1662
1663 if (!hpriv->remapped_nvme)
1664 return;
1665
1666 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1667 hpriv->remapped_nvme);
1668 dev_warn(&pdev->dev,
1669 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1670
1671 /*
1672 * Don't rely on the msi-x capability in the remap case,
1673 * share the legacy interrupt across ahci and remapped devices.
1674 */
1675 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1676 }
1677
ahci_get_irq_vector(struct ata_host * host,int port)1678 static int ahci_get_irq_vector(struct ata_host *host, int port)
1679 {
1680 return pci_irq_vector(to_pci_dev(host->dev), port);
1681 }
1682
ahci_init_msi(struct pci_dev * pdev,unsigned int n_ports,struct ahci_host_priv * hpriv)1683 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1684 struct ahci_host_priv *hpriv)
1685 {
1686 int nvec;
1687
1688 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1689 return -ENODEV;
1690
1691 /*
1692 * If number of MSIs is less than number of ports then Sharing Last
1693 * Message mode could be enforced. In this case assume that advantage
1694 * of multipe MSIs is negated and use single MSI mode instead.
1695 */
1696 if (n_ports > 1) {
1697 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1698 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1699 if (nvec > 0) {
1700 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1701 hpriv->get_irq_vector = ahci_get_irq_vector;
1702 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1703 return nvec;
1704 }
1705
1706 /*
1707 * Fallback to single MSI mode if the controller
1708 * enforced MRSM mode.
1709 */
1710 printk(KERN_INFO
1711 "ahci: MRSM is on, fallback to single MSI\n");
1712 pci_free_irq_vectors(pdev);
1713 }
1714 }
1715
1716 /*
1717 * If the host is not capable of supporting per-port vectors, fall
1718 * back to single MSI before finally attempting single MSI-X.
1719 */
1720 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1721 if (nvec == 1)
1722 return nvec;
1723 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1724 }
1725
ahci_update_initial_lpm_policy(struct ata_port * ap,struct ahci_host_priv * hpriv)1726 static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1727 struct ahci_host_priv *hpriv)
1728 {
1729 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1730
1731
1732 /* Ignore processing for chipsets that don't use policy */
1733 if (!(hpriv->flags & AHCI_HFLAG_USE_LPM_POLICY))
1734 return;
1735
1736 /* user modified policy via module param */
1737 if (mobile_lpm_policy != -1) {
1738 policy = mobile_lpm_policy;
1739 goto update_policy;
1740 }
1741
1742 if (policy > ATA_LPM_MED_POWER && pm_suspend_default_s2idle()) {
1743 if (hpriv->cap & HOST_CAP_PART)
1744 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1745 else if (hpriv->cap & HOST_CAP_SSC)
1746 policy = ATA_LPM_MIN_POWER;
1747 }
1748
1749 update_policy:
1750 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1751 ap->target_lpm_policy = policy;
1752 }
1753
ahci_intel_pcs_quirk(struct pci_dev * pdev,struct ahci_host_priv * hpriv)1754 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1755 {
1756 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1757 u16 tmp16;
1758
1759 /*
1760 * Only apply the 6-port PCS quirk for known legacy platforms.
1761 */
1762 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1763 return;
1764
1765 /* Skip applying the quirk on Denverton and beyond */
1766 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
1767 return;
1768
1769 /*
1770 * port_map is determined from PORTS_IMPL PCI register which is
1771 * implemented as write or write-once register. If the register
1772 * isn't programmed, ahci automatically generates it from number
1773 * of ports, which is good enough for PCS programming. It is
1774 * otherwise expected that platform firmware enables the ports
1775 * before the OS boots.
1776 */
1777 pci_read_config_word(pdev, PCS_6, &tmp16);
1778 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1779 tmp16 |= hpriv->port_map;
1780 pci_write_config_word(pdev, PCS_6, tmp16);
1781 }
1782 }
1783
remapped_nvme_show(struct device * dev,struct device_attribute * attr,char * buf)1784 static ssize_t remapped_nvme_show(struct device *dev,
1785 struct device_attribute *attr,
1786 char *buf)
1787 {
1788 struct ata_host *host = dev_get_drvdata(dev);
1789 struct ahci_host_priv *hpriv = host->private_data;
1790
1791 return sysfs_emit(buf, "%u\n", hpriv->remapped_nvme);
1792 }
1793
1794 static DEVICE_ATTR_RO(remapped_nvme);
1795
ahci_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)1796 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1797 {
1798 unsigned int board_id = ent->driver_data;
1799 struct ata_port_info pi = ahci_port_info[board_id];
1800 const struct ata_port_info *ppi[] = { &pi, NULL };
1801 struct device *dev = &pdev->dev;
1802 struct ahci_host_priv *hpriv;
1803 struct ata_host *host;
1804 int n_ports, i, rc;
1805 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1806
1807 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1808
1809 ata_print_version_once(&pdev->dev, DRV_VERSION);
1810
1811 /* The AHCI driver can only drive the SATA ports, the PATA driver
1812 can drive them all so if both drivers are selected make sure
1813 AHCI stays out of the way */
1814 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1815 return -ENODEV;
1816
1817 /* Apple BIOS on MCP89 prevents us using AHCI */
1818 if (is_mcp89_apple(pdev))
1819 ahci_mcp89_apple_enable(pdev);
1820
1821 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1822 * At the moment, we can only use the AHCI mode. Let the users know
1823 * that for SAS drives they're out of luck.
1824 */
1825 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1826 dev_info(&pdev->dev,
1827 "PDC42819 can only drive SATA devices with this driver\n");
1828
1829 /* Some devices use non-standard BARs */
1830 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1831 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1832 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1833 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1834 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1835 if (pdev->device == 0xa01c)
1836 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1837 if (pdev->device == 0xa084)
1838 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1839 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1840 if (pdev->device == 0x7a08)
1841 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
1842 }
1843
1844 /* acquire resources */
1845 rc = pcim_enable_device(pdev);
1846 if (rc)
1847 return rc;
1848
1849 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1850 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1851 u8 map;
1852
1853 /* ICH6s share the same PCI ID for both piix and ahci
1854 * modes. Enabling ahci mode while MAP indicates
1855 * combined mode is a bad idea. Yield to ata_piix.
1856 */
1857 pci_read_config_byte(pdev, ICH_MAP, &map);
1858 if (map & 0x3) {
1859 dev_info(&pdev->dev,
1860 "controller is in combined mode, can't enable AHCI mode\n");
1861 return -ENODEV;
1862 }
1863 }
1864
1865 /* AHCI controllers often implement SFF compatible interface.
1866 * Grab all PCI BARs just in case.
1867 */
1868 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1869 if (rc == -EBUSY)
1870 pcim_pin_device(pdev);
1871 if (rc)
1872 return rc;
1873
1874 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1875 if (!hpriv)
1876 return -ENOMEM;
1877 hpriv->flags |= (unsigned long)pi.private_data;
1878
1879 /* MCP65 revision A1 and A2 can't do MSI */
1880 if (board_id == board_ahci_mcp65 &&
1881 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1882 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1883
1884 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1885 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1886 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1887
1888 /* only some SB600s can do 64bit DMA */
1889 if (ahci_sb600_enable_64bit(pdev))
1890 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1891
1892 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1893
1894 /* detect remapped nvme devices */
1895 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1896
1897 sysfs_add_file_to_group(&pdev->dev.kobj,
1898 &dev_attr_remapped_nvme.attr,
1899 NULL);
1900
1901 /* must set flag prior to save config in order to take effect */
1902 if (ahci_broken_devslp(pdev))
1903 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1904
1905 #ifdef CONFIG_ARM64
1906 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1907 pdev->device == 0xa235 &&
1908 pdev->revision < 0x30)
1909 hpriv->flags |= AHCI_HFLAG_NO_SXS;
1910
1911 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1912 hpriv->irq_handler = ahci_thunderx_irq_handler;
1913 #endif
1914
1915 /* save initial config */
1916 ahci_pci_save_initial_config(pdev, hpriv);
1917
1918 /* prepare host */
1919 if (hpriv->cap & HOST_CAP_NCQ) {
1920 pi.flags |= ATA_FLAG_NCQ;
1921 /*
1922 * Auto-activate optimization is supposed to be
1923 * supported on all AHCI controllers indicating NCQ
1924 * capability, but it seems to be broken on some
1925 * chipsets including NVIDIAs.
1926 */
1927 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1928 pi.flags |= ATA_FLAG_FPDMA_AA;
1929
1930 /*
1931 * All AHCI controllers should be forward-compatible
1932 * with the new auxiliary field. This code should be
1933 * conditionalized if any buggy AHCI controllers are
1934 * encountered.
1935 */
1936 pi.flags |= ATA_FLAG_FPDMA_AUX;
1937 }
1938
1939 if (hpriv->cap & HOST_CAP_PMP)
1940 pi.flags |= ATA_FLAG_PMP;
1941
1942 ahci_set_em_messages(hpriv, &pi);
1943
1944 if (ahci_broken_system_poweroff(pdev)) {
1945 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1946 dev_info(&pdev->dev,
1947 "quirky BIOS, skipping spindown on poweroff\n");
1948 }
1949
1950 if (ahci_broken_lpm(pdev)) {
1951 pi.flags |= ATA_FLAG_NO_LPM;
1952 dev_warn(&pdev->dev,
1953 "BIOS update required for Link Power Management support\n");
1954 }
1955
1956 if (ahci_broken_suspend(pdev)) {
1957 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1958 dev_warn(&pdev->dev,
1959 "BIOS update required for suspend/resume\n");
1960 }
1961
1962 if (ahci_broken_online(pdev)) {
1963 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1964 dev_info(&pdev->dev,
1965 "online status unreliable, applying workaround\n");
1966 }
1967
1968
1969 /* Acer SA5-271 workaround modifies private_data */
1970 acer_sa5_271_workaround(hpriv, pdev);
1971
1972 /* CAP.NP sometimes indicate the index of the last enabled
1973 * port, at other times, that of the last possible port, so
1974 * determining the maximum port number requires looking at
1975 * both CAP.NP and port_map.
1976 */
1977 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1978
1979 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1980 if (!host) {
1981 rc = -ENOMEM;
1982 goto err_rm_sysfs_file;
1983 }
1984 host->private_data = hpriv;
1985
1986 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1987 /* legacy intx interrupts */
1988 pci_intx(pdev, 1);
1989 }
1990 hpriv->irq = pci_irq_vector(pdev, 0);
1991
1992 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1993 host->flags |= ATA_HOST_PARALLEL_SCAN;
1994 else
1995 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1996
1997 if (!(hpriv->cap & HOST_CAP_PART))
1998 host->flags |= ATA_HOST_NO_PART;
1999
2000 if (!(hpriv->cap & HOST_CAP_SSC))
2001 host->flags |= ATA_HOST_NO_SSC;
2002
2003 if (!(hpriv->cap2 & HOST_CAP2_SDS))
2004 host->flags |= ATA_HOST_NO_DEVSLP;
2005
2006 if (pi.flags & ATA_FLAG_EM)
2007 ahci_reset_em(host);
2008
2009 for (i = 0; i < host->n_ports; i++) {
2010 struct ata_port *ap = host->ports[i];
2011
2012 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
2013 ata_port_pbar_desc(ap, ahci_pci_bar,
2014 0x100 + ap->port_no * 0x80, "port");
2015
2016 /* set enclosure management message type */
2017 if (ap->flags & ATA_FLAG_EM)
2018 ap->em_message_type = hpriv->em_msg_type;
2019
2020 ahci_update_initial_lpm_policy(ap, hpriv);
2021
2022 /* disabled/not-implemented port */
2023 if (!(hpriv->port_map & (1 << i)))
2024 ap->ops = &ata_dummy_port_ops;
2025 }
2026
2027 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2028 ahci_p5wdh_workaround(host);
2029
2030 /* apply gtf filter quirk */
2031 ahci_gtf_filter_workaround(host);
2032
2033 /* initialize adapter */
2034 rc = ahci_configure_dma_masks(pdev, hpriv);
2035 if (rc)
2036 goto err_rm_sysfs_file;
2037
2038 rc = ahci_pci_reset_controller(host);
2039 if (rc)
2040 goto err_rm_sysfs_file;
2041
2042 ahci_pci_init_controller(host);
2043 ahci_pci_print_info(host);
2044
2045 pci_set_master(pdev);
2046
2047 rc = ahci_host_activate(host, &ahci_sht);
2048 if (rc)
2049 goto err_rm_sysfs_file;
2050
2051 pm_runtime_put_noidle(&pdev->dev);
2052 return 0;
2053
2054 err_rm_sysfs_file:
2055 sysfs_remove_file_from_group(&pdev->dev.kobj,
2056 &dev_attr_remapped_nvme.attr, NULL);
2057 return rc;
2058 }
2059
ahci_shutdown_one(struct pci_dev * pdev)2060 static void ahci_shutdown_one(struct pci_dev *pdev)
2061 {
2062 ata_pci_shutdown_one(pdev);
2063 }
2064
ahci_remove_one(struct pci_dev * pdev)2065 static void ahci_remove_one(struct pci_dev *pdev)
2066 {
2067 sysfs_remove_file_from_group(&pdev->dev.kobj,
2068 &dev_attr_remapped_nvme.attr,
2069 NULL);
2070 pm_runtime_get_noresume(&pdev->dev);
2071 ata_pci_remove_one(pdev);
2072 }
2073
2074 module_pci_driver(ahci_pci_driver);
2075
2076 MODULE_AUTHOR("Jeff Garzik");
2077 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2078 MODULE_LICENSE("GPL");
2079 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2080 MODULE_VERSION(DRV_VERSION);
2081