1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * adv7604 - Analog Devices ADV7604 video decoder driver
4 *
5 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
6 *
7 */
8
9 /*
10 * References (c = chapter, p = page):
11 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
12 * Revision 2.5, June 2010
13 * REF_02 - Analog devices, Register map documentation, Documentation of
14 * the register maps, Software manual, Rev. F, June 2010
15 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
16 */
17
18 #include <linux/delay.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/hdmi.h>
21 #include <linux/i2c.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/of_graph.h>
25 #include <linux/slab.h>
26 #include <linux/v4l2-dv-timings.h>
27 #include <linux/videodev2.h>
28 #include <linux/workqueue.h>
29 #include <linux/regmap.h>
30 #include <linux/interrupt.h>
31
32 #include <media/i2c/adv7604.h>
33 #include <media/cec.h>
34 #include <media/v4l2-ctrls.h>
35 #include <media/v4l2-device.h>
36 #include <media/v4l2-event.h>
37 #include <media/v4l2-dv-timings.h>
38 #include <media/v4l2-fwnode.h>
39
40 static int debug;
41 module_param(debug, int, 0644);
42 MODULE_PARM_DESC(debug, "debug level (0-2)");
43
44 MODULE_DESCRIPTION("Analog Devices ADV7604/10/11/12 video decoder driver");
45 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
46 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
47 MODULE_LICENSE("GPL");
48
49 /* ADV7604 system clock frequency */
50 #define ADV76XX_FSC (28636360)
51
52 #define ADV76XX_RGB_OUT (1 << 1)
53
54 #define ADV76XX_OP_FORMAT_SEL_8BIT (0 << 0)
55 #define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0)
56 #define ADV76XX_OP_FORMAT_SEL_12BIT (2 << 0)
57
58 #define ADV76XX_OP_MODE_SEL_SDR_422 (0 << 5)
59 #define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5)
60 #define ADV76XX_OP_MODE_SEL_SDR_444 (2 << 5)
61 #define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5)
62 #define ADV76XX_OP_MODE_SEL_SDR_422_2X (4 << 5)
63 #define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5)
64
65 #define ADV76XX_OP_CH_SEL_GBR (0 << 5)
66 #define ADV76XX_OP_CH_SEL_GRB (1 << 5)
67 #define ADV76XX_OP_CH_SEL_BGR (2 << 5)
68 #define ADV76XX_OP_CH_SEL_RGB (3 << 5)
69 #define ADV76XX_OP_CH_SEL_BRG (4 << 5)
70 #define ADV76XX_OP_CH_SEL_RBG (5 << 5)
71
72 #define ADV76XX_OP_SWAP_CB_CR (1 << 0)
73
74 #define ADV76XX_MAX_ADDRS (3)
75
76 #define ADV76XX_MAX_EDID_BLOCKS 4
77
78 enum adv76xx_type {
79 ADV7604,
80 ADV7611, // including ADV7610
81 ADV7612,
82 };
83
84 struct adv76xx_reg_seq {
85 unsigned int reg;
86 u8 val;
87 };
88
89 struct adv76xx_format_info {
90 u32 code;
91 u8 op_ch_sel;
92 bool rgb_out;
93 bool swap_cb_cr;
94 u8 op_format_sel;
95 };
96
97 struct adv76xx_cfg_read_infoframe {
98 const char *desc;
99 u8 present_mask;
100 u8 head_addr;
101 u8 payload_addr;
102 };
103
104 struct adv76xx_chip_info {
105 enum adv76xx_type type;
106
107 bool has_afe;
108 unsigned int max_port;
109 unsigned int num_dv_ports;
110
111 unsigned int edid_enable_reg;
112 unsigned int edid_status_reg;
113 unsigned int edid_segment_reg;
114 unsigned int edid_segment_mask;
115 unsigned int edid_spa_loc_reg;
116 unsigned int edid_spa_loc_msb_mask;
117 unsigned int edid_spa_port_b_reg;
118 unsigned int lcf_reg;
119
120 unsigned int cable_det_mask;
121 unsigned int tdms_lock_mask;
122 unsigned int fmt_change_digital_mask;
123 unsigned int cp_csc;
124
125 unsigned int cec_irq_status;
126 unsigned int cec_rx_enable;
127 unsigned int cec_rx_enable_mask;
128 bool cec_irq_swap;
129
130 const struct adv76xx_format_info *formats;
131 unsigned int nformats;
132
133 void (*set_termination)(struct v4l2_subdev *sd, bool enable);
134 void (*setup_irqs)(struct v4l2_subdev *sd);
135 unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
136 unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
137
138 /* 0 = AFE, 1 = HDMI */
139 const struct adv76xx_reg_seq *recommended_settings[2];
140 unsigned int num_recommended_settings[2];
141
142 unsigned long page_mask;
143
144 /* Masks for timings */
145 unsigned int linewidth_mask;
146 unsigned int field0_height_mask;
147 unsigned int field1_height_mask;
148 unsigned int hfrontporch_mask;
149 unsigned int hsync_mask;
150 unsigned int hbackporch_mask;
151 unsigned int field0_vfrontporch_mask;
152 unsigned int field1_vfrontporch_mask;
153 unsigned int field0_vsync_mask;
154 unsigned int field1_vsync_mask;
155 unsigned int field0_vbackporch_mask;
156 unsigned int field1_vbackporch_mask;
157 };
158
159 /*
160 **********************************************************************
161 *
162 * Arrays with configuration parameters for the ADV7604
163 *
164 **********************************************************************
165 */
166
167 struct adv76xx_state {
168 const struct adv76xx_chip_info *info;
169 struct adv76xx_platform_data pdata;
170
171 struct gpio_desc *hpd_gpio[4];
172 struct gpio_desc *reset_gpio;
173
174 struct v4l2_subdev sd;
175 struct media_pad pads[ADV76XX_PAD_MAX];
176 unsigned int source_pad;
177
178 struct v4l2_ctrl_handler hdl;
179
180 enum adv76xx_pad selected_input;
181
182 struct v4l2_dv_timings timings;
183 const struct adv76xx_format_info *format;
184
185 struct {
186 u8 edid[ADV76XX_MAX_EDID_BLOCKS * 128];
187 u32 present;
188 unsigned blocks;
189 } edid;
190 u16 spa_port_a[2];
191 struct v4l2_fract aspect_ratio;
192 u32 rgb_quantization_range;
193 struct delayed_work delayed_work_enable_hotplug;
194 bool restart_stdi_once;
195
196 /* CEC */
197 struct cec_adapter *cec_adap;
198 u8 cec_addr[ADV76XX_MAX_ADDRS];
199 u8 cec_valid_addrs;
200 bool cec_enabled_adap;
201
202 /* i2c clients */
203 struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX];
204
205 /* Regmaps */
206 struct regmap *regmap[ADV76XX_PAGE_MAX];
207
208 /* controls */
209 struct v4l2_ctrl *detect_tx_5v_ctrl;
210 struct v4l2_ctrl *analog_sampling_phase_ctrl;
211 struct v4l2_ctrl *free_run_color_manual_ctrl;
212 struct v4l2_ctrl *free_run_color_ctrl;
213 struct v4l2_ctrl *rgb_quantization_range_ctrl;
214 };
215
adv76xx_has_afe(struct adv76xx_state * state)216 static bool adv76xx_has_afe(struct adv76xx_state *state)
217 {
218 return state->info->has_afe;
219 }
220
221 /* Unsupported timings. This device cannot support 720p30. */
222 static const struct v4l2_dv_timings adv76xx_timings_exceptions[] = {
223 V4L2_DV_BT_CEA_1280X720P30,
224 { }
225 };
226
adv76xx_check_dv_timings(const struct v4l2_dv_timings * t,void * hdl)227 static bool adv76xx_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
228 {
229 int i;
230
231 for (i = 0; adv76xx_timings_exceptions[i].bt.width; i++)
232 if (v4l2_match_dv_timings(t, adv76xx_timings_exceptions + i, 0, false))
233 return false;
234 return true;
235 }
236
237 struct adv76xx_video_standards {
238 struct v4l2_dv_timings timings;
239 u8 vid_std;
240 u8 v_freq;
241 };
242
243 /* sorted by number of lines */
244 static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = {
245 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
246 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
247 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
248 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
249 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
250 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
251 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
252 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
253 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
254 /* TODO add 1920x1080P60_RB (CVT timing) */
255 { },
256 };
257
258 /* sorted by number of lines */
259 static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = {
260 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
261 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
262 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
263 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
264 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
265 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
266 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
267 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
268 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
269 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
270 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
271 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
272 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
273 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
274 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
275 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
276 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
277 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
278 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
279 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
280 /* TODO add 1600X1200P60_RB (not a DMT timing) */
281 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
282 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
283 { },
284 };
285
286 /* sorted by number of lines */
287 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = {
288 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
289 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
290 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
291 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
292 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
293 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
294 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
295 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
296 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
297 { },
298 };
299
300 /* sorted by number of lines */
301 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = {
302 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
303 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
304 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
305 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
306 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
307 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
308 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
309 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
310 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
311 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
312 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
313 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
314 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
315 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
316 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
317 { },
318 };
319
320 static const struct v4l2_event adv76xx_ev_fmt = {
321 .type = V4L2_EVENT_SOURCE_CHANGE,
322 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
323 };
324
325 /* ----------------------------------------------------------------------- */
326
to_state(struct v4l2_subdev * sd)327 static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd)
328 {
329 return container_of(sd, struct adv76xx_state, sd);
330 }
331
htotal(const struct v4l2_bt_timings * t)332 static inline unsigned htotal(const struct v4l2_bt_timings *t)
333 {
334 return V4L2_DV_BT_FRAME_WIDTH(t);
335 }
336
vtotal(const struct v4l2_bt_timings * t)337 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
338 {
339 return V4L2_DV_BT_FRAME_HEIGHT(t);
340 }
341
342 /* ----------------------------------------------------------------------- */
343
adv76xx_read_check(struct adv76xx_state * state,int client_page,u8 reg)344 static int adv76xx_read_check(struct adv76xx_state *state,
345 int client_page, u8 reg)
346 {
347 struct i2c_client *client = state->i2c_clients[client_page];
348 int err;
349 unsigned int val;
350
351 err = regmap_read(state->regmap[client_page], reg, &val);
352
353 if (err) {
354 v4l_err(client, "error reading %02x, %02x\n",
355 client->addr, reg);
356 return err;
357 }
358 return val;
359 }
360
361 /* adv76xx_write_block(): Write raw data with a maximum of I2C_SMBUS_BLOCK_MAX
362 * size to one or more registers.
363 *
364 * A value of zero will be returned on success, a negative errno will
365 * be returned in error cases.
366 */
adv76xx_write_block(struct adv76xx_state * state,int client_page,unsigned int init_reg,const void * val,size_t val_len)367 static int adv76xx_write_block(struct adv76xx_state *state, int client_page,
368 unsigned int init_reg, const void *val,
369 size_t val_len)
370 {
371 struct regmap *regmap = state->regmap[client_page];
372
373 if (val_len > I2C_SMBUS_BLOCK_MAX)
374 val_len = I2C_SMBUS_BLOCK_MAX;
375
376 return regmap_raw_write(regmap, init_reg, val, val_len);
377 }
378
379 /* ----------------------------------------------------------------------- */
380
io_read(struct v4l2_subdev * sd,u8 reg)381 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
382 {
383 struct adv76xx_state *state = to_state(sd);
384
385 return adv76xx_read_check(state, ADV76XX_PAGE_IO, reg);
386 }
387
io_write(struct v4l2_subdev * sd,u8 reg,u8 val)388 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
389 {
390 struct adv76xx_state *state = to_state(sd);
391
392 return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val);
393 }
394
io_write_clr_set(struct v4l2_subdev * sd,u8 reg,u8 mask,u8 val)395 static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask,
396 u8 val)
397 {
398 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
399 }
400
avlink_read(struct v4l2_subdev * sd,u8 reg)401 static inline int __always_unused avlink_read(struct v4l2_subdev *sd, u8 reg)
402 {
403 struct adv76xx_state *state = to_state(sd);
404
405 return adv76xx_read_check(state, ADV7604_PAGE_AVLINK, reg);
406 }
407
avlink_write(struct v4l2_subdev * sd,u8 reg,u8 val)408 static inline int __always_unused avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
409 {
410 struct adv76xx_state *state = to_state(sd);
411
412 return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val);
413 }
414
cec_read(struct v4l2_subdev * sd,u8 reg)415 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
416 {
417 struct adv76xx_state *state = to_state(sd);
418
419 return adv76xx_read_check(state, ADV76XX_PAGE_CEC, reg);
420 }
421
cec_write(struct v4l2_subdev * sd,u8 reg,u8 val)422 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
423 {
424 struct adv76xx_state *state = to_state(sd);
425
426 return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val);
427 }
428
cec_write_clr_set(struct v4l2_subdev * sd,u8 reg,u8 mask,u8 val)429 static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask,
430 u8 val)
431 {
432 return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);
433 }
434
infoframe_read(struct v4l2_subdev * sd,u8 reg)435 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
436 {
437 struct adv76xx_state *state = to_state(sd);
438
439 return adv76xx_read_check(state, ADV76XX_PAGE_INFOFRAME, reg);
440 }
441
infoframe_write(struct v4l2_subdev * sd,u8 reg,u8 val)442 static inline int __always_unused infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
443 {
444 struct adv76xx_state *state = to_state(sd);
445
446 return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val);
447 }
448
afe_read(struct v4l2_subdev * sd,u8 reg)449 static inline int __always_unused afe_read(struct v4l2_subdev *sd, u8 reg)
450 {
451 struct adv76xx_state *state = to_state(sd);
452
453 return adv76xx_read_check(state, ADV76XX_PAGE_AFE, reg);
454 }
455
afe_write(struct v4l2_subdev * sd,u8 reg,u8 val)456 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
457 {
458 struct adv76xx_state *state = to_state(sd);
459
460 return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val);
461 }
462
rep_read(struct v4l2_subdev * sd,u8 reg)463 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
464 {
465 struct adv76xx_state *state = to_state(sd);
466
467 return adv76xx_read_check(state, ADV76XX_PAGE_REP, reg);
468 }
469
rep_write(struct v4l2_subdev * sd,u8 reg,u8 val)470 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
471 {
472 struct adv76xx_state *state = to_state(sd);
473
474 return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val);
475 }
476
rep_write_clr_set(struct v4l2_subdev * sd,u8 reg,u8 mask,u8 val)477 static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
478 {
479 return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
480 }
481
edid_read(struct v4l2_subdev * sd,u8 reg)482 static inline int __always_unused edid_read(struct v4l2_subdev *sd, u8 reg)
483 {
484 struct adv76xx_state *state = to_state(sd);
485
486 return adv76xx_read_check(state, ADV76XX_PAGE_EDID, reg);
487 }
488
edid_write(struct v4l2_subdev * sd,u8 reg,u8 val)489 static inline int __always_unused edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
490 {
491 struct adv76xx_state *state = to_state(sd);
492
493 return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val);
494 }
495
edid_write_block(struct v4l2_subdev * sd,unsigned int total_len,const u8 * val)496 static inline int edid_write_block(struct v4l2_subdev *sd,
497 unsigned int total_len, const u8 *val)
498 {
499 struct adv76xx_state *state = to_state(sd);
500 int err = 0;
501 int i = 0;
502 int len = 0;
503
504 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n",
505 __func__, total_len);
506
507 while (!err && i < total_len) {
508 len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ?
509 I2C_SMBUS_BLOCK_MAX :
510 (total_len - i);
511
512 err = adv76xx_write_block(state, ADV76XX_PAGE_EDID,
513 i, val + i, len);
514 i += len;
515 }
516
517 return err;
518 }
519
adv76xx_set_hpd(struct adv76xx_state * state,unsigned int hpd)520 static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd)
521 {
522 const struct adv76xx_chip_info *info = state->info;
523 unsigned int i;
524
525 if (info->type == ADV7604) {
526 for (i = 0; i < state->info->num_dv_ports; ++i)
527 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));
528 } else {
529 for (i = 0; i < state->info->num_dv_ports; ++i)
530 io_write_clr_set(&state->sd, 0x20, 0x80 >> i,
531 (!!(hpd & BIT(i))) << (7 - i));
532 }
533
534 v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd);
535 }
536
adv76xx_delayed_work_enable_hotplug(struct work_struct * work)537 static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work)
538 {
539 struct delayed_work *dwork = to_delayed_work(work);
540 struct adv76xx_state *state = container_of(dwork, struct adv76xx_state,
541 delayed_work_enable_hotplug);
542 struct v4l2_subdev *sd = &state->sd;
543
544 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
545
546 adv76xx_set_hpd(state, state->edid.present);
547 }
548
hdmi_read(struct v4l2_subdev * sd,u8 reg)549 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
550 {
551 struct adv76xx_state *state = to_state(sd);
552
553 return adv76xx_read_check(state, ADV76XX_PAGE_HDMI, reg);
554 }
555
hdmi_read16(struct v4l2_subdev * sd,u8 reg,u16 mask)556 static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
557 {
558 return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
559 }
560
hdmi_write(struct v4l2_subdev * sd,u8 reg,u8 val)561 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
562 {
563 struct adv76xx_state *state = to_state(sd);
564
565 return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val);
566 }
567
hdmi_write_clr_set(struct v4l2_subdev * sd,u8 reg,u8 mask,u8 val)568 static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
569 {
570 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
571 }
572
test_write(struct v4l2_subdev * sd,u8 reg,u8 val)573 static inline int __always_unused test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
574 {
575 struct adv76xx_state *state = to_state(sd);
576
577 return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val);
578 }
579
cp_read(struct v4l2_subdev * sd,u8 reg)580 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
581 {
582 struct adv76xx_state *state = to_state(sd);
583
584 return adv76xx_read_check(state, ADV76XX_PAGE_CP, reg);
585 }
586
cp_read16(struct v4l2_subdev * sd,u8 reg,u16 mask)587 static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
588 {
589 return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
590 }
591
cp_write(struct v4l2_subdev * sd,u8 reg,u8 val)592 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
593 {
594 struct adv76xx_state *state = to_state(sd);
595
596 return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val);
597 }
598
cp_write_clr_set(struct v4l2_subdev * sd,u8 reg,u8 mask,u8 val)599 static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
600 {
601 return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
602 }
603
vdp_read(struct v4l2_subdev * sd,u8 reg)604 static inline int __always_unused vdp_read(struct v4l2_subdev *sd, u8 reg)
605 {
606 struct adv76xx_state *state = to_state(sd);
607
608 return adv76xx_read_check(state, ADV7604_PAGE_VDP, reg);
609 }
610
vdp_write(struct v4l2_subdev * sd,u8 reg,u8 val)611 static inline int __always_unused vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
612 {
613 struct adv76xx_state *state = to_state(sd);
614
615 return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val);
616 }
617
618 #define ADV76XX_REG(page, offset) (((page) << 8) | (offset))
619 #define ADV76XX_REG_SEQ_TERM 0xffff
620
621 #ifdef CONFIG_VIDEO_ADV_DEBUG
adv76xx_read_reg(struct v4l2_subdev * sd,unsigned int reg)622 static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg)
623 {
624 struct adv76xx_state *state = to_state(sd);
625 unsigned int page = reg >> 8;
626 unsigned int val;
627 int err;
628
629 if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask))
630 return -EINVAL;
631
632 reg &= 0xff;
633 err = regmap_read(state->regmap[page], reg, &val);
634
635 return err ? err : val;
636 }
637 #endif
638
adv76xx_write_reg(struct v4l2_subdev * sd,unsigned int reg,u8 val)639 static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
640 {
641 struct adv76xx_state *state = to_state(sd);
642 unsigned int page = reg >> 8;
643
644 if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask))
645 return -EINVAL;
646
647 reg &= 0xff;
648
649 return regmap_write(state->regmap[page], reg, val);
650 }
651
adv76xx_write_reg_seq(struct v4l2_subdev * sd,const struct adv76xx_reg_seq * reg_seq)652 static void adv76xx_write_reg_seq(struct v4l2_subdev *sd,
653 const struct adv76xx_reg_seq *reg_seq)
654 {
655 unsigned int i;
656
657 for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++)
658 adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
659 }
660
661 /* -----------------------------------------------------------------------------
662 * Format helpers
663 */
664
665 static const struct adv76xx_format_info adv7604_formats[] = {
666 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
667 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
668 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
669 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
670 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
671 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
672 { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false,
673 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
674 { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true,
675 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
676 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
677 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
678 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
679 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
680 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
681 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
682 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
683 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
684 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
685 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
686 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
687 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
688 { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false,
689 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
690 { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true,
691 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
692 { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false,
693 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
694 { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true,
695 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
696 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
697 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
698 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
699 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
700 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
701 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
702 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
703 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
704 };
705
706 static const struct adv76xx_format_info adv7611_formats[] = {
707 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
708 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
709 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
710 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
711 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
712 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
713 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
714 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
715 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
716 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
717 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
718 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
719 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
720 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
721 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
722 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
723 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
724 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
725 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
726 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
727 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
728 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
729 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
730 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
731 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
732 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
733 };
734
735 static const struct adv76xx_format_info adv7612_formats[] = {
736 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
737 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
738 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
739 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
740 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
741 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
742 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
743 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
744 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
745 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
746 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
747 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
748 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
749 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
750 };
751
752 static const struct adv76xx_format_info *
adv76xx_format_info(struct adv76xx_state * state,u32 code)753 adv76xx_format_info(struct adv76xx_state *state, u32 code)
754 {
755 unsigned int i;
756
757 for (i = 0; i < state->info->nformats; ++i) {
758 if (state->info->formats[i].code == code)
759 return &state->info->formats[i];
760 }
761
762 return NULL;
763 }
764
765 /* ----------------------------------------------------------------------- */
766
is_analog_input(struct v4l2_subdev * sd)767 static inline bool is_analog_input(struct v4l2_subdev *sd)
768 {
769 struct adv76xx_state *state = to_state(sd);
770
771 return state->selected_input == ADV7604_PAD_VGA_RGB ||
772 state->selected_input == ADV7604_PAD_VGA_COMP;
773 }
774
is_digital_input(struct v4l2_subdev * sd)775 static inline bool is_digital_input(struct v4l2_subdev *sd)
776 {
777 struct adv76xx_state *state = to_state(sd);
778
779 return state->selected_input == ADV76XX_PAD_HDMI_PORT_A ||
780 state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
781 state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
782 state->selected_input == ADV7604_PAD_HDMI_PORT_D;
783 }
784
785 static const struct v4l2_dv_timings_cap adv7604_timings_cap_analog = {
786 .type = V4L2_DV_BT_656_1120,
787 /* keep this initialization for compatibility with GCC < 4.4.6 */
788 .reserved = { 0 },
789 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000,
790 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
791 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
792 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
793 V4L2_DV_BT_CAP_CUSTOM)
794 };
795
796 static const struct v4l2_dv_timings_cap adv76xx_timings_cap_digital = {
797 .type = V4L2_DV_BT_656_1120,
798 /* keep this initialization for compatibility with GCC < 4.4.6 */
799 .reserved = { 0 },
800 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 225000000,
801 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
802 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
803 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
804 V4L2_DV_BT_CAP_CUSTOM)
805 };
806
807 /*
808 * Return the DV timings capabilities for the requested sink pad. As a special
809 * case, pad value -1 returns the capabilities for the currently selected input.
810 */
811 static const struct v4l2_dv_timings_cap *
adv76xx_get_dv_timings_cap(struct v4l2_subdev * sd,int pad)812 adv76xx_get_dv_timings_cap(struct v4l2_subdev *sd, int pad)
813 {
814 if (pad == -1) {
815 struct adv76xx_state *state = to_state(sd);
816
817 pad = state->selected_input;
818 }
819
820 switch (pad) {
821 case ADV76XX_PAD_HDMI_PORT_A:
822 case ADV7604_PAD_HDMI_PORT_B:
823 case ADV7604_PAD_HDMI_PORT_C:
824 case ADV7604_PAD_HDMI_PORT_D:
825 return &adv76xx_timings_cap_digital;
826
827 case ADV7604_PAD_VGA_RGB:
828 case ADV7604_PAD_VGA_COMP:
829 default:
830 return &adv7604_timings_cap_analog;
831 }
832 }
833
834
835 /* ----------------------------------------------------------------------- */
836
837 #ifdef CONFIG_VIDEO_ADV_DEBUG
adv76xx_inv_register(struct v4l2_subdev * sd)838 static void adv76xx_inv_register(struct v4l2_subdev *sd)
839 {
840 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
841 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
842 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
843 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
844 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
845 v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
846 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
847 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
848 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
849 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
850 v4l2_info(sd, "0xa00-0xaff: Test Map\n");
851 v4l2_info(sd, "0xb00-0xbff: CP Map\n");
852 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
853 }
854
adv76xx_g_register(struct v4l2_subdev * sd,struct v4l2_dbg_register * reg)855 static int adv76xx_g_register(struct v4l2_subdev *sd,
856 struct v4l2_dbg_register *reg)
857 {
858 int ret;
859
860 ret = adv76xx_read_reg(sd, reg->reg);
861 if (ret < 0) {
862 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
863 adv76xx_inv_register(sd);
864 return ret;
865 }
866
867 reg->size = 1;
868 reg->val = ret;
869
870 return 0;
871 }
872
adv76xx_s_register(struct v4l2_subdev * sd,const struct v4l2_dbg_register * reg)873 static int adv76xx_s_register(struct v4l2_subdev *sd,
874 const struct v4l2_dbg_register *reg)
875 {
876 int ret;
877
878 ret = adv76xx_write_reg(sd, reg->reg, reg->val);
879 if (ret < 0) {
880 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
881 adv76xx_inv_register(sd);
882 return ret;
883 }
884
885 return 0;
886 }
887 #endif
888
adv7604_read_cable_det(struct v4l2_subdev * sd)889 static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
890 {
891 u8 value = io_read(sd, 0x6f);
892
893 return ((value & 0x10) >> 4)
894 | ((value & 0x08) >> 2)
895 | ((value & 0x04) << 0)
896 | ((value & 0x02) << 2);
897 }
898
adv7611_read_cable_det(struct v4l2_subdev * sd)899 static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
900 {
901 u8 value = io_read(sd, 0x6f);
902
903 return value & 1;
904 }
905
adv7612_read_cable_det(struct v4l2_subdev * sd)906 static unsigned int adv7612_read_cable_det(struct v4l2_subdev *sd)
907 {
908 /* Reads CABLE_DET_A_RAW. For input B support, need to
909 * account for bit 7 [MSB] of 0x6a (ie. CABLE_DET_B_RAW)
910 */
911 u8 value = io_read(sd, 0x6f);
912
913 return value & 1;
914 }
915
adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev * sd)916 static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
917 {
918 struct adv76xx_state *state = to_state(sd);
919 const struct adv76xx_chip_info *info = state->info;
920 u16 cable_det = info->read_cable_det(sd);
921
922 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det);
923 }
924
find_and_set_predefined_video_timings(struct v4l2_subdev * sd,u8 prim_mode,const struct adv76xx_video_standards * predef_vid_timings,const struct v4l2_dv_timings * timings)925 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
926 u8 prim_mode,
927 const struct adv76xx_video_standards *predef_vid_timings,
928 const struct v4l2_dv_timings *timings)
929 {
930 int i;
931
932 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
933 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
934 is_digital_input(sd) ? 250000 : 1000000, false))
935 continue;
936 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
937 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
938 prim_mode); /* v_freq and prim mode */
939 return 0;
940 }
941
942 return -1;
943 }
944
configure_predefined_video_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)945 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
946 struct v4l2_dv_timings *timings)
947 {
948 struct adv76xx_state *state = to_state(sd);
949 int err;
950
951 v4l2_dbg(1, debug, sd, "%s", __func__);
952
953 if (adv76xx_has_afe(state)) {
954 /* reset to default values */
955 io_write(sd, 0x16, 0x43);
956 io_write(sd, 0x17, 0x5a);
957 }
958 /* disable embedded syncs for auto graphics mode */
959 cp_write_clr_set(sd, 0x81, 0x10, 0x00);
960 cp_write(sd, 0x8f, 0x00);
961 cp_write(sd, 0x90, 0x00);
962 cp_write(sd, 0xa2, 0x00);
963 cp_write(sd, 0xa3, 0x00);
964 cp_write(sd, 0xa4, 0x00);
965 cp_write(sd, 0xa5, 0x00);
966 cp_write(sd, 0xa6, 0x00);
967 cp_write(sd, 0xa7, 0x00);
968 cp_write(sd, 0xab, 0x00);
969 cp_write(sd, 0xac, 0x00);
970
971 if (is_analog_input(sd)) {
972 err = find_and_set_predefined_video_timings(sd,
973 0x01, adv7604_prim_mode_comp, timings);
974 if (err)
975 err = find_and_set_predefined_video_timings(sd,
976 0x02, adv7604_prim_mode_gr, timings);
977 } else if (is_digital_input(sd)) {
978 err = find_and_set_predefined_video_timings(sd,
979 0x05, adv76xx_prim_mode_hdmi_comp, timings);
980 if (err)
981 err = find_and_set_predefined_video_timings(sd,
982 0x06, adv76xx_prim_mode_hdmi_gr, timings);
983 } else {
984 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
985 __func__, state->selected_input);
986 err = -1;
987 }
988
989
990 return err;
991 }
992
configure_custom_video_timings(struct v4l2_subdev * sd,const struct v4l2_bt_timings * bt)993 static void configure_custom_video_timings(struct v4l2_subdev *sd,
994 const struct v4l2_bt_timings *bt)
995 {
996 struct adv76xx_state *state = to_state(sd);
997 u32 width = htotal(bt);
998 u32 height = vtotal(bt);
999 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
1000 u16 cp_start_eav = width - bt->hfrontporch;
1001 u16 cp_start_vbi = height - bt->vfrontporch;
1002 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
1003 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
1004 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0;
1005 const u8 pll[2] = {
1006 0xc0 | ((width >> 8) & 0x1f),
1007 width & 0xff
1008 };
1009
1010 v4l2_dbg(2, debug, sd, "%s\n", __func__);
1011
1012 if (is_analog_input(sd)) {
1013 /* auto graphics */
1014 io_write(sd, 0x00, 0x07); /* video std */
1015 io_write(sd, 0x01, 0x02); /* prim mode */
1016 /* enable embedded syncs for auto graphics mode */
1017 cp_write_clr_set(sd, 0x81, 0x10, 0x10);
1018
1019 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
1020 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
1021 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
1022 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_IO],
1023 0x16, pll, 2))
1024 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
1025
1026 /* active video - horizontal timing */
1027 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
1028 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
1029 ((cp_start_eav >> 8) & 0x0f));
1030 cp_write(sd, 0xa4, cp_start_eav & 0xff);
1031
1032 /* active video - vertical timing */
1033 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1034 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1035 ((cp_end_vbi >> 8) & 0xf));
1036 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1037 } else if (is_digital_input(sd)) {
1038 /* set default prim_mode/vid_std for HDMI
1039 according to [REF_03, c. 4.2] */
1040 io_write(sd, 0x00, 0x02); /* video std */
1041 io_write(sd, 0x01, 0x06); /* prim mode */
1042 } else {
1043 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1044 __func__, state->selected_input);
1045 }
1046
1047 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1048 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1049 cp_write(sd, 0xab, (height >> 4) & 0xff);
1050 cp_write(sd, 0xac, (height & 0x0f) << 4);
1051 }
1052
adv76xx_set_offset(struct v4l2_subdev * sd,bool auto_offset,u16 offset_a,u16 offset_b,u16 offset_c)1053 static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
1054 {
1055 struct adv76xx_state *state = to_state(sd);
1056 u8 offset_buf[4];
1057
1058 if (auto_offset) {
1059 offset_a = 0x3ff;
1060 offset_b = 0x3ff;
1061 offset_c = 0x3ff;
1062 }
1063
1064 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1065 __func__, auto_offset ? "Auto" : "Manual",
1066 offset_a, offset_b, offset_c);
1067
1068 offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1069 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1070 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1071 offset_buf[3] = offset_c & 0x0ff;
1072
1073 /* Registers must be written in this order with no i2c access in between */
1074 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1075 0x77, offset_buf, 4))
1076 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1077 }
1078
adv76xx_set_gain(struct v4l2_subdev * sd,bool auto_gain,u16 gain_a,u16 gain_b,u16 gain_c)1079 static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1080 {
1081 struct adv76xx_state *state = to_state(sd);
1082 u8 gain_buf[4];
1083 u8 gain_man = 1;
1084 u8 agc_mode_man = 1;
1085
1086 if (auto_gain) {
1087 gain_man = 0;
1088 agc_mode_man = 0;
1089 gain_a = 0x100;
1090 gain_b = 0x100;
1091 gain_c = 0x100;
1092 }
1093
1094 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1095 __func__, auto_gain ? "Auto" : "Manual",
1096 gain_a, gain_b, gain_c);
1097
1098 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1099 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1100 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1101 gain_buf[3] = ((gain_c & 0x0ff));
1102
1103 /* Registers must be written in this order with no i2c access in between */
1104 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1105 0x73, gain_buf, 4))
1106 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1107 }
1108
set_rgb_quantization_range(struct v4l2_subdev * sd)1109 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1110 {
1111 struct adv76xx_state *state = to_state(sd);
1112 bool rgb_output = io_read(sd, 0x02) & 0x02;
1113 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1114 u8 y = HDMI_COLORSPACE_RGB;
1115
1116 if (hdmi_signal && (io_read(sd, 0x60) & 1))
1117 y = infoframe_read(sd, 0x01) >> 5;
1118
1119 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1120 __func__, state->rgb_quantization_range,
1121 rgb_output, hdmi_signal);
1122
1123 adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0);
1124 adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0);
1125 io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4);
1126
1127 switch (state->rgb_quantization_range) {
1128 case V4L2_DV_RGB_RANGE_AUTO:
1129 if (state->selected_input == ADV7604_PAD_VGA_RGB) {
1130 /* Receiving analog RGB signal
1131 * Set RGB full range (0-255) */
1132 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1133 break;
1134 }
1135
1136 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1137 /* Receiving analog YPbPr signal
1138 * Set automode */
1139 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1140 break;
1141 }
1142
1143 if (hdmi_signal) {
1144 /* Receiving HDMI signal
1145 * Set automode */
1146 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1147 break;
1148 }
1149
1150 /* Receiving DVI-D signal
1151 * ADV7604 selects RGB limited range regardless of
1152 * input format (CE/IT) in automatic mode */
1153 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
1154 /* RGB limited range (16-235) */
1155 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1156 } else {
1157 /* RGB full range (0-255) */
1158 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1159
1160 if (is_digital_input(sd) && rgb_output) {
1161 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1162 } else {
1163 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1164 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1165 }
1166 }
1167 break;
1168 case V4L2_DV_RGB_RANGE_LIMITED:
1169 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1170 /* YCrCb limited range (16-235) */
1171 io_write_clr_set(sd, 0x02, 0xf0, 0x20);
1172 break;
1173 }
1174
1175 if (y != HDMI_COLORSPACE_RGB)
1176 break;
1177
1178 /* RGB limited range (16-235) */
1179 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1180
1181 break;
1182 case V4L2_DV_RGB_RANGE_FULL:
1183 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1184 /* YCrCb full range (0-255) */
1185 io_write_clr_set(sd, 0x02, 0xf0, 0x60);
1186 break;
1187 }
1188
1189 if (y != HDMI_COLORSPACE_RGB)
1190 break;
1191
1192 /* RGB full range (0-255) */
1193 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1194
1195 if (is_analog_input(sd) || hdmi_signal)
1196 break;
1197
1198 /* Adjust gain/offset for DVI-D signals only */
1199 if (rgb_output) {
1200 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1201 } else {
1202 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1203 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1204 }
1205 break;
1206 }
1207 }
1208
adv76xx_s_ctrl(struct v4l2_ctrl * ctrl)1209 static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl)
1210 {
1211 struct v4l2_subdev *sd =
1212 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1213
1214 struct adv76xx_state *state = to_state(sd);
1215
1216 switch (ctrl->id) {
1217 case V4L2_CID_BRIGHTNESS:
1218 cp_write(sd, 0x3c, ctrl->val);
1219 return 0;
1220 case V4L2_CID_CONTRAST:
1221 cp_write(sd, 0x3a, ctrl->val);
1222 return 0;
1223 case V4L2_CID_SATURATION:
1224 cp_write(sd, 0x3b, ctrl->val);
1225 return 0;
1226 case V4L2_CID_HUE:
1227 cp_write(sd, 0x3d, ctrl->val);
1228 return 0;
1229 case V4L2_CID_DV_RX_RGB_RANGE:
1230 state->rgb_quantization_range = ctrl->val;
1231 set_rgb_quantization_range(sd);
1232 return 0;
1233 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1234 if (!adv76xx_has_afe(state))
1235 return -EINVAL;
1236 /* Set the analog sampling phase. This is needed to find the
1237 best sampling phase for analog video: an application or
1238 driver has to try a number of phases and analyze the picture
1239 quality before settling on the best performing phase. */
1240 afe_write(sd, 0xc8, ctrl->val);
1241 return 0;
1242 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1243 /* Use the default blue color for free running mode,
1244 or supply your own. */
1245 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
1246 return 0;
1247 case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
1248 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1249 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1250 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1251 return 0;
1252 }
1253 return -EINVAL;
1254 }
1255
adv76xx_g_volatile_ctrl(struct v4l2_ctrl * ctrl)1256 static int adv76xx_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1257 {
1258 struct v4l2_subdev *sd =
1259 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1260
1261 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {
1262 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
1263 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))
1264 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3;
1265 return 0;
1266 }
1267 return -EINVAL;
1268 }
1269
1270 /* ----------------------------------------------------------------------- */
1271
no_power(struct v4l2_subdev * sd)1272 static inline bool no_power(struct v4l2_subdev *sd)
1273 {
1274 /* Entire chip or CP powered off */
1275 return io_read(sd, 0x0c) & 0x24;
1276 }
1277
no_signal_tmds(struct v4l2_subdev * sd)1278 static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1279 {
1280 struct adv76xx_state *state = to_state(sd);
1281
1282 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
1283 }
1284
no_lock_tmds(struct v4l2_subdev * sd)1285 static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1286 {
1287 struct adv76xx_state *state = to_state(sd);
1288 const struct adv76xx_chip_info *info = state->info;
1289
1290 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
1291 }
1292
is_hdmi(struct v4l2_subdev * sd)1293 static inline bool is_hdmi(struct v4l2_subdev *sd)
1294 {
1295 return hdmi_read(sd, 0x05) & 0x80;
1296 }
1297
no_lock_sspd(struct v4l2_subdev * sd)1298 static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1299 {
1300 struct adv76xx_state *state = to_state(sd);
1301
1302 /*
1303 * Chips without a AFE don't expose registers for the SSPD, so just assume
1304 * that we have a lock.
1305 */
1306 if (adv76xx_has_afe(state))
1307 return false;
1308
1309 /* TODO channel 2 */
1310 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1311 }
1312
no_lock_stdi(struct v4l2_subdev * sd)1313 static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1314 {
1315 /* TODO channel 2 */
1316 return !(cp_read(sd, 0xb1) & 0x80);
1317 }
1318
no_signal(struct v4l2_subdev * sd)1319 static inline bool no_signal(struct v4l2_subdev *sd)
1320 {
1321 bool ret;
1322
1323 ret = no_power(sd);
1324
1325 ret |= no_lock_stdi(sd);
1326 ret |= no_lock_sspd(sd);
1327
1328 if (is_digital_input(sd)) {
1329 ret |= no_lock_tmds(sd);
1330 ret |= no_signal_tmds(sd);
1331 }
1332
1333 return ret;
1334 }
1335
no_lock_cp(struct v4l2_subdev * sd)1336 static inline bool no_lock_cp(struct v4l2_subdev *sd)
1337 {
1338 struct adv76xx_state *state = to_state(sd);
1339
1340 if (!adv76xx_has_afe(state))
1341 return false;
1342
1343 /* CP has detected a non standard number of lines on the incoming
1344 video compared to what it is configured to receive by s_dv_timings */
1345 return io_read(sd, 0x12) & 0x01;
1346 }
1347
in_free_run(struct v4l2_subdev * sd)1348 static inline bool in_free_run(struct v4l2_subdev *sd)
1349 {
1350 return cp_read(sd, 0xff) & 0x10;
1351 }
1352
adv76xx_g_input_status(struct v4l2_subdev * sd,u32 * status)1353 static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status)
1354 {
1355 *status = 0;
1356 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1357 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1358 if (!in_free_run(sd) && no_lock_cp(sd))
1359 *status |= is_digital_input(sd) ?
1360 V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1361
1362 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1363
1364 return 0;
1365 }
1366
1367 /* ----------------------------------------------------------------------- */
1368
1369 struct stdi_readback {
1370 u16 bl, lcf, lcvs;
1371 u8 hs_pol, vs_pol;
1372 bool interlaced;
1373 };
1374
stdi2dv_timings(struct v4l2_subdev * sd,struct stdi_readback * stdi,struct v4l2_dv_timings * timings)1375 static int stdi2dv_timings(struct v4l2_subdev *sd,
1376 struct stdi_readback *stdi,
1377 struct v4l2_dv_timings *timings)
1378 {
1379 struct adv76xx_state *state = to_state(sd);
1380 u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl;
1381 u32 pix_clk;
1382 int i;
1383
1384 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1385 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1386
1387 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1388 adv76xx_get_dv_timings_cap(sd, -1),
1389 adv76xx_check_dv_timings, NULL))
1390 continue;
1391 if (vtotal(bt) != stdi->lcf + 1)
1392 continue;
1393 if (bt->vsync != stdi->lcvs)
1394 continue;
1395
1396 pix_clk = hfreq * htotal(bt);
1397
1398 if ((pix_clk < bt->pixelclock + 1000000) &&
1399 (pix_clk > bt->pixelclock - 1000000)) {
1400 *timings = v4l2_dv_timings_presets[i];
1401 return 0;
1402 }
1403 }
1404
1405 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0,
1406 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1407 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1408 false, adv76xx_get_dv_timings_cap(sd, -1), timings))
1409 return 0;
1410 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1411 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1412 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1413 false, state->aspect_ratio,
1414 adv76xx_get_dv_timings_cap(sd, -1), timings))
1415 return 0;
1416
1417 v4l2_dbg(2, debug, sd,
1418 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1419 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1420 stdi->hs_pol, stdi->vs_pol);
1421 return -1;
1422 }
1423
1424
read_stdi(struct v4l2_subdev * sd,struct stdi_readback * stdi)1425 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1426 {
1427 struct adv76xx_state *state = to_state(sd);
1428 const struct adv76xx_chip_info *info = state->info;
1429 u8 polarity;
1430
1431 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1432 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1433 return -1;
1434 }
1435
1436 /* read STDI */
1437 stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
1438 stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
1439 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1440 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1441
1442 if (adv76xx_has_afe(state)) {
1443 /* read SSPD */
1444 polarity = cp_read(sd, 0xb5);
1445 if ((polarity & 0x03) == 0x01) {
1446 stdi->hs_pol = polarity & 0x10
1447 ? (polarity & 0x08 ? '+' : '-') : 'x';
1448 stdi->vs_pol = polarity & 0x40
1449 ? (polarity & 0x20 ? '+' : '-') : 'x';
1450 } else {
1451 stdi->hs_pol = 'x';
1452 stdi->vs_pol = 'x';
1453 }
1454 } else {
1455 polarity = hdmi_read(sd, 0x05);
1456 stdi->hs_pol = polarity & 0x20 ? '+' : '-';
1457 stdi->vs_pol = polarity & 0x10 ? '+' : '-';
1458 }
1459
1460 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1461 v4l2_dbg(2, debug, sd,
1462 "%s: signal lost during readout of STDI/SSPD\n", __func__);
1463 return -1;
1464 }
1465
1466 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1467 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1468 memset(stdi, 0, sizeof(struct stdi_readback));
1469 return -1;
1470 }
1471
1472 v4l2_dbg(2, debug, sd,
1473 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1474 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1475 stdi->hs_pol, stdi->vs_pol,
1476 stdi->interlaced ? "interlaced" : "progressive");
1477
1478 return 0;
1479 }
1480
adv76xx_enum_dv_timings(struct v4l2_subdev * sd,struct v4l2_enum_dv_timings * timings)1481 static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd,
1482 struct v4l2_enum_dv_timings *timings)
1483 {
1484 struct adv76xx_state *state = to_state(sd);
1485
1486 if (timings->pad >= state->source_pad)
1487 return -EINVAL;
1488
1489 return v4l2_enum_dv_timings_cap(timings,
1490 adv76xx_get_dv_timings_cap(sd, timings->pad),
1491 adv76xx_check_dv_timings, NULL);
1492 }
1493
adv76xx_dv_timings_cap(struct v4l2_subdev * sd,struct v4l2_dv_timings_cap * cap)1494 static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd,
1495 struct v4l2_dv_timings_cap *cap)
1496 {
1497 struct adv76xx_state *state = to_state(sd);
1498 unsigned int pad = cap->pad;
1499
1500 if (cap->pad >= state->source_pad)
1501 return -EINVAL;
1502
1503 *cap = *adv76xx_get_dv_timings_cap(sd, pad);
1504 cap->pad = pad;
1505
1506 return 0;
1507 }
1508
1509 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1510 if the format is listed in adv76xx_timings[] */
adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1511 static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1512 struct v4l2_dv_timings *timings)
1513 {
1514 v4l2_find_dv_timings_cap(timings, adv76xx_get_dv_timings_cap(sd, -1),
1515 is_digital_input(sd) ? 250000 : 1000000,
1516 adv76xx_check_dv_timings, NULL);
1517 }
1518
adv7604_read_hdmi_pixelclock(struct v4l2_subdev * sd)1519 static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1520 {
1521 int a, b;
1522
1523 a = hdmi_read(sd, 0x06);
1524 b = hdmi_read(sd, 0x3b);
1525 if (a < 0 || b < 0)
1526 return 0;
1527
1528 return a * 1000000 + ((b & 0x30) >> 4) * 250000;
1529 }
1530
adv7611_read_hdmi_pixelclock(struct v4l2_subdev * sd)1531 static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1532 {
1533 int a, b;
1534
1535 a = hdmi_read(sd, 0x51);
1536 b = hdmi_read(sd, 0x52);
1537 if (a < 0 || b < 0)
1538 return 0;
1539
1540 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
1541 }
1542
adv76xx_read_hdmi_pixelclock(struct v4l2_subdev * sd)1543 static unsigned int adv76xx_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1544 {
1545 struct adv76xx_state *state = to_state(sd);
1546 const struct adv76xx_chip_info *info = state->info;
1547 unsigned int freq, bits_per_channel, pixelrepetition;
1548
1549 freq = info->read_hdmi_pixelclock(sd);
1550 if (is_hdmi(sd)) {
1551 /* adjust for deep color mode and pixel repetition */
1552 bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1553 pixelrepetition = (hdmi_read(sd, 0x05) & 0x0f) + 1;
1554
1555 freq = freq * 8 / bits_per_channel / pixelrepetition;
1556 }
1557
1558 return freq;
1559 }
1560
adv76xx_query_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1561 static int adv76xx_query_dv_timings(struct v4l2_subdev *sd,
1562 struct v4l2_dv_timings *timings)
1563 {
1564 struct adv76xx_state *state = to_state(sd);
1565 const struct adv76xx_chip_info *info = state->info;
1566 struct v4l2_bt_timings *bt = &timings->bt;
1567 struct stdi_readback stdi;
1568
1569 if (!timings)
1570 return -EINVAL;
1571
1572 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1573
1574 if (no_signal(sd)) {
1575 state->restart_stdi_once = true;
1576 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1577 return -ENOLINK;
1578 }
1579
1580 /* read STDI */
1581 if (read_stdi(sd, &stdi)) {
1582 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1583 return -ENOLINK;
1584 }
1585 bt->interlaced = stdi.interlaced ?
1586 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1587
1588 if (is_digital_input(sd)) {
1589 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1590 u8 vic = 0;
1591 u32 w, h;
1592
1593 w = hdmi_read16(sd, 0x07, info->linewidth_mask);
1594 h = hdmi_read16(sd, 0x09, info->field0_height_mask);
1595
1596 if (hdmi_signal && (io_read(sd, 0x60) & 1))
1597 vic = infoframe_read(sd, 0x04);
1598
1599 if (vic && v4l2_find_dv_timings_cea861_vic(timings, vic) &&
1600 bt->width == w && bt->height == h)
1601 goto found;
1602
1603 timings->type = V4L2_DV_BT_656_1120;
1604
1605 bt->width = w;
1606 bt->height = h;
1607 bt->pixelclock = adv76xx_read_hdmi_pixelclock(sd);
1608 bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask);
1609 bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask);
1610 bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask);
1611 bt->vfrontporch = hdmi_read16(sd, 0x2a,
1612 info->field0_vfrontporch_mask) / 2;
1613 bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2;
1614 bt->vbackporch = hdmi_read16(sd, 0x32,
1615 info->field0_vbackporch_mask) / 2;
1616 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1617 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1618 if (bt->interlaced == V4L2_DV_INTERLACED) {
1619 bt->height += hdmi_read16(sd, 0x0b,
1620 info->field1_height_mask);
1621 bt->il_vfrontporch = hdmi_read16(sd, 0x2c,
1622 info->field1_vfrontporch_mask) / 2;
1623 bt->il_vsync = hdmi_read16(sd, 0x30,
1624 info->field1_vsync_mask) / 2;
1625 bt->il_vbackporch = hdmi_read16(sd, 0x34,
1626 info->field1_vbackporch_mask) / 2;
1627 }
1628 adv76xx_fill_optional_dv_timings_fields(sd, timings);
1629 } else {
1630 /* find format
1631 * Since LCVS values are inaccurate [REF_03, p. 275-276],
1632 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1633 */
1634 if (!stdi2dv_timings(sd, &stdi, timings))
1635 goto found;
1636 stdi.lcvs += 1;
1637 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1638 if (!stdi2dv_timings(sd, &stdi, timings))
1639 goto found;
1640 stdi.lcvs -= 2;
1641 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1642 if (stdi2dv_timings(sd, &stdi, timings)) {
1643 /*
1644 * The STDI block may measure wrong values, especially
1645 * for lcvs and lcf. If the driver can not find any
1646 * valid timing, the STDI block is restarted to measure
1647 * the video timings again. The function will return an
1648 * error, but the restart of STDI will generate a new
1649 * STDI interrupt and the format detection process will
1650 * restart.
1651 */
1652 if (state->restart_stdi_once) {
1653 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1654 /* TODO restart STDI for Sync Channel 2 */
1655 /* enter one-shot mode */
1656 cp_write_clr_set(sd, 0x86, 0x06, 0x00);
1657 /* trigger STDI restart */
1658 cp_write_clr_set(sd, 0x86, 0x06, 0x04);
1659 /* reset to continuous mode */
1660 cp_write_clr_set(sd, 0x86, 0x06, 0x02);
1661 state->restart_stdi_once = false;
1662 return -ENOLINK;
1663 }
1664 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1665 return -ERANGE;
1666 }
1667 state->restart_stdi_once = true;
1668 }
1669 found:
1670
1671 if (no_signal(sd)) {
1672 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1673 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1674 return -ENOLINK;
1675 }
1676
1677 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1678 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1679 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1680 __func__, (u32)bt->pixelclock);
1681 return -ERANGE;
1682 }
1683
1684 if (debug > 1)
1685 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ",
1686 timings, true);
1687
1688 return 0;
1689 }
1690
adv76xx_s_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1691 static int adv76xx_s_dv_timings(struct v4l2_subdev *sd,
1692 struct v4l2_dv_timings *timings)
1693 {
1694 struct adv76xx_state *state = to_state(sd);
1695 struct v4l2_bt_timings *bt;
1696 int err;
1697
1698 if (!timings)
1699 return -EINVAL;
1700
1701 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
1702 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1703 return 0;
1704 }
1705
1706 bt = &timings->bt;
1707
1708 if (!v4l2_valid_dv_timings(timings, adv76xx_get_dv_timings_cap(sd, -1),
1709 adv76xx_check_dv_timings, NULL))
1710 return -ERANGE;
1711
1712 adv76xx_fill_optional_dv_timings_fields(sd, timings);
1713
1714 state->timings = *timings;
1715
1716 cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
1717
1718 /* Use prim_mode and vid_std when available */
1719 err = configure_predefined_video_timings(sd, timings);
1720 if (err) {
1721 /* custom settings when the video format
1722 does not have prim_mode/vid_std */
1723 configure_custom_video_timings(sd, bt);
1724 }
1725
1726 set_rgb_quantization_range(sd);
1727
1728 if (debug > 1)
1729 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ",
1730 timings, true);
1731 return 0;
1732 }
1733
adv76xx_g_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1734 static int adv76xx_g_dv_timings(struct v4l2_subdev *sd,
1735 struct v4l2_dv_timings *timings)
1736 {
1737 struct adv76xx_state *state = to_state(sd);
1738
1739 *timings = state->timings;
1740 return 0;
1741 }
1742
adv7604_set_termination(struct v4l2_subdev * sd,bool enable)1743 static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
1744 {
1745 hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
1746 }
1747
adv7611_set_termination(struct v4l2_subdev * sd,bool enable)1748 static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
1749 {
1750 hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
1751 }
1752
enable_input(struct v4l2_subdev * sd)1753 static void enable_input(struct v4l2_subdev *sd)
1754 {
1755 struct adv76xx_state *state = to_state(sd);
1756
1757 if (is_analog_input(sd)) {
1758 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1759 } else if (is_digital_input(sd)) {
1760 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
1761 state->info->set_termination(sd, true);
1762 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
1763 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
1764 } else {
1765 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1766 __func__, state->selected_input);
1767 }
1768 }
1769
disable_input(struct v4l2_subdev * sd)1770 static void disable_input(struct v4l2_subdev *sd)
1771 {
1772 struct adv76xx_state *state = to_state(sd);
1773
1774 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
1775 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
1776 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
1777 state->info->set_termination(sd, false);
1778 }
1779
select_input(struct v4l2_subdev * sd)1780 static void select_input(struct v4l2_subdev *sd)
1781 {
1782 struct adv76xx_state *state = to_state(sd);
1783 const struct adv76xx_chip_info *info = state->info;
1784
1785 if (is_analog_input(sd)) {
1786 adv76xx_write_reg_seq(sd, info->recommended_settings[0]);
1787
1788 afe_write(sd, 0x00, 0x08); /* power up ADC */
1789 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1790 afe_write(sd, 0xc8, 0x00); /* phase control */
1791 } else if (is_digital_input(sd)) {
1792 hdmi_write(sd, 0x00, state->selected_input & 0x03);
1793
1794 adv76xx_write_reg_seq(sd, info->recommended_settings[1]);
1795
1796 if (adv76xx_has_afe(state)) {
1797 afe_write(sd, 0x00, 0xff); /* power down ADC */
1798 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1799 afe_write(sd, 0xc8, 0x40); /* phase control */
1800 }
1801
1802 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1803 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1804 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1805 } else {
1806 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1807 __func__, state->selected_input);
1808 }
1809
1810 /* Enable video adjustment (contrast, saturation, brightness and hue) */
1811 cp_write_clr_set(sd, 0x3e, 0x80, 0x80);
1812 }
1813
adv76xx_s_routing(struct v4l2_subdev * sd,u32 input,u32 output,u32 config)1814 static int adv76xx_s_routing(struct v4l2_subdev *sd,
1815 u32 input, u32 output, u32 config)
1816 {
1817 struct adv76xx_state *state = to_state(sd);
1818
1819 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1820 __func__, input, state->selected_input);
1821
1822 if (input == state->selected_input)
1823 return 0;
1824
1825 if (input > state->info->max_port)
1826 return -EINVAL;
1827
1828 state->selected_input = input;
1829
1830 disable_input(sd);
1831 select_input(sd);
1832 enable_input(sd);
1833
1834 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
1835
1836 return 0;
1837 }
1838
adv76xx_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)1839 static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd,
1840 struct v4l2_subdev_state *sd_state,
1841 struct v4l2_subdev_mbus_code_enum *code)
1842 {
1843 struct adv76xx_state *state = to_state(sd);
1844
1845 if (code->index >= state->info->nformats)
1846 return -EINVAL;
1847
1848 code->code = state->info->formats[code->index].code;
1849
1850 return 0;
1851 }
1852
adv76xx_fill_format(struct adv76xx_state * state,struct v4l2_mbus_framefmt * format)1853 static void adv76xx_fill_format(struct adv76xx_state *state,
1854 struct v4l2_mbus_framefmt *format)
1855 {
1856 memset(format, 0, sizeof(*format));
1857
1858 format->width = state->timings.bt.width;
1859 format->height = state->timings.bt.height;
1860 format->field = V4L2_FIELD_NONE;
1861 format->colorspace = V4L2_COLORSPACE_SRGB;
1862
1863 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
1864 format->colorspace = (state->timings.bt.height <= 576) ?
1865 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1866 }
1867
1868 /*
1869 * Compute the op_ch_sel value required to obtain on the bus the component order
1870 * corresponding to the selected format taking into account bus reordering
1871 * applied by the board at the output of the device.
1872 *
1873 * The following table gives the op_ch_value from the format component order
1874 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
1875 * adv76xx_bus_order value in row).
1876 *
1877 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
1878 * ----------+-------------------------------------------------
1879 * RGB (NOP) | GBR GRB BGR RGB BRG RBG
1880 * GRB (1-2) | BGR RGB GBR GRB RBG BRG
1881 * RBG (2-3) | GRB GBR BRG RBG BGR RGB
1882 * BGR (1-3) | RBG BRG RGB BGR GRB GBR
1883 * BRG (ROR) | BRG RBG GRB GBR RGB BGR
1884 * GBR (ROL) | RGB BGR RBG BRG GBR GRB
1885 */
adv76xx_op_ch_sel(struct adv76xx_state * state)1886 static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state)
1887 {
1888 #define _SEL(a,b,c,d,e,f) { \
1889 ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \
1890 ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f }
1891 #define _BUS(x) [ADV7604_BUS_ORDER_##x]
1892
1893 static const unsigned int op_ch_sel[6][6] = {
1894 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
1895 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
1896 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
1897 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
1898 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
1899 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
1900 };
1901
1902 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
1903 }
1904
adv76xx_setup_format(struct adv76xx_state * state)1905 static void adv76xx_setup_format(struct adv76xx_state *state)
1906 {
1907 struct v4l2_subdev *sd = &state->sd;
1908
1909 io_write_clr_set(sd, 0x02, 0x02,
1910 state->format->rgb_out ? ADV76XX_RGB_OUT : 0);
1911 io_write(sd, 0x03, state->format->op_format_sel |
1912 state->pdata.op_format_mode_sel);
1913 io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state));
1914 io_write_clr_set(sd, 0x05, 0x01,
1915 state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0);
1916 set_rgb_quantization_range(sd);
1917 }
1918
adv76xx_get_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)1919 static int adv76xx_get_format(struct v4l2_subdev *sd,
1920 struct v4l2_subdev_state *sd_state,
1921 struct v4l2_subdev_format *format)
1922 {
1923 struct adv76xx_state *state = to_state(sd);
1924
1925 if (format->pad != state->source_pad)
1926 return -EINVAL;
1927
1928 adv76xx_fill_format(state, &format->format);
1929
1930 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1931 struct v4l2_mbus_framefmt *fmt;
1932
1933 fmt = v4l2_subdev_get_try_format(sd, sd_state, format->pad);
1934 format->format.code = fmt->code;
1935 } else {
1936 format->format.code = state->format->code;
1937 }
1938
1939 return 0;
1940 }
1941
adv76xx_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_selection * sel)1942 static int adv76xx_get_selection(struct v4l2_subdev *sd,
1943 struct v4l2_subdev_state *sd_state,
1944 struct v4l2_subdev_selection *sel)
1945 {
1946 struct adv76xx_state *state = to_state(sd);
1947
1948 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1949 return -EINVAL;
1950 /* Only CROP, CROP_DEFAULT and CROP_BOUNDS are supported */
1951 if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS)
1952 return -EINVAL;
1953
1954 sel->r.left = 0;
1955 sel->r.top = 0;
1956 sel->r.width = state->timings.bt.width;
1957 sel->r.height = state->timings.bt.height;
1958
1959 return 0;
1960 }
1961
adv76xx_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)1962 static int adv76xx_set_format(struct v4l2_subdev *sd,
1963 struct v4l2_subdev_state *sd_state,
1964 struct v4l2_subdev_format *format)
1965 {
1966 struct adv76xx_state *state = to_state(sd);
1967 const struct adv76xx_format_info *info;
1968
1969 if (format->pad != state->source_pad)
1970 return -EINVAL;
1971
1972 info = adv76xx_format_info(state, format->format.code);
1973 if (!info)
1974 info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
1975
1976 adv76xx_fill_format(state, &format->format);
1977 format->format.code = info->code;
1978
1979 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1980 struct v4l2_mbus_framefmt *fmt;
1981
1982 fmt = v4l2_subdev_get_try_format(sd, sd_state, format->pad);
1983 fmt->code = format->format.code;
1984 } else {
1985 state->format = info;
1986 adv76xx_setup_format(state);
1987 }
1988
1989 return 0;
1990 }
1991
1992 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
adv76xx_cec_tx_raw_status(struct v4l2_subdev * sd,u8 tx_raw_status)1993 static void adv76xx_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status)
1994 {
1995 struct adv76xx_state *state = to_state(sd);
1996
1997 if ((cec_read(sd, 0x11) & 0x01) == 0) {
1998 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__);
1999 return;
2000 }
2001
2002 if (tx_raw_status & 0x02) {
2003 v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n",
2004 __func__);
2005 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST,
2006 1, 0, 0, 0);
2007 return;
2008 }
2009 if (tx_raw_status & 0x04) {
2010 u8 status;
2011 u8 nack_cnt;
2012 u8 low_drive_cnt;
2013
2014 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__);
2015 /*
2016 * We set this status bit since this hardware performs
2017 * retransmissions.
2018 */
2019 status = CEC_TX_STATUS_MAX_RETRIES;
2020 nack_cnt = cec_read(sd, 0x14) & 0xf;
2021 if (nack_cnt)
2022 status |= CEC_TX_STATUS_NACK;
2023 low_drive_cnt = cec_read(sd, 0x14) >> 4;
2024 if (low_drive_cnt)
2025 status |= CEC_TX_STATUS_LOW_DRIVE;
2026 cec_transmit_done(state->cec_adap, status,
2027 0, nack_cnt, low_drive_cnt, 0);
2028 return;
2029 }
2030 if (tx_raw_status & 0x01) {
2031 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__);
2032 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);
2033 return;
2034 }
2035 }
2036
adv76xx_cec_isr(struct v4l2_subdev * sd,bool * handled)2037 static void adv76xx_cec_isr(struct v4l2_subdev *sd, bool *handled)
2038 {
2039 struct adv76xx_state *state = to_state(sd);
2040 const struct adv76xx_chip_info *info = state->info;
2041 u8 cec_irq;
2042
2043 /* cec controller */
2044 cec_irq = io_read(sd, info->cec_irq_status) & 0x0f;
2045 if (!cec_irq)
2046 return;
2047
2048 v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq);
2049 adv76xx_cec_tx_raw_status(sd, cec_irq);
2050 if (cec_irq & 0x08) {
2051 struct cec_msg msg;
2052
2053 msg.len = cec_read(sd, 0x25) & 0x1f;
2054 if (msg.len > CEC_MAX_MSG_SIZE)
2055 msg.len = CEC_MAX_MSG_SIZE;
2056
2057 if (msg.len) {
2058 u8 i;
2059
2060 for (i = 0; i < msg.len; i++)
2061 msg.msg[i] = cec_read(sd, i + 0x15);
2062 cec_write(sd, info->cec_rx_enable,
2063 info->cec_rx_enable_mask); /* re-enable rx */
2064 cec_received_msg(state->cec_adap, &msg);
2065 }
2066 }
2067
2068 if (info->cec_irq_swap) {
2069 /*
2070 * Note: the bit order is swapped between 0x4d and 0x4e
2071 * on adv7604
2072 */
2073 cec_irq = ((cec_irq & 0x08) >> 3) | ((cec_irq & 0x04) >> 1) |
2074 ((cec_irq & 0x02) << 1) | ((cec_irq & 0x01) << 3);
2075 }
2076 io_write(sd, info->cec_irq_status + 1, cec_irq);
2077
2078 if (handled)
2079 *handled = true;
2080 }
2081
adv76xx_cec_adap_enable(struct cec_adapter * adap,bool enable)2082 static int adv76xx_cec_adap_enable(struct cec_adapter *adap, bool enable)
2083 {
2084 struct adv76xx_state *state = cec_get_drvdata(adap);
2085 const struct adv76xx_chip_info *info = state->info;
2086 struct v4l2_subdev *sd = &state->sd;
2087
2088 if (!state->cec_enabled_adap && enable) {
2089 cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */
2090 cec_write(sd, 0x2c, 0x01); /* cec soft reset */
2091 cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */
2092 /* enabled irqs: */
2093 /* tx: ready */
2094 /* tx: arbitration lost */
2095 /* tx: retry timeout */
2096 /* rx: ready */
2097 io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x0f);
2098 cec_write(sd, info->cec_rx_enable, info->cec_rx_enable_mask);
2099 } else if (state->cec_enabled_adap && !enable) {
2100 /* disable cec interrupts */
2101 io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x00);
2102 /* disable address mask 1-3 */
2103 cec_write_clr_set(sd, 0x27, 0x70, 0x00);
2104 /* power down cec section */
2105 cec_write_clr_set(sd, 0x2a, 0x01, 0x00);
2106 state->cec_valid_addrs = 0;
2107 }
2108 state->cec_enabled_adap = enable;
2109 adv76xx_s_detect_tx_5v_ctrl(sd);
2110 return 0;
2111 }
2112
adv76xx_cec_adap_log_addr(struct cec_adapter * adap,u8 addr)2113 static int adv76xx_cec_adap_log_addr(struct cec_adapter *adap, u8 addr)
2114 {
2115 struct adv76xx_state *state = cec_get_drvdata(adap);
2116 struct v4l2_subdev *sd = &state->sd;
2117 unsigned int i, free_idx = ADV76XX_MAX_ADDRS;
2118
2119 if (!state->cec_enabled_adap)
2120 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO;
2121
2122 if (addr == CEC_LOG_ADDR_INVALID) {
2123 cec_write_clr_set(sd, 0x27, 0x70, 0);
2124 state->cec_valid_addrs = 0;
2125 return 0;
2126 }
2127
2128 for (i = 0; i < ADV76XX_MAX_ADDRS; i++) {
2129 bool is_valid = state->cec_valid_addrs & (1 << i);
2130
2131 if (free_idx == ADV76XX_MAX_ADDRS && !is_valid)
2132 free_idx = i;
2133 if (is_valid && state->cec_addr[i] == addr)
2134 return 0;
2135 }
2136 if (i == ADV76XX_MAX_ADDRS) {
2137 i = free_idx;
2138 if (i == ADV76XX_MAX_ADDRS)
2139 return -ENXIO;
2140 }
2141 state->cec_addr[i] = addr;
2142 state->cec_valid_addrs |= 1 << i;
2143
2144 switch (i) {
2145 case 0:
2146 /* enable address mask 0 */
2147 cec_write_clr_set(sd, 0x27, 0x10, 0x10);
2148 /* set address for mask 0 */
2149 cec_write_clr_set(sd, 0x28, 0x0f, addr);
2150 break;
2151 case 1:
2152 /* enable address mask 1 */
2153 cec_write_clr_set(sd, 0x27, 0x20, 0x20);
2154 /* set address for mask 1 */
2155 cec_write_clr_set(sd, 0x28, 0xf0, addr << 4);
2156 break;
2157 case 2:
2158 /* enable address mask 2 */
2159 cec_write_clr_set(sd, 0x27, 0x40, 0x40);
2160 /* set address for mask 1 */
2161 cec_write_clr_set(sd, 0x29, 0x0f, addr);
2162 break;
2163 }
2164 return 0;
2165 }
2166
adv76xx_cec_adap_transmit(struct cec_adapter * adap,u8 attempts,u32 signal_free_time,struct cec_msg * msg)2167 static int adv76xx_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2168 u32 signal_free_time, struct cec_msg *msg)
2169 {
2170 struct adv76xx_state *state = cec_get_drvdata(adap);
2171 struct v4l2_subdev *sd = &state->sd;
2172 u8 len = msg->len;
2173 unsigned int i;
2174
2175 /*
2176 * The number of retries is the number of attempts - 1, but retry
2177 * at least once. It's not clear if a value of 0 is allowed, so
2178 * let's do at least one retry.
2179 */
2180 cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4);
2181
2182 if (len > 16) {
2183 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len);
2184 return -EINVAL;
2185 }
2186
2187 /* write data */
2188 for (i = 0; i < len; i++)
2189 cec_write(sd, i, msg->msg[i]);
2190
2191 /* set length (data + header) */
2192 cec_write(sd, 0x10, len);
2193 /* start transmit, enable tx */
2194 cec_write(sd, 0x11, 0x01);
2195 return 0;
2196 }
2197
2198 static const struct cec_adap_ops adv76xx_cec_adap_ops = {
2199 .adap_enable = adv76xx_cec_adap_enable,
2200 .adap_log_addr = adv76xx_cec_adap_log_addr,
2201 .adap_transmit = adv76xx_cec_adap_transmit,
2202 };
2203 #endif
2204
adv76xx_isr(struct v4l2_subdev * sd,u32 status,bool * handled)2205 static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
2206 {
2207 struct adv76xx_state *state = to_state(sd);
2208 const struct adv76xx_chip_info *info = state->info;
2209 const u8 irq_reg_0x43 = io_read(sd, 0x43);
2210 const u8 irq_reg_0x6b = io_read(sd, 0x6b);
2211 const u8 irq_reg_0x70 = io_read(sd, 0x70);
2212 u8 fmt_change_digital;
2213 u8 fmt_change;
2214 u8 tx_5v;
2215
2216 if (irq_reg_0x43)
2217 io_write(sd, 0x44, irq_reg_0x43);
2218 if (irq_reg_0x70)
2219 io_write(sd, 0x71, irq_reg_0x70);
2220 if (irq_reg_0x6b)
2221 io_write(sd, 0x6c, irq_reg_0x6b);
2222
2223 v4l2_dbg(2, debug, sd, "%s: ", __func__);
2224
2225 /* format change */
2226 fmt_change = irq_reg_0x43 & 0x98;
2227 fmt_change_digital = is_digital_input(sd)
2228 ? irq_reg_0x6b & info->fmt_change_digital_mask
2229 : 0;
2230
2231 if (fmt_change || fmt_change_digital) {
2232 v4l2_dbg(1, debug, sd,
2233 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
2234 __func__, fmt_change, fmt_change_digital);
2235
2236 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
2237
2238 if (handled)
2239 *handled = true;
2240 }
2241 /* HDMI/DVI mode */
2242 if (irq_reg_0x6b & 0x01) {
2243 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
2244 (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
2245 set_rgb_quantization_range(sd);
2246 if (handled)
2247 *handled = true;
2248 }
2249
2250 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
2251 /* cec */
2252 adv76xx_cec_isr(sd, handled);
2253 #endif
2254
2255 /* tx 5v detect */
2256 tx_5v = irq_reg_0x70 & info->cable_det_mask;
2257 if (tx_5v) {
2258 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
2259 adv76xx_s_detect_tx_5v_ctrl(sd);
2260 if (handled)
2261 *handled = true;
2262 }
2263 return 0;
2264 }
2265
adv76xx_irq_handler(int irq,void * dev_id)2266 static irqreturn_t adv76xx_irq_handler(int irq, void *dev_id)
2267 {
2268 struct adv76xx_state *state = dev_id;
2269 bool handled = false;
2270
2271 adv76xx_isr(&state->sd, 0, &handled);
2272
2273 return handled ? IRQ_HANDLED : IRQ_NONE;
2274 }
2275
adv76xx_get_edid(struct v4l2_subdev * sd,struct v4l2_edid * edid)2276 static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2277 {
2278 struct adv76xx_state *state = to_state(sd);
2279 u8 *data = NULL;
2280
2281 memset(edid->reserved, 0, sizeof(edid->reserved));
2282
2283 switch (edid->pad) {
2284 case ADV76XX_PAD_HDMI_PORT_A:
2285 case ADV7604_PAD_HDMI_PORT_B:
2286 case ADV7604_PAD_HDMI_PORT_C:
2287 case ADV7604_PAD_HDMI_PORT_D:
2288 if (state->edid.present & (1 << edid->pad))
2289 data = state->edid.edid;
2290 break;
2291 default:
2292 return -EINVAL;
2293 }
2294
2295 if (edid->start_block == 0 && edid->blocks == 0) {
2296 edid->blocks = data ? state->edid.blocks : 0;
2297 return 0;
2298 }
2299
2300 if (!data)
2301 return -ENODATA;
2302
2303 if (edid->start_block >= state->edid.blocks)
2304 return -EINVAL;
2305
2306 if (edid->start_block + edid->blocks > state->edid.blocks)
2307 edid->blocks = state->edid.blocks - edid->start_block;
2308
2309 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
2310
2311 return 0;
2312 }
2313
adv76xx_set_edid(struct v4l2_subdev * sd,struct v4l2_edid * edid)2314 static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2315 {
2316 struct adv76xx_state *state = to_state(sd);
2317 const struct adv76xx_chip_info *info = state->info;
2318 unsigned int spa_loc;
2319 u16 pa, parent_pa;
2320 int err;
2321 int i;
2322
2323 memset(edid->reserved, 0, sizeof(edid->reserved));
2324
2325 if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
2326 return -EINVAL;
2327 if (edid->start_block != 0)
2328 return -EINVAL;
2329 if (edid->blocks == 0) {
2330 /* Disable hotplug and I2C access to EDID RAM from DDC port */
2331 state->edid.present &= ~(1 << edid->pad);
2332 adv76xx_set_hpd(state, state->edid.present);
2333 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2334
2335 /* Fall back to a 16:9 aspect ratio */
2336 state->aspect_ratio.numerator = 16;
2337 state->aspect_ratio.denominator = 9;
2338
2339 if (!state->edid.present) {
2340 state->edid.blocks = 0;
2341 cec_phys_addr_invalidate(state->cec_adap);
2342 }
2343
2344 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
2345 __func__, edid->pad, state->edid.present);
2346 return 0;
2347 }
2348 if (edid->blocks > ADV76XX_MAX_EDID_BLOCKS) {
2349 edid->blocks = ADV76XX_MAX_EDID_BLOCKS;
2350 return -E2BIG;
2351 }
2352
2353 pa = v4l2_get_edid_phys_addr(edid->edid, edid->blocks * 128, &spa_loc);
2354 err = v4l2_phys_addr_validate(pa, &parent_pa, NULL);
2355 if (err)
2356 return err;
2357
2358 if (!spa_loc) {
2359 /*
2360 * There is no SPA, so just set spa_loc to 128 and pa to whatever
2361 * data is there.
2362 */
2363 spa_loc = 128;
2364 pa = (edid->edid[spa_loc] << 8) | edid->edid[spa_loc + 1];
2365 }
2366
2367 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
2368 __func__, edid->pad, state->edid.present);
2369
2370 /* Disable hotplug and I2C access to EDID RAM from DDC port */
2371 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
2372 adv76xx_set_hpd(state, 0);
2373 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
2374
2375 switch (edid->pad) {
2376 case ADV76XX_PAD_HDMI_PORT_A:
2377 state->spa_port_a[0] = pa >> 8;
2378 state->spa_port_a[1] = pa & 0xff;
2379 break;
2380 case ADV7604_PAD_HDMI_PORT_B:
2381 rep_write(sd, info->edid_spa_port_b_reg, pa >> 8);
2382 rep_write(sd, info->edid_spa_port_b_reg + 1, pa & 0xff);
2383 break;
2384 case ADV7604_PAD_HDMI_PORT_C:
2385 rep_write(sd, info->edid_spa_port_b_reg + 2, pa >> 8);
2386 rep_write(sd, info->edid_spa_port_b_reg + 3, pa & 0xff);
2387 break;
2388 case ADV7604_PAD_HDMI_PORT_D:
2389 rep_write(sd, info->edid_spa_port_b_reg + 4, pa >> 8);
2390 rep_write(sd, info->edid_spa_port_b_reg + 5, pa & 0xff);
2391 break;
2392 default:
2393 return -EINVAL;
2394 }
2395
2396 if (info->edid_spa_loc_reg) {
2397 u8 mask = info->edid_spa_loc_msb_mask;
2398
2399 rep_write(sd, info->edid_spa_loc_reg, spa_loc & 0xff);
2400 rep_write_clr_set(sd, info->edid_spa_loc_reg + 1,
2401 mask, (spa_loc & 0x100) ? mask : 0);
2402 }
2403
2404 edid->edid[spa_loc] = state->spa_port_a[0];
2405 edid->edid[spa_loc + 1] = state->spa_port_a[1];
2406
2407 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
2408 state->edid.blocks = edid->blocks;
2409 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
2410 edid->edid[0x16]);
2411 state->edid.present |= 1 << edid->pad;
2412
2413 rep_write_clr_set(sd, info->edid_segment_reg,
2414 info->edid_segment_mask, 0);
2415 err = edid_write_block(sd, 128 * min(edid->blocks, 2U), state->edid.edid);
2416 if (err < 0) {
2417 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
2418 return err;
2419 }
2420 if (edid->blocks > 2) {
2421 rep_write_clr_set(sd, info->edid_segment_reg,
2422 info->edid_segment_mask,
2423 info->edid_segment_mask);
2424 err = edid_write_block(sd, 128 * (edid->blocks - 2),
2425 state->edid.edid + 256);
2426 if (err < 0) {
2427 v4l2_err(sd, "error %d writing edid pad %d\n",
2428 err, edid->pad);
2429 return err;
2430 }
2431 }
2432
2433 /* adv76xx calculates the checksums and enables I2C access to internal
2434 EDID RAM from DDC port. */
2435 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2436
2437 for (i = 0; i < 1000; i++) {
2438 if (rep_read(sd, info->edid_status_reg) & state->edid.present)
2439 break;
2440 mdelay(1);
2441 }
2442 if (i == 1000) {
2443 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
2444 return -EIO;
2445 }
2446 cec_s_phys_addr(state->cec_adap, parent_pa, false);
2447
2448 /* enable hotplug after 100 ms */
2449 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10);
2450 return 0;
2451 }
2452
2453 /*********** avi info frame CEA-861-E **************/
2454
2455 static const struct adv76xx_cfg_read_infoframe adv76xx_cri[] = {
2456 { "AVI", 0x01, 0xe0, 0x00 },
2457 { "Audio", 0x02, 0xe3, 0x1c },
2458 { "SDP", 0x04, 0xe6, 0x2a },
2459 { "Vendor", 0x10, 0xec, 0x54 }
2460 };
2461
adv76xx_read_infoframe(struct v4l2_subdev * sd,int index,union hdmi_infoframe * frame)2462 static int adv76xx_read_infoframe(struct v4l2_subdev *sd, int index,
2463 union hdmi_infoframe *frame)
2464 {
2465 uint8_t buffer[32];
2466 u8 len;
2467 int i;
2468
2469 if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) {
2470 v4l2_info(sd, "%s infoframe not received\n",
2471 adv76xx_cri[index].desc);
2472 return -ENOENT;
2473 }
2474
2475 for (i = 0; i < 3; i++)
2476 buffer[i] = infoframe_read(sd,
2477 adv76xx_cri[index].head_addr + i);
2478
2479 len = buffer[2] + 1;
2480
2481 if (len + 3 > sizeof(buffer)) {
2482 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__,
2483 adv76xx_cri[index].desc, len);
2484 return -ENOENT;
2485 }
2486
2487 for (i = 0; i < len; i++)
2488 buffer[i + 3] = infoframe_read(sd,
2489 adv76xx_cri[index].payload_addr + i);
2490
2491 if (hdmi_infoframe_unpack(frame, buffer, len + 3) < 0) {
2492 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__,
2493 adv76xx_cri[index].desc);
2494 return -ENOENT;
2495 }
2496 return 0;
2497 }
2498
adv76xx_log_infoframes(struct v4l2_subdev * sd)2499 static void adv76xx_log_infoframes(struct v4l2_subdev *sd)
2500 {
2501 int i;
2502
2503 if (!is_hdmi(sd)) {
2504 v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
2505 return;
2506 }
2507
2508 for (i = 0; i < ARRAY_SIZE(adv76xx_cri); i++) {
2509 union hdmi_infoframe frame;
2510 struct i2c_client *client = v4l2_get_subdevdata(sd);
2511
2512 if (!adv76xx_read_infoframe(sd, i, &frame))
2513 hdmi_infoframe_log(KERN_INFO, &client->dev, &frame);
2514 }
2515 }
2516
adv76xx_log_status(struct v4l2_subdev * sd)2517 static int adv76xx_log_status(struct v4l2_subdev *sd)
2518 {
2519 struct adv76xx_state *state = to_state(sd);
2520 const struct adv76xx_chip_info *info = state->info;
2521 struct v4l2_dv_timings timings;
2522 struct stdi_readback stdi;
2523 int ret;
2524 u8 reg_io_0x02;
2525 u8 edid_enabled;
2526 u8 cable_det;
2527 static const char * const csc_coeff_sel_rb[16] = {
2528 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2529 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2530 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2531 "reserved", "reserved", "reserved", "reserved", "manual"
2532 };
2533 static const char * const input_color_space_txt[16] = {
2534 "RGB limited range (16-235)", "RGB full range (0-255)",
2535 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2536 "xvYCC Bt.601", "xvYCC Bt.709",
2537 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2538 "invalid", "invalid", "invalid", "invalid", "invalid",
2539 "invalid", "invalid", "automatic"
2540 };
2541 static const char * const hdmi_color_space_txt[16] = {
2542 "RGB limited range (16-235)", "RGB full range (0-255)",
2543 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2544 "xvYCC Bt.601", "xvYCC Bt.709",
2545 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2546 "sYCC", "opYCC 601", "opRGB", "invalid", "invalid",
2547 "invalid", "invalid", "invalid"
2548 };
2549 static const char * const rgb_quantization_range_txt[] = {
2550 "Automatic",
2551 "RGB limited range (16-235)",
2552 "RGB full range (0-255)",
2553 };
2554 static const char * const deep_color_mode_txt[4] = {
2555 "8-bits per channel",
2556 "10-bits per channel",
2557 "12-bits per channel",
2558 "16-bits per channel (not supported)"
2559 };
2560
2561 v4l2_info(sd, "-----Chip status-----\n");
2562 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2563 edid_enabled = rep_read(sd, info->edid_status_reg);
2564 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
2565 ((edid_enabled & 0x01) ? "Yes" : "No"),
2566 ((edid_enabled & 0x02) ? "Yes" : "No"),
2567 ((edid_enabled & 0x04) ? "Yes" : "No"),
2568 ((edid_enabled & 0x08) ? "Yes" : "No"));
2569 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ?
2570 "enabled" : "disabled");
2571 if (state->cec_enabled_adap) {
2572 int i;
2573
2574 for (i = 0; i < ADV76XX_MAX_ADDRS; i++) {
2575 bool is_valid = state->cec_valid_addrs & (1 << i);
2576
2577 if (is_valid)
2578 v4l2_info(sd, "CEC Logical Address: 0x%x\n",
2579 state->cec_addr[i]);
2580 }
2581 }
2582
2583 v4l2_info(sd, "-----Signal status-----\n");
2584 cable_det = info->read_cable_det(sd);
2585 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
2586 ((cable_det & 0x01) ? "Yes" : "No"),
2587 ((cable_det & 0x02) ? "Yes" : "No"),
2588 ((cable_det & 0x04) ? "Yes" : "No"),
2589 ((cable_det & 0x08) ? "Yes" : "No"));
2590 v4l2_info(sd, "TMDS signal detected: %s\n",
2591 no_signal_tmds(sd) ? "false" : "true");
2592 v4l2_info(sd, "TMDS signal locked: %s\n",
2593 no_lock_tmds(sd) ? "false" : "true");
2594 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
2595 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
2596 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
2597 v4l2_info(sd, "CP free run: %s\n",
2598 (in_free_run(sd)) ? "on" : "off");
2599 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2600 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2601 (io_read(sd, 0x01) & 0x70) >> 4);
2602
2603 v4l2_info(sd, "-----Video Timings-----\n");
2604 if (read_stdi(sd, &stdi))
2605 v4l2_info(sd, "STDI: not locked\n");
2606 else
2607 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
2608 stdi.lcf, stdi.bl, stdi.lcvs,
2609 stdi.interlaced ? "interlaced" : "progressive",
2610 stdi.hs_pol, stdi.vs_pol);
2611 if (adv76xx_query_dv_timings(sd, &timings))
2612 v4l2_info(sd, "No video detected\n");
2613 else
2614 v4l2_print_dv_timings(sd->name, "Detected format: ",
2615 &timings, true);
2616 v4l2_print_dv_timings(sd->name, "Configured format: ",
2617 &state->timings, true);
2618
2619 if (no_signal(sd))
2620 return 0;
2621
2622 v4l2_info(sd, "-----Color space-----\n");
2623 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2624 rgb_quantization_range_txt[state->rgb_quantization_range]);
2625
2626 ret = io_read(sd, 0x02);
2627 if (ret < 0) {
2628 v4l2_info(sd, "Can't read Input/Output color space\n");
2629 } else {
2630 reg_io_0x02 = ret;
2631
2632 v4l2_info(sd, "Input color space: %s\n",
2633 input_color_space_txt[reg_io_0x02 >> 4]);
2634 v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n",
2635 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2636 (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ?
2637 "(16-235)" : "(0-255)",
2638 (reg_io_0x02 & 0x08) ? "enabled" : "disabled");
2639 }
2640 v4l2_info(sd, "Color space conversion: %s\n",
2641 csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]);
2642
2643 if (!is_digital_input(sd))
2644 return 0;
2645
2646 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2647 v4l2_info(sd, "Digital video port selected: %c\n",
2648 (hdmi_read(sd, 0x00) & 0x03) + 'A');
2649 v4l2_info(sd, "HDCP encrypted content: %s\n",
2650 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2651 v4l2_info(sd, "HDCP keys read: %s%s\n",
2652 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2653 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2654 if (is_hdmi(sd)) {
2655 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2656 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2657 bool audio_mute = io_read(sd, 0x65) & 0x40;
2658
2659 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2660 audio_pll_locked ? "locked" : "not locked",
2661 audio_sample_packet_detect ? "detected" : "not detected",
2662 audio_mute ? "muted" : "enabled");
2663 if (audio_pll_locked && audio_sample_packet_detect) {
2664 v4l2_info(sd, "Audio format: %s\n",
2665 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
2666 }
2667 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2668 (hdmi_read(sd, 0x5c) << 8) +
2669 (hdmi_read(sd, 0x5d) & 0xf0));
2670 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2671 (hdmi_read(sd, 0x5e) << 8) +
2672 hdmi_read(sd, 0x5f));
2673 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2674
2675 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
2676 v4l2_info(sd, "HDMI colorspace: %s\n", hdmi_color_space_txt[hdmi_read(sd, 0x53) & 0xf]);
2677
2678 adv76xx_log_infoframes(sd);
2679 }
2680
2681 return 0;
2682 }
2683
adv76xx_subscribe_event(struct v4l2_subdev * sd,struct v4l2_fh * fh,struct v4l2_event_subscription * sub)2684 static int adv76xx_subscribe_event(struct v4l2_subdev *sd,
2685 struct v4l2_fh *fh,
2686 struct v4l2_event_subscription *sub)
2687 {
2688 switch (sub->type) {
2689 case V4L2_EVENT_SOURCE_CHANGE:
2690 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
2691 case V4L2_EVENT_CTRL:
2692 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
2693 default:
2694 return -EINVAL;
2695 }
2696 }
2697
adv76xx_registered(struct v4l2_subdev * sd)2698 static int adv76xx_registered(struct v4l2_subdev *sd)
2699 {
2700 struct adv76xx_state *state = to_state(sd);
2701 struct i2c_client *client = v4l2_get_subdevdata(sd);
2702 int err;
2703
2704 err = cec_register_adapter(state->cec_adap, &client->dev);
2705 if (err)
2706 cec_delete_adapter(state->cec_adap);
2707 return err;
2708 }
2709
adv76xx_unregistered(struct v4l2_subdev * sd)2710 static void adv76xx_unregistered(struct v4l2_subdev *sd)
2711 {
2712 struct adv76xx_state *state = to_state(sd);
2713
2714 cec_unregister_adapter(state->cec_adap);
2715 }
2716
2717 /* ----------------------------------------------------------------------- */
2718
2719 static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = {
2720 .s_ctrl = adv76xx_s_ctrl,
2721 .g_volatile_ctrl = adv76xx_g_volatile_ctrl,
2722 };
2723
2724 static const struct v4l2_subdev_core_ops adv76xx_core_ops = {
2725 .log_status = adv76xx_log_status,
2726 .interrupt_service_routine = adv76xx_isr,
2727 .subscribe_event = adv76xx_subscribe_event,
2728 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
2729 #ifdef CONFIG_VIDEO_ADV_DEBUG
2730 .g_register = adv76xx_g_register,
2731 .s_register = adv76xx_s_register,
2732 #endif
2733 };
2734
2735 static const struct v4l2_subdev_video_ops adv76xx_video_ops = {
2736 .s_routing = adv76xx_s_routing,
2737 .g_input_status = adv76xx_g_input_status,
2738 .s_dv_timings = adv76xx_s_dv_timings,
2739 .g_dv_timings = adv76xx_g_dv_timings,
2740 .query_dv_timings = adv76xx_query_dv_timings,
2741 };
2742
2743 static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = {
2744 .enum_mbus_code = adv76xx_enum_mbus_code,
2745 .get_selection = adv76xx_get_selection,
2746 .get_fmt = adv76xx_get_format,
2747 .set_fmt = adv76xx_set_format,
2748 .get_edid = adv76xx_get_edid,
2749 .set_edid = adv76xx_set_edid,
2750 .dv_timings_cap = adv76xx_dv_timings_cap,
2751 .enum_dv_timings = adv76xx_enum_dv_timings,
2752 };
2753
2754 static const struct v4l2_subdev_ops adv76xx_ops = {
2755 .core = &adv76xx_core_ops,
2756 .video = &adv76xx_video_ops,
2757 .pad = &adv76xx_pad_ops,
2758 };
2759
2760 static const struct v4l2_subdev_internal_ops adv76xx_int_ops = {
2761 .registered = adv76xx_registered,
2762 .unregistered = adv76xx_unregistered,
2763 };
2764
2765 /* -------------------------- custom ctrls ---------------------------------- */
2766
2767 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
2768 .ops = &adv76xx_ctrl_ops,
2769 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2770 .name = "Analog Sampling Phase",
2771 .type = V4L2_CTRL_TYPE_INTEGER,
2772 .min = 0,
2773 .max = 0x1f,
2774 .step = 1,
2775 .def = 0,
2776 };
2777
2778 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = {
2779 .ops = &adv76xx_ctrl_ops,
2780 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2781 .name = "Free Running Color, Manual",
2782 .type = V4L2_CTRL_TYPE_BOOLEAN,
2783 .min = false,
2784 .max = true,
2785 .step = 1,
2786 .def = false,
2787 };
2788
2789 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = {
2790 .ops = &adv76xx_ctrl_ops,
2791 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2792 .name = "Free Running Color",
2793 .type = V4L2_CTRL_TYPE_INTEGER,
2794 .min = 0x0,
2795 .max = 0xffffff,
2796 .step = 0x1,
2797 .def = 0x0,
2798 };
2799
2800 /* ----------------------------------------------------------------------- */
2801
2802 struct adv76xx_register_map {
2803 const char *name;
2804 u8 default_addr;
2805 };
2806
2807 static const struct adv76xx_register_map adv76xx_default_addresses[] = {
2808 [ADV76XX_PAGE_IO] = { "main", 0x4c },
2809 [ADV7604_PAGE_AVLINK] = { "avlink", 0x42 },
2810 [ADV76XX_PAGE_CEC] = { "cec", 0x40 },
2811 [ADV76XX_PAGE_INFOFRAME] = { "infoframe", 0x3e },
2812 [ADV7604_PAGE_ESDP] = { "esdp", 0x38 },
2813 [ADV7604_PAGE_DPP] = { "dpp", 0x3c },
2814 [ADV76XX_PAGE_AFE] = { "afe", 0x26 },
2815 [ADV76XX_PAGE_REP] = { "rep", 0x32 },
2816 [ADV76XX_PAGE_EDID] = { "edid", 0x36 },
2817 [ADV76XX_PAGE_HDMI] = { "hdmi", 0x34 },
2818 [ADV76XX_PAGE_TEST] = { "test", 0x30 },
2819 [ADV76XX_PAGE_CP] = { "cp", 0x22 },
2820 [ADV7604_PAGE_VDP] = { "vdp", 0x24 },
2821 };
2822
adv76xx_core_init(struct v4l2_subdev * sd)2823 static int adv76xx_core_init(struct v4l2_subdev *sd)
2824 {
2825 struct adv76xx_state *state = to_state(sd);
2826 const struct adv76xx_chip_info *info = state->info;
2827 struct adv76xx_platform_data *pdata = &state->pdata;
2828
2829 hdmi_write(sd, 0x48,
2830 (pdata->disable_pwrdnb ? 0x80 : 0) |
2831 (pdata->disable_cable_det_rst ? 0x40 : 0));
2832
2833 disable_input(sd);
2834
2835 if (pdata->default_input >= 0 &&
2836 pdata->default_input < state->source_pad) {
2837 state->selected_input = pdata->default_input;
2838 select_input(sd);
2839 enable_input(sd);
2840 }
2841
2842 /* power */
2843 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2844 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
2845 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
2846
2847 /* HPD */
2848 if (info->type != ADV7604) {
2849 /* Set manual HPD values to 0 */
2850 io_write_clr_set(sd, 0x20, 0xc0, 0);
2851 /*
2852 * Set HPA_DELAY to 200 ms and set automatic HPD control
2853 * to: internal EDID is active AND a cable is detected
2854 * AND the manual HPD control is set to 1.
2855 */
2856 hdmi_write_clr_set(sd, 0x6c, 0xf6, 0x26);
2857 }
2858
2859 /* video format */
2860 io_write_clr_set(sd, 0x02, 0x0f, pdata->alt_gamma << 3);
2861 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
2862 pdata->insert_av_codes << 2 |
2863 pdata->replicate_av_codes << 1);
2864 adv76xx_setup_format(state);
2865
2866 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
2867
2868 /* VS, HS polarities */
2869 io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 |
2870 pdata->inv_hs_pol << 1 | pdata->inv_llc_pol);
2871
2872 /* Adjust drive strength */
2873 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2874 pdata->dr_str_clk << 2 |
2875 pdata->dr_str_sync);
2876
2877 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2878 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2879 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
2880 ADI recommended setting [REF_01, c. 2.3.3] */
2881 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
2882 ADI recommended setting [REF_01, c. 2.3.3] */
2883 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2884 for digital formats */
2885
2886 /* HDMI audio */
2887 hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2888 hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
2889 hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
2890
2891 /* TODO from platform data */
2892 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2893
2894 if (adv76xx_has_afe(state)) {
2895 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2896 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
2897 }
2898
2899 /* interrupts */
2900 io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */
2901 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
2902 io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2903 io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */
2904 info->setup_irqs(sd);
2905
2906 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2907 }
2908
adv7604_setup_irqs(struct v4l2_subdev * sd)2909 static void adv7604_setup_irqs(struct v4l2_subdev *sd)
2910 {
2911 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2912 }
2913
adv7611_setup_irqs(struct v4l2_subdev * sd)2914 static void adv7611_setup_irqs(struct v4l2_subdev *sd)
2915 {
2916 io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
2917 }
2918
adv7612_setup_irqs(struct v4l2_subdev * sd)2919 static void adv7612_setup_irqs(struct v4l2_subdev *sd)
2920 {
2921 io_write(sd, 0x41, 0xd0); /* disable INT2 */
2922 }
2923
adv76xx_unregister_clients(struct adv76xx_state * state)2924 static void adv76xx_unregister_clients(struct adv76xx_state *state)
2925 {
2926 unsigned int i;
2927
2928 for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i)
2929 i2c_unregister_device(state->i2c_clients[i]);
2930 }
2931
adv76xx_dummy_client(struct v4l2_subdev * sd,unsigned int page)2932 static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd,
2933 unsigned int page)
2934 {
2935 struct i2c_client *client = v4l2_get_subdevdata(sd);
2936 struct adv76xx_state *state = to_state(sd);
2937 struct adv76xx_platform_data *pdata = &state->pdata;
2938 unsigned int io_reg = 0xf2 + page;
2939 struct i2c_client *new_client;
2940
2941 if (pdata && pdata->i2c_addresses[page])
2942 new_client = i2c_new_dummy_device(client->adapter,
2943 pdata->i2c_addresses[page]);
2944 else
2945 new_client = i2c_new_ancillary_device(client,
2946 adv76xx_default_addresses[page].name,
2947 adv76xx_default_addresses[page].default_addr);
2948
2949 if (!IS_ERR(new_client))
2950 io_write(sd, io_reg, new_client->addr << 1);
2951
2952 return new_client;
2953 }
2954
2955 static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = {
2956 /* reset ADI recommended settings for HDMI: */
2957 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2958 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2959 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2960 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2961 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
2962 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2963 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
2964 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
2965 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2966 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2967 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
2968 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
2969 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
2970
2971 /* set ADI recommended settings for digitizer */
2972 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2973 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
2974 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
2975 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2976 { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
2977 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
2978
2979 { ADV76XX_REG_SEQ_TERM, 0 },
2980 };
2981
2982 static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = {
2983 /* set ADI recommended settings for HDMI: */
2984 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2985 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
2986 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
2987 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
2988 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2989 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
2990 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
2991 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2992 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2993 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
2994 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
2995 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
2996
2997 /* reset ADI recommended settings for digitizer */
2998 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2999 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
3000 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
3001
3002 { ADV76XX_REG_SEQ_TERM, 0 },
3003 };
3004
3005 static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = {
3006 /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */
3007 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
3008 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
3009 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
3010 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
3011 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
3012 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
3013 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
3014 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
3015 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
3016 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 },
3017 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e },
3018
3019 { ADV76XX_REG_SEQ_TERM, 0 },
3020 };
3021
3022 static const struct adv76xx_reg_seq adv7612_recommended_settings_hdmi[] = {
3023 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
3024 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
3025 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
3026 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
3027 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
3028 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
3029 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
3030 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
3031 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
3032 { ADV76XX_REG_SEQ_TERM, 0 },
3033 };
3034
3035 static const struct adv76xx_chip_info adv76xx_chip_info[] = {
3036 [ADV7604] = {
3037 .type = ADV7604,
3038 .has_afe = true,
3039 .max_port = ADV7604_PAD_VGA_COMP,
3040 .num_dv_ports = 4,
3041 .edid_enable_reg = 0x77,
3042 .edid_status_reg = 0x7d,
3043 .edid_segment_reg = 0x77,
3044 .edid_segment_mask = 0x10,
3045 .edid_spa_loc_reg = 0x76,
3046 .edid_spa_loc_msb_mask = 0x40,
3047 .edid_spa_port_b_reg = 0x70,
3048 .lcf_reg = 0xb3,
3049 .tdms_lock_mask = 0xe0,
3050 .cable_det_mask = 0x1e,
3051 .fmt_change_digital_mask = 0xc1,
3052 .cp_csc = 0xfc,
3053 .cec_irq_status = 0x4d,
3054 .cec_rx_enable = 0x26,
3055 .cec_rx_enable_mask = 0x01,
3056 .cec_irq_swap = true,
3057 .formats = adv7604_formats,
3058 .nformats = ARRAY_SIZE(adv7604_formats),
3059 .set_termination = adv7604_set_termination,
3060 .setup_irqs = adv7604_setup_irqs,
3061 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock,
3062 .read_cable_det = adv7604_read_cable_det,
3063 .recommended_settings = {
3064 [0] = adv7604_recommended_settings_afe,
3065 [1] = adv7604_recommended_settings_hdmi,
3066 },
3067 .num_recommended_settings = {
3068 [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
3069 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
3070 },
3071 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
3072 BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) |
3073 BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
3074 BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) |
3075 BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) |
3076 BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) |
3077 BIT(ADV7604_PAGE_VDP),
3078 .linewidth_mask = 0xfff,
3079 .field0_height_mask = 0xfff,
3080 .field1_height_mask = 0xfff,
3081 .hfrontporch_mask = 0x3ff,
3082 .hsync_mask = 0x3ff,
3083 .hbackporch_mask = 0x3ff,
3084 .field0_vfrontporch_mask = 0x1fff,
3085 .field0_vsync_mask = 0x1fff,
3086 .field0_vbackporch_mask = 0x1fff,
3087 .field1_vfrontporch_mask = 0x1fff,
3088 .field1_vsync_mask = 0x1fff,
3089 .field1_vbackporch_mask = 0x1fff,
3090 },
3091 [ADV7611] = {
3092 .type = ADV7611,
3093 .has_afe = false,
3094 .max_port = ADV76XX_PAD_HDMI_PORT_A,
3095 .num_dv_ports = 1,
3096 .edid_enable_reg = 0x74,
3097 .edid_status_reg = 0x76,
3098 .edid_segment_reg = 0x7a,
3099 .edid_segment_mask = 0x01,
3100 .lcf_reg = 0xa3,
3101 .tdms_lock_mask = 0x43,
3102 .cable_det_mask = 0x01,
3103 .fmt_change_digital_mask = 0x03,
3104 .cp_csc = 0xf4,
3105 .cec_irq_status = 0x93,
3106 .cec_rx_enable = 0x2c,
3107 .cec_rx_enable_mask = 0x02,
3108 .formats = adv7611_formats,
3109 .nformats = ARRAY_SIZE(adv7611_formats),
3110 .set_termination = adv7611_set_termination,
3111 .setup_irqs = adv7611_setup_irqs,
3112 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
3113 .read_cable_det = adv7611_read_cable_det,
3114 .recommended_settings = {
3115 [1] = adv7611_recommended_settings_hdmi,
3116 },
3117 .num_recommended_settings = {
3118 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
3119 },
3120 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
3121 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
3122 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) |
3123 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
3124 .linewidth_mask = 0x1fff,
3125 .field0_height_mask = 0x1fff,
3126 .field1_height_mask = 0x1fff,
3127 .hfrontporch_mask = 0x1fff,
3128 .hsync_mask = 0x1fff,
3129 .hbackporch_mask = 0x1fff,
3130 .field0_vfrontporch_mask = 0x3fff,
3131 .field0_vsync_mask = 0x3fff,
3132 .field0_vbackporch_mask = 0x3fff,
3133 .field1_vfrontporch_mask = 0x3fff,
3134 .field1_vsync_mask = 0x3fff,
3135 .field1_vbackporch_mask = 0x3fff,
3136 },
3137 [ADV7612] = {
3138 .type = ADV7612,
3139 .has_afe = false,
3140 .max_port = ADV76XX_PAD_HDMI_PORT_A, /* B not supported */
3141 .num_dv_ports = 1, /* normally 2 */
3142 .edid_enable_reg = 0x74,
3143 .edid_status_reg = 0x76,
3144 .edid_segment_reg = 0x7a,
3145 .edid_segment_mask = 0x01,
3146 .edid_spa_loc_reg = 0x70,
3147 .edid_spa_loc_msb_mask = 0x01,
3148 .edid_spa_port_b_reg = 0x52,
3149 .lcf_reg = 0xa3,
3150 .tdms_lock_mask = 0x43,
3151 .cable_det_mask = 0x01,
3152 .fmt_change_digital_mask = 0x03,
3153 .cp_csc = 0xf4,
3154 .cec_irq_status = 0x93,
3155 .cec_rx_enable = 0x2c,
3156 .cec_rx_enable_mask = 0x02,
3157 .formats = adv7612_formats,
3158 .nformats = ARRAY_SIZE(adv7612_formats),
3159 .set_termination = adv7611_set_termination,
3160 .setup_irqs = adv7612_setup_irqs,
3161 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
3162 .read_cable_det = adv7612_read_cable_det,
3163 .recommended_settings = {
3164 [1] = adv7612_recommended_settings_hdmi,
3165 },
3166 .num_recommended_settings = {
3167 [1] = ARRAY_SIZE(adv7612_recommended_settings_hdmi),
3168 },
3169 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
3170 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
3171 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) |
3172 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
3173 .linewidth_mask = 0x1fff,
3174 .field0_height_mask = 0x1fff,
3175 .field1_height_mask = 0x1fff,
3176 .hfrontporch_mask = 0x1fff,
3177 .hsync_mask = 0x1fff,
3178 .hbackporch_mask = 0x1fff,
3179 .field0_vfrontporch_mask = 0x3fff,
3180 .field0_vsync_mask = 0x3fff,
3181 .field0_vbackporch_mask = 0x3fff,
3182 .field1_vfrontporch_mask = 0x3fff,
3183 .field1_vsync_mask = 0x3fff,
3184 .field1_vbackporch_mask = 0x3fff,
3185 },
3186 };
3187
3188 static const struct i2c_device_id adv76xx_i2c_id[] = {
3189 { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] },
3190 { "adv7610", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] },
3191 { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] },
3192 { "adv7612", (kernel_ulong_t)&adv76xx_chip_info[ADV7612] },
3193 { }
3194 };
3195 MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id);
3196
3197 static const struct of_device_id adv76xx_of_id[] __maybe_unused = {
3198 { .compatible = "adi,adv7610", .data = &adv76xx_chip_info[ADV7611] },
3199 { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] },
3200 { .compatible = "adi,adv7612", .data = &adv76xx_chip_info[ADV7612] },
3201 { }
3202 };
3203 MODULE_DEVICE_TABLE(of, adv76xx_of_id);
3204
adv76xx_parse_dt(struct adv76xx_state * state)3205 static int adv76xx_parse_dt(struct adv76xx_state *state)
3206 {
3207 struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
3208 struct device_node *endpoint;
3209 struct device_node *np;
3210 unsigned int flags;
3211 int ret;
3212 u32 v;
3213
3214 np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node;
3215
3216 /* Parse the endpoint. */
3217 endpoint = of_graph_get_next_endpoint(np, NULL);
3218 if (!endpoint)
3219 return -EINVAL;
3220
3221 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint), &bus_cfg);
3222 of_node_put(endpoint);
3223 if (ret)
3224 return ret;
3225
3226 if (!of_property_read_u32(np, "default-input", &v))
3227 state->pdata.default_input = v;
3228 else
3229 state->pdata.default_input = -1;
3230
3231 flags = bus_cfg.bus.parallel.flags;
3232
3233 if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
3234 state->pdata.inv_hs_pol = 1;
3235
3236 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
3237 state->pdata.inv_vs_pol = 1;
3238
3239 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
3240 state->pdata.inv_llc_pol = 1;
3241
3242 if (bus_cfg.bus_type == V4L2_MBUS_BT656)
3243 state->pdata.insert_av_codes = 1;
3244
3245 /* Disable the interrupt for now as no DT-based board uses it. */
3246 state->pdata.int1_config = ADV76XX_INT1_CONFIG_ACTIVE_HIGH;
3247
3248 /* Hardcode the remaining platform data fields. */
3249 state->pdata.disable_pwrdnb = 0;
3250 state->pdata.disable_cable_det_rst = 0;
3251 state->pdata.blank_data = 1;
3252 state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0;
3253 state->pdata.bus_order = ADV7604_BUS_ORDER_RGB;
3254 state->pdata.dr_str_data = ADV76XX_DR_STR_MEDIUM_HIGH;
3255 state->pdata.dr_str_clk = ADV76XX_DR_STR_MEDIUM_HIGH;
3256 state->pdata.dr_str_sync = ADV76XX_DR_STR_MEDIUM_HIGH;
3257
3258 return 0;
3259 }
3260
3261 static const struct regmap_config adv76xx_regmap_cnf[] = {
3262 {
3263 .name = "io",
3264 .reg_bits = 8,
3265 .val_bits = 8,
3266
3267 .max_register = 0xff,
3268 .cache_type = REGCACHE_NONE,
3269 },
3270 {
3271 .name = "avlink",
3272 .reg_bits = 8,
3273 .val_bits = 8,
3274
3275 .max_register = 0xff,
3276 .cache_type = REGCACHE_NONE,
3277 },
3278 {
3279 .name = "cec",
3280 .reg_bits = 8,
3281 .val_bits = 8,
3282
3283 .max_register = 0xff,
3284 .cache_type = REGCACHE_NONE,
3285 },
3286 {
3287 .name = "infoframe",
3288 .reg_bits = 8,
3289 .val_bits = 8,
3290
3291 .max_register = 0xff,
3292 .cache_type = REGCACHE_NONE,
3293 },
3294 {
3295 .name = "esdp",
3296 .reg_bits = 8,
3297 .val_bits = 8,
3298
3299 .max_register = 0xff,
3300 .cache_type = REGCACHE_NONE,
3301 },
3302 {
3303 .name = "epp",
3304 .reg_bits = 8,
3305 .val_bits = 8,
3306
3307 .max_register = 0xff,
3308 .cache_type = REGCACHE_NONE,
3309 },
3310 {
3311 .name = "afe",
3312 .reg_bits = 8,
3313 .val_bits = 8,
3314
3315 .max_register = 0xff,
3316 .cache_type = REGCACHE_NONE,
3317 },
3318 {
3319 .name = "rep",
3320 .reg_bits = 8,
3321 .val_bits = 8,
3322
3323 .max_register = 0xff,
3324 .cache_type = REGCACHE_NONE,
3325 },
3326 {
3327 .name = "edid",
3328 .reg_bits = 8,
3329 .val_bits = 8,
3330
3331 .max_register = 0xff,
3332 .cache_type = REGCACHE_NONE,
3333 },
3334
3335 {
3336 .name = "hdmi",
3337 .reg_bits = 8,
3338 .val_bits = 8,
3339
3340 .max_register = 0xff,
3341 .cache_type = REGCACHE_NONE,
3342 },
3343 {
3344 .name = "test",
3345 .reg_bits = 8,
3346 .val_bits = 8,
3347
3348 .max_register = 0xff,
3349 .cache_type = REGCACHE_NONE,
3350 },
3351 {
3352 .name = "cp",
3353 .reg_bits = 8,
3354 .val_bits = 8,
3355
3356 .max_register = 0xff,
3357 .cache_type = REGCACHE_NONE,
3358 },
3359 {
3360 .name = "vdp",
3361 .reg_bits = 8,
3362 .val_bits = 8,
3363
3364 .max_register = 0xff,
3365 .cache_type = REGCACHE_NONE,
3366 },
3367 };
3368
configure_regmap(struct adv76xx_state * state,int region)3369 static int configure_regmap(struct adv76xx_state *state, int region)
3370 {
3371 int err;
3372
3373 if (!state->i2c_clients[region])
3374 return -ENODEV;
3375
3376 state->regmap[region] =
3377 devm_regmap_init_i2c(state->i2c_clients[region],
3378 &adv76xx_regmap_cnf[region]);
3379
3380 if (IS_ERR(state->regmap[region])) {
3381 err = PTR_ERR(state->regmap[region]);
3382 v4l_err(state->i2c_clients[region],
3383 "Error initializing regmap %d with error %d\n",
3384 region, err);
3385 return -EINVAL;
3386 }
3387
3388 return 0;
3389 }
3390
configure_regmaps(struct adv76xx_state * state)3391 static int configure_regmaps(struct adv76xx_state *state)
3392 {
3393 int i, err;
3394
3395 for (i = ADV7604_PAGE_AVLINK ; i < ADV76XX_PAGE_MAX; i++) {
3396 err = configure_regmap(state, i);
3397 if (err && (err != -ENODEV))
3398 return err;
3399 }
3400 return 0;
3401 }
3402
adv76xx_reset(struct adv76xx_state * state)3403 static void adv76xx_reset(struct adv76xx_state *state)
3404 {
3405 if (state->reset_gpio) {
3406 /* ADV76XX can be reset by a low reset pulse of minimum 5 ms. */
3407 gpiod_set_value_cansleep(state->reset_gpio, 0);
3408 usleep_range(5000, 10000);
3409 gpiod_set_value_cansleep(state->reset_gpio, 1);
3410 /* It is recommended to wait 5 ms after the low pulse before */
3411 /* an I2C write is performed to the ADV76XX. */
3412 usleep_range(5000, 10000);
3413 }
3414 }
3415
adv76xx_probe(struct i2c_client * client)3416 static int adv76xx_probe(struct i2c_client *client)
3417 {
3418 const struct i2c_device_id *id = i2c_client_get_device_id(client);
3419 static const struct v4l2_dv_timings cea640x480 =
3420 V4L2_DV_BT_CEA_640X480P59_94;
3421 struct adv76xx_state *state;
3422 struct v4l2_ctrl_handler *hdl;
3423 struct v4l2_ctrl *ctrl;
3424 struct v4l2_subdev *sd;
3425 unsigned int i;
3426 unsigned int val, val2;
3427 int err;
3428
3429 /* Check if the adapter supports the needed features */
3430 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
3431 return -EIO;
3432 v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n",
3433 client->addr << 1);
3434
3435 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
3436 if (!state)
3437 return -ENOMEM;
3438
3439 state->i2c_clients[ADV76XX_PAGE_IO] = client;
3440
3441 /* initialize variables */
3442 state->restart_stdi_once = true;
3443 state->selected_input = ~0;
3444
3445 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
3446 const struct of_device_id *oid;
3447
3448 oid = of_match_node(adv76xx_of_id, client->dev.of_node);
3449 state->info = oid->data;
3450
3451 err = adv76xx_parse_dt(state);
3452 if (err < 0) {
3453 v4l_err(client, "DT parsing error\n");
3454 return err;
3455 }
3456 } else if (client->dev.platform_data) {
3457 struct adv76xx_platform_data *pdata = client->dev.platform_data;
3458
3459 state->info = (const struct adv76xx_chip_info *)id->driver_data;
3460 state->pdata = *pdata;
3461 } else {
3462 v4l_err(client, "No platform data!\n");
3463 return -ENODEV;
3464 }
3465
3466 /* Request GPIOs. */
3467 for (i = 0; i < state->info->num_dv_ports; ++i) {
3468 state->hpd_gpio[i] =
3469 devm_gpiod_get_index_optional(&client->dev, "hpd", i,
3470 GPIOD_OUT_LOW);
3471 if (IS_ERR(state->hpd_gpio[i]))
3472 return PTR_ERR(state->hpd_gpio[i]);
3473
3474 if (state->hpd_gpio[i])
3475 v4l_info(client, "Handling HPD %u GPIO\n", i);
3476 }
3477 state->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
3478 GPIOD_OUT_HIGH);
3479 if (IS_ERR(state->reset_gpio))
3480 return PTR_ERR(state->reset_gpio);
3481
3482 adv76xx_reset(state);
3483
3484 state->timings = cea640x480;
3485 state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
3486
3487 sd = &state->sd;
3488 v4l2_i2c_subdev_init(sd, client, &adv76xx_ops);
3489 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
3490 id->name, i2c_adapter_id(client->adapter),
3491 client->addr);
3492 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
3493 sd->internal_ops = &adv76xx_int_ops;
3494
3495 /* Configure IO Regmap region */
3496 err = configure_regmap(state, ADV76XX_PAGE_IO);
3497
3498 if (err) {
3499 v4l2_err(sd, "Error configuring IO regmap region\n");
3500 return -ENODEV;
3501 }
3502
3503 /*
3504 * Verify that the chip is present. On ADV7604 the RD_INFO register only
3505 * identifies the revision, while on ADV7611 it identifies the model as
3506 * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611.
3507 */
3508 switch (state->info->type) {
3509 case ADV7604:
3510 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val);
3511 if (err) {
3512 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3513 return -ENODEV;
3514 }
3515 if (val != 0x68) {
3516 v4l2_err(sd, "not an ADV7604 on address 0x%x\n",
3517 client->addr << 1);
3518 return -ENODEV;
3519 }
3520 break;
3521 case ADV7611:
3522 case ADV7612:
3523 err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3524 0xea,
3525 &val);
3526 if (err) {
3527 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3528 return -ENODEV;
3529 }
3530 val2 = val << 8;
3531 err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3532 0xeb,
3533 &val);
3534 if (err) {
3535 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3536 return -ENODEV;
3537 }
3538 val |= val2;
3539 if ((state->info->type == ADV7611 && val != 0x2051) ||
3540 (state->info->type == ADV7612 && val != 0x2041)) {
3541 v4l2_err(sd, "not an %s on address 0x%x\n",
3542 state->info->type == ADV7611 ? "ADV7610/11" : "ADV7612",
3543 client->addr << 1);
3544 return -ENODEV;
3545 }
3546 break;
3547 }
3548
3549 /* control handlers */
3550 hdl = &state->hdl;
3551 v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8);
3552
3553 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3554 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
3555 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3556 V4L2_CID_CONTRAST, 0, 255, 1, 128);
3557 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3558 V4L2_CID_SATURATION, 0, 255, 1, 128);
3559 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3560 V4L2_CID_HUE, 0, 255, 1, 0);
3561 ctrl = v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
3562 V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC,
3563 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
3564 if (ctrl)
3565 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
3566
3567 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
3568 V4L2_CID_DV_RX_POWER_PRESENT, 0,
3569 (1 << state->info->num_dv_ports) - 1, 0, 0);
3570 state->rgb_quantization_range_ctrl =
3571 v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
3572 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
3573 0, V4L2_DV_RGB_RANGE_AUTO);
3574
3575 /* custom controls */
3576 if (adv76xx_has_afe(state))
3577 state->analog_sampling_phase_ctrl =
3578 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
3579 state->free_run_color_manual_ctrl =
3580 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL);
3581 state->free_run_color_ctrl =
3582 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL);
3583
3584 sd->ctrl_handler = hdl;
3585 if (hdl->error) {
3586 err = hdl->error;
3587 goto err_hdl;
3588 }
3589 if (adv76xx_s_detect_tx_5v_ctrl(sd)) {
3590 err = -ENODEV;
3591 goto err_hdl;
3592 }
3593
3594 for (i = 1; i < ADV76XX_PAGE_MAX; ++i) {
3595 struct i2c_client *dummy_client;
3596
3597 if (!(BIT(i) & state->info->page_mask))
3598 continue;
3599
3600 dummy_client = adv76xx_dummy_client(sd, i);
3601 if (IS_ERR(dummy_client)) {
3602 err = PTR_ERR(dummy_client);
3603 v4l2_err(sd, "failed to create i2c client %u\n", i);
3604 goto err_i2c;
3605 }
3606
3607 state->i2c_clients[i] = dummy_client;
3608 }
3609
3610 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
3611 adv76xx_delayed_work_enable_hotplug);
3612
3613 state->source_pad = state->info->num_dv_ports
3614 + (state->info->has_afe ? 2 : 0);
3615 for (i = 0; i < state->source_pad; ++i)
3616 state->pads[i].flags = MEDIA_PAD_FL_SINK;
3617 state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE;
3618 sd->entity.function = MEDIA_ENT_F_DV_DECODER;
3619
3620 err = media_entity_pads_init(&sd->entity, state->source_pad + 1,
3621 state->pads);
3622 if (err)
3623 goto err_work_queues;
3624
3625 /* Configure regmaps */
3626 err = configure_regmaps(state);
3627 if (err)
3628 goto err_entity;
3629
3630 err = adv76xx_core_init(sd);
3631 if (err)
3632 goto err_entity;
3633
3634 if (client->irq) {
3635 err = devm_request_threaded_irq(&client->dev,
3636 client->irq,
3637 NULL, adv76xx_irq_handler,
3638 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
3639 client->name, state);
3640 if (err)
3641 goto err_entity;
3642 }
3643
3644 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
3645 state->cec_adap = cec_allocate_adapter(&adv76xx_cec_adap_ops,
3646 state, dev_name(&client->dev),
3647 CEC_CAP_DEFAULTS, ADV76XX_MAX_ADDRS);
3648 err = PTR_ERR_OR_ZERO(state->cec_adap);
3649 if (err)
3650 goto err_entity;
3651 #endif
3652
3653 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3654 client->addr << 1, client->adapter->name);
3655
3656 err = v4l2_async_register_subdev(sd);
3657 if (err)
3658 goto err_entity;
3659
3660 return 0;
3661
3662 err_entity:
3663 media_entity_cleanup(&sd->entity);
3664 err_work_queues:
3665 cancel_delayed_work(&state->delayed_work_enable_hotplug);
3666 err_i2c:
3667 adv76xx_unregister_clients(state);
3668 err_hdl:
3669 v4l2_ctrl_handler_free(hdl);
3670 return err;
3671 }
3672
3673 /* ----------------------------------------------------------------------- */
3674
adv76xx_remove(struct i2c_client * client)3675 static void adv76xx_remove(struct i2c_client *client)
3676 {
3677 struct v4l2_subdev *sd = i2c_get_clientdata(client);
3678 struct adv76xx_state *state = to_state(sd);
3679
3680 /* disable interrupts */
3681 io_write(sd, 0x40, 0);
3682 io_write(sd, 0x41, 0);
3683 io_write(sd, 0x46, 0);
3684 io_write(sd, 0x6e, 0);
3685 io_write(sd, 0x73, 0);
3686
3687 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
3688 v4l2_async_unregister_subdev(sd);
3689 media_entity_cleanup(&sd->entity);
3690 adv76xx_unregister_clients(to_state(sd));
3691 v4l2_ctrl_handler_free(sd->ctrl_handler);
3692 }
3693
3694 /* ----------------------------------------------------------------------- */
3695
3696 static struct i2c_driver adv76xx_driver = {
3697 .driver = {
3698 .name = "adv7604",
3699 .of_match_table = of_match_ptr(adv76xx_of_id),
3700 },
3701 .probe = adv76xx_probe,
3702 .remove = adv76xx_remove,
3703 .id_table = adv76xx_i2c_id,
3704 };
3705
3706 module_i2c_driver(adv76xx_driver);
3707