1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2 /* Copyright(c) 2015 - 2021 Intel Corporation */
3 #include <adf_accel_devices.h>
4 #include <adf_common_drv.h>
5 #include <adf_gen2_config.h>
6 #include <adf_gen2_dc.h>
7 #include <adf_gen2_hw_data.h>
8 #include <adf_gen2_pfvf.h>
9 #include <adf_pfvf_vf_msg.h>
10 #include "adf_c62xvf_hw_data.h"
11 
12 static struct adf_hw_device_class c62xiov_class = {
13 	.name = ADF_C62XVF_DEVICE_NAME,
14 	.type = DEV_C62XVF,
15 	.instances = 0
16 };
17 
get_accel_mask(struct adf_hw_device_data * self)18 static u32 get_accel_mask(struct adf_hw_device_data *self)
19 {
20 	return ADF_C62XIOV_ACCELERATORS_MASK;
21 }
22 
get_ae_mask(struct adf_hw_device_data * self)23 static u32 get_ae_mask(struct adf_hw_device_data *self)
24 {
25 	return ADF_C62XIOV_ACCELENGINES_MASK;
26 }
27 
get_num_accels(struct adf_hw_device_data * self)28 static u32 get_num_accels(struct adf_hw_device_data *self)
29 {
30 	return ADF_C62XIOV_MAX_ACCELERATORS;
31 }
32 
get_num_aes(struct adf_hw_device_data * self)33 static u32 get_num_aes(struct adf_hw_device_data *self)
34 {
35 	return ADF_C62XIOV_MAX_ACCELENGINES;
36 }
37 
get_misc_bar_id(struct adf_hw_device_data * self)38 static u32 get_misc_bar_id(struct adf_hw_device_data *self)
39 {
40 	return ADF_C62XIOV_PMISC_BAR;
41 }
42 
get_etr_bar_id(struct adf_hw_device_data * self)43 static u32 get_etr_bar_id(struct adf_hw_device_data *self)
44 {
45 	return ADF_C62XIOV_ETR_BAR;
46 }
47 
get_sku(struct adf_hw_device_data * self)48 static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
49 {
50 	return DEV_SKU_VF;
51 }
52 
adf_vf_int_noop(struct adf_accel_dev * accel_dev)53 static int adf_vf_int_noop(struct adf_accel_dev *accel_dev)
54 {
55 	return 0;
56 }
57 
adf_vf_void_noop(struct adf_accel_dev * accel_dev)58 static void adf_vf_void_noop(struct adf_accel_dev *accel_dev)
59 {
60 }
61 
adf_init_hw_data_c62xiov(struct adf_hw_device_data * hw_data)62 void adf_init_hw_data_c62xiov(struct adf_hw_device_data *hw_data)
63 {
64 	hw_data->dev_class = &c62xiov_class;
65 	hw_data->num_banks = ADF_C62XIOV_ETR_MAX_BANKS;
66 	hw_data->num_rings_per_bank = ADF_ETR_MAX_RINGS_PER_BANK;
67 	hw_data->num_accel = ADF_C62XIOV_MAX_ACCELERATORS;
68 	hw_data->num_logical_accel = 1;
69 	hw_data->num_engines = ADF_C62XIOV_MAX_ACCELENGINES;
70 	hw_data->tx_rx_gap = ADF_C62XIOV_RX_RINGS_OFFSET;
71 	hw_data->tx_rings_mask = ADF_C62XIOV_TX_RINGS_MASK;
72 	hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP;
73 	hw_data->alloc_irq = adf_vf_isr_resource_alloc;
74 	hw_data->free_irq = adf_vf_isr_resource_free;
75 	hw_data->enable_error_correction = adf_vf_void_noop;
76 	hw_data->init_admin_comms = adf_vf_int_noop;
77 	hw_data->exit_admin_comms = adf_vf_void_noop;
78 	hw_data->send_admin_init = adf_vf2pf_notify_init;
79 	hw_data->init_arb = adf_vf_int_noop;
80 	hw_data->exit_arb = adf_vf_void_noop;
81 	hw_data->disable_iov = adf_vf2pf_notify_shutdown;
82 	hw_data->get_accel_mask = get_accel_mask;
83 	hw_data->get_ae_mask = get_ae_mask;
84 	hw_data->get_num_accels = get_num_accels;
85 	hw_data->get_num_aes = get_num_aes;
86 	hw_data->get_etr_bar_id = get_etr_bar_id;
87 	hw_data->get_misc_bar_id = get_misc_bar_id;
88 	hw_data->get_sku = get_sku;
89 	hw_data->enable_ints = adf_vf_void_noop;
90 	hw_data->dev_class->instances++;
91 	hw_data->dev_config = adf_gen2_dev_config;
92 	adf_devmgr_update_class_index(hw_data);
93 	adf_gen2_init_vf_pfvf_ops(&hw_data->pfvf_ops);
94 	adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
95 	adf_gen2_init_dc_ops(&hw_data->dc_ops);
96 }
97 
adf_clean_hw_data_c62xiov(struct adf_hw_device_data * hw_data)98 void adf_clean_hw_data_c62xiov(struct adf_hw_device_data *hw_data)
99 {
100 	hw_data->dev_class->instances--;
101 	adf_devmgr_update_class_index(hw_data);
102 }
103