xref: /openbmc/linux/sound/soc/codecs/adau1373.c (revision da27e493)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Analog Devices ADAU1373 Audio Codec drive
4  *
5  * Copyright 2011 Analog Devices Inc.
6  * Author: Lars-Peter Clausen <lars@metafoo.de>
7  */
8 
9 #include <linux/module.h>
10 #include <linux/init.h>
11 #include <linux/delay.h>
12 #include <linux/pm.h>
13 #include <linux/i2c.h>
14 #include <linux/slab.h>
15 
16 #include <sound/core.h>
17 #include <sound/pcm.h>
18 #include <sound/pcm_params.h>
19 #include <sound/tlv.h>
20 #include <sound/soc.h>
21 #include <sound/adau1373.h>
22 
23 #include "adau1373.h"
24 #include "adau-utils.h"
25 
26 struct adau1373_dai {
27 	unsigned int clk_src;
28 	unsigned int sysclk;
29 	bool enable_src;
30 	bool clock_provider;
31 };
32 
33 struct adau1373 {
34 	struct regmap *regmap;
35 	struct adau1373_dai dais[3];
36 };
37 
38 #define ADAU1373_INPUT_MODE	0x00
39 #define ADAU1373_AINL_CTRL(x)	(0x01 + (x) * 2)
40 #define ADAU1373_AINR_CTRL(x)	(0x02 + (x) * 2)
41 #define ADAU1373_LLINE_OUT(x)	(0x9 + (x) * 2)
42 #define ADAU1373_RLINE_OUT(x)	(0xa + (x) * 2)
43 #define ADAU1373_LSPK_OUT	0x0d
44 #define ADAU1373_RSPK_OUT	0x0e
45 #define ADAU1373_LHP_OUT	0x0f
46 #define ADAU1373_RHP_OUT	0x10
47 #define ADAU1373_ADC_GAIN	0x11
48 #define ADAU1373_LADC_MIXER	0x12
49 #define ADAU1373_RADC_MIXER	0x13
50 #define ADAU1373_LLINE1_MIX	0x14
51 #define ADAU1373_RLINE1_MIX	0x15
52 #define ADAU1373_LLINE2_MIX	0x16
53 #define ADAU1373_RLINE2_MIX	0x17
54 #define ADAU1373_LSPK_MIX	0x18
55 #define ADAU1373_RSPK_MIX	0x19
56 #define ADAU1373_LHP_MIX	0x1a
57 #define ADAU1373_RHP_MIX	0x1b
58 #define ADAU1373_EP_MIX		0x1c
59 #define ADAU1373_HP_CTRL	0x1d
60 #define ADAU1373_HP_CTRL2	0x1e
61 #define ADAU1373_LS_CTRL	0x1f
62 #define ADAU1373_EP_CTRL	0x21
63 #define ADAU1373_MICBIAS_CTRL1	0x22
64 #define ADAU1373_MICBIAS_CTRL2	0x23
65 #define ADAU1373_OUTPUT_CTRL	0x24
66 #define ADAU1373_PWDN_CTRL1	0x25
67 #define ADAU1373_PWDN_CTRL2	0x26
68 #define ADAU1373_PWDN_CTRL3	0x27
69 #define ADAU1373_DPLL_CTRL(x)	(0x28 + (x) * 7)
70 #define ADAU1373_PLL_CTRL1(x)	(0x29 + (x) * 7)
71 #define ADAU1373_PLL_CTRL2(x)	(0x2a + (x) * 7)
72 #define ADAU1373_PLL_CTRL3(x)	(0x2b + (x) * 7)
73 #define ADAU1373_PLL_CTRL4(x)	(0x2c + (x) * 7)
74 #define ADAU1373_PLL_CTRL5(x)	(0x2d + (x) * 7)
75 #define ADAU1373_PLL_CTRL6(x)	(0x2e + (x) * 7)
76 #define ADAU1373_HEADDECT	0x36
77 #define ADAU1373_ADC_DAC_STATUS	0x37
78 #define ADAU1373_ADC_CTRL	0x3c
79 #define ADAU1373_DAI(x)		(0x44 + (x))
80 #define ADAU1373_CLK_SRC_DIV(x)	(0x40 + (x) * 2)
81 #define ADAU1373_BCLKDIV(x)	(0x47 + (x))
82 #define ADAU1373_SRC_RATIOA(x)	(0x4a + (x) * 2)
83 #define ADAU1373_SRC_RATIOB(x)	(0x4b + (x) * 2)
84 #define ADAU1373_DEEMP_CTRL	0x50
85 #define ADAU1373_SRC_DAI_CTRL(x) (0x51 + (x))
86 #define ADAU1373_DIN_MIX_CTRL(x) (0x56 + (x))
87 #define ADAU1373_DOUT_MIX_CTRL(x) (0x5b + (x))
88 #define ADAU1373_DAI_PBL_VOL(x)	(0x62 + (x) * 2)
89 #define ADAU1373_DAI_PBR_VOL(x)	(0x63 + (x) * 2)
90 #define ADAU1373_DAI_RECL_VOL(x) (0x68 + (x) * 2)
91 #define ADAU1373_DAI_RECR_VOL(x) (0x69 + (x) * 2)
92 #define ADAU1373_DAC1_PBL_VOL	0x6e
93 #define ADAU1373_DAC1_PBR_VOL	0x6f
94 #define ADAU1373_DAC2_PBL_VOL	0x70
95 #define ADAU1373_DAC2_PBR_VOL	0x71
96 #define ADAU1373_ADC_RECL_VOL	0x72
97 #define ADAU1373_ADC_RECR_VOL	0x73
98 #define ADAU1373_DMIC_RECL_VOL	0x74
99 #define ADAU1373_DMIC_RECR_VOL	0x75
100 #define ADAU1373_VOL_GAIN1	0x76
101 #define ADAU1373_VOL_GAIN2	0x77
102 #define ADAU1373_VOL_GAIN3	0x78
103 #define ADAU1373_HPF_CTRL	0x7d
104 #define ADAU1373_BASS1		0x7e
105 #define ADAU1373_BASS2		0x7f
106 #define ADAU1373_DRC(x)		(0x80 + (x) * 0x10)
107 #define ADAU1373_3D_CTRL1	0xc0
108 #define ADAU1373_3D_CTRL2	0xc1
109 #define ADAU1373_FDSP_SEL1	0xdc
110 #define ADAU1373_FDSP_SEL2	0xdd
111 #define ADAU1373_FDSP_SEL3	0xde
112 #define ADAU1373_FDSP_SEL4	0xdf
113 #define ADAU1373_DIGMICCTRL	0xe2
114 #define ADAU1373_DIGEN		0xeb
115 #define ADAU1373_SOFT_RESET	0xff
116 
117 
118 #define ADAU1373_PLL_CTRL6_DPLL_BYPASS	BIT(1)
119 #define ADAU1373_PLL_CTRL6_PLL_EN	BIT(0)
120 
121 #define ADAU1373_DAI_INVERT_BCLK	BIT(7)
122 #define ADAU1373_DAI_MASTER		BIT(6)
123 #define ADAU1373_DAI_INVERT_LRCLK	BIT(4)
124 #define ADAU1373_DAI_WLEN_16		0x0
125 #define ADAU1373_DAI_WLEN_20		0x4
126 #define ADAU1373_DAI_WLEN_24		0x8
127 #define ADAU1373_DAI_WLEN_32		0xc
128 #define ADAU1373_DAI_WLEN_MASK		0xc
129 #define ADAU1373_DAI_FORMAT_RIGHT_J	0x0
130 #define ADAU1373_DAI_FORMAT_LEFT_J	0x1
131 #define ADAU1373_DAI_FORMAT_I2S		0x2
132 #define ADAU1373_DAI_FORMAT_DSP		0x3
133 
134 #define ADAU1373_BCLKDIV_SOURCE		BIT(5)
135 #define ADAU1373_BCLKDIV_SR_MASK	(0x07 << 2)
136 #define ADAU1373_BCLKDIV_BCLK_MASK	0x03
137 #define ADAU1373_BCLKDIV_32		0x03
138 #define ADAU1373_BCLKDIV_64		0x02
139 #define ADAU1373_BCLKDIV_128		0x01
140 #define ADAU1373_BCLKDIV_256		0x00
141 
142 #define ADAU1373_ADC_CTRL_PEAK_DETECT	BIT(0)
143 #define ADAU1373_ADC_CTRL_RESET		BIT(1)
144 #define ADAU1373_ADC_CTRL_RESET_FORCE	BIT(2)
145 
146 #define ADAU1373_OUTPUT_CTRL_LDIFF	BIT(3)
147 #define ADAU1373_OUTPUT_CTRL_LNFBEN	BIT(2)
148 
149 #define ADAU1373_PWDN_CTRL3_PWR_EN BIT(0)
150 
151 #define ADAU1373_EP_CTRL_MICBIAS1_OFFSET 4
152 #define ADAU1373_EP_CTRL_MICBIAS2_OFFSET 2
153 
154 static const struct reg_default adau1373_reg_defaults[] = {
155 	{ ADAU1373_INPUT_MODE,		0x00 },
156 	{ ADAU1373_AINL_CTRL(0),	0x00 },
157 	{ ADAU1373_AINR_CTRL(0),	0x00 },
158 	{ ADAU1373_AINL_CTRL(1),	0x00 },
159 	{ ADAU1373_AINR_CTRL(1),	0x00 },
160 	{ ADAU1373_AINL_CTRL(2),	0x00 },
161 	{ ADAU1373_AINR_CTRL(2),	0x00 },
162 	{ ADAU1373_AINL_CTRL(3),	0x00 },
163 	{ ADAU1373_AINR_CTRL(3),	0x00 },
164 	{ ADAU1373_LLINE_OUT(0),	0x00 },
165 	{ ADAU1373_RLINE_OUT(0),	0x00 },
166 	{ ADAU1373_LLINE_OUT(1),	0x00 },
167 	{ ADAU1373_RLINE_OUT(1),	0x00 },
168 	{ ADAU1373_LSPK_OUT,		0x00 },
169 	{ ADAU1373_RSPK_OUT,		0x00 },
170 	{ ADAU1373_LHP_OUT,		0x00 },
171 	{ ADAU1373_RHP_OUT,		0x00 },
172 	{ ADAU1373_ADC_GAIN,		0x00 },
173 	{ ADAU1373_LADC_MIXER,		0x00 },
174 	{ ADAU1373_RADC_MIXER,		0x00 },
175 	{ ADAU1373_LLINE1_MIX,		0x00 },
176 	{ ADAU1373_RLINE1_MIX,		0x00 },
177 	{ ADAU1373_LLINE2_MIX,		0x00 },
178 	{ ADAU1373_RLINE2_MIX,		0x00 },
179 	{ ADAU1373_LSPK_MIX,		0x00 },
180 	{ ADAU1373_RSPK_MIX,		0x00 },
181 	{ ADAU1373_LHP_MIX,		0x00 },
182 	{ ADAU1373_RHP_MIX,		0x00 },
183 	{ ADAU1373_EP_MIX,		0x00 },
184 	{ ADAU1373_HP_CTRL,		0x00 },
185 	{ ADAU1373_HP_CTRL2,		0x00 },
186 	{ ADAU1373_LS_CTRL,		0x00 },
187 	{ ADAU1373_EP_CTRL,		0x00 },
188 	{ ADAU1373_MICBIAS_CTRL1,	0x00 },
189 	{ ADAU1373_MICBIAS_CTRL2,	0x00 },
190 	{ ADAU1373_OUTPUT_CTRL,		0x00 },
191 	{ ADAU1373_PWDN_CTRL1,		0x00 },
192 	{ ADAU1373_PWDN_CTRL2,		0x00 },
193 	{ ADAU1373_PWDN_CTRL3,		0x00 },
194 	{ ADAU1373_DPLL_CTRL(0),	0x00 },
195 	{ ADAU1373_PLL_CTRL1(0),	0x00 },
196 	{ ADAU1373_PLL_CTRL2(0),	0x00 },
197 	{ ADAU1373_PLL_CTRL3(0),	0x00 },
198 	{ ADAU1373_PLL_CTRL4(0),	0x00 },
199 	{ ADAU1373_PLL_CTRL5(0),	0x00 },
200 	{ ADAU1373_PLL_CTRL6(0),	0x02 },
201 	{ ADAU1373_DPLL_CTRL(1),	0x00 },
202 	{ ADAU1373_PLL_CTRL1(1),	0x00 },
203 	{ ADAU1373_PLL_CTRL2(1),	0x00 },
204 	{ ADAU1373_PLL_CTRL3(1),	0x00 },
205 	{ ADAU1373_PLL_CTRL4(1),	0x00 },
206 	{ ADAU1373_PLL_CTRL5(1),	0x00 },
207 	{ ADAU1373_PLL_CTRL6(1),	0x02 },
208 	{ ADAU1373_HEADDECT,		0x00 },
209 	{ ADAU1373_ADC_CTRL,		0x00 },
210 	{ ADAU1373_CLK_SRC_DIV(0),	0x00 },
211 	{ ADAU1373_CLK_SRC_DIV(1),	0x00 },
212 	{ ADAU1373_DAI(0),		0x0a },
213 	{ ADAU1373_DAI(1),		0x0a },
214 	{ ADAU1373_DAI(2),		0x0a },
215 	{ ADAU1373_BCLKDIV(0),		0x00 },
216 	{ ADAU1373_BCLKDIV(1),		0x00 },
217 	{ ADAU1373_BCLKDIV(2),		0x00 },
218 	{ ADAU1373_SRC_RATIOA(0),	0x00 },
219 	{ ADAU1373_SRC_RATIOB(0),	0x00 },
220 	{ ADAU1373_SRC_RATIOA(1),	0x00 },
221 	{ ADAU1373_SRC_RATIOB(1),	0x00 },
222 	{ ADAU1373_SRC_RATIOA(2),	0x00 },
223 	{ ADAU1373_SRC_RATIOB(2),	0x00 },
224 	{ ADAU1373_DEEMP_CTRL,		0x00 },
225 	{ ADAU1373_SRC_DAI_CTRL(0),	0x08 },
226 	{ ADAU1373_SRC_DAI_CTRL(1),	0x08 },
227 	{ ADAU1373_SRC_DAI_CTRL(2),	0x08 },
228 	{ ADAU1373_DIN_MIX_CTRL(0),	0x00 },
229 	{ ADAU1373_DIN_MIX_CTRL(1),	0x00 },
230 	{ ADAU1373_DIN_MIX_CTRL(2),	0x00 },
231 	{ ADAU1373_DIN_MIX_CTRL(3),	0x00 },
232 	{ ADAU1373_DIN_MIX_CTRL(4),	0x00 },
233 	{ ADAU1373_DOUT_MIX_CTRL(0),	0x00 },
234 	{ ADAU1373_DOUT_MIX_CTRL(1),	0x00 },
235 	{ ADAU1373_DOUT_MIX_CTRL(2),	0x00 },
236 	{ ADAU1373_DOUT_MIX_CTRL(3),	0x00 },
237 	{ ADAU1373_DOUT_MIX_CTRL(4),	0x00 },
238 	{ ADAU1373_DAI_PBL_VOL(0),	0x00 },
239 	{ ADAU1373_DAI_PBR_VOL(0),	0x00 },
240 	{ ADAU1373_DAI_PBL_VOL(1),	0x00 },
241 	{ ADAU1373_DAI_PBR_VOL(1),	0x00 },
242 	{ ADAU1373_DAI_PBL_VOL(2),	0x00 },
243 	{ ADAU1373_DAI_PBR_VOL(2),	0x00 },
244 	{ ADAU1373_DAI_RECL_VOL(0),	0x00 },
245 	{ ADAU1373_DAI_RECR_VOL(0),	0x00 },
246 	{ ADAU1373_DAI_RECL_VOL(1),	0x00 },
247 	{ ADAU1373_DAI_RECR_VOL(1),	0x00 },
248 	{ ADAU1373_DAI_RECL_VOL(2),	0x00 },
249 	{ ADAU1373_DAI_RECR_VOL(2),	0x00 },
250 	{ ADAU1373_DAC1_PBL_VOL,	0x00 },
251 	{ ADAU1373_DAC1_PBR_VOL,	0x00 },
252 	{ ADAU1373_DAC2_PBL_VOL,	0x00 },
253 	{ ADAU1373_DAC2_PBR_VOL,	0x00 },
254 	{ ADAU1373_ADC_RECL_VOL,	0x00 },
255 	{ ADAU1373_ADC_RECR_VOL,	0x00 },
256 	{ ADAU1373_DMIC_RECL_VOL,	0x00 },
257 	{ ADAU1373_DMIC_RECR_VOL,	0x00 },
258 	{ ADAU1373_VOL_GAIN1,		0x00 },
259 	{ ADAU1373_VOL_GAIN2,		0x00 },
260 	{ ADAU1373_VOL_GAIN3,		0x00 },
261 	{ ADAU1373_HPF_CTRL,		0x00 },
262 	{ ADAU1373_BASS1,		0x00 },
263 	{ ADAU1373_BASS2,		0x00 },
264 	{ ADAU1373_DRC(0) + 0x0,	0x78 },
265 	{ ADAU1373_DRC(0) + 0x1,	0x18 },
266 	{ ADAU1373_DRC(0) + 0x2,	0x00 },
267 	{ ADAU1373_DRC(0) + 0x3,	0x00 },
268 	{ ADAU1373_DRC(0) + 0x4,	0x00 },
269 	{ ADAU1373_DRC(0) + 0x5,	0xc0 },
270 	{ ADAU1373_DRC(0) + 0x6,	0x00 },
271 	{ ADAU1373_DRC(0) + 0x7,	0x00 },
272 	{ ADAU1373_DRC(0) + 0x8,	0x00 },
273 	{ ADAU1373_DRC(0) + 0x9,	0xc0 },
274 	{ ADAU1373_DRC(0) + 0xa,	0x88 },
275 	{ ADAU1373_DRC(0) + 0xb,	0x7a },
276 	{ ADAU1373_DRC(0) + 0xc,	0xdf },
277 	{ ADAU1373_DRC(0) + 0xd,	0x20 },
278 	{ ADAU1373_DRC(0) + 0xe,	0x00 },
279 	{ ADAU1373_DRC(0) + 0xf,	0x00 },
280 	{ ADAU1373_DRC(1) + 0x0,	0x78 },
281 	{ ADAU1373_DRC(1) + 0x1,	0x18 },
282 	{ ADAU1373_DRC(1) + 0x2,	0x00 },
283 	{ ADAU1373_DRC(1) + 0x3,	0x00 },
284 	{ ADAU1373_DRC(1) + 0x4,	0x00 },
285 	{ ADAU1373_DRC(1) + 0x5,	0xc0 },
286 	{ ADAU1373_DRC(1) + 0x6,	0x00 },
287 	{ ADAU1373_DRC(1) + 0x7,	0x00 },
288 	{ ADAU1373_DRC(1) + 0x8,	0x00 },
289 	{ ADAU1373_DRC(1) + 0x9,	0xc0 },
290 	{ ADAU1373_DRC(1) + 0xa,	0x88 },
291 	{ ADAU1373_DRC(1) + 0xb,	0x7a },
292 	{ ADAU1373_DRC(1) + 0xc,	0xdf },
293 	{ ADAU1373_DRC(1) + 0xd,	0x20 },
294 	{ ADAU1373_DRC(1) + 0xe,	0x00 },
295 	{ ADAU1373_DRC(1) + 0xf,	0x00 },
296 	{ ADAU1373_DRC(2) + 0x0,	0x78 },
297 	{ ADAU1373_DRC(2) + 0x1,	0x18 },
298 	{ ADAU1373_DRC(2) + 0x2,	0x00 },
299 	{ ADAU1373_DRC(2) + 0x3,	0x00 },
300 	{ ADAU1373_DRC(2) + 0x4,	0x00 },
301 	{ ADAU1373_DRC(2) + 0x5,	0xc0 },
302 	{ ADAU1373_DRC(2) + 0x6,	0x00 },
303 	{ ADAU1373_DRC(2) + 0x7,	0x00 },
304 	{ ADAU1373_DRC(2) + 0x8,	0x00 },
305 	{ ADAU1373_DRC(2) + 0x9,	0xc0 },
306 	{ ADAU1373_DRC(2) + 0xa,	0x88 },
307 	{ ADAU1373_DRC(2) + 0xb,	0x7a },
308 	{ ADAU1373_DRC(2) + 0xc,	0xdf },
309 	{ ADAU1373_DRC(2) + 0xd,	0x20 },
310 	{ ADAU1373_DRC(2) + 0xe,	0x00 },
311 	{ ADAU1373_DRC(2) + 0xf,	0x00 },
312 	{ ADAU1373_3D_CTRL1,		0x00 },
313 	{ ADAU1373_3D_CTRL2,		0x00 },
314 	{ ADAU1373_FDSP_SEL1,		0x00 },
315 	{ ADAU1373_FDSP_SEL2,		0x00 },
316 	{ ADAU1373_FDSP_SEL2,		0x00 },
317 	{ ADAU1373_FDSP_SEL4,		0x00 },
318 	{ ADAU1373_DIGMICCTRL,		0x00 },
319 	{ ADAU1373_DIGEN,		0x00 },
320 };
321 
322 static const DECLARE_TLV_DB_RANGE(adau1373_out_tlv,
323 	0, 7, TLV_DB_SCALE_ITEM(-7900, 400, 1),
324 	8, 15, TLV_DB_SCALE_ITEM(-4700, 300, 0),
325 	16, 23, TLV_DB_SCALE_ITEM(-2300, 200, 0),
326 	24, 31, TLV_DB_SCALE_ITEM(-700, 100, 0)
327 );
328 
329 static const DECLARE_TLV_DB_MINMAX(adau1373_digital_tlv, -9563, 0);
330 static const DECLARE_TLV_DB_SCALE(adau1373_in_pga_tlv, -1300, 100, 1);
331 static const DECLARE_TLV_DB_SCALE(adau1373_ep_tlv, -600, 600, 1);
332 
333 static const DECLARE_TLV_DB_SCALE(adau1373_input_boost_tlv, 0, 2000, 0);
334 static const DECLARE_TLV_DB_SCALE(adau1373_gain_boost_tlv, 0, 600, 0);
335 static const DECLARE_TLV_DB_SCALE(adau1373_speaker_boost_tlv, 1200, 600, 0);
336 
337 static const char *adau1373_fdsp_sel_text[] = {
338 	"None",
339 	"Channel 1",
340 	"Channel 2",
341 	"Channel 3",
342 	"Channel 4",
343 	"Channel 5",
344 };
345 
346 static SOC_ENUM_SINGLE_DECL(adau1373_drc1_channel_enum,
347 	ADAU1373_FDSP_SEL1, 4, adau1373_fdsp_sel_text);
348 static SOC_ENUM_SINGLE_DECL(adau1373_drc2_channel_enum,
349 	ADAU1373_FDSP_SEL1, 0, adau1373_fdsp_sel_text);
350 static SOC_ENUM_SINGLE_DECL(adau1373_drc3_channel_enum,
351 	ADAU1373_FDSP_SEL2, 0, adau1373_fdsp_sel_text);
352 static SOC_ENUM_SINGLE_DECL(adau1373_hpf_channel_enum,
353 	ADAU1373_FDSP_SEL3, 0, adau1373_fdsp_sel_text);
354 static SOC_ENUM_SINGLE_DECL(adau1373_bass_channel_enum,
355 	ADAU1373_FDSP_SEL4, 4, adau1373_fdsp_sel_text);
356 
357 static const char *adau1373_hpf_cutoff_text[] = {
358 	"3.7Hz", "50Hz", "100Hz", "150Hz", "200Hz", "250Hz", "300Hz", "350Hz",
359 	"400Hz", "450Hz", "500Hz", "550Hz", "600Hz", "650Hz", "700Hz", "750Hz",
360 	"800Hz",
361 };
362 
363 static SOC_ENUM_SINGLE_DECL(adau1373_hpf_cutoff_enum,
364 	ADAU1373_HPF_CTRL, 3, adau1373_hpf_cutoff_text);
365 
366 static const char *adau1373_bass_lpf_cutoff_text[] = {
367 	"801Hz", "1001Hz",
368 };
369 
370 static const char *adau1373_bass_clip_level_text[] = {
371 	"0.125", "0.250", "0.370", "0.500", "0.625", "0.750", "0.875",
372 };
373 
374 static const unsigned int adau1373_bass_clip_level_values[] = {
375 	1, 2, 3, 4, 5, 6, 7,
376 };
377 
378 static const char *adau1373_bass_hpf_cutoff_text[] = {
379 	"158Hz", "232Hz", "347Hz", "520Hz",
380 };
381 
382 static const DECLARE_TLV_DB_RANGE(adau1373_bass_tlv,
383 	0, 2, TLV_DB_SCALE_ITEM(-600, 600, 1),
384 	3, 4, TLV_DB_SCALE_ITEM(950, 250, 0),
385 	5, 7, TLV_DB_SCALE_ITEM(1400, 150, 0)
386 );
387 
388 static SOC_ENUM_SINGLE_DECL(adau1373_bass_lpf_cutoff_enum,
389 	ADAU1373_BASS1, 5, adau1373_bass_lpf_cutoff_text);
390 
391 static SOC_VALUE_ENUM_SINGLE_DECL(adau1373_bass_clip_level_enum,
392 	ADAU1373_BASS1, 2, 7, adau1373_bass_clip_level_text,
393 	adau1373_bass_clip_level_values);
394 
395 static SOC_ENUM_SINGLE_DECL(adau1373_bass_hpf_cutoff_enum,
396 	ADAU1373_BASS1, 0, adau1373_bass_hpf_cutoff_text);
397 
398 static const char *adau1373_3d_level_text[] = {
399 	"0%", "6.67%", "13.33%", "20%", "26.67%", "33.33%",
400 	"40%", "46.67%", "53.33%", "60%", "66.67%", "73.33%",
401 	"80%", "86.67", "99.33%", "100%"
402 };
403 
404 static const char *adau1373_3d_cutoff_text[] = {
405 	"No 3D", "0.03125 fs", "0.04583 fs", "0.075 fs", "0.11458 fs",
406 	"0.16875 fs", "0.27083 fs"
407 };
408 
409 static SOC_ENUM_SINGLE_DECL(adau1373_3d_level_enum,
410 	ADAU1373_3D_CTRL1, 4, adau1373_3d_level_text);
411 static SOC_ENUM_SINGLE_DECL(adau1373_3d_cutoff_enum,
412 	ADAU1373_3D_CTRL1, 0, adau1373_3d_cutoff_text);
413 
414 static const DECLARE_TLV_DB_RANGE(adau1373_3d_tlv,
415 	0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
416 	1, 7, TLV_DB_LINEAR_ITEM(-1800, -120)
417 );
418 
419 static const char *adau1373_lr_mux_text[] = {
420 	"Mute",
421 	"Right Channel (L+R)",
422 	"Left Channel (L+R)",
423 	"Stereo",
424 };
425 
426 static SOC_ENUM_SINGLE_DECL(adau1373_lineout1_lr_mux_enum,
427 	ADAU1373_OUTPUT_CTRL, 4, adau1373_lr_mux_text);
428 static SOC_ENUM_SINGLE_DECL(adau1373_lineout2_lr_mux_enum,
429 	ADAU1373_OUTPUT_CTRL, 6, adau1373_lr_mux_text);
430 static SOC_ENUM_SINGLE_DECL(adau1373_speaker_lr_mux_enum,
431 	ADAU1373_LS_CTRL, 4, adau1373_lr_mux_text);
432 
433 static const struct snd_kcontrol_new adau1373_controls[] = {
434 	SOC_DOUBLE_R_TLV("AIF1 Capture Volume", ADAU1373_DAI_RECL_VOL(0),
435 		ADAU1373_DAI_RECR_VOL(0), 0, 0xff, 1, adau1373_digital_tlv),
436 	SOC_DOUBLE_R_TLV("AIF2 Capture Volume", ADAU1373_DAI_RECL_VOL(1),
437 		ADAU1373_DAI_RECR_VOL(1), 0, 0xff, 1, adau1373_digital_tlv),
438 	SOC_DOUBLE_R_TLV("AIF3 Capture Volume", ADAU1373_DAI_RECL_VOL(2),
439 		ADAU1373_DAI_RECR_VOL(2), 0, 0xff, 1, adau1373_digital_tlv),
440 
441 	SOC_DOUBLE_R_TLV("ADC Capture Volume", ADAU1373_ADC_RECL_VOL,
442 		ADAU1373_ADC_RECR_VOL, 0, 0xff, 1, adau1373_digital_tlv),
443 	SOC_DOUBLE_R_TLV("DMIC Capture Volume", ADAU1373_DMIC_RECL_VOL,
444 		ADAU1373_DMIC_RECR_VOL, 0, 0xff, 1, adau1373_digital_tlv),
445 
446 	SOC_DOUBLE_R_TLV("AIF1 Playback Volume", ADAU1373_DAI_PBL_VOL(0),
447 		ADAU1373_DAI_PBR_VOL(0), 0, 0xff, 1, adau1373_digital_tlv),
448 	SOC_DOUBLE_R_TLV("AIF2 Playback Volume", ADAU1373_DAI_PBL_VOL(1),
449 		ADAU1373_DAI_PBR_VOL(1), 0, 0xff, 1, adau1373_digital_tlv),
450 	SOC_DOUBLE_R_TLV("AIF3 Playback Volume", ADAU1373_DAI_PBL_VOL(2),
451 		ADAU1373_DAI_PBR_VOL(2), 0, 0xff, 1, adau1373_digital_tlv),
452 
453 	SOC_DOUBLE_R_TLV("DAC1 Playback Volume", ADAU1373_DAC1_PBL_VOL,
454 		ADAU1373_DAC1_PBR_VOL, 0, 0xff, 1, adau1373_digital_tlv),
455 	SOC_DOUBLE_R_TLV("DAC2 Playback Volume", ADAU1373_DAC2_PBL_VOL,
456 		ADAU1373_DAC2_PBR_VOL, 0, 0xff, 1, adau1373_digital_tlv),
457 
458 	SOC_DOUBLE_R_TLV("Lineout1 Playback Volume", ADAU1373_LLINE_OUT(0),
459 		ADAU1373_RLINE_OUT(0), 0, 0x1f, 0, adau1373_out_tlv),
460 	SOC_DOUBLE_R_TLV("Speaker Playback Volume", ADAU1373_LSPK_OUT,
461 		ADAU1373_RSPK_OUT, 0, 0x1f, 0, adau1373_out_tlv),
462 	SOC_DOUBLE_R_TLV("Headphone Playback Volume", ADAU1373_LHP_OUT,
463 		ADAU1373_RHP_OUT, 0, 0x1f, 0, adau1373_out_tlv),
464 
465 	SOC_DOUBLE_R_TLV("Input 1 Capture Volume", ADAU1373_AINL_CTRL(0),
466 		ADAU1373_AINR_CTRL(0), 0, 0x1f, 0, adau1373_in_pga_tlv),
467 	SOC_DOUBLE_R_TLV("Input 2 Capture Volume", ADAU1373_AINL_CTRL(1),
468 		ADAU1373_AINR_CTRL(1), 0, 0x1f, 0, adau1373_in_pga_tlv),
469 	SOC_DOUBLE_R_TLV("Input 3 Capture Volume", ADAU1373_AINL_CTRL(2),
470 		ADAU1373_AINR_CTRL(2), 0, 0x1f, 0, adau1373_in_pga_tlv),
471 	SOC_DOUBLE_R_TLV("Input 4 Capture Volume", ADAU1373_AINL_CTRL(3),
472 		ADAU1373_AINR_CTRL(3), 0, 0x1f, 0, adau1373_in_pga_tlv),
473 
474 	SOC_SINGLE_TLV("Earpiece Playback Volume", ADAU1373_EP_CTRL, 0, 3, 0,
475 		adau1373_ep_tlv),
476 
477 	SOC_DOUBLE_TLV("AIF3 Boost Playback Volume", ADAU1373_VOL_GAIN1, 4, 5,
478 		1, 0, adau1373_gain_boost_tlv),
479 	SOC_DOUBLE_TLV("AIF2 Boost Playback Volume", ADAU1373_VOL_GAIN1, 2, 3,
480 		1, 0, adau1373_gain_boost_tlv),
481 	SOC_DOUBLE_TLV("AIF1 Boost Playback Volume", ADAU1373_VOL_GAIN1, 0, 1,
482 		1, 0, adau1373_gain_boost_tlv),
483 	SOC_DOUBLE_TLV("AIF3 Boost Capture Volume", ADAU1373_VOL_GAIN2, 4, 5,
484 		1, 0, adau1373_gain_boost_tlv),
485 	SOC_DOUBLE_TLV("AIF2 Boost Capture Volume", ADAU1373_VOL_GAIN2, 2, 3,
486 		1, 0, adau1373_gain_boost_tlv),
487 	SOC_DOUBLE_TLV("AIF1 Boost Capture Volume", ADAU1373_VOL_GAIN2, 0, 1,
488 		1, 0, adau1373_gain_boost_tlv),
489 	SOC_DOUBLE_TLV("DMIC Boost Capture Volume", ADAU1373_VOL_GAIN3, 6, 7,
490 		1, 0, adau1373_gain_boost_tlv),
491 	SOC_DOUBLE_TLV("ADC Boost Capture Volume", ADAU1373_VOL_GAIN3, 4, 5,
492 		1, 0, adau1373_gain_boost_tlv),
493 	SOC_DOUBLE_TLV("DAC2 Boost Playback Volume", ADAU1373_VOL_GAIN3, 2, 3,
494 		1, 0, adau1373_gain_boost_tlv),
495 	SOC_DOUBLE_TLV("DAC1 Boost Playback Volume", ADAU1373_VOL_GAIN3, 0, 1,
496 		1, 0, adau1373_gain_boost_tlv),
497 
498 	SOC_DOUBLE_TLV("Input 1 Boost Capture Volume", ADAU1373_ADC_GAIN, 0, 4,
499 		1, 0, adau1373_input_boost_tlv),
500 	SOC_DOUBLE_TLV("Input 2 Boost Capture Volume", ADAU1373_ADC_GAIN, 1, 5,
501 		1, 0, adau1373_input_boost_tlv),
502 	SOC_DOUBLE_TLV("Input 3 Boost Capture Volume", ADAU1373_ADC_GAIN, 2, 6,
503 		1, 0, adau1373_input_boost_tlv),
504 	SOC_DOUBLE_TLV("Input 4 Boost Capture Volume", ADAU1373_ADC_GAIN, 3, 7,
505 		1, 0, adau1373_input_boost_tlv),
506 
507 	SOC_DOUBLE_TLV("Speaker Boost Playback Volume", ADAU1373_LS_CTRL, 2, 3,
508 		1, 0, adau1373_speaker_boost_tlv),
509 
510 	SOC_ENUM("Lineout1 LR Mux", adau1373_lineout1_lr_mux_enum),
511 	SOC_ENUM("Speaker LR Mux", adau1373_speaker_lr_mux_enum),
512 
513 	SOC_ENUM("HPF Cutoff", adau1373_hpf_cutoff_enum),
514 	SOC_DOUBLE("HPF Switch", ADAU1373_HPF_CTRL, 1, 0, 1, 0),
515 	SOC_ENUM("HPF Channel", adau1373_hpf_channel_enum),
516 
517 	SOC_ENUM("Bass HPF Cutoff", adau1373_bass_hpf_cutoff_enum),
518 	SOC_ENUM("Bass Clip Level Threshold", adau1373_bass_clip_level_enum),
519 	SOC_ENUM("Bass LPF Cutoff", adau1373_bass_lpf_cutoff_enum),
520 	SOC_DOUBLE("Bass Playback Switch", ADAU1373_BASS2, 0, 1, 1, 0),
521 	SOC_SINGLE_TLV("Bass Playback Volume", ADAU1373_BASS2, 2, 7, 0,
522 	    adau1373_bass_tlv),
523 	SOC_ENUM("Bass Channel", adau1373_bass_channel_enum),
524 
525 	SOC_ENUM("3D Freq", adau1373_3d_cutoff_enum),
526 	SOC_ENUM("3D Level", adau1373_3d_level_enum),
527 	SOC_SINGLE("3D Playback Switch", ADAU1373_3D_CTRL2, 0, 1, 0),
528 	SOC_SINGLE_TLV("3D Playback Volume", ADAU1373_3D_CTRL2, 2, 7, 0,
529 		adau1373_3d_tlv),
530 	SOC_ENUM("3D Channel", adau1373_bass_channel_enum),
531 
532 	SOC_SINGLE("Zero Cross Switch", ADAU1373_PWDN_CTRL3, 7, 1, 0),
533 };
534 
535 static const struct snd_kcontrol_new adau1373_lineout2_controls[] = {
536 	SOC_DOUBLE_R_TLV("Lineout2 Playback Volume", ADAU1373_LLINE_OUT(1),
537 		ADAU1373_RLINE_OUT(1), 0, 0x1f, 0, adau1373_out_tlv),
538 	SOC_ENUM("Lineout2 LR Mux", adau1373_lineout2_lr_mux_enum),
539 };
540 
541 static const struct snd_kcontrol_new adau1373_drc_controls[] = {
542 	SOC_ENUM("DRC1 Channel", adau1373_drc1_channel_enum),
543 	SOC_ENUM("DRC2 Channel", adau1373_drc2_channel_enum),
544 	SOC_ENUM("DRC3 Channel", adau1373_drc3_channel_enum),
545 };
546 
adau1373_pll_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)547 static int adau1373_pll_event(struct snd_soc_dapm_widget *w,
548 	struct snd_kcontrol *kcontrol, int event)
549 {
550 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
551 	struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
552 	unsigned int pll_id = w->name[3] - '1';
553 	unsigned int val;
554 
555 	if (SND_SOC_DAPM_EVENT_ON(event))
556 		val = ADAU1373_PLL_CTRL6_PLL_EN;
557 	else
558 		val = 0;
559 
560 	regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id),
561 		ADAU1373_PLL_CTRL6_PLL_EN, val);
562 
563 	if (SND_SOC_DAPM_EVENT_ON(event))
564 		mdelay(5);
565 
566 	return 0;
567 }
568 
569 static const char *adau1373_decimator_text[] = {
570 	"ADC",
571 	"DMIC1",
572 };
573 
574 static SOC_ENUM_SINGLE_VIRT_DECL(adau1373_decimator_enum,
575 	adau1373_decimator_text);
576 
577 static const struct snd_kcontrol_new adau1373_decimator_mux =
578 	SOC_DAPM_ENUM("Decimator Mux", adau1373_decimator_enum);
579 
580 static const struct snd_kcontrol_new adau1373_left_adc_mixer_controls[] = {
581 	SOC_DAPM_SINGLE("DAC1 Switch", ADAU1373_LADC_MIXER, 4, 1, 0),
582 	SOC_DAPM_SINGLE("Input 4 Switch", ADAU1373_LADC_MIXER, 3, 1, 0),
583 	SOC_DAPM_SINGLE("Input 3 Switch", ADAU1373_LADC_MIXER, 2, 1, 0),
584 	SOC_DAPM_SINGLE("Input 2 Switch", ADAU1373_LADC_MIXER, 1, 1, 0),
585 	SOC_DAPM_SINGLE("Input 1 Switch", ADAU1373_LADC_MIXER, 0, 1, 0),
586 };
587 
588 static const struct snd_kcontrol_new adau1373_right_adc_mixer_controls[] = {
589 	SOC_DAPM_SINGLE("DAC1 Switch", ADAU1373_RADC_MIXER, 4, 1, 0),
590 	SOC_DAPM_SINGLE("Input 4 Switch", ADAU1373_RADC_MIXER, 3, 1, 0),
591 	SOC_DAPM_SINGLE("Input 3 Switch", ADAU1373_RADC_MIXER, 2, 1, 0),
592 	SOC_DAPM_SINGLE("Input 2 Switch", ADAU1373_RADC_MIXER, 1, 1, 0),
593 	SOC_DAPM_SINGLE("Input 1 Switch", ADAU1373_RADC_MIXER, 0, 1, 0),
594 };
595 
596 #define DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(_name, _reg) \
597 const struct snd_kcontrol_new _name[] = { \
598 	SOC_DAPM_SINGLE("Left DAC2 Switch", _reg, 7, 1, 0), \
599 	SOC_DAPM_SINGLE("Right DAC2 Switch", _reg, 6, 1, 0), \
600 	SOC_DAPM_SINGLE("Left DAC1 Switch", _reg, 5, 1, 0), \
601 	SOC_DAPM_SINGLE("Right DAC1 Switch", _reg, 4, 1, 0), \
602 	SOC_DAPM_SINGLE("Input 4 Bypass Switch", _reg, 3, 1, 0), \
603 	SOC_DAPM_SINGLE("Input 3 Bypass Switch", _reg, 2, 1, 0), \
604 	SOC_DAPM_SINGLE("Input 2 Bypass Switch", _reg, 1, 1, 0), \
605 	SOC_DAPM_SINGLE("Input 1 Bypass Switch", _reg, 0, 1, 0), \
606 }
607 
608 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_line1_mixer_controls,
609 	ADAU1373_LLINE1_MIX);
610 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_line1_mixer_controls,
611 	ADAU1373_RLINE1_MIX);
612 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_line2_mixer_controls,
613 	ADAU1373_LLINE2_MIX);
614 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_line2_mixer_controls,
615 	ADAU1373_RLINE2_MIX);
616 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_spk_mixer_controls,
617 	ADAU1373_LSPK_MIX);
618 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_spk_mixer_controls,
619 	ADAU1373_RSPK_MIX);
620 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_ep_mixer_controls,
621 	ADAU1373_EP_MIX);
622 
623 static const struct snd_kcontrol_new adau1373_left_hp_mixer_controls[] = {
624 	SOC_DAPM_SINGLE("Left DAC1 Switch", ADAU1373_LHP_MIX, 5, 1, 0),
625 	SOC_DAPM_SINGLE("Left DAC2 Switch", ADAU1373_LHP_MIX, 4, 1, 0),
626 	SOC_DAPM_SINGLE("Input 4 Bypass Switch", ADAU1373_LHP_MIX, 3, 1, 0),
627 	SOC_DAPM_SINGLE("Input 3 Bypass Switch", ADAU1373_LHP_MIX, 2, 1, 0),
628 	SOC_DAPM_SINGLE("Input 2 Bypass Switch", ADAU1373_LHP_MIX, 1, 1, 0),
629 	SOC_DAPM_SINGLE("Input 1 Bypass Switch", ADAU1373_LHP_MIX, 0, 1, 0),
630 };
631 
632 static const struct snd_kcontrol_new adau1373_right_hp_mixer_controls[] = {
633 	SOC_DAPM_SINGLE("Right DAC1 Switch", ADAU1373_RHP_MIX, 5, 1, 0),
634 	SOC_DAPM_SINGLE("Right DAC2 Switch", ADAU1373_RHP_MIX, 4, 1, 0),
635 	SOC_DAPM_SINGLE("Input 4 Bypass Switch", ADAU1373_RHP_MIX, 3, 1, 0),
636 	SOC_DAPM_SINGLE("Input 3 Bypass Switch", ADAU1373_RHP_MIX, 2, 1, 0),
637 	SOC_DAPM_SINGLE("Input 2 Bypass Switch", ADAU1373_RHP_MIX, 1, 1, 0),
638 	SOC_DAPM_SINGLE("Input 1 Bypass Switch", ADAU1373_RHP_MIX, 0, 1, 0),
639 };
640 
641 #define DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(_name, _reg) \
642 const struct snd_kcontrol_new _name[] = { \
643 	SOC_DAPM_SINGLE("DMIC2 Swapped Switch", _reg, 6, 1, 0), \
644 	SOC_DAPM_SINGLE("DMIC2 Switch", _reg, 5, 1, 0), \
645 	SOC_DAPM_SINGLE("ADC/DMIC1 Swapped Switch", _reg, 4, 1, 0), \
646 	SOC_DAPM_SINGLE("ADC/DMIC1 Switch", _reg, 3, 1, 0), \
647 	SOC_DAPM_SINGLE("AIF3 Switch", _reg, 2, 1, 0), \
648 	SOC_DAPM_SINGLE("AIF2 Switch", _reg, 1, 1, 0), \
649 	SOC_DAPM_SINGLE("AIF1 Switch", _reg, 0, 1, 0), \
650 }
651 
652 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel1_mixer_controls,
653 	ADAU1373_DIN_MIX_CTRL(0));
654 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel2_mixer_controls,
655 	ADAU1373_DIN_MIX_CTRL(1));
656 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel3_mixer_controls,
657 	ADAU1373_DIN_MIX_CTRL(2));
658 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel4_mixer_controls,
659 	ADAU1373_DIN_MIX_CTRL(3));
660 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel5_mixer_controls,
661 	ADAU1373_DIN_MIX_CTRL(4));
662 
663 #define DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(_name, _reg) \
664 const struct snd_kcontrol_new _name[] = { \
665 	SOC_DAPM_SINGLE("DSP Channel5 Switch", _reg, 4, 1, 0), \
666 	SOC_DAPM_SINGLE("DSP Channel4 Switch", _reg, 3, 1, 0), \
667 	SOC_DAPM_SINGLE("DSP Channel3 Switch", _reg, 2, 1, 0), \
668 	SOC_DAPM_SINGLE("DSP Channel2 Switch", _reg, 1, 1, 0), \
669 	SOC_DAPM_SINGLE("DSP Channel1 Switch", _reg, 0, 1, 0), \
670 }
671 
672 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif1_mixer_controls,
673 	ADAU1373_DOUT_MIX_CTRL(0));
674 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif2_mixer_controls,
675 	ADAU1373_DOUT_MIX_CTRL(1));
676 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif3_mixer_controls,
677 	ADAU1373_DOUT_MIX_CTRL(2));
678 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_dac1_mixer_controls,
679 	ADAU1373_DOUT_MIX_CTRL(3));
680 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_dac2_mixer_controls,
681 	ADAU1373_DOUT_MIX_CTRL(4));
682 
683 static const struct snd_soc_dapm_widget adau1373_dapm_widgets[] = {
684 	/* Datasheet claims Left ADC is bit 6 and Right ADC is bit 7, but that
685 	 * doesn't seem to be the case. */
686 	SND_SOC_DAPM_ADC("Left ADC", NULL, ADAU1373_PWDN_CTRL1, 7, 0),
687 	SND_SOC_DAPM_ADC("Right ADC", NULL, ADAU1373_PWDN_CTRL1, 6, 0),
688 
689 	SND_SOC_DAPM_ADC("DMIC1", NULL, ADAU1373_DIGMICCTRL, 0, 0),
690 	SND_SOC_DAPM_ADC("DMIC2", NULL, ADAU1373_DIGMICCTRL, 2, 0),
691 
692 	SND_SOC_DAPM_MUX("Decimator Mux", SND_SOC_NOPM, 0, 0,
693 		&adau1373_decimator_mux),
694 
695 	SND_SOC_DAPM_SUPPLY("MICBIAS2", ADAU1373_PWDN_CTRL1, 5, 0, NULL, 0),
696 	SND_SOC_DAPM_SUPPLY("MICBIAS1", ADAU1373_PWDN_CTRL1, 4, 0, NULL, 0),
697 
698 	SND_SOC_DAPM_PGA("IN4PGA", ADAU1373_PWDN_CTRL1, 3, 0, NULL, 0),
699 	SND_SOC_DAPM_PGA("IN3PGA", ADAU1373_PWDN_CTRL1, 2, 0, NULL, 0),
700 	SND_SOC_DAPM_PGA("IN2PGA", ADAU1373_PWDN_CTRL1, 1, 0, NULL, 0),
701 	SND_SOC_DAPM_PGA("IN1PGA", ADAU1373_PWDN_CTRL1, 0, 0, NULL, 0),
702 
703 	SND_SOC_DAPM_DAC("Left DAC2", NULL, ADAU1373_PWDN_CTRL2, 7, 0),
704 	SND_SOC_DAPM_DAC("Right DAC2", NULL, ADAU1373_PWDN_CTRL2, 6, 0),
705 	SND_SOC_DAPM_DAC("Left DAC1", NULL, ADAU1373_PWDN_CTRL2, 5, 0),
706 	SND_SOC_DAPM_DAC("Right DAC1", NULL, ADAU1373_PWDN_CTRL2, 4, 0),
707 
708 	SOC_MIXER_ARRAY("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
709 		adau1373_left_adc_mixer_controls),
710 	SOC_MIXER_ARRAY("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
711 		adau1373_right_adc_mixer_controls),
712 
713 	SOC_MIXER_ARRAY("Left Lineout2 Mixer", ADAU1373_PWDN_CTRL2, 3, 0,
714 		adau1373_left_line2_mixer_controls),
715 	SOC_MIXER_ARRAY("Right Lineout2 Mixer", ADAU1373_PWDN_CTRL2, 2, 0,
716 		adau1373_right_line2_mixer_controls),
717 	SOC_MIXER_ARRAY("Left Lineout1 Mixer", ADAU1373_PWDN_CTRL2, 1, 0,
718 		adau1373_left_line1_mixer_controls),
719 	SOC_MIXER_ARRAY("Right Lineout1 Mixer", ADAU1373_PWDN_CTRL2, 0, 0,
720 		adau1373_right_line1_mixer_controls),
721 
722 	SOC_MIXER_ARRAY("Earpiece Mixer", ADAU1373_PWDN_CTRL3, 4, 0,
723 		adau1373_ep_mixer_controls),
724 	SOC_MIXER_ARRAY("Left Speaker Mixer", ADAU1373_PWDN_CTRL3, 3, 0,
725 		adau1373_left_spk_mixer_controls),
726 	SOC_MIXER_ARRAY("Right Speaker Mixer", ADAU1373_PWDN_CTRL3, 2, 0,
727 		adau1373_right_spk_mixer_controls),
728 	SOC_MIXER_ARRAY("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
729 		adau1373_left_hp_mixer_controls),
730 	SOC_MIXER_ARRAY("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
731 		adau1373_right_hp_mixer_controls),
732 	SND_SOC_DAPM_SUPPLY("Headphone Enable", ADAU1373_PWDN_CTRL3, 1, 0,
733 		NULL, 0),
734 
735 	SND_SOC_DAPM_SUPPLY("AIF1 CLK", ADAU1373_SRC_DAI_CTRL(0), 0, 0,
736 	    NULL, 0),
737 	SND_SOC_DAPM_SUPPLY("AIF2 CLK", ADAU1373_SRC_DAI_CTRL(1), 0, 0,
738 	    NULL, 0),
739 	SND_SOC_DAPM_SUPPLY("AIF3 CLK", ADAU1373_SRC_DAI_CTRL(2), 0, 0,
740 	    NULL, 0),
741 	SND_SOC_DAPM_SUPPLY("AIF1 IN SRC", ADAU1373_SRC_DAI_CTRL(0), 2, 0,
742 	    NULL, 0),
743 	SND_SOC_DAPM_SUPPLY("AIF1 OUT SRC", ADAU1373_SRC_DAI_CTRL(0), 1, 0,
744 	    NULL, 0),
745 	SND_SOC_DAPM_SUPPLY("AIF2 IN SRC", ADAU1373_SRC_DAI_CTRL(1), 2, 0,
746 	    NULL, 0),
747 	SND_SOC_DAPM_SUPPLY("AIF2 OUT SRC", ADAU1373_SRC_DAI_CTRL(1), 1, 0,
748 	    NULL, 0),
749 	SND_SOC_DAPM_SUPPLY("AIF3 IN SRC", ADAU1373_SRC_DAI_CTRL(2), 2, 0,
750 	    NULL, 0),
751 	SND_SOC_DAPM_SUPPLY("AIF3 OUT SRC", ADAU1373_SRC_DAI_CTRL(2), 1, 0,
752 	    NULL, 0),
753 
754 	SND_SOC_DAPM_AIF_IN("AIF1 IN", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
755 	SND_SOC_DAPM_AIF_OUT("AIF1 OUT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
756 	SND_SOC_DAPM_AIF_IN("AIF2 IN", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
757 	SND_SOC_DAPM_AIF_OUT("AIF2 OUT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
758 	SND_SOC_DAPM_AIF_IN("AIF3 IN", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
759 	SND_SOC_DAPM_AIF_OUT("AIF3 OUT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
760 
761 	SOC_MIXER_ARRAY("DSP Channel1 Mixer", SND_SOC_NOPM, 0, 0,
762 		adau1373_dsp_channel1_mixer_controls),
763 	SOC_MIXER_ARRAY("DSP Channel2 Mixer", SND_SOC_NOPM, 0, 0,
764 		adau1373_dsp_channel2_mixer_controls),
765 	SOC_MIXER_ARRAY("DSP Channel3 Mixer", SND_SOC_NOPM, 0, 0,
766 		adau1373_dsp_channel3_mixer_controls),
767 	SOC_MIXER_ARRAY("DSP Channel4 Mixer", SND_SOC_NOPM, 0, 0,
768 		adau1373_dsp_channel4_mixer_controls),
769 	SOC_MIXER_ARRAY("DSP Channel5 Mixer", SND_SOC_NOPM, 0, 0,
770 		adau1373_dsp_channel5_mixer_controls),
771 
772 	SOC_MIXER_ARRAY("AIF1 Mixer", SND_SOC_NOPM, 0, 0,
773 		adau1373_aif1_mixer_controls),
774 	SOC_MIXER_ARRAY("AIF2 Mixer", SND_SOC_NOPM, 0, 0,
775 		adau1373_aif2_mixer_controls),
776 	SOC_MIXER_ARRAY("AIF3 Mixer", SND_SOC_NOPM, 0, 0,
777 		adau1373_aif3_mixer_controls),
778 	SOC_MIXER_ARRAY("DAC1 Mixer", SND_SOC_NOPM, 0, 0,
779 		adau1373_dac1_mixer_controls),
780 	SOC_MIXER_ARRAY("DAC2 Mixer", SND_SOC_NOPM, 0, 0,
781 		adau1373_dac2_mixer_controls),
782 
783 	SND_SOC_DAPM_SUPPLY("DSP", ADAU1373_DIGEN, 4, 0, NULL, 0),
784 	SND_SOC_DAPM_SUPPLY("Recording Engine B", ADAU1373_DIGEN, 3, 0, NULL, 0),
785 	SND_SOC_DAPM_SUPPLY("Recording Engine A", ADAU1373_DIGEN, 2, 0, NULL, 0),
786 	SND_SOC_DAPM_SUPPLY("Playback Engine B", ADAU1373_DIGEN, 1, 0, NULL, 0),
787 	SND_SOC_DAPM_SUPPLY("Playback Engine A", ADAU1373_DIGEN, 0, 0, NULL, 0),
788 
789 	SND_SOC_DAPM_SUPPLY("PLL1", SND_SOC_NOPM, 0, 0, adau1373_pll_event,
790 		SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
791 	SND_SOC_DAPM_SUPPLY("PLL2", SND_SOC_NOPM, 0, 0, adau1373_pll_event,
792 		SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
793 	SND_SOC_DAPM_SUPPLY("SYSCLK1", ADAU1373_CLK_SRC_DIV(0), 7, 0, NULL, 0),
794 	SND_SOC_DAPM_SUPPLY("SYSCLK2", ADAU1373_CLK_SRC_DIV(1), 7, 0, NULL, 0),
795 
796 	SND_SOC_DAPM_INPUT("AIN1L"),
797 	SND_SOC_DAPM_INPUT("AIN1R"),
798 	SND_SOC_DAPM_INPUT("AIN2L"),
799 	SND_SOC_DAPM_INPUT("AIN2R"),
800 	SND_SOC_DAPM_INPUT("AIN3L"),
801 	SND_SOC_DAPM_INPUT("AIN3R"),
802 	SND_SOC_DAPM_INPUT("AIN4L"),
803 	SND_SOC_DAPM_INPUT("AIN4R"),
804 
805 	SND_SOC_DAPM_INPUT("DMIC1DAT"),
806 	SND_SOC_DAPM_INPUT("DMIC2DAT"),
807 
808 	SND_SOC_DAPM_OUTPUT("LOUT1L"),
809 	SND_SOC_DAPM_OUTPUT("LOUT1R"),
810 	SND_SOC_DAPM_OUTPUT("LOUT2L"),
811 	SND_SOC_DAPM_OUTPUT("LOUT2R"),
812 	SND_SOC_DAPM_OUTPUT("HPL"),
813 	SND_SOC_DAPM_OUTPUT("HPR"),
814 	SND_SOC_DAPM_OUTPUT("SPKL"),
815 	SND_SOC_DAPM_OUTPUT("SPKR"),
816 	SND_SOC_DAPM_OUTPUT("EP"),
817 };
818 
adau1373_check_aif_clk(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)819 static int adau1373_check_aif_clk(struct snd_soc_dapm_widget *source,
820 	struct snd_soc_dapm_widget *sink)
821 {
822 	struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
823 	struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
824 	unsigned int dai;
825 	const char *clk;
826 
827 	dai = sink->name[3] - '1';
828 
829 	if (!adau1373->dais[dai].clock_provider)
830 		return 0;
831 
832 	if (adau1373->dais[dai].clk_src == ADAU1373_CLK_SRC_PLL1)
833 		clk = "SYSCLK1";
834 	else
835 		clk = "SYSCLK2";
836 
837 	return strcmp(source->name, clk) == 0;
838 }
839 
adau1373_check_src(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)840 static int adau1373_check_src(struct snd_soc_dapm_widget *source,
841 	struct snd_soc_dapm_widget *sink)
842 {
843 	struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
844 	struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
845 	unsigned int dai;
846 
847 	dai = sink->name[3] - '1';
848 
849 	return adau1373->dais[dai].enable_src;
850 }
851 
852 #define DSP_CHANNEL_MIXER_ROUTES(_sink) \
853 	{ _sink, "DMIC2 Swapped Switch", "DMIC2" }, \
854 	{ _sink, "DMIC2 Switch", "DMIC2" }, \
855 	{ _sink, "ADC/DMIC1 Swapped Switch", "Decimator Mux" }, \
856 	{ _sink, "ADC/DMIC1 Switch", "Decimator Mux" }, \
857 	{ _sink, "AIF1 Switch", "AIF1 IN" }, \
858 	{ _sink, "AIF2 Switch", "AIF2 IN" }, \
859 	{ _sink, "AIF3 Switch", "AIF3 IN" }
860 
861 #define DSP_OUTPUT_MIXER_ROUTES(_sink) \
862 	{ _sink, "DSP Channel1 Switch", "DSP Channel1 Mixer" }, \
863 	{ _sink, "DSP Channel2 Switch", "DSP Channel2 Mixer" }, \
864 	{ _sink, "DSP Channel3 Switch", "DSP Channel3 Mixer" }, \
865 	{ _sink, "DSP Channel4 Switch", "DSP Channel4 Mixer" }, \
866 	{ _sink, "DSP Channel5 Switch", "DSP Channel5 Mixer" }
867 
868 #define LEFT_OUTPUT_MIXER_ROUTES(_sink) \
869 	{ _sink, "Right DAC2 Switch", "Right DAC2" }, \
870 	{ _sink, "Left DAC2 Switch", "Left DAC2" }, \
871 	{ _sink, "Right DAC1 Switch", "Right DAC1" }, \
872 	{ _sink, "Left DAC1 Switch", "Left DAC1" }, \
873 	{ _sink, "Input 1 Bypass Switch", "IN1PGA" }, \
874 	{ _sink, "Input 2 Bypass Switch", "IN2PGA" }, \
875 	{ _sink, "Input 3 Bypass Switch", "IN3PGA" }, \
876 	{ _sink, "Input 4 Bypass Switch", "IN4PGA" }
877 
878 #define RIGHT_OUTPUT_MIXER_ROUTES(_sink) \
879 	{ _sink, "Right DAC2 Switch", "Right DAC2" }, \
880 	{ _sink, "Left DAC2 Switch", "Left DAC2" }, \
881 	{ _sink, "Right DAC1 Switch", "Right DAC1" }, \
882 	{ _sink, "Left DAC1 Switch", "Left DAC1" }, \
883 	{ _sink, "Input 1 Bypass Switch", "IN1PGA" }, \
884 	{ _sink, "Input 2 Bypass Switch", "IN2PGA" }, \
885 	{ _sink, "Input 3 Bypass Switch", "IN3PGA" }, \
886 	{ _sink, "Input 4 Bypass Switch", "IN4PGA" }
887 
888 static const struct snd_soc_dapm_route adau1373_dapm_routes[] = {
889 	{ "Left ADC Mixer", "DAC1 Switch", "Left DAC1" },
890 	{ "Left ADC Mixer", "Input 1 Switch", "IN1PGA" },
891 	{ "Left ADC Mixer", "Input 2 Switch", "IN2PGA" },
892 	{ "Left ADC Mixer", "Input 3 Switch", "IN3PGA" },
893 	{ "Left ADC Mixer", "Input 4 Switch", "IN4PGA" },
894 
895 	{ "Right ADC Mixer", "DAC1 Switch", "Right DAC1" },
896 	{ "Right ADC Mixer", "Input 1 Switch", "IN1PGA" },
897 	{ "Right ADC Mixer", "Input 2 Switch", "IN2PGA" },
898 	{ "Right ADC Mixer", "Input 3 Switch", "IN3PGA" },
899 	{ "Right ADC Mixer", "Input 4 Switch", "IN4PGA" },
900 
901 	{ "Left ADC", NULL, "Left ADC Mixer" },
902 	{ "Right ADC", NULL, "Right ADC Mixer" },
903 
904 	{ "Decimator Mux", "ADC", "Left ADC" },
905 	{ "Decimator Mux", "ADC", "Right ADC" },
906 	{ "Decimator Mux", "DMIC1", "DMIC1" },
907 
908 	DSP_CHANNEL_MIXER_ROUTES("DSP Channel1 Mixer"),
909 	DSP_CHANNEL_MIXER_ROUTES("DSP Channel2 Mixer"),
910 	DSP_CHANNEL_MIXER_ROUTES("DSP Channel3 Mixer"),
911 	DSP_CHANNEL_MIXER_ROUTES("DSP Channel4 Mixer"),
912 	DSP_CHANNEL_MIXER_ROUTES("DSP Channel5 Mixer"),
913 
914 	DSP_OUTPUT_MIXER_ROUTES("AIF1 Mixer"),
915 	DSP_OUTPUT_MIXER_ROUTES("AIF2 Mixer"),
916 	DSP_OUTPUT_MIXER_ROUTES("AIF3 Mixer"),
917 	DSP_OUTPUT_MIXER_ROUTES("DAC1 Mixer"),
918 	DSP_OUTPUT_MIXER_ROUTES("DAC2 Mixer"),
919 
920 	{ "AIF1 OUT", NULL, "AIF1 Mixer" },
921 	{ "AIF2 OUT", NULL, "AIF2 Mixer" },
922 	{ "AIF3 OUT", NULL, "AIF3 Mixer" },
923 	{ "Left DAC1", NULL, "DAC1 Mixer" },
924 	{ "Right DAC1", NULL, "DAC1 Mixer" },
925 	{ "Left DAC2", NULL, "DAC2 Mixer" },
926 	{ "Right DAC2", NULL, "DAC2 Mixer" },
927 
928 	LEFT_OUTPUT_MIXER_ROUTES("Left Lineout1 Mixer"),
929 	RIGHT_OUTPUT_MIXER_ROUTES("Right Lineout1 Mixer"),
930 	LEFT_OUTPUT_MIXER_ROUTES("Left Lineout2 Mixer"),
931 	RIGHT_OUTPUT_MIXER_ROUTES("Right Lineout2 Mixer"),
932 	LEFT_OUTPUT_MIXER_ROUTES("Left Speaker Mixer"),
933 	RIGHT_OUTPUT_MIXER_ROUTES("Right Speaker Mixer"),
934 
935 	{ "Left Headphone Mixer", "Left DAC2 Switch", "Left DAC2" },
936 	{ "Left Headphone Mixer", "Left DAC1 Switch", "Left DAC1" },
937 	{ "Left Headphone Mixer", "Input 1 Bypass Switch", "IN1PGA" },
938 	{ "Left Headphone Mixer", "Input 2 Bypass Switch", "IN2PGA" },
939 	{ "Left Headphone Mixer", "Input 3 Bypass Switch", "IN3PGA" },
940 	{ "Left Headphone Mixer", "Input 4 Bypass Switch", "IN4PGA" },
941 	{ "Right Headphone Mixer", "Right DAC2 Switch", "Right DAC2" },
942 	{ "Right Headphone Mixer", "Right DAC1 Switch", "Right DAC1" },
943 	{ "Right Headphone Mixer", "Input 1 Bypass Switch", "IN1PGA" },
944 	{ "Right Headphone Mixer", "Input 2 Bypass Switch", "IN2PGA" },
945 	{ "Right Headphone Mixer", "Input 3 Bypass Switch", "IN3PGA" },
946 	{ "Right Headphone Mixer", "Input 4 Bypass Switch", "IN4PGA" },
947 
948 	{ "Left Headphone Mixer", NULL, "Headphone Enable" },
949 	{ "Right Headphone Mixer", NULL, "Headphone Enable" },
950 
951 	{ "Earpiece Mixer", "Right DAC2 Switch", "Right DAC2" },
952 	{ "Earpiece Mixer", "Left DAC2 Switch", "Left DAC2" },
953 	{ "Earpiece Mixer", "Right DAC1 Switch", "Right DAC1" },
954 	{ "Earpiece Mixer", "Left DAC1 Switch", "Left DAC1" },
955 	{ "Earpiece Mixer", "Input 1 Bypass Switch", "IN1PGA" },
956 	{ "Earpiece Mixer", "Input 2 Bypass Switch", "IN2PGA" },
957 	{ "Earpiece Mixer", "Input 3 Bypass Switch", "IN3PGA" },
958 	{ "Earpiece Mixer", "Input 4 Bypass Switch", "IN4PGA" },
959 
960 	{ "LOUT1L", NULL, "Left Lineout1 Mixer" },
961 	{ "LOUT1R", NULL, "Right Lineout1 Mixer" },
962 	{ "LOUT2L", NULL, "Left Lineout2 Mixer" },
963 	{ "LOUT2R", NULL, "Right Lineout2 Mixer" },
964 	{ "SPKL", NULL, "Left Speaker Mixer" },
965 	{ "SPKR", NULL, "Right Speaker Mixer" },
966 	{ "HPL", NULL, "Left Headphone Mixer" },
967 	{ "HPR", NULL, "Right Headphone Mixer" },
968 	{ "EP", NULL, "Earpiece Mixer" },
969 
970 	{ "IN1PGA", NULL, "AIN1L" },
971 	{ "IN2PGA", NULL, "AIN2L" },
972 	{ "IN3PGA", NULL, "AIN3L" },
973 	{ "IN4PGA", NULL, "AIN4L" },
974 	{ "IN1PGA", NULL, "AIN1R" },
975 	{ "IN2PGA", NULL, "AIN2R" },
976 	{ "IN3PGA", NULL, "AIN3R" },
977 	{ "IN4PGA", NULL, "AIN4R" },
978 
979 	{ "SYSCLK1", NULL, "PLL1" },
980 	{ "SYSCLK2", NULL, "PLL2" },
981 
982 	{ "Left DAC1", NULL, "SYSCLK1" },
983 	{ "Right DAC1", NULL, "SYSCLK1" },
984 	{ "Left DAC2", NULL, "SYSCLK1" },
985 	{ "Right DAC2", NULL, "SYSCLK1" },
986 	{ "Left ADC", NULL, "SYSCLK1" },
987 	{ "Right ADC", NULL, "SYSCLK1" },
988 
989 	{ "DSP", NULL, "SYSCLK1" },
990 
991 	{ "AIF1 Mixer", NULL, "DSP" },
992 	{ "AIF2 Mixer", NULL, "DSP" },
993 	{ "AIF3 Mixer", NULL, "DSP" },
994 	{ "DAC1 Mixer", NULL, "DSP" },
995 	{ "DAC2 Mixer", NULL, "DSP" },
996 	{ "DAC1 Mixer", NULL, "Playback Engine A" },
997 	{ "DAC2 Mixer", NULL, "Playback Engine B" },
998 	{ "Left ADC Mixer", NULL, "Recording Engine A" },
999 	{ "Right ADC Mixer", NULL, "Recording Engine A" },
1000 
1001 	{ "AIF1 CLK", NULL, "SYSCLK1", adau1373_check_aif_clk },
1002 	{ "AIF2 CLK", NULL, "SYSCLK1", adau1373_check_aif_clk },
1003 	{ "AIF3 CLK", NULL, "SYSCLK1", adau1373_check_aif_clk },
1004 	{ "AIF1 CLK", NULL, "SYSCLK2", adau1373_check_aif_clk },
1005 	{ "AIF2 CLK", NULL, "SYSCLK2", adau1373_check_aif_clk },
1006 	{ "AIF3 CLK", NULL, "SYSCLK2", adau1373_check_aif_clk },
1007 
1008 	{ "AIF1 IN", NULL, "AIF1 CLK" },
1009 	{ "AIF1 OUT", NULL, "AIF1 CLK" },
1010 	{ "AIF2 IN", NULL, "AIF2 CLK" },
1011 	{ "AIF2 OUT", NULL, "AIF2 CLK" },
1012 	{ "AIF3 IN", NULL, "AIF3 CLK" },
1013 	{ "AIF3 OUT", NULL, "AIF3 CLK" },
1014 	{ "AIF1 IN", NULL, "AIF1 IN SRC", adau1373_check_src },
1015 	{ "AIF1 OUT", NULL, "AIF1 OUT SRC", adau1373_check_src },
1016 	{ "AIF2 IN", NULL, "AIF2 IN SRC", adau1373_check_src },
1017 	{ "AIF2 OUT", NULL, "AIF2 OUT SRC", adau1373_check_src },
1018 	{ "AIF3 IN", NULL, "AIF3 IN SRC", adau1373_check_src },
1019 	{ "AIF3 OUT", NULL, "AIF3 OUT SRC", adau1373_check_src },
1020 
1021 	{ "DMIC1", NULL, "DMIC1DAT" },
1022 	{ "DMIC1", NULL, "SYSCLK1" },
1023 	{ "DMIC1", NULL, "Recording Engine A" },
1024 	{ "DMIC2", NULL, "DMIC2DAT" },
1025 	{ "DMIC2", NULL, "SYSCLK1" },
1026 	{ "DMIC2", NULL, "Recording Engine B" },
1027 };
1028 
adau1373_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1029 static int adau1373_hw_params(struct snd_pcm_substream *substream,
1030 	struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1031 {
1032 	struct snd_soc_component *component = dai->component;
1033 	struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
1034 	struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id];
1035 	unsigned int div;
1036 	unsigned int freq;
1037 	unsigned int ctrl;
1038 
1039 	freq = adau1373_dai->sysclk;
1040 
1041 	if (freq % params_rate(params) != 0)
1042 		return -EINVAL;
1043 
1044 	switch (freq / params_rate(params)) {
1045 	case 1024: /* sysclk / 256 */
1046 		div = 0;
1047 		break;
1048 	case 1536: /* 2/3 sysclk / 256 */
1049 		div = 1;
1050 		break;
1051 	case 2048: /* 1/2 sysclk / 256 */
1052 		div = 2;
1053 		break;
1054 	case 3072: /* 1/3 sysclk / 256 */
1055 		div = 3;
1056 		break;
1057 	case 4096: /* 1/4 sysclk / 256 */
1058 		div = 4;
1059 		break;
1060 	case 6144: /* 1/6 sysclk / 256 */
1061 		div = 5;
1062 		break;
1063 	case 5632: /* 2/11 sysclk / 256 */
1064 		div = 6;
1065 		break;
1066 	default:
1067 		return -EINVAL;
1068 	}
1069 
1070 	adau1373_dai->enable_src = (div != 0);
1071 
1072 	regmap_update_bits(adau1373->regmap, ADAU1373_BCLKDIV(dai->id),
1073 		ADAU1373_BCLKDIV_SR_MASK | ADAU1373_BCLKDIV_BCLK_MASK,
1074 		(div << 2) | ADAU1373_BCLKDIV_64);
1075 
1076 	switch (params_width(params)) {
1077 	case 16:
1078 		ctrl = ADAU1373_DAI_WLEN_16;
1079 		break;
1080 	case 20:
1081 		ctrl = ADAU1373_DAI_WLEN_20;
1082 		break;
1083 	case 24:
1084 		ctrl = ADAU1373_DAI_WLEN_24;
1085 		break;
1086 	case 32:
1087 		ctrl = ADAU1373_DAI_WLEN_32;
1088 		break;
1089 	default:
1090 		return -EINVAL;
1091 	}
1092 
1093 	return regmap_update_bits(adau1373->regmap, ADAU1373_DAI(dai->id),
1094 			ADAU1373_DAI_WLEN_MASK, ctrl);
1095 }
1096 
adau1373_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)1097 static int adau1373_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1098 {
1099 	struct snd_soc_component *component = dai->component;
1100 	struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
1101 	struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id];
1102 	unsigned int ctrl;
1103 
1104 	switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1105 	case SND_SOC_DAIFMT_CBP_CFP:
1106 		ctrl = ADAU1373_DAI_MASTER;
1107 		adau1373_dai->clock_provider = true;
1108 		break;
1109 	case SND_SOC_DAIFMT_CBC_CFC:
1110 		ctrl = 0;
1111 		adau1373_dai->clock_provider = false;
1112 		break;
1113 	default:
1114 		return -EINVAL;
1115 	}
1116 
1117 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1118 	case SND_SOC_DAIFMT_I2S:
1119 		ctrl |= ADAU1373_DAI_FORMAT_I2S;
1120 		break;
1121 	case SND_SOC_DAIFMT_LEFT_J:
1122 		ctrl |= ADAU1373_DAI_FORMAT_LEFT_J;
1123 		break;
1124 	case SND_SOC_DAIFMT_RIGHT_J:
1125 		ctrl |= ADAU1373_DAI_FORMAT_RIGHT_J;
1126 		break;
1127 	case SND_SOC_DAIFMT_DSP_B:
1128 		ctrl |= ADAU1373_DAI_FORMAT_DSP;
1129 		break;
1130 	default:
1131 		return -EINVAL;
1132 	}
1133 
1134 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1135 	case SND_SOC_DAIFMT_NB_NF:
1136 		break;
1137 	case SND_SOC_DAIFMT_IB_NF:
1138 		ctrl |= ADAU1373_DAI_INVERT_BCLK;
1139 		break;
1140 	case SND_SOC_DAIFMT_NB_IF:
1141 		ctrl |= ADAU1373_DAI_INVERT_LRCLK;
1142 		break;
1143 	case SND_SOC_DAIFMT_IB_IF:
1144 		ctrl |= ADAU1373_DAI_INVERT_LRCLK | ADAU1373_DAI_INVERT_BCLK;
1145 		break;
1146 	default:
1147 		return -EINVAL;
1148 	}
1149 
1150 	regmap_update_bits(adau1373->regmap, ADAU1373_DAI(dai->id),
1151 		~ADAU1373_DAI_WLEN_MASK, ctrl);
1152 
1153 	return 0;
1154 }
1155 
adau1373_set_dai_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)1156 static int adau1373_set_dai_sysclk(struct snd_soc_dai *dai,
1157 	int clk_id, unsigned int freq, int dir)
1158 {
1159 	struct adau1373 *adau1373 = snd_soc_component_get_drvdata(dai->component);
1160 	struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id];
1161 
1162 	switch (clk_id) {
1163 	case ADAU1373_CLK_SRC_PLL1:
1164 	case ADAU1373_CLK_SRC_PLL2:
1165 		break;
1166 	default:
1167 		return -EINVAL;
1168 	}
1169 
1170 	adau1373_dai->sysclk = freq;
1171 	adau1373_dai->clk_src = clk_id;
1172 
1173 	regmap_update_bits(adau1373->regmap, ADAU1373_BCLKDIV(dai->id),
1174 		ADAU1373_BCLKDIV_SOURCE, clk_id << 5);
1175 
1176 	return 0;
1177 }
1178 
1179 static const struct snd_soc_dai_ops adau1373_dai_ops = {
1180 	.hw_params	= adau1373_hw_params,
1181 	.set_sysclk	= adau1373_set_dai_sysclk,
1182 	.set_fmt	= adau1373_set_dai_fmt,
1183 };
1184 
1185 #define ADAU1373_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1186 	SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1187 
1188 static struct snd_soc_dai_driver adau1373_dai_driver[] = {
1189 	{
1190 		.id = 0,
1191 		.name = "adau1373-aif1",
1192 		.playback = {
1193 			.stream_name = "AIF1 Playback",
1194 			.channels_min = 2,
1195 			.channels_max = 2,
1196 			.rates = SNDRV_PCM_RATE_8000_48000,
1197 			.formats = ADAU1373_FORMATS,
1198 		},
1199 		.capture = {
1200 			.stream_name = "AIF1 Capture",
1201 			.channels_min = 2,
1202 			.channels_max = 2,
1203 			.rates = SNDRV_PCM_RATE_8000_48000,
1204 			.formats = ADAU1373_FORMATS,
1205 		},
1206 		.ops = &adau1373_dai_ops,
1207 		.symmetric_rate = 1,
1208 	},
1209 	{
1210 		.id = 1,
1211 		.name = "adau1373-aif2",
1212 		.playback = {
1213 			.stream_name = "AIF2 Playback",
1214 			.channels_min = 2,
1215 			.channels_max = 2,
1216 			.rates = SNDRV_PCM_RATE_8000_48000,
1217 			.formats = ADAU1373_FORMATS,
1218 		},
1219 		.capture = {
1220 			.stream_name = "AIF2 Capture",
1221 			.channels_min = 2,
1222 			.channels_max = 2,
1223 			.rates = SNDRV_PCM_RATE_8000_48000,
1224 			.formats = ADAU1373_FORMATS,
1225 		},
1226 		.ops = &adau1373_dai_ops,
1227 		.symmetric_rate = 1,
1228 	},
1229 	{
1230 		.id = 2,
1231 		.name = "adau1373-aif3",
1232 		.playback = {
1233 			.stream_name = "AIF3 Playback",
1234 			.channels_min = 2,
1235 			.channels_max = 2,
1236 			.rates = SNDRV_PCM_RATE_8000_48000,
1237 			.formats = ADAU1373_FORMATS,
1238 		},
1239 		.capture = {
1240 			.stream_name = "AIF3 Capture",
1241 			.channels_min = 2,
1242 			.channels_max = 2,
1243 			.rates = SNDRV_PCM_RATE_8000_48000,
1244 			.formats = ADAU1373_FORMATS,
1245 		},
1246 		.ops = &adau1373_dai_ops,
1247 		.symmetric_rate = 1,
1248 	},
1249 };
1250 
adau1373_set_pll(struct snd_soc_component * component,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)1251 static int adau1373_set_pll(struct snd_soc_component *component, int pll_id,
1252 	int source, unsigned int freq_in, unsigned int freq_out)
1253 {
1254 	struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
1255 	unsigned int dpll_div = 0;
1256 	uint8_t pll_regs[5];
1257 	int ret;
1258 
1259 	switch (pll_id) {
1260 	case ADAU1373_PLL1:
1261 	case ADAU1373_PLL2:
1262 		break;
1263 	default:
1264 		return -EINVAL;
1265 	}
1266 
1267 	switch (source) {
1268 	case ADAU1373_PLL_SRC_BCLK1:
1269 	case ADAU1373_PLL_SRC_BCLK2:
1270 	case ADAU1373_PLL_SRC_BCLK3:
1271 	case ADAU1373_PLL_SRC_LRCLK1:
1272 	case ADAU1373_PLL_SRC_LRCLK2:
1273 	case ADAU1373_PLL_SRC_LRCLK3:
1274 	case ADAU1373_PLL_SRC_MCLK1:
1275 	case ADAU1373_PLL_SRC_MCLK2:
1276 	case ADAU1373_PLL_SRC_GPIO1:
1277 	case ADAU1373_PLL_SRC_GPIO2:
1278 	case ADAU1373_PLL_SRC_GPIO3:
1279 	case ADAU1373_PLL_SRC_GPIO4:
1280 		break;
1281 	default:
1282 		return -EINVAL;
1283 	}
1284 
1285 	if (freq_in < 7813 || freq_in > 27000000)
1286 		return -EINVAL;
1287 
1288 	if (freq_out < 45158000 || freq_out > 49152000)
1289 		return -EINVAL;
1290 
1291 	/* APLL input needs to be >= 8Mhz, so in case freq_in is less we use the
1292 	 * DPLL to get it there. DPLL_out = (DPLL_in / div) * 1024 */
1293 	while (freq_in < 8000000) {
1294 		freq_in *= 2;
1295 		dpll_div++;
1296 	}
1297 
1298 	ret = adau_calc_pll_cfg(freq_in, freq_out, pll_regs);
1299 	if (ret)
1300 		return -EINVAL;
1301 
1302 	if (dpll_div) {
1303 		dpll_div = 11 - dpll_div;
1304 		regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id),
1305 			ADAU1373_PLL_CTRL6_DPLL_BYPASS, 0);
1306 	} else {
1307 		regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id),
1308 			ADAU1373_PLL_CTRL6_DPLL_BYPASS,
1309 			ADAU1373_PLL_CTRL6_DPLL_BYPASS);
1310 	}
1311 
1312 	regmap_write(adau1373->regmap, ADAU1373_DPLL_CTRL(pll_id),
1313 		(source << 4) | dpll_div);
1314 	regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL1(pll_id), pll_regs[0]);
1315 	regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL2(pll_id), pll_regs[1]);
1316 	regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL3(pll_id), pll_regs[2]);
1317 	regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL4(pll_id), pll_regs[3]);
1318 	regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL5(pll_id), pll_regs[4]);
1319 
1320 	/* Set sysclk to pll_rate / 4 */
1321 	regmap_update_bits(adau1373->regmap, ADAU1373_CLK_SRC_DIV(pll_id), 0x3f, 0x09);
1322 
1323 	return 0;
1324 }
1325 
adau1373_load_drc_settings(struct adau1373 * adau1373,unsigned int nr,uint8_t * drc)1326 static void adau1373_load_drc_settings(struct adau1373 *adau1373,
1327 	unsigned int nr, uint8_t *drc)
1328 {
1329 	unsigned int i;
1330 
1331 	for (i = 0; i < ADAU1373_DRC_SIZE; ++i)
1332 		regmap_write(adau1373->regmap, ADAU1373_DRC(nr) + i, drc[i]);
1333 }
1334 
adau1373_valid_micbias(enum adau1373_micbias_voltage micbias)1335 static bool adau1373_valid_micbias(enum adau1373_micbias_voltage micbias)
1336 {
1337 	switch (micbias) {
1338 	case ADAU1373_MICBIAS_2_9V:
1339 	case ADAU1373_MICBIAS_2_2V:
1340 	case ADAU1373_MICBIAS_2_6V:
1341 	case ADAU1373_MICBIAS_1_8V:
1342 		return true;
1343 	default:
1344 		break;
1345 	}
1346 	return false;
1347 }
1348 
adau1373_probe(struct snd_soc_component * component)1349 static int adau1373_probe(struct snd_soc_component *component)
1350 {
1351 	struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
1352 	struct adau1373_platform_data *pdata = component->dev->platform_data;
1353 	bool lineout_differential = false;
1354 	unsigned int val;
1355 	int i;
1356 
1357 	if (pdata) {
1358 		if (pdata->num_drc > ARRAY_SIZE(pdata->drc_setting))
1359 			return -EINVAL;
1360 
1361 		if (!adau1373_valid_micbias(pdata->micbias1) ||
1362 			!adau1373_valid_micbias(pdata->micbias2))
1363 			return -EINVAL;
1364 
1365 		for (i = 0; i < pdata->num_drc; ++i) {
1366 			adau1373_load_drc_settings(adau1373, i,
1367 				pdata->drc_setting[i]);
1368 		}
1369 
1370 		snd_soc_add_component_controls(component, adau1373_drc_controls,
1371 			pdata->num_drc);
1372 
1373 		val = 0;
1374 		for (i = 0; i < 4; ++i) {
1375 			if (pdata->input_differential[i])
1376 				val |= BIT(i);
1377 		}
1378 		regmap_write(adau1373->regmap, ADAU1373_INPUT_MODE, val);
1379 
1380 		val = 0;
1381 		if (pdata->lineout_differential)
1382 			val |= ADAU1373_OUTPUT_CTRL_LDIFF;
1383 		if (pdata->lineout_ground_sense)
1384 			val |= ADAU1373_OUTPUT_CTRL_LNFBEN;
1385 		regmap_write(adau1373->regmap, ADAU1373_OUTPUT_CTRL, val);
1386 
1387 		lineout_differential = pdata->lineout_differential;
1388 
1389 		regmap_write(adau1373->regmap, ADAU1373_EP_CTRL,
1390 			(pdata->micbias1 << ADAU1373_EP_CTRL_MICBIAS1_OFFSET) |
1391 			(pdata->micbias2 << ADAU1373_EP_CTRL_MICBIAS2_OFFSET));
1392 	}
1393 
1394 	if (!lineout_differential) {
1395 		snd_soc_add_component_controls(component, adau1373_lineout2_controls,
1396 			ARRAY_SIZE(adau1373_lineout2_controls));
1397 	}
1398 
1399 	regmap_write(adau1373->regmap, ADAU1373_ADC_CTRL,
1400 	    ADAU1373_ADC_CTRL_RESET_FORCE | ADAU1373_ADC_CTRL_PEAK_DETECT);
1401 
1402 	return 0;
1403 }
1404 
adau1373_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)1405 static int adau1373_set_bias_level(struct snd_soc_component *component,
1406 	enum snd_soc_bias_level level)
1407 {
1408 	struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
1409 
1410 	switch (level) {
1411 	case SND_SOC_BIAS_ON:
1412 		break;
1413 	case SND_SOC_BIAS_PREPARE:
1414 		break;
1415 	case SND_SOC_BIAS_STANDBY:
1416 		regmap_update_bits(adau1373->regmap, ADAU1373_PWDN_CTRL3,
1417 			ADAU1373_PWDN_CTRL3_PWR_EN, ADAU1373_PWDN_CTRL3_PWR_EN);
1418 		break;
1419 	case SND_SOC_BIAS_OFF:
1420 		regmap_update_bits(adau1373->regmap, ADAU1373_PWDN_CTRL3,
1421 			ADAU1373_PWDN_CTRL3_PWR_EN, 0);
1422 		break;
1423 	}
1424 	return 0;
1425 }
1426 
adau1373_resume(struct snd_soc_component * component)1427 static int adau1373_resume(struct snd_soc_component *component)
1428 {
1429 	struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
1430 
1431 	regcache_sync(adau1373->regmap);
1432 
1433 	return 0;
1434 }
1435 
adau1373_register_volatile(struct device * dev,unsigned int reg)1436 static bool adau1373_register_volatile(struct device *dev, unsigned int reg)
1437 {
1438 	switch (reg) {
1439 	case ADAU1373_SOFT_RESET:
1440 	case ADAU1373_ADC_DAC_STATUS:
1441 		return true;
1442 	default:
1443 		return false;
1444 	}
1445 }
1446 
1447 static const struct regmap_config adau1373_regmap_config = {
1448 	.val_bits = 8,
1449 	.reg_bits = 8,
1450 
1451 	.volatile_reg = adau1373_register_volatile,
1452 	.max_register = ADAU1373_SOFT_RESET,
1453 
1454 	.cache_type = REGCACHE_MAPLE,
1455 	.reg_defaults = adau1373_reg_defaults,
1456 	.num_reg_defaults = ARRAY_SIZE(adau1373_reg_defaults),
1457 };
1458 
1459 static const struct snd_soc_component_driver adau1373_component_driver = {
1460 	.probe			= adau1373_probe,
1461 	.resume			= adau1373_resume,
1462 	.set_bias_level		= adau1373_set_bias_level,
1463 	.set_pll		= adau1373_set_pll,
1464 	.controls		= adau1373_controls,
1465 	.num_controls		= ARRAY_SIZE(adau1373_controls),
1466 	.dapm_widgets		= adau1373_dapm_widgets,
1467 	.num_dapm_widgets	= ARRAY_SIZE(adau1373_dapm_widgets),
1468 	.dapm_routes		= adau1373_dapm_routes,
1469 	.num_dapm_routes	= ARRAY_SIZE(adau1373_dapm_routes),
1470 	.use_pmdown_time	= 1,
1471 	.endianness		= 1,
1472 };
1473 
adau1373_i2c_probe(struct i2c_client * client)1474 static int adau1373_i2c_probe(struct i2c_client *client)
1475 {
1476 	struct adau1373 *adau1373;
1477 	int ret;
1478 
1479 	adau1373 = devm_kzalloc(&client->dev, sizeof(*adau1373), GFP_KERNEL);
1480 	if (!adau1373)
1481 		return -ENOMEM;
1482 
1483 	adau1373->regmap = devm_regmap_init_i2c(client,
1484 		&adau1373_regmap_config);
1485 	if (IS_ERR(adau1373->regmap))
1486 		return PTR_ERR(adau1373->regmap);
1487 
1488 	regmap_write(adau1373->regmap, ADAU1373_SOFT_RESET, 0x00);
1489 
1490 	dev_set_drvdata(&client->dev, adau1373);
1491 
1492 	ret = devm_snd_soc_register_component(&client->dev,
1493 			&adau1373_component_driver,
1494 			adau1373_dai_driver, ARRAY_SIZE(adau1373_dai_driver));
1495 	return ret;
1496 }
1497 
1498 static const struct i2c_device_id adau1373_i2c_id[] = {
1499 	{ "adau1373", 0 },
1500 	{ }
1501 };
1502 MODULE_DEVICE_TABLE(i2c, adau1373_i2c_id);
1503 
1504 static struct i2c_driver adau1373_i2c_driver = {
1505 	.driver = {
1506 		.name = "adau1373",
1507 	},
1508 	.probe = adau1373_i2c_probe,
1509 	.id_table = adau1373_i2c_id,
1510 };
1511 
1512 module_i2c_driver(adau1373_i2c_driver);
1513 
1514 MODULE_DESCRIPTION("ASoC ADAU1373 driver");
1515 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1516 MODULE_LICENSE("GPL");
1517