1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2022 Analog Devices, Inc.
4 * Author: Cosmin Tanislav <cosmin.tanislav@analog.com>
5 */
6
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/err.h>
14 #include <linux/gpio/driver.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/property.h>
20 #include <linux/regmap.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/spi/spi.h>
23 #include <linux/units.h>
24
25 #include <asm/div64.h>
26 #include <asm/unaligned.h>
27
28 #include <linux/iio/buffer.h>
29 #include <linux/iio/iio.h>
30 #include <linux/iio/kfifo_buf.h>
31 #include <linux/iio/sysfs.h>
32
33 #define AD4130_NAME "ad4130"
34
35 #define AD4130_COMMS_READ_MASK BIT(6)
36
37 #define AD4130_STATUS_REG 0x00
38
39 #define AD4130_ADC_CONTROL_REG 0x01
40 #define AD4130_ADC_CONTROL_BIPOLAR_MASK BIT(14)
41 #define AD4130_ADC_CONTROL_INT_REF_VAL_MASK BIT(13)
42 #define AD4130_INT_REF_2_5V 2500000
43 #define AD4130_INT_REF_1_25V 1250000
44 #define AD4130_ADC_CONTROL_CSB_EN_MASK BIT(9)
45 #define AD4130_ADC_CONTROL_INT_REF_EN_MASK BIT(8)
46 #define AD4130_ADC_CONTROL_MODE_MASK GENMASK(5, 2)
47 #define AD4130_ADC_CONTROL_MCLK_SEL_MASK GENMASK(1, 0)
48 #define AD4130_MCLK_FREQ_76_8KHZ 76800
49 #define AD4130_MCLK_FREQ_153_6KHZ 153600
50
51 #define AD4130_DATA_REG 0x02
52
53 #define AD4130_IO_CONTROL_REG 0x03
54 #define AD4130_IO_CONTROL_INT_PIN_SEL_MASK GENMASK(9, 8)
55 #define AD4130_IO_CONTROL_GPIO_DATA_MASK GENMASK(7, 4)
56 #define AD4130_IO_CONTROL_GPIO_CTRL_MASK GENMASK(3, 0)
57
58 #define AD4130_VBIAS_REG 0x04
59
60 #define AD4130_ID_REG 0x05
61
62 #define AD4130_ERROR_REG 0x06
63
64 #define AD4130_ERROR_EN_REG 0x07
65
66 #define AD4130_MCLK_COUNT_REG 0x08
67
68 #define AD4130_CHANNEL_X_REG(x) (0x09 + (x))
69 #define AD4130_CHANNEL_EN_MASK BIT(23)
70 #define AD4130_CHANNEL_SETUP_MASK GENMASK(22, 20)
71 #define AD4130_CHANNEL_AINP_MASK GENMASK(17, 13)
72 #define AD4130_CHANNEL_AINM_MASK GENMASK(12, 8)
73 #define AD4130_CHANNEL_IOUT1_MASK GENMASK(7, 4)
74 #define AD4130_CHANNEL_IOUT2_MASK GENMASK(3, 0)
75
76 #define AD4130_CONFIG_X_REG(x) (0x19 + (x))
77 #define AD4130_CONFIG_IOUT1_VAL_MASK GENMASK(15, 13)
78 #define AD4130_CONFIG_IOUT2_VAL_MASK GENMASK(12, 10)
79 #define AD4130_CONFIG_BURNOUT_MASK GENMASK(9, 8)
80 #define AD4130_CONFIG_REF_BUFP_MASK BIT(7)
81 #define AD4130_CONFIG_REF_BUFM_MASK BIT(6)
82 #define AD4130_CONFIG_REF_SEL_MASK GENMASK(5, 4)
83 #define AD4130_CONFIG_PGA_MASK GENMASK(3, 1)
84
85 #define AD4130_FILTER_X_REG(x) (0x21 + (x))
86 #define AD4130_FILTER_MODE_MASK GENMASK(15, 12)
87 #define AD4130_FILTER_SELECT_MASK GENMASK(10, 0)
88 #define AD4130_FILTER_SELECT_MIN 1
89
90 #define AD4130_OFFSET_X_REG(x) (0x29 + (x))
91
92 #define AD4130_GAIN_X_REG(x) (0x31 + (x))
93
94 #define AD4130_MISC_REG 0x39
95
96 #define AD4130_FIFO_CONTROL_REG 0x3a
97 #define AD4130_FIFO_CONTROL_HEADER_MASK BIT(18)
98 #define AD4130_FIFO_CONTROL_MODE_MASK GENMASK(17, 16)
99 #define AD4130_FIFO_CONTROL_WM_INT_EN_MASK BIT(9)
100 #define AD4130_FIFO_CONTROL_WM_MASK GENMASK(7, 0)
101 #define AD4130_WATERMARK_256 0
102
103 #define AD4130_FIFO_STATUS_REG 0x3b
104
105 #define AD4130_FIFO_THRESHOLD_REG 0x3c
106
107 #define AD4130_FIFO_DATA_REG 0x3d
108 #define AD4130_FIFO_SIZE 256
109 #define AD4130_FIFO_MAX_SAMPLE_SIZE 3
110
111 #define AD4130_MAX_ANALOG_PINS 16
112 #define AD4130_MAX_CHANNELS 16
113 #define AD4130_MAX_DIFF_INPUTS 30
114 #define AD4130_MAX_GPIOS 4
115 #define AD4130_MAX_ODR 2400
116 #define AD4130_MAX_PGA 8
117 #define AD4130_MAX_SETUPS 8
118
119 #define AD4130_AIN2_P1 0x2
120 #define AD4130_AIN3_P2 0x3
121
122 #define AD4130_RESET_BUF_SIZE 8
123 #define AD4130_RESET_SLEEP_US (160 * MICRO / AD4130_MCLK_FREQ_76_8KHZ)
124
125 #define AD4130_INVALID_SLOT -1
126
127 static const unsigned int ad4130_reg_size[] = {
128 [AD4130_STATUS_REG] = 1,
129 [AD4130_ADC_CONTROL_REG] = 2,
130 [AD4130_DATA_REG] = 3,
131 [AD4130_IO_CONTROL_REG] = 2,
132 [AD4130_VBIAS_REG] = 2,
133 [AD4130_ID_REG] = 1,
134 [AD4130_ERROR_REG] = 2,
135 [AD4130_ERROR_EN_REG] = 2,
136 [AD4130_MCLK_COUNT_REG] = 1,
137 [AD4130_CHANNEL_X_REG(0) ... AD4130_CHANNEL_X_REG(AD4130_MAX_CHANNELS - 1)] = 3,
138 [AD4130_CONFIG_X_REG(0) ... AD4130_CONFIG_X_REG(AD4130_MAX_SETUPS - 1)] = 2,
139 [AD4130_FILTER_X_REG(0) ... AD4130_FILTER_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
140 [AD4130_OFFSET_X_REG(0) ... AD4130_OFFSET_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
141 [AD4130_GAIN_X_REG(0) ... AD4130_GAIN_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
142 [AD4130_MISC_REG] = 2,
143 [AD4130_FIFO_CONTROL_REG] = 3,
144 [AD4130_FIFO_STATUS_REG] = 1,
145 [AD4130_FIFO_THRESHOLD_REG] = 3,
146 [AD4130_FIFO_DATA_REG] = 3,
147 };
148
149 enum ad4130_int_ref_val {
150 AD4130_INT_REF_VAL_2_5V,
151 AD4130_INT_REF_VAL_1_25V,
152 };
153
154 enum ad4130_mclk_sel {
155 AD4130_MCLK_76_8KHZ,
156 AD4130_MCLK_76_8KHZ_OUT,
157 AD4130_MCLK_76_8KHZ_EXT,
158 AD4130_MCLK_153_6KHZ_EXT,
159 };
160
161 enum ad4130_int_pin_sel {
162 AD4130_INT_PIN_INT,
163 AD4130_INT_PIN_CLK,
164 AD4130_INT_PIN_P2,
165 AD4130_INT_PIN_DOUT,
166 };
167
168 enum ad4130_iout {
169 AD4130_IOUT_OFF,
170 AD4130_IOUT_10000NA,
171 AD4130_IOUT_20000NA,
172 AD4130_IOUT_50000NA,
173 AD4130_IOUT_100000NA,
174 AD4130_IOUT_150000NA,
175 AD4130_IOUT_200000NA,
176 AD4130_IOUT_100NA,
177 AD4130_IOUT_MAX
178 };
179
180 enum ad4130_burnout {
181 AD4130_BURNOUT_OFF,
182 AD4130_BURNOUT_500NA,
183 AD4130_BURNOUT_2000NA,
184 AD4130_BURNOUT_4000NA,
185 AD4130_BURNOUT_MAX
186 };
187
188 enum ad4130_ref_sel {
189 AD4130_REF_REFIN1,
190 AD4130_REF_REFIN2,
191 AD4130_REF_REFOUT_AVSS,
192 AD4130_REF_AVDD_AVSS,
193 AD4130_REF_SEL_MAX
194 };
195
196 enum ad4130_fifo_mode {
197 AD4130_FIFO_MODE_DISABLED = 0b00,
198 AD4130_FIFO_MODE_WM = 0b01,
199 };
200
201 enum ad4130_mode {
202 AD4130_MODE_CONTINUOUS = 0b0000,
203 AD4130_MODE_IDLE = 0b0100,
204 };
205
206 enum ad4130_filter_mode {
207 AD4130_FILTER_SINC4,
208 AD4130_FILTER_SINC4_SINC1,
209 AD4130_FILTER_SINC3,
210 AD4130_FILTER_SINC3_REJ60,
211 AD4130_FILTER_SINC3_SINC1,
212 AD4130_FILTER_SINC3_PF1,
213 AD4130_FILTER_SINC3_PF2,
214 AD4130_FILTER_SINC3_PF3,
215 AD4130_FILTER_SINC3_PF4,
216 };
217
218 enum ad4130_pin_function {
219 AD4130_PIN_FN_NONE,
220 AD4130_PIN_FN_SPECIAL = BIT(0),
221 AD4130_PIN_FN_DIFF = BIT(1),
222 AD4130_PIN_FN_EXCITATION = BIT(2),
223 AD4130_PIN_FN_VBIAS = BIT(3),
224 };
225
226 /*
227 * If you make adaptations in this struct, you most likely also have to adapt
228 * ad4130_setup_info_eq(), too.
229 */
230 struct ad4130_setup_info {
231 unsigned int iout0_val;
232 unsigned int iout1_val;
233 unsigned int burnout;
234 unsigned int pga;
235 unsigned int fs;
236 u32 ref_sel;
237 enum ad4130_filter_mode filter_mode;
238 bool ref_bufp;
239 bool ref_bufm;
240 };
241
242 struct ad4130_slot_info {
243 struct ad4130_setup_info setup;
244 unsigned int enabled_channels;
245 unsigned int channels;
246 };
247
248 struct ad4130_chan_info {
249 struct ad4130_setup_info setup;
250 u32 iout0;
251 u32 iout1;
252 int slot;
253 bool enabled;
254 bool initialized;
255 };
256
257 struct ad4130_filter_config {
258 enum ad4130_filter_mode filter_mode;
259 unsigned int odr_div;
260 unsigned int fs_max;
261 enum iio_available_type samp_freq_avail_type;
262 int samp_freq_avail_len;
263 int samp_freq_avail[3][2];
264 };
265
266 struct ad4130_state {
267 struct regmap *regmap;
268 struct spi_device *spi;
269 struct clk *mclk;
270 struct regulator_bulk_data regulators[4];
271 u32 irq_trigger;
272 u32 inv_irq_trigger;
273
274 /*
275 * Synchronize access to members the of driver state, and ensure
276 * atomicity of consecutive regmap operations.
277 */
278 struct mutex lock;
279 struct completion completion;
280
281 struct iio_chan_spec chans[AD4130_MAX_CHANNELS];
282 struct ad4130_chan_info chans_info[AD4130_MAX_CHANNELS];
283 struct ad4130_slot_info slots_info[AD4130_MAX_SETUPS];
284 enum ad4130_pin_function pins_fn[AD4130_MAX_ANALOG_PINS];
285 u32 vbias_pins[AD4130_MAX_ANALOG_PINS];
286 u32 num_vbias_pins;
287 int scale_tbls[AD4130_REF_SEL_MAX][AD4130_MAX_PGA][2];
288 struct gpio_chip gc;
289 struct clk_hw int_clk_hw;
290
291 u32 int_pin_sel;
292 u32 int_ref_uv;
293 u32 mclk_sel;
294 bool int_ref_en;
295 bool bipolar;
296
297 unsigned int num_enabled_channels;
298 unsigned int effective_watermark;
299 unsigned int watermark;
300
301 struct spi_message fifo_msg;
302 struct spi_transfer fifo_xfer[2];
303
304 /*
305 * DMA (thus cache coherency maintenance) requires any transfer
306 * buffers to live in their own cache lines. As the use of these
307 * buffers is synchronous, all of the buffers used for DMA in this
308 * driver may share a cache line.
309 */
310 u8 reset_buf[AD4130_RESET_BUF_SIZE] __aligned(IIO_DMA_MINALIGN);
311 u8 reg_write_tx_buf[4];
312 u8 reg_read_tx_buf[1];
313 u8 reg_read_rx_buf[3];
314 u8 fifo_tx_buf[2];
315 u8 fifo_rx_buf[AD4130_FIFO_SIZE *
316 AD4130_FIFO_MAX_SAMPLE_SIZE];
317 };
318
319 static const char * const ad4130_int_pin_names[] = {
320 [AD4130_INT_PIN_INT] = "int",
321 [AD4130_INT_PIN_CLK] = "clk",
322 [AD4130_INT_PIN_P2] = "p2",
323 [AD4130_INT_PIN_DOUT] = "dout",
324 };
325
326 static const unsigned int ad4130_iout_current_na_tbl[AD4130_IOUT_MAX] = {
327 [AD4130_IOUT_OFF] = 0,
328 [AD4130_IOUT_100NA] = 100,
329 [AD4130_IOUT_10000NA] = 10000,
330 [AD4130_IOUT_20000NA] = 20000,
331 [AD4130_IOUT_50000NA] = 50000,
332 [AD4130_IOUT_100000NA] = 100000,
333 [AD4130_IOUT_150000NA] = 150000,
334 [AD4130_IOUT_200000NA] = 200000,
335 };
336
337 static const unsigned int ad4130_burnout_current_na_tbl[AD4130_BURNOUT_MAX] = {
338 [AD4130_BURNOUT_OFF] = 0,
339 [AD4130_BURNOUT_500NA] = 500,
340 [AD4130_BURNOUT_2000NA] = 2000,
341 [AD4130_BURNOUT_4000NA] = 4000,
342 };
343
344 #define AD4130_VARIABLE_ODR_CONFIG(_filter_mode, _odr_div, _fs_max) \
345 { \
346 .filter_mode = (_filter_mode), \
347 .odr_div = (_odr_div), \
348 .fs_max = (_fs_max), \
349 .samp_freq_avail_type = IIO_AVAIL_RANGE, \
350 .samp_freq_avail = { \
351 { AD4130_MAX_ODR, (_odr_div) * (_fs_max) }, \
352 { AD4130_MAX_ODR, (_odr_div) * (_fs_max) }, \
353 { AD4130_MAX_ODR, (_odr_div) }, \
354 }, \
355 }
356
357 #define AD4130_FIXED_ODR_CONFIG(_filter_mode, _odr_div) \
358 { \
359 .filter_mode = (_filter_mode), \
360 .odr_div = (_odr_div), \
361 .fs_max = AD4130_FILTER_SELECT_MIN, \
362 .samp_freq_avail_type = IIO_AVAIL_LIST, \
363 .samp_freq_avail_len = 1, \
364 .samp_freq_avail = { \
365 { AD4130_MAX_ODR, (_odr_div) }, \
366 }, \
367 }
368
369 static const struct ad4130_filter_config ad4130_filter_configs[] = {
370 AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC4, 1, 10),
371 AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC4_SINC1, 11, 10),
372 AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC3, 1, 2047),
373 AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC3_REJ60, 1, 2047),
374 AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC3_SINC1, 10, 2047),
375 AD4130_FIXED_ODR_CONFIG(AD4130_FILTER_SINC3_PF1, 92),
376 AD4130_FIXED_ODR_CONFIG(AD4130_FILTER_SINC3_PF2, 100),
377 AD4130_FIXED_ODR_CONFIG(AD4130_FILTER_SINC3_PF3, 124),
378 AD4130_FIXED_ODR_CONFIG(AD4130_FILTER_SINC3_PF4, 148),
379 };
380
381 static const char * const ad4130_filter_modes_str[] = {
382 [AD4130_FILTER_SINC4] = "sinc4",
383 [AD4130_FILTER_SINC4_SINC1] = "sinc4+sinc1",
384 [AD4130_FILTER_SINC3] = "sinc3",
385 [AD4130_FILTER_SINC3_REJ60] = "sinc3+rej60",
386 [AD4130_FILTER_SINC3_SINC1] = "sinc3+sinc1",
387 [AD4130_FILTER_SINC3_PF1] = "sinc3+pf1",
388 [AD4130_FILTER_SINC3_PF2] = "sinc3+pf2",
389 [AD4130_FILTER_SINC3_PF3] = "sinc3+pf3",
390 [AD4130_FILTER_SINC3_PF4] = "sinc3+pf4",
391 };
392
ad4130_get_reg_size(struct ad4130_state * st,unsigned int reg,unsigned int * size)393 static int ad4130_get_reg_size(struct ad4130_state *st, unsigned int reg,
394 unsigned int *size)
395 {
396 if (reg >= ARRAY_SIZE(ad4130_reg_size))
397 return -EINVAL;
398
399 *size = ad4130_reg_size[reg];
400
401 return 0;
402 }
403
ad4130_data_reg_size(struct ad4130_state * st)404 static unsigned int ad4130_data_reg_size(struct ad4130_state *st)
405 {
406 unsigned int data_reg_size;
407 int ret;
408
409 ret = ad4130_get_reg_size(st, AD4130_DATA_REG, &data_reg_size);
410 if (ret)
411 return 0;
412
413 return data_reg_size;
414 }
415
ad4130_resolution(struct ad4130_state * st)416 static unsigned int ad4130_resolution(struct ad4130_state *st)
417 {
418 return ad4130_data_reg_size(st) * BITS_PER_BYTE;
419 }
420
ad4130_reg_write(void * context,unsigned int reg,unsigned int val)421 static int ad4130_reg_write(void *context, unsigned int reg, unsigned int val)
422 {
423 struct ad4130_state *st = context;
424 unsigned int size;
425 int ret;
426
427 ret = ad4130_get_reg_size(st, reg, &size);
428 if (ret)
429 return ret;
430
431 st->reg_write_tx_buf[0] = reg;
432
433 switch (size) {
434 case 3:
435 put_unaligned_be24(val, &st->reg_write_tx_buf[1]);
436 break;
437 case 2:
438 put_unaligned_be16(val, &st->reg_write_tx_buf[1]);
439 break;
440 case 1:
441 st->reg_write_tx_buf[1] = val;
442 break;
443 default:
444 return -EINVAL;
445 }
446
447 return spi_write(st->spi, st->reg_write_tx_buf, size + 1);
448 }
449
ad4130_reg_read(void * context,unsigned int reg,unsigned int * val)450 static int ad4130_reg_read(void *context, unsigned int reg, unsigned int *val)
451 {
452 struct ad4130_state *st = context;
453 struct spi_transfer t[] = {
454 {
455 .tx_buf = st->reg_read_tx_buf,
456 .len = sizeof(st->reg_read_tx_buf),
457 },
458 {
459 .rx_buf = st->reg_read_rx_buf,
460 },
461 };
462 unsigned int size;
463 int ret;
464
465 ret = ad4130_get_reg_size(st, reg, &size);
466 if (ret)
467 return ret;
468
469 st->reg_read_tx_buf[0] = AD4130_COMMS_READ_MASK | reg;
470 t[1].len = size;
471
472 ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
473 if (ret)
474 return ret;
475
476 switch (size) {
477 case 3:
478 *val = get_unaligned_be24(st->reg_read_rx_buf);
479 break;
480 case 2:
481 *val = get_unaligned_be16(st->reg_read_rx_buf);
482 break;
483 case 1:
484 *val = st->reg_read_rx_buf[0];
485 break;
486 default:
487 return -EINVAL;
488 }
489
490 return 0;
491 }
492
493 static const struct regmap_config ad4130_regmap_config = {
494 .reg_read = ad4130_reg_read,
495 .reg_write = ad4130_reg_write,
496 };
497
ad4130_gpio_init_valid_mask(struct gpio_chip * gc,unsigned long * valid_mask,unsigned int ngpios)498 static int ad4130_gpio_init_valid_mask(struct gpio_chip *gc,
499 unsigned long *valid_mask,
500 unsigned int ngpios)
501 {
502 struct ad4130_state *st = gpiochip_get_data(gc);
503 unsigned int i;
504
505 /*
506 * Output-only GPIO functionality is available on pins AIN2 through
507 * AIN5. If these pins are used for anything else, do not expose them.
508 */
509 for (i = 0; i < ngpios; i++) {
510 unsigned int pin = i + AD4130_AIN2_P1;
511 bool valid = st->pins_fn[pin] == AD4130_PIN_FN_NONE;
512
513 __assign_bit(i, valid_mask, valid);
514 }
515
516 return 0;
517 }
518
ad4130_gpio_get_direction(struct gpio_chip * gc,unsigned int offset)519 static int ad4130_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
520 {
521 return GPIO_LINE_DIRECTION_OUT;
522 }
523
ad4130_gpio_set(struct gpio_chip * gc,unsigned int offset,int value)524 static void ad4130_gpio_set(struct gpio_chip *gc, unsigned int offset,
525 int value)
526 {
527 struct ad4130_state *st = gpiochip_get_data(gc);
528 unsigned int mask = FIELD_PREP(AD4130_IO_CONTROL_GPIO_DATA_MASK,
529 BIT(offset));
530
531 regmap_update_bits(st->regmap, AD4130_IO_CONTROL_REG, mask,
532 value ? mask : 0);
533 }
534
ad4130_set_mode(struct ad4130_state * st,enum ad4130_mode mode)535 static int ad4130_set_mode(struct ad4130_state *st, enum ad4130_mode mode)
536 {
537 return regmap_update_bits(st->regmap, AD4130_ADC_CONTROL_REG,
538 AD4130_ADC_CONTROL_MODE_MASK,
539 FIELD_PREP(AD4130_ADC_CONTROL_MODE_MASK, mode));
540 }
541
ad4130_set_watermark_interrupt_en(struct ad4130_state * st,bool en)542 static int ad4130_set_watermark_interrupt_en(struct ad4130_state *st, bool en)
543 {
544 return regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG,
545 AD4130_FIFO_CONTROL_WM_INT_EN_MASK,
546 FIELD_PREP(AD4130_FIFO_CONTROL_WM_INT_EN_MASK, en));
547 }
548
ad4130_watermark_reg_val(unsigned int val)549 static unsigned int ad4130_watermark_reg_val(unsigned int val)
550 {
551 if (val == AD4130_FIFO_SIZE)
552 val = AD4130_WATERMARK_256;
553
554 return val;
555 }
556
ad4130_set_fifo_mode(struct ad4130_state * st,enum ad4130_fifo_mode mode)557 static int ad4130_set_fifo_mode(struct ad4130_state *st,
558 enum ad4130_fifo_mode mode)
559 {
560 return regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG,
561 AD4130_FIFO_CONTROL_MODE_MASK,
562 FIELD_PREP(AD4130_FIFO_CONTROL_MODE_MASK, mode));
563 }
564
ad4130_push_fifo_data(struct iio_dev * indio_dev)565 static void ad4130_push_fifo_data(struct iio_dev *indio_dev)
566 {
567 struct ad4130_state *st = iio_priv(indio_dev);
568 unsigned int data_reg_size = ad4130_data_reg_size(st);
569 unsigned int transfer_len = st->effective_watermark * data_reg_size;
570 unsigned int set_size = st->num_enabled_channels * data_reg_size;
571 unsigned int i;
572 int ret;
573
574 st->fifo_tx_buf[1] = ad4130_watermark_reg_val(st->effective_watermark);
575 st->fifo_xfer[1].len = transfer_len;
576
577 ret = spi_sync(st->spi, &st->fifo_msg);
578 if (ret)
579 return;
580
581 for (i = 0; i < transfer_len; i += set_size)
582 iio_push_to_buffers(indio_dev, &st->fifo_rx_buf[i]);
583 }
584
ad4130_irq_handler(int irq,void * private)585 static irqreturn_t ad4130_irq_handler(int irq, void *private)
586 {
587 struct iio_dev *indio_dev = private;
588 struct ad4130_state *st = iio_priv(indio_dev);
589
590 if (iio_buffer_enabled(indio_dev))
591 ad4130_push_fifo_data(indio_dev);
592 else
593 complete(&st->completion);
594
595 return IRQ_HANDLED;
596 }
597
ad4130_setup_info_eq(struct ad4130_setup_info * a,struct ad4130_setup_info * b)598 static bool ad4130_setup_info_eq(struct ad4130_setup_info *a,
599 struct ad4130_setup_info *b)
600 {
601 /*
602 * This is just to make sure that the comparison is adapted after
603 * struct ad4130_setup_info was changed.
604 */
605 static_assert(sizeof(*a) ==
606 sizeof(struct {
607 unsigned int iout0_val;
608 unsigned int iout1_val;
609 unsigned int burnout;
610 unsigned int pga;
611 unsigned int fs;
612 u32 ref_sel;
613 enum ad4130_filter_mode filter_mode;
614 bool ref_bufp;
615 bool ref_bufm;
616 }));
617
618 if (a->iout0_val != b->iout0_val ||
619 a->iout1_val != b->iout1_val ||
620 a->burnout != b->burnout ||
621 a->pga != b->pga ||
622 a->fs != b->fs ||
623 a->ref_sel != b->ref_sel ||
624 a->filter_mode != b->filter_mode ||
625 a->ref_bufp != b->ref_bufp ||
626 a->ref_bufm != b->ref_bufm)
627 return false;
628
629 return true;
630 }
631
ad4130_find_slot(struct ad4130_state * st,struct ad4130_setup_info * target_setup_info,unsigned int * slot,bool * overwrite)632 static int ad4130_find_slot(struct ad4130_state *st,
633 struct ad4130_setup_info *target_setup_info,
634 unsigned int *slot, bool *overwrite)
635 {
636 unsigned int i;
637
638 *slot = AD4130_INVALID_SLOT;
639 *overwrite = false;
640
641 for (i = 0; i < AD4130_MAX_SETUPS; i++) {
642 struct ad4130_slot_info *slot_info = &st->slots_info[i];
643
644 /* Immediately accept a matching setup info. */
645 if (ad4130_setup_info_eq(target_setup_info, &slot_info->setup)) {
646 *slot = i;
647 return 0;
648 }
649
650 /* Ignore all setups which are used by enabled channels. */
651 if (slot_info->enabled_channels)
652 continue;
653
654 /* Find the least used slot. */
655 if (*slot == AD4130_INVALID_SLOT ||
656 slot_info->channels < st->slots_info[*slot].channels)
657 *slot = i;
658 }
659
660 if (*slot == AD4130_INVALID_SLOT)
661 return -EINVAL;
662
663 *overwrite = true;
664
665 return 0;
666 }
667
ad4130_unlink_channel(struct ad4130_state * st,unsigned int channel)668 static void ad4130_unlink_channel(struct ad4130_state *st, unsigned int channel)
669 {
670 struct ad4130_chan_info *chan_info = &st->chans_info[channel];
671 struct ad4130_slot_info *slot_info = &st->slots_info[chan_info->slot];
672
673 chan_info->slot = AD4130_INVALID_SLOT;
674 slot_info->channels--;
675 }
676
ad4130_unlink_slot(struct ad4130_state * st,unsigned int slot)677 static int ad4130_unlink_slot(struct ad4130_state *st, unsigned int slot)
678 {
679 unsigned int i;
680
681 for (i = 0; i < AD4130_MAX_CHANNELS; i++) {
682 struct ad4130_chan_info *chan_info = &st->chans_info[i];
683
684 if (!chan_info->initialized || chan_info->slot != slot)
685 continue;
686
687 ad4130_unlink_channel(st, i);
688 }
689
690 return 0;
691 }
692
ad4130_link_channel_slot(struct ad4130_state * st,unsigned int channel,unsigned int slot)693 static int ad4130_link_channel_slot(struct ad4130_state *st,
694 unsigned int channel, unsigned int slot)
695 {
696 struct ad4130_slot_info *slot_info = &st->slots_info[slot];
697 struct ad4130_chan_info *chan_info = &st->chans_info[channel];
698 int ret;
699
700 ret = regmap_update_bits(st->regmap, AD4130_CHANNEL_X_REG(channel),
701 AD4130_CHANNEL_SETUP_MASK,
702 FIELD_PREP(AD4130_CHANNEL_SETUP_MASK, slot));
703 if (ret)
704 return ret;
705
706 chan_info->slot = slot;
707 slot_info->channels++;
708
709 return 0;
710 }
711
ad4130_write_slot_setup(struct ad4130_state * st,unsigned int slot,struct ad4130_setup_info * setup_info)712 static int ad4130_write_slot_setup(struct ad4130_state *st,
713 unsigned int slot,
714 struct ad4130_setup_info *setup_info)
715 {
716 unsigned int val;
717 int ret;
718
719 val = FIELD_PREP(AD4130_CONFIG_IOUT1_VAL_MASK, setup_info->iout0_val) |
720 FIELD_PREP(AD4130_CONFIG_IOUT1_VAL_MASK, setup_info->iout1_val) |
721 FIELD_PREP(AD4130_CONFIG_BURNOUT_MASK, setup_info->burnout) |
722 FIELD_PREP(AD4130_CONFIG_REF_BUFP_MASK, setup_info->ref_bufp) |
723 FIELD_PREP(AD4130_CONFIG_REF_BUFM_MASK, setup_info->ref_bufm) |
724 FIELD_PREP(AD4130_CONFIG_REF_SEL_MASK, setup_info->ref_sel) |
725 FIELD_PREP(AD4130_CONFIG_PGA_MASK, setup_info->pga);
726
727 ret = regmap_write(st->regmap, AD4130_CONFIG_X_REG(slot), val);
728 if (ret)
729 return ret;
730
731 val = FIELD_PREP(AD4130_FILTER_MODE_MASK, setup_info->filter_mode) |
732 FIELD_PREP(AD4130_FILTER_SELECT_MASK, setup_info->fs);
733
734 ret = regmap_write(st->regmap, AD4130_FILTER_X_REG(slot), val);
735 if (ret)
736 return ret;
737
738 memcpy(&st->slots_info[slot].setup, setup_info, sizeof(*setup_info));
739
740 return 0;
741 }
742
ad4130_write_channel_setup(struct ad4130_state * st,unsigned int channel,bool on_enable)743 static int ad4130_write_channel_setup(struct ad4130_state *st,
744 unsigned int channel, bool on_enable)
745 {
746 struct ad4130_chan_info *chan_info = &st->chans_info[channel];
747 struct ad4130_setup_info *setup_info = &chan_info->setup;
748 bool overwrite;
749 int slot;
750 int ret;
751
752 /*
753 * The following cases need to be handled.
754 *
755 * 1. Enabled and linked channel with setup changes:
756 * - Find a slot. If not possible, return error.
757 * - Unlink channel from current slot.
758 * - If the slot has channels linked to it, unlink all channels, and
759 * write the new setup to it.
760 * - Link channel to new slot.
761 *
762 * 2. Soon to be enabled and unlinked channel:
763 * - Find a slot. If not possible, return error.
764 * - If the slot has channels linked to it, unlink all channels, and
765 * write the new setup to it.
766 * - Link channel to the slot.
767 *
768 * 3. Disabled and linked channel with setup changes:
769 * - Unlink channel from current slot.
770 *
771 * 4. Soon to be enabled and linked channel:
772 * 5. Disabled and unlinked channel with setup changes:
773 * - Do nothing.
774 */
775
776 /* Case 4 */
777 if (on_enable && chan_info->slot != AD4130_INVALID_SLOT)
778 return 0;
779
780 if (!on_enable && !chan_info->enabled) {
781 if (chan_info->slot != AD4130_INVALID_SLOT)
782 /* Case 3 */
783 ad4130_unlink_channel(st, channel);
784
785 /* Cases 3 & 5 */
786 return 0;
787 }
788
789 /* Cases 1 & 2 */
790 ret = ad4130_find_slot(st, setup_info, &slot, &overwrite);
791 if (ret)
792 return ret;
793
794 if (chan_info->slot != AD4130_INVALID_SLOT)
795 /* Case 1 */
796 ad4130_unlink_channel(st, channel);
797
798 if (overwrite) {
799 ret = ad4130_unlink_slot(st, slot);
800 if (ret)
801 return ret;
802
803 ret = ad4130_write_slot_setup(st, slot, setup_info);
804 if (ret)
805 return ret;
806 }
807
808 return ad4130_link_channel_slot(st, channel, slot);
809 }
810
ad4130_set_channel_enable(struct ad4130_state * st,unsigned int channel,bool status)811 static int ad4130_set_channel_enable(struct ad4130_state *st,
812 unsigned int channel, bool status)
813 {
814 struct ad4130_chan_info *chan_info = &st->chans_info[channel];
815 struct ad4130_slot_info *slot_info;
816 int ret;
817
818 if (chan_info->enabled == status)
819 return 0;
820
821 if (status) {
822 ret = ad4130_write_channel_setup(st, channel, true);
823 if (ret)
824 return ret;
825 }
826
827 slot_info = &st->slots_info[chan_info->slot];
828
829 ret = regmap_update_bits(st->regmap, AD4130_CHANNEL_X_REG(channel),
830 AD4130_CHANNEL_EN_MASK,
831 FIELD_PREP(AD4130_CHANNEL_EN_MASK, status));
832 if (ret)
833 return ret;
834
835 slot_info->enabled_channels += status ? 1 : -1;
836 chan_info->enabled = status;
837
838 return 0;
839 }
840
841 /*
842 * Table 58. FILTER_MODE_n bits and Filter Types of the datasheet describes
843 * the relation between filter mode, ODR and FS.
844 *
845 * Notice that the max ODR of each filter mode is not necessarily the
846 * absolute max ODR supported by the chip.
847 *
848 * The ODR divider is not explicitly specified, but it can be deduced based
849 * on the ODR range of each filter mode.
850 *
851 * For example, for Sinc4+Sinc1, max ODR is 218.18. That means that the
852 * absolute max ODR is divided by 11 to achieve the max ODR of this filter
853 * mode.
854 *
855 * The formulas for converting between ODR and FS for a specific filter
856 * mode can be deduced from the same table.
857 *
858 * Notice that FS = 1 actually means max ODR, and that ODR decreases by
859 * (maximum ODR / maximum FS) for each increment of FS.
860 *
861 * odr = MAX_ODR / odr_div * (1 - (fs - 1) / fs_max) <=>
862 * odr = MAX_ODR * (1 - (fs - 1) / fs_max) / odr_div <=>
863 * odr = MAX_ODR * (1 - (fs - 1) / fs_max) / odr_div <=>
864 * odr = MAX_ODR * (fs_max - fs + 1) / (fs_max * odr_div)
865 * (used in ad4130_fs_to_freq)
866 *
867 * For the opposite formula, FS can be extracted from the last one.
868 *
869 * MAX_ODR * (fs_max - fs + 1) = fs_max * odr_div * odr <=>
870 * fs_max - fs + 1 = fs_max * odr_div * odr / MAX_ODR <=>
871 * fs = 1 + fs_max - fs_max * odr_div * odr / MAX_ODR
872 * (used in ad4130_fs_to_freq)
873 */
874
ad4130_freq_to_fs(enum ad4130_filter_mode filter_mode,int val,int val2,unsigned int * fs)875 static void ad4130_freq_to_fs(enum ad4130_filter_mode filter_mode,
876 int val, int val2, unsigned int *fs)
877 {
878 const struct ad4130_filter_config *filter_config =
879 &ad4130_filter_configs[filter_mode];
880 u64 dividend, divisor;
881 int temp;
882
883 dividend = filter_config->fs_max * filter_config->odr_div *
884 ((u64)val * NANO + val2);
885 divisor = (u64)AD4130_MAX_ODR * NANO;
886
887 temp = AD4130_FILTER_SELECT_MIN + filter_config->fs_max -
888 DIV64_U64_ROUND_CLOSEST(dividend, divisor);
889
890 if (temp < AD4130_FILTER_SELECT_MIN)
891 temp = AD4130_FILTER_SELECT_MIN;
892 else if (temp > filter_config->fs_max)
893 temp = filter_config->fs_max;
894
895 *fs = temp;
896 }
897
ad4130_fs_to_freq(enum ad4130_filter_mode filter_mode,unsigned int fs,int * val,int * val2)898 static void ad4130_fs_to_freq(enum ad4130_filter_mode filter_mode,
899 unsigned int fs, int *val, int *val2)
900 {
901 const struct ad4130_filter_config *filter_config =
902 &ad4130_filter_configs[filter_mode];
903 unsigned int dividend, divisor;
904 u64 temp;
905
906 dividend = (filter_config->fs_max - fs + AD4130_FILTER_SELECT_MIN) *
907 AD4130_MAX_ODR;
908 divisor = filter_config->fs_max * filter_config->odr_div;
909
910 temp = div_u64((u64)dividend * NANO, divisor);
911 *val = div_u64_rem(temp, NANO, val2);
912 }
913
ad4130_set_filter_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int val)914 static int ad4130_set_filter_mode(struct iio_dev *indio_dev,
915 const struct iio_chan_spec *chan,
916 unsigned int val)
917 {
918 struct ad4130_state *st = iio_priv(indio_dev);
919 unsigned int channel = chan->scan_index;
920 struct ad4130_chan_info *chan_info = &st->chans_info[channel];
921 struct ad4130_setup_info *setup_info = &chan_info->setup;
922 enum ad4130_filter_mode old_filter_mode;
923 int freq_val, freq_val2;
924 unsigned int old_fs;
925 int ret = 0;
926
927 mutex_lock(&st->lock);
928 if (setup_info->filter_mode == val)
929 goto out;
930
931 old_fs = setup_info->fs;
932 old_filter_mode = setup_info->filter_mode;
933
934 /*
935 * When switching between filter modes, try to match the ODR as
936 * close as possible. To do this, convert the current FS into ODR
937 * using the old filter mode, then convert it back into FS using
938 * the new filter mode.
939 */
940 ad4130_fs_to_freq(setup_info->filter_mode, setup_info->fs,
941 &freq_val, &freq_val2);
942
943 ad4130_freq_to_fs(val, freq_val, freq_val2, &setup_info->fs);
944
945 setup_info->filter_mode = val;
946
947 ret = ad4130_write_channel_setup(st, channel, false);
948 if (ret) {
949 setup_info->fs = old_fs;
950 setup_info->filter_mode = old_filter_mode;
951 }
952
953 out:
954 mutex_unlock(&st->lock);
955
956 return ret;
957 }
958
ad4130_get_filter_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)959 static int ad4130_get_filter_mode(struct iio_dev *indio_dev,
960 const struct iio_chan_spec *chan)
961 {
962 struct ad4130_state *st = iio_priv(indio_dev);
963 unsigned int channel = chan->scan_index;
964 struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup;
965 enum ad4130_filter_mode filter_mode;
966
967 mutex_lock(&st->lock);
968 filter_mode = setup_info->filter_mode;
969 mutex_unlock(&st->lock);
970
971 return filter_mode;
972 }
973
974 static const struct iio_enum ad4130_filter_mode_enum = {
975 .items = ad4130_filter_modes_str,
976 .num_items = ARRAY_SIZE(ad4130_filter_modes_str),
977 .set = ad4130_set_filter_mode,
978 .get = ad4130_get_filter_mode,
979 };
980
981 static const struct iio_chan_spec_ext_info ad4130_filter_mode_ext_info[] = {
982 IIO_ENUM("filter_mode", IIO_SEPARATE, &ad4130_filter_mode_enum),
983 IIO_ENUM_AVAILABLE("filter_mode", IIO_SHARED_BY_TYPE,
984 &ad4130_filter_mode_enum),
985 { }
986 };
987
988 static const struct iio_chan_spec ad4130_channel_template = {
989 .type = IIO_VOLTAGE,
990 .indexed = 1,
991 .differential = 1,
992 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
993 BIT(IIO_CHAN_INFO_SCALE) |
994 BIT(IIO_CHAN_INFO_OFFSET) |
995 BIT(IIO_CHAN_INFO_SAMP_FREQ),
996 .info_mask_separate_available = BIT(IIO_CHAN_INFO_SCALE) |
997 BIT(IIO_CHAN_INFO_SAMP_FREQ),
998 .ext_info = ad4130_filter_mode_ext_info,
999 .scan_type = {
1000 .sign = 'u',
1001 .endianness = IIO_BE,
1002 },
1003 };
1004
ad4130_set_channel_pga(struct ad4130_state * st,unsigned int channel,int val,int val2)1005 static int ad4130_set_channel_pga(struct ad4130_state *st, unsigned int channel,
1006 int val, int val2)
1007 {
1008 struct ad4130_chan_info *chan_info = &st->chans_info[channel];
1009 struct ad4130_setup_info *setup_info = &chan_info->setup;
1010 unsigned int pga, old_pga;
1011 int ret = 0;
1012
1013 for (pga = 0; pga < AD4130_MAX_PGA; pga++)
1014 if (val == st->scale_tbls[setup_info->ref_sel][pga][0] &&
1015 val2 == st->scale_tbls[setup_info->ref_sel][pga][1])
1016 break;
1017
1018 if (pga == AD4130_MAX_PGA)
1019 return -EINVAL;
1020
1021 mutex_lock(&st->lock);
1022 if (pga == setup_info->pga)
1023 goto out;
1024
1025 old_pga = setup_info->pga;
1026 setup_info->pga = pga;
1027
1028 ret = ad4130_write_channel_setup(st, channel, false);
1029 if (ret)
1030 setup_info->pga = old_pga;
1031
1032 out:
1033 mutex_unlock(&st->lock);
1034
1035 return ret;
1036 }
1037
ad4130_set_channel_freq(struct ad4130_state * st,unsigned int channel,int val,int val2)1038 static int ad4130_set_channel_freq(struct ad4130_state *st,
1039 unsigned int channel, int val, int val2)
1040 {
1041 struct ad4130_chan_info *chan_info = &st->chans_info[channel];
1042 struct ad4130_setup_info *setup_info = &chan_info->setup;
1043 unsigned int fs, old_fs;
1044 int ret = 0;
1045
1046 mutex_lock(&st->lock);
1047 old_fs = setup_info->fs;
1048
1049 ad4130_freq_to_fs(setup_info->filter_mode, val, val2, &fs);
1050
1051 if (fs == setup_info->fs)
1052 goto out;
1053
1054 setup_info->fs = fs;
1055
1056 ret = ad4130_write_channel_setup(st, channel, false);
1057 if (ret)
1058 setup_info->fs = old_fs;
1059
1060 out:
1061 mutex_unlock(&st->lock);
1062
1063 return ret;
1064 }
1065
_ad4130_read_sample(struct iio_dev * indio_dev,unsigned int channel,int * val)1066 static int _ad4130_read_sample(struct iio_dev *indio_dev, unsigned int channel,
1067 int *val)
1068 {
1069 struct ad4130_state *st = iio_priv(indio_dev);
1070 int ret;
1071
1072 ret = ad4130_set_channel_enable(st, channel, true);
1073 if (ret)
1074 return ret;
1075
1076 reinit_completion(&st->completion);
1077
1078 ret = ad4130_set_mode(st, AD4130_MODE_CONTINUOUS);
1079 if (ret)
1080 return ret;
1081
1082 ret = wait_for_completion_timeout(&st->completion,
1083 msecs_to_jiffies(1000));
1084 if (!ret)
1085 return -ETIMEDOUT;
1086
1087 ret = ad4130_set_mode(st, AD4130_MODE_IDLE);
1088 if (ret)
1089 return ret;
1090
1091 ret = regmap_read(st->regmap, AD4130_DATA_REG, val);
1092 if (ret)
1093 return ret;
1094
1095 ret = ad4130_set_channel_enable(st, channel, false);
1096 if (ret)
1097 return ret;
1098
1099 return IIO_VAL_INT;
1100 }
1101
ad4130_read_sample(struct iio_dev * indio_dev,unsigned int channel,int * val)1102 static int ad4130_read_sample(struct iio_dev *indio_dev, unsigned int channel,
1103 int *val)
1104 {
1105 struct ad4130_state *st = iio_priv(indio_dev);
1106 int ret;
1107
1108 ret = iio_device_claim_direct_mode(indio_dev);
1109 if (ret)
1110 return ret;
1111
1112 mutex_lock(&st->lock);
1113 ret = _ad4130_read_sample(indio_dev, channel, val);
1114 mutex_unlock(&st->lock);
1115
1116 iio_device_release_direct_mode(indio_dev);
1117
1118 return ret;
1119 }
1120
ad4130_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)1121 static int ad4130_read_raw(struct iio_dev *indio_dev,
1122 struct iio_chan_spec const *chan,
1123 int *val, int *val2, long info)
1124 {
1125 struct ad4130_state *st = iio_priv(indio_dev);
1126 unsigned int channel = chan->scan_index;
1127 struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup;
1128
1129 switch (info) {
1130 case IIO_CHAN_INFO_RAW:
1131 return ad4130_read_sample(indio_dev, channel, val);
1132 case IIO_CHAN_INFO_SCALE:
1133 mutex_lock(&st->lock);
1134 *val = st->scale_tbls[setup_info->ref_sel][setup_info->pga][0];
1135 *val2 = st->scale_tbls[setup_info->ref_sel][setup_info->pga][1];
1136 mutex_unlock(&st->lock);
1137
1138 return IIO_VAL_INT_PLUS_NANO;
1139 case IIO_CHAN_INFO_OFFSET:
1140 *val = st->bipolar ? -BIT(chan->scan_type.realbits - 1) : 0;
1141
1142 return IIO_VAL_INT;
1143 case IIO_CHAN_INFO_SAMP_FREQ:
1144 mutex_lock(&st->lock);
1145 ad4130_fs_to_freq(setup_info->filter_mode, setup_info->fs,
1146 val, val2);
1147 mutex_unlock(&st->lock);
1148
1149 return IIO_VAL_INT_PLUS_NANO;
1150 default:
1151 return -EINVAL;
1152 }
1153 }
1154
ad4130_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long info)1155 static int ad4130_read_avail(struct iio_dev *indio_dev,
1156 struct iio_chan_spec const *chan,
1157 const int **vals, int *type, int *length,
1158 long info)
1159 {
1160 struct ad4130_state *st = iio_priv(indio_dev);
1161 unsigned int channel = chan->scan_index;
1162 struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup;
1163 const struct ad4130_filter_config *filter_config;
1164
1165 switch (info) {
1166 case IIO_CHAN_INFO_SCALE:
1167 *vals = (int *)st->scale_tbls[setup_info->ref_sel];
1168 *length = ARRAY_SIZE(st->scale_tbls[setup_info->ref_sel]) * 2;
1169
1170 *type = IIO_VAL_INT_PLUS_NANO;
1171
1172 return IIO_AVAIL_LIST;
1173 case IIO_CHAN_INFO_SAMP_FREQ:
1174 mutex_lock(&st->lock);
1175 filter_config = &ad4130_filter_configs[setup_info->filter_mode];
1176 mutex_unlock(&st->lock);
1177
1178 *vals = (int *)filter_config->samp_freq_avail;
1179 *length = filter_config->samp_freq_avail_len * 2;
1180 *type = IIO_VAL_FRACTIONAL;
1181
1182 return filter_config->samp_freq_avail_type;
1183 default:
1184 return -EINVAL;
1185 }
1186 }
1187
ad4130_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long info)1188 static int ad4130_write_raw_get_fmt(struct iio_dev *indio_dev,
1189 struct iio_chan_spec const *chan,
1190 long info)
1191 {
1192 switch (info) {
1193 case IIO_CHAN_INFO_SCALE:
1194 case IIO_CHAN_INFO_SAMP_FREQ:
1195 return IIO_VAL_INT_PLUS_NANO;
1196 default:
1197 return -EINVAL;
1198 }
1199 }
1200
ad4130_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)1201 static int ad4130_write_raw(struct iio_dev *indio_dev,
1202 struct iio_chan_spec const *chan,
1203 int val, int val2, long info)
1204 {
1205 struct ad4130_state *st = iio_priv(indio_dev);
1206 unsigned int channel = chan->scan_index;
1207
1208 switch (info) {
1209 case IIO_CHAN_INFO_SCALE:
1210 return ad4130_set_channel_pga(st, channel, val, val2);
1211 case IIO_CHAN_INFO_SAMP_FREQ:
1212 return ad4130_set_channel_freq(st, channel, val, val2);
1213 default:
1214 return -EINVAL;
1215 }
1216 }
1217
ad4130_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)1218 static int ad4130_reg_access(struct iio_dev *indio_dev, unsigned int reg,
1219 unsigned int writeval, unsigned int *readval)
1220 {
1221 struct ad4130_state *st = iio_priv(indio_dev);
1222
1223 if (readval)
1224 return regmap_read(st->regmap, reg, readval);
1225
1226 return regmap_write(st->regmap, reg, writeval);
1227 }
1228
ad4130_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)1229 static int ad4130_update_scan_mode(struct iio_dev *indio_dev,
1230 const unsigned long *scan_mask)
1231 {
1232 struct ad4130_state *st = iio_priv(indio_dev);
1233 unsigned int channel;
1234 unsigned int val = 0;
1235 int ret;
1236
1237 mutex_lock(&st->lock);
1238
1239 for_each_set_bit(channel, scan_mask, indio_dev->num_channels) {
1240 ret = ad4130_set_channel_enable(st, channel, true);
1241 if (ret)
1242 goto out;
1243
1244 val++;
1245 }
1246
1247 st->num_enabled_channels = val;
1248
1249 out:
1250 mutex_unlock(&st->lock);
1251
1252 return 0;
1253 }
1254
ad4130_set_fifo_watermark(struct iio_dev * indio_dev,unsigned int val)1255 static int ad4130_set_fifo_watermark(struct iio_dev *indio_dev, unsigned int val)
1256 {
1257 struct ad4130_state *st = iio_priv(indio_dev);
1258 unsigned int eff;
1259 int ret;
1260
1261 if (val > AD4130_FIFO_SIZE)
1262 return -EINVAL;
1263
1264 eff = val * st->num_enabled_channels;
1265 if (eff > AD4130_FIFO_SIZE)
1266 /*
1267 * Always set watermark to a multiple of the number of
1268 * enabled channels to avoid making the FIFO unaligned.
1269 */
1270 eff = rounddown(AD4130_FIFO_SIZE, st->num_enabled_channels);
1271
1272 mutex_lock(&st->lock);
1273
1274 ret = regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG,
1275 AD4130_FIFO_CONTROL_WM_MASK,
1276 FIELD_PREP(AD4130_FIFO_CONTROL_WM_MASK,
1277 ad4130_watermark_reg_val(eff)));
1278 if (ret)
1279 goto out;
1280
1281 st->effective_watermark = eff;
1282 st->watermark = val;
1283
1284 out:
1285 mutex_unlock(&st->lock);
1286
1287 return ret;
1288 }
1289
1290 static const struct iio_info ad4130_info = {
1291 .read_raw = ad4130_read_raw,
1292 .read_avail = ad4130_read_avail,
1293 .write_raw_get_fmt = ad4130_write_raw_get_fmt,
1294 .write_raw = ad4130_write_raw,
1295 .update_scan_mode = ad4130_update_scan_mode,
1296 .hwfifo_set_watermark = ad4130_set_fifo_watermark,
1297 .debugfs_reg_access = ad4130_reg_access,
1298 };
1299
ad4130_buffer_postenable(struct iio_dev * indio_dev)1300 static int ad4130_buffer_postenable(struct iio_dev *indio_dev)
1301 {
1302 struct ad4130_state *st = iio_priv(indio_dev);
1303 int ret;
1304
1305 mutex_lock(&st->lock);
1306
1307 ret = ad4130_set_watermark_interrupt_en(st, true);
1308 if (ret)
1309 goto out;
1310
1311 ret = irq_set_irq_type(st->spi->irq, st->inv_irq_trigger);
1312 if (ret)
1313 goto out;
1314
1315 ret = ad4130_set_fifo_mode(st, AD4130_FIFO_MODE_WM);
1316 if (ret)
1317 goto out;
1318
1319 ret = ad4130_set_mode(st, AD4130_MODE_CONTINUOUS);
1320
1321 out:
1322 mutex_unlock(&st->lock);
1323
1324 return ret;
1325 }
1326
ad4130_buffer_predisable(struct iio_dev * indio_dev)1327 static int ad4130_buffer_predisable(struct iio_dev *indio_dev)
1328 {
1329 struct ad4130_state *st = iio_priv(indio_dev);
1330 unsigned int i;
1331 int ret;
1332
1333 mutex_lock(&st->lock);
1334
1335 ret = ad4130_set_mode(st, AD4130_MODE_IDLE);
1336 if (ret)
1337 goto out;
1338
1339 ret = irq_set_irq_type(st->spi->irq, st->irq_trigger);
1340 if (ret)
1341 goto out;
1342
1343 ret = ad4130_set_fifo_mode(st, AD4130_FIFO_MODE_DISABLED);
1344 if (ret)
1345 goto out;
1346
1347 ret = ad4130_set_watermark_interrupt_en(st, false);
1348 if (ret)
1349 goto out;
1350
1351 /*
1352 * update_scan_mode() is not called in the disable path, disable all
1353 * channels here.
1354 */
1355 for (i = 0; i < indio_dev->num_channels; i++) {
1356 ret = ad4130_set_channel_enable(st, i, false);
1357 if (ret)
1358 goto out;
1359 }
1360
1361 out:
1362 mutex_unlock(&st->lock);
1363
1364 return ret;
1365 }
1366
1367 static const struct iio_buffer_setup_ops ad4130_buffer_ops = {
1368 .postenable = ad4130_buffer_postenable,
1369 .predisable = ad4130_buffer_predisable,
1370 };
1371
hwfifo_watermark_show(struct device * dev,struct device_attribute * attr,char * buf)1372 static ssize_t hwfifo_watermark_show(struct device *dev,
1373 struct device_attribute *attr, char *buf)
1374 {
1375 struct ad4130_state *st = iio_priv(dev_to_iio_dev(dev));
1376 unsigned int val;
1377
1378 mutex_lock(&st->lock);
1379 val = st->watermark;
1380 mutex_unlock(&st->lock);
1381
1382 return sysfs_emit(buf, "%d\n", val);
1383 }
1384
hwfifo_enabled_show(struct device * dev,struct device_attribute * attr,char * buf)1385 static ssize_t hwfifo_enabled_show(struct device *dev,
1386 struct device_attribute *attr, char *buf)
1387 {
1388 struct ad4130_state *st = iio_priv(dev_to_iio_dev(dev));
1389 unsigned int val;
1390 int ret;
1391
1392 ret = regmap_read(st->regmap, AD4130_FIFO_CONTROL_REG, &val);
1393 if (ret)
1394 return ret;
1395
1396 val = FIELD_GET(AD4130_FIFO_CONTROL_MODE_MASK, val);
1397
1398 return sysfs_emit(buf, "%d\n", val != AD4130_FIFO_MODE_DISABLED);
1399 }
1400
hwfifo_watermark_min_show(struct device * dev,struct device_attribute * attr,char * buf)1401 static ssize_t hwfifo_watermark_min_show(struct device *dev,
1402 struct device_attribute *attr,
1403 char *buf)
1404 {
1405 return sysfs_emit(buf, "%s\n", "1");
1406 }
1407
hwfifo_watermark_max_show(struct device * dev,struct device_attribute * attr,char * buf)1408 static ssize_t hwfifo_watermark_max_show(struct device *dev,
1409 struct device_attribute *attr,
1410 char *buf)
1411 {
1412 return sysfs_emit(buf, "%s\n", __stringify(AD4130_FIFO_SIZE));
1413 }
1414
1415 static IIO_DEVICE_ATTR_RO(hwfifo_watermark_min, 0);
1416 static IIO_DEVICE_ATTR_RO(hwfifo_watermark_max, 0);
1417 static IIO_DEVICE_ATTR_RO(hwfifo_watermark, 0);
1418 static IIO_DEVICE_ATTR_RO(hwfifo_enabled, 0);
1419
1420 static const struct iio_dev_attr *ad4130_fifo_attributes[] = {
1421 &iio_dev_attr_hwfifo_watermark_min,
1422 &iio_dev_attr_hwfifo_watermark_max,
1423 &iio_dev_attr_hwfifo_watermark,
1424 &iio_dev_attr_hwfifo_enabled,
1425 NULL
1426 };
1427
_ad4130_find_table_index(const unsigned int * tbl,size_t len,unsigned int val)1428 static int _ad4130_find_table_index(const unsigned int *tbl, size_t len,
1429 unsigned int val)
1430 {
1431 unsigned int i;
1432
1433 for (i = 0; i < len; i++)
1434 if (tbl[i] == val)
1435 return i;
1436
1437 return -EINVAL;
1438 }
1439
1440 #define ad4130_find_table_index(table, val) \
1441 _ad4130_find_table_index(table, ARRAY_SIZE(table), val)
1442
ad4130_get_ref_voltage(struct ad4130_state * st,enum ad4130_ref_sel ref_sel)1443 static int ad4130_get_ref_voltage(struct ad4130_state *st,
1444 enum ad4130_ref_sel ref_sel)
1445 {
1446 switch (ref_sel) {
1447 case AD4130_REF_REFIN1:
1448 return regulator_get_voltage(st->regulators[2].consumer);
1449 case AD4130_REF_REFIN2:
1450 return regulator_get_voltage(st->regulators[3].consumer);
1451 case AD4130_REF_AVDD_AVSS:
1452 return regulator_get_voltage(st->regulators[0].consumer);
1453 case AD4130_REF_REFOUT_AVSS:
1454 return st->int_ref_uv;
1455 default:
1456 return -EINVAL;
1457 }
1458 }
1459
ad4130_parse_fw_setup(struct ad4130_state * st,struct fwnode_handle * child,struct ad4130_setup_info * setup_info)1460 static int ad4130_parse_fw_setup(struct ad4130_state *st,
1461 struct fwnode_handle *child,
1462 struct ad4130_setup_info *setup_info)
1463 {
1464 struct device *dev = &st->spi->dev;
1465 u32 tmp;
1466 int ret;
1467
1468 tmp = 0;
1469 fwnode_property_read_u32(child, "adi,excitation-current-0-nanoamp", &tmp);
1470 ret = ad4130_find_table_index(ad4130_iout_current_na_tbl, tmp);
1471 if (ret < 0)
1472 return dev_err_probe(dev, ret,
1473 "Invalid excitation current %unA\n", tmp);
1474 setup_info->iout0_val = ret;
1475
1476 tmp = 0;
1477 fwnode_property_read_u32(child, "adi,excitation-current-1-nanoamp", &tmp);
1478 ret = ad4130_find_table_index(ad4130_iout_current_na_tbl, tmp);
1479 if (ret < 0)
1480 return dev_err_probe(dev, ret,
1481 "Invalid excitation current %unA\n", tmp);
1482 setup_info->iout1_val = ret;
1483
1484 tmp = 0;
1485 fwnode_property_read_u32(child, "adi,burnout-current-nanoamp", &tmp);
1486 ret = ad4130_find_table_index(ad4130_burnout_current_na_tbl, tmp);
1487 if (ret < 0)
1488 return dev_err_probe(dev, ret,
1489 "Invalid burnout current %unA\n", tmp);
1490 setup_info->burnout = ret;
1491
1492 setup_info->ref_bufp = fwnode_property_read_bool(child, "adi,buffered-positive");
1493 setup_info->ref_bufm = fwnode_property_read_bool(child, "adi,buffered-negative");
1494
1495 setup_info->ref_sel = AD4130_REF_REFIN1;
1496 fwnode_property_read_u32(child, "adi,reference-select",
1497 &setup_info->ref_sel);
1498 if (setup_info->ref_sel >= AD4130_REF_SEL_MAX)
1499 return dev_err_probe(dev, -EINVAL,
1500 "Invalid reference selected %u\n",
1501 setup_info->ref_sel);
1502
1503 if (setup_info->ref_sel == AD4130_REF_REFOUT_AVSS)
1504 st->int_ref_en = true;
1505
1506 ret = ad4130_get_ref_voltage(st, setup_info->ref_sel);
1507 if (ret < 0)
1508 return dev_err_probe(dev, ret, "Cannot use reference %u\n",
1509 setup_info->ref_sel);
1510
1511 return 0;
1512 }
1513
ad4130_validate_diff_channel(struct ad4130_state * st,u32 pin)1514 static int ad4130_validate_diff_channel(struct ad4130_state *st, u32 pin)
1515 {
1516 struct device *dev = &st->spi->dev;
1517
1518 if (pin >= AD4130_MAX_DIFF_INPUTS)
1519 return dev_err_probe(dev, -EINVAL,
1520 "Invalid differential channel %u\n", pin);
1521
1522 if (pin >= AD4130_MAX_ANALOG_PINS)
1523 return 0;
1524
1525 if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL)
1526 return dev_err_probe(dev, -EINVAL,
1527 "Pin %u already used with fn %u\n", pin,
1528 st->pins_fn[pin]);
1529
1530 st->pins_fn[pin] |= AD4130_PIN_FN_DIFF;
1531
1532 return 0;
1533 }
1534
ad4130_validate_diff_channels(struct ad4130_state * st,u32 * pins,unsigned int len)1535 static int ad4130_validate_diff_channels(struct ad4130_state *st,
1536 u32 *pins, unsigned int len)
1537 {
1538 unsigned int i;
1539 int ret;
1540
1541 for (i = 0; i < len; i++) {
1542 ret = ad4130_validate_diff_channel(st, pins[i]);
1543 if (ret)
1544 return ret;
1545 }
1546
1547 return 0;
1548 }
1549
ad4130_validate_excitation_pin(struct ad4130_state * st,u32 pin)1550 static int ad4130_validate_excitation_pin(struct ad4130_state *st, u32 pin)
1551 {
1552 struct device *dev = &st->spi->dev;
1553
1554 if (pin >= AD4130_MAX_ANALOG_PINS)
1555 return dev_err_probe(dev, -EINVAL,
1556 "Invalid excitation pin %u\n", pin);
1557
1558 if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL)
1559 return dev_err_probe(dev, -EINVAL,
1560 "Pin %u already used with fn %u\n", pin,
1561 st->pins_fn[pin]);
1562
1563 st->pins_fn[pin] |= AD4130_PIN_FN_EXCITATION;
1564
1565 return 0;
1566 }
1567
ad4130_validate_vbias_pin(struct ad4130_state * st,u32 pin)1568 static int ad4130_validate_vbias_pin(struct ad4130_state *st, u32 pin)
1569 {
1570 struct device *dev = &st->spi->dev;
1571
1572 if (pin >= AD4130_MAX_ANALOG_PINS)
1573 return dev_err_probe(dev, -EINVAL, "Invalid vbias pin %u\n",
1574 pin);
1575
1576 if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL)
1577 return dev_err_probe(dev, -EINVAL,
1578 "Pin %u already used with fn %u\n", pin,
1579 st->pins_fn[pin]);
1580
1581 st->pins_fn[pin] |= AD4130_PIN_FN_VBIAS;
1582
1583 return 0;
1584 }
1585
ad4130_validate_vbias_pins(struct ad4130_state * st,u32 * pins,unsigned int len)1586 static int ad4130_validate_vbias_pins(struct ad4130_state *st,
1587 u32 *pins, unsigned int len)
1588 {
1589 unsigned int i;
1590 int ret;
1591
1592 for (i = 0; i < st->num_vbias_pins; i++) {
1593 ret = ad4130_validate_vbias_pin(st, pins[i]);
1594 if (ret)
1595 return ret;
1596 }
1597
1598 return 0;
1599 }
1600
ad4130_parse_fw_channel(struct iio_dev * indio_dev,struct fwnode_handle * child)1601 static int ad4130_parse_fw_channel(struct iio_dev *indio_dev,
1602 struct fwnode_handle *child)
1603 {
1604 struct ad4130_state *st = iio_priv(indio_dev);
1605 unsigned int resolution = ad4130_resolution(st);
1606 unsigned int index = indio_dev->num_channels++;
1607 struct device *dev = &st->spi->dev;
1608 struct ad4130_chan_info *chan_info;
1609 struct iio_chan_spec *chan;
1610 u32 pins[2];
1611 int ret;
1612
1613 if (index >= AD4130_MAX_CHANNELS)
1614 return dev_err_probe(dev, -EINVAL, "Too many channels\n");
1615
1616 chan = &st->chans[index];
1617 chan_info = &st->chans_info[index];
1618
1619 *chan = ad4130_channel_template;
1620 chan->scan_type.realbits = resolution;
1621 chan->scan_type.storagebits = resolution;
1622 chan->scan_index = index;
1623
1624 chan_info->slot = AD4130_INVALID_SLOT;
1625 chan_info->setup.fs = AD4130_FILTER_SELECT_MIN;
1626 chan_info->initialized = true;
1627
1628 ret = fwnode_property_read_u32_array(child, "diff-channels", pins,
1629 ARRAY_SIZE(pins));
1630 if (ret)
1631 return ret;
1632
1633 ret = ad4130_validate_diff_channels(st, pins, ARRAY_SIZE(pins));
1634 if (ret)
1635 return ret;
1636
1637 chan->channel = pins[0];
1638 chan->channel2 = pins[1];
1639
1640 ret = ad4130_parse_fw_setup(st, child, &chan_info->setup);
1641 if (ret)
1642 return ret;
1643
1644 fwnode_property_read_u32(child, "adi,excitation-pin-0",
1645 &chan_info->iout0);
1646 if (chan_info->setup.iout0_val != AD4130_IOUT_OFF) {
1647 ret = ad4130_validate_excitation_pin(st, chan_info->iout0);
1648 if (ret)
1649 return ret;
1650 }
1651
1652 fwnode_property_read_u32(child, "adi,excitation-pin-1",
1653 &chan_info->iout1);
1654 if (chan_info->setup.iout1_val != AD4130_IOUT_OFF) {
1655 ret = ad4130_validate_excitation_pin(st, chan_info->iout1);
1656 if (ret)
1657 return ret;
1658 }
1659
1660 return 0;
1661 }
1662
ad4130_parse_fw_children(struct iio_dev * indio_dev)1663 static int ad4130_parse_fw_children(struct iio_dev *indio_dev)
1664 {
1665 struct ad4130_state *st = iio_priv(indio_dev);
1666 struct device *dev = &st->spi->dev;
1667 struct fwnode_handle *child;
1668 int ret;
1669
1670 indio_dev->channels = st->chans;
1671
1672 device_for_each_child_node(dev, child) {
1673 ret = ad4130_parse_fw_channel(indio_dev, child);
1674 if (ret) {
1675 fwnode_handle_put(child);
1676 return ret;
1677 }
1678 }
1679
1680 return 0;
1681 }
1682
ad4310_parse_fw(struct iio_dev * indio_dev)1683 static int ad4310_parse_fw(struct iio_dev *indio_dev)
1684 {
1685 struct ad4130_state *st = iio_priv(indio_dev);
1686 struct device *dev = &st->spi->dev;
1687 u32 ext_clk_freq = AD4130_MCLK_FREQ_76_8KHZ;
1688 unsigned int i;
1689 int avdd_uv;
1690 int irq;
1691 int ret;
1692
1693 st->mclk = devm_clk_get_optional(dev, "mclk");
1694 if (IS_ERR(st->mclk))
1695 return dev_err_probe(dev, PTR_ERR(st->mclk),
1696 "Failed to get mclk\n");
1697
1698 st->int_pin_sel = AD4130_INT_PIN_INT;
1699
1700 for (i = 0; i < ARRAY_SIZE(ad4130_int_pin_names); i++) {
1701 irq = fwnode_irq_get_byname(dev_fwnode(dev),
1702 ad4130_int_pin_names[i]);
1703 if (irq > 0) {
1704 st->int_pin_sel = i;
1705 break;
1706 }
1707 }
1708
1709 if (st->int_pin_sel == AD4130_INT_PIN_DOUT)
1710 return dev_err_probe(dev, -EINVAL,
1711 "Cannot use DOUT as interrupt pin\n");
1712
1713 if (st->int_pin_sel == AD4130_INT_PIN_P2)
1714 st->pins_fn[AD4130_AIN3_P2] = AD4130_PIN_FN_SPECIAL;
1715
1716 device_property_read_u32(dev, "adi,ext-clk-freq-hz", &ext_clk_freq);
1717 if (ext_clk_freq != AD4130_MCLK_FREQ_153_6KHZ &&
1718 ext_clk_freq != AD4130_MCLK_FREQ_76_8KHZ)
1719 return dev_err_probe(dev, -EINVAL,
1720 "Invalid external clock frequency %u\n",
1721 ext_clk_freq);
1722
1723 if (st->mclk && ext_clk_freq == AD4130_MCLK_FREQ_153_6KHZ)
1724 st->mclk_sel = AD4130_MCLK_153_6KHZ_EXT;
1725 else if (st->mclk)
1726 st->mclk_sel = AD4130_MCLK_76_8KHZ_EXT;
1727 else
1728 st->mclk_sel = AD4130_MCLK_76_8KHZ;
1729
1730 if (st->int_pin_sel == AD4130_INT_PIN_CLK &&
1731 st->mclk_sel != AD4130_MCLK_76_8KHZ)
1732 return dev_err_probe(dev, -EINVAL,
1733 "Invalid clock %u for interrupt pin %u\n",
1734 st->mclk_sel, st->int_pin_sel);
1735
1736 st->int_ref_uv = AD4130_INT_REF_2_5V;
1737
1738 /*
1739 * When the AVDD supply is set to below 2.5V the internal reference of
1740 * 1.25V should be selected.
1741 * See datasheet page 37, section ADC REFERENCE.
1742 */
1743 avdd_uv = regulator_get_voltage(st->regulators[0].consumer);
1744 if (avdd_uv > 0 && avdd_uv < AD4130_INT_REF_2_5V)
1745 st->int_ref_uv = AD4130_INT_REF_1_25V;
1746
1747 st->bipolar = device_property_read_bool(dev, "adi,bipolar");
1748
1749 ret = device_property_count_u32(dev, "adi,vbias-pins");
1750 if (ret > 0) {
1751 if (ret > AD4130_MAX_ANALOG_PINS)
1752 return dev_err_probe(dev, -EINVAL,
1753 "Too many vbias pins %u\n", ret);
1754
1755 st->num_vbias_pins = ret;
1756
1757 ret = device_property_read_u32_array(dev, "adi,vbias-pins",
1758 st->vbias_pins,
1759 st->num_vbias_pins);
1760 if (ret)
1761 return dev_err_probe(dev, ret,
1762 "Failed to read vbias pins\n");
1763
1764 ret = ad4130_validate_vbias_pins(st, st->vbias_pins,
1765 st->num_vbias_pins);
1766 if (ret)
1767 return ret;
1768 }
1769
1770 ret = ad4130_parse_fw_children(indio_dev);
1771 if (ret)
1772 return ret;
1773
1774 return 0;
1775 }
1776
ad4130_fill_scale_tbls(struct ad4130_state * st)1777 static void ad4130_fill_scale_tbls(struct ad4130_state *st)
1778 {
1779 unsigned int pow = ad4130_resolution(st) - st->bipolar;
1780 unsigned int i, j;
1781
1782 for (i = 0; i < AD4130_REF_SEL_MAX; i++) {
1783 int ret;
1784 u64 nv;
1785
1786 ret = ad4130_get_ref_voltage(st, i);
1787 if (ret < 0)
1788 continue;
1789
1790 nv = (u64)ret * NANO;
1791
1792 for (j = 0; j < AD4130_MAX_PGA; j++)
1793 st->scale_tbls[i][j][1] = div_u64(nv >> (pow + j), MILLI);
1794 }
1795 }
1796
ad4130_clk_disable_unprepare(void * clk)1797 static void ad4130_clk_disable_unprepare(void *clk)
1798 {
1799 clk_disable_unprepare(clk);
1800 }
1801
ad4130_set_mclk_sel(struct ad4130_state * st,enum ad4130_mclk_sel mclk_sel)1802 static int ad4130_set_mclk_sel(struct ad4130_state *st,
1803 enum ad4130_mclk_sel mclk_sel)
1804 {
1805 return regmap_update_bits(st->regmap, AD4130_ADC_CONTROL_REG,
1806 AD4130_ADC_CONTROL_MCLK_SEL_MASK,
1807 FIELD_PREP(AD4130_ADC_CONTROL_MCLK_SEL_MASK,
1808 mclk_sel));
1809 }
1810
ad4130_int_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1811 static unsigned long ad4130_int_clk_recalc_rate(struct clk_hw *hw,
1812 unsigned long parent_rate)
1813 {
1814 return AD4130_MCLK_FREQ_76_8KHZ;
1815 }
1816
ad4130_int_clk_is_enabled(struct clk_hw * hw)1817 static int ad4130_int_clk_is_enabled(struct clk_hw *hw)
1818 {
1819 struct ad4130_state *st = container_of(hw, struct ad4130_state, int_clk_hw);
1820
1821 return st->mclk_sel == AD4130_MCLK_76_8KHZ_OUT;
1822 }
1823
ad4130_int_clk_prepare(struct clk_hw * hw)1824 static int ad4130_int_clk_prepare(struct clk_hw *hw)
1825 {
1826 struct ad4130_state *st = container_of(hw, struct ad4130_state, int_clk_hw);
1827 int ret;
1828
1829 ret = ad4130_set_mclk_sel(st, AD4130_MCLK_76_8KHZ_OUT);
1830 if (ret)
1831 return ret;
1832
1833 st->mclk_sel = AD4130_MCLK_76_8KHZ_OUT;
1834
1835 return 0;
1836 }
1837
ad4130_int_clk_unprepare(struct clk_hw * hw)1838 static void ad4130_int_clk_unprepare(struct clk_hw *hw)
1839 {
1840 struct ad4130_state *st = container_of(hw, struct ad4130_state, int_clk_hw);
1841 int ret;
1842
1843 ret = ad4130_set_mclk_sel(st, AD4130_MCLK_76_8KHZ);
1844 if (ret)
1845 return;
1846
1847 st->mclk_sel = AD4130_MCLK_76_8KHZ;
1848 }
1849
1850 static const struct clk_ops ad4130_int_clk_ops = {
1851 .recalc_rate = ad4130_int_clk_recalc_rate,
1852 .is_enabled = ad4130_int_clk_is_enabled,
1853 .prepare = ad4130_int_clk_prepare,
1854 .unprepare = ad4130_int_clk_unprepare,
1855 };
1856
ad4130_clk_del_provider(void * of_node)1857 static void ad4130_clk_del_provider(void *of_node)
1858 {
1859 of_clk_del_provider(of_node);
1860 }
1861
ad4130_setup_int_clk(struct ad4130_state * st)1862 static int ad4130_setup_int_clk(struct ad4130_state *st)
1863 {
1864 struct device *dev = &st->spi->dev;
1865 struct device_node *of_node = dev_of_node(dev);
1866 struct clk_init_data init = {};
1867 const char *clk_name;
1868 struct clk *clk;
1869 int ret;
1870
1871 if (st->int_pin_sel == AD4130_INT_PIN_CLK ||
1872 st->mclk_sel != AD4130_MCLK_76_8KHZ)
1873 return 0;
1874
1875 if (!of_node)
1876 return 0;
1877
1878 clk_name = of_node->name;
1879 of_property_read_string(of_node, "clock-output-names", &clk_name);
1880
1881 init.name = clk_name;
1882 init.ops = &ad4130_int_clk_ops;
1883
1884 st->int_clk_hw.init = &init;
1885 clk = devm_clk_register(dev, &st->int_clk_hw);
1886 if (IS_ERR(clk))
1887 return PTR_ERR(clk);
1888
1889 ret = of_clk_add_provider(of_node, of_clk_src_simple_get, clk);
1890 if (ret)
1891 return ret;
1892
1893 return devm_add_action_or_reset(dev, ad4130_clk_del_provider, of_node);
1894 }
1895
ad4130_setup(struct iio_dev * indio_dev)1896 static int ad4130_setup(struct iio_dev *indio_dev)
1897 {
1898 struct ad4130_state *st = iio_priv(indio_dev);
1899 struct device *dev = &st->spi->dev;
1900 unsigned int int_ref_val;
1901 unsigned long rate = AD4130_MCLK_FREQ_76_8KHZ;
1902 unsigned int val;
1903 unsigned int i;
1904 int ret;
1905
1906 if (st->mclk_sel == AD4130_MCLK_153_6KHZ_EXT)
1907 rate = AD4130_MCLK_FREQ_153_6KHZ;
1908
1909 ret = clk_set_rate(st->mclk, rate);
1910 if (ret)
1911 return ret;
1912
1913 ret = clk_prepare_enable(st->mclk);
1914 if (ret)
1915 return ret;
1916
1917 ret = devm_add_action_or_reset(dev, ad4130_clk_disable_unprepare,
1918 st->mclk);
1919 if (ret)
1920 return ret;
1921
1922 if (st->int_ref_uv == AD4130_INT_REF_2_5V)
1923 int_ref_val = AD4130_INT_REF_VAL_2_5V;
1924 else
1925 int_ref_val = AD4130_INT_REF_VAL_1_25V;
1926
1927 /* Switch to SPI 4-wire mode. */
1928 val = FIELD_PREP(AD4130_ADC_CONTROL_CSB_EN_MASK, 1);
1929 val |= FIELD_PREP(AD4130_ADC_CONTROL_BIPOLAR_MASK, st->bipolar);
1930 val |= FIELD_PREP(AD4130_ADC_CONTROL_INT_REF_EN_MASK, st->int_ref_en);
1931 val |= FIELD_PREP(AD4130_ADC_CONTROL_MODE_MASK, AD4130_MODE_IDLE);
1932 val |= FIELD_PREP(AD4130_ADC_CONTROL_MCLK_SEL_MASK, st->mclk_sel);
1933 val |= FIELD_PREP(AD4130_ADC_CONTROL_INT_REF_VAL_MASK, int_ref_val);
1934
1935 ret = regmap_write(st->regmap, AD4130_ADC_CONTROL_REG, val);
1936 if (ret)
1937 return ret;
1938
1939 /*
1940 * Configure unused GPIOs for output. If configured, the interrupt
1941 * function of P2 takes priority over the GPIO out function.
1942 */
1943 val = 0;
1944 for (i = 0; i < AD4130_MAX_GPIOS; i++)
1945 if (st->pins_fn[i + AD4130_AIN2_P1] == AD4130_PIN_FN_NONE)
1946 val |= FIELD_PREP(AD4130_IO_CONTROL_GPIO_CTRL_MASK, BIT(i));
1947
1948 val |= FIELD_PREP(AD4130_IO_CONTROL_INT_PIN_SEL_MASK, st->int_pin_sel);
1949
1950 ret = regmap_write(st->regmap, AD4130_IO_CONTROL_REG, val);
1951 if (ret)
1952 return ret;
1953
1954 val = 0;
1955 for (i = 0; i < st->num_vbias_pins; i++)
1956 val |= BIT(st->vbias_pins[i]);
1957
1958 ret = regmap_write(st->regmap, AD4130_VBIAS_REG, val);
1959 if (ret)
1960 return ret;
1961
1962 ret = regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG,
1963 AD4130_FIFO_CONTROL_HEADER_MASK, 0);
1964 if (ret)
1965 return ret;
1966
1967 /* FIFO watermark interrupt starts out as enabled, disable it. */
1968 ret = ad4130_set_watermark_interrupt_en(st, false);
1969 if (ret)
1970 return ret;
1971
1972 /* Setup channels. */
1973 for (i = 0; i < indio_dev->num_channels; i++) {
1974 struct ad4130_chan_info *chan_info = &st->chans_info[i];
1975 struct iio_chan_spec *chan = &st->chans[i];
1976 unsigned int val;
1977
1978 val = FIELD_PREP(AD4130_CHANNEL_AINP_MASK, chan->channel) |
1979 FIELD_PREP(AD4130_CHANNEL_AINM_MASK, chan->channel2) |
1980 FIELD_PREP(AD4130_CHANNEL_IOUT1_MASK, chan_info->iout0) |
1981 FIELD_PREP(AD4130_CHANNEL_IOUT2_MASK, chan_info->iout1);
1982
1983 ret = regmap_write(st->regmap, AD4130_CHANNEL_X_REG(i), val);
1984 if (ret)
1985 return ret;
1986 }
1987
1988 return 0;
1989 }
1990
ad4130_soft_reset(struct ad4130_state * st)1991 static int ad4130_soft_reset(struct ad4130_state *st)
1992 {
1993 int ret;
1994
1995 ret = spi_write(st->spi, st->reset_buf, sizeof(st->reset_buf));
1996 if (ret)
1997 return ret;
1998
1999 fsleep(AD4130_RESET_SLEEP_US);
2000
2001 return 0;
2002 }
2003
ad4130_disable_regulators(void * data)2004 static void ad4130_disable_regulators(void *data)
2005 {
2006 struct ad4130_state *st = data;
2007
2008 regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators);
2009 }
2010
ad4130_probe(struct spi_device * spi)2011 static int ad4130_probe(struct spi_device *spi)
2012 {
2013 struct device *dev = &spi->dev;
2014 struct iio_dev *indio_dev;
2015 struct ad4130_state *st;
2016 int ret;
2017
2018 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
2019 if (!indio_dev)
2020 return -ENOMEM;
2021
2022 st = iio_priv(indio_dev);
2023
2024 memset(st->reset_buf, 0xff, sizeof(st->reset_buf));
2025 init_completion(&st->completion);
2026 mutex_init(&st->lock);
2027 st->spi = spi;
2028
2029 /*
2030 * Xfer: [ XFR1 ] [ XFR2 ]
2031 * Master: 0x7D N ......................
2032 * Slave: ...... DATA1 DATA2 ... DATAN
2033 */
2034 st->fifo_tx_buf[0] = AD4130_COMMS_READ_MASK | AD4130_FIFO_DATA_REG;
2035 st->fifo_xfer[0].tx_buf = st->fifo_tx_buf;
2036 st->fifo_xfer[0].len = sizeof(st->fifo_tx_buf);
2037 st->fifo_xfer[1].rx_buf = st->fifo_rx_buf;
2038 spi_message_init_with_transfers(&st->fifo_msg, st->fifo_xfer,
2039 ARRAY_SIZE(st->fifo_xfer));
2040
2041 indio_dev->name = AD4130_NAME;
2042 indio_dev->modes = INDIO_DIRECT_MODE;
2043 indio_dev->info = &ad4130_info;
2044
2045 st->regmap = devm_regmap_init(dev, NULL, st, &ad4130_regmap_config);
2046 if (IS_ERR(st->regmap))
2047 return PTR_ERR(st->regmap);
2048
2049 st->regulators[0].supply = "avdd";
2050 st->regulators[1].supply = "iovdd";
2051 st->regulators[2].supply = "refin1";
2052 st->regulators[3].supply = "refin2";
2053
2054 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->regulators),
2055 st->regulators);
2056 if (ret)
2057 return dev_err_probe(dev, ret, "Failed to get regulators\n");
2058
2059 ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators);
2060 if (ret)
2061 return dev_err_probe(dev, ret, "Failed to enable regulators\n");
2062
2063 ret = devm_add_action_or_reset(dev, ad4130_disable_regulators, st);
2064 if (ret)
2065 return dev_err_probe(dev, ret,
2066 "Failed to add regulators disable action\n");
2067
2068 ret = ad4130_soft_reset(st);
2069 if (ret)
2070 return ret;
2071
2072 ret = ad4310_parse_fw(indio_dev);
2073 if (ret)
2074 return ret;
2075
2076 ret = ad4130_setup(indio_dev);
2077 if (ret)
2078 return ret;
2079
2080 ret = ad4130_setup_int_clk(st);
2081 if (ret)
2082 return ret;
2083
2084 ad4130_fill_scale_tbls(st);
2085
2086 st->gc.owner = THIS_MODULE;
2087 st->gc.label = AD4130_NAME;
2088 st->gc.base = -1;
2089 st->gc.ngpio = AD4130_MAX_GPIOS;
2090 st->gc.parent = dev;
2091 st->gc.can_sleep = true;
2092 st->gc.init_valid_mask = ad4130_gpio_init_valid_mask;
2093 st->gc.get_direction = ad4130_gpio_get_direction;
2094 st->gc.set = ad4130_gpio_set;
2095
2096 ret = devm_gpiochip_add_data(dev, &st->gc, st);
2097 if (ret)
2098 return ret;
2099
2100 ret = devm_iio_kfifo_buffer_setup_ext(dev, indio_dev,
2101 &ad4130_buffer_ops,
2102 ad4130_fifo_attributes);
2103 if (ret)
2104 return ret;
2105
2106 ret = devm_request_threaded_irq(dev, spi->irq, NULL,
2107 ad4130_irq_handler, IRQF_ONESHOT,
2108 indio_dev->name, indio_dev);
2109 if (ret)
2110 return dev_err_probe(dev, ret, "Failed to request irq\n");
2111
2112 /*
2113 * When the chip enters FIFO mode, IRQ polarity is inverted.
2114 * When the chip exits FIFO mode, IRQ polarity returns to normal.
2115 * See datasheet pages: 65, FIFO Watermark Interrupt section,
2116 * and 71, Bit Descriptions for STATUS Register, RDYB.
2117 * Cache the normal and inverted IRQ triggers to set them when
2118 * entering and exiting FIFO mode.
2119 */
2120 st->irq_trigger = irq_get_trigger_type(spi->irq);
2121 if (st->irq_trigger & IRQF_TRIGGER_RISING)
2122 st->inv_irq_trigger = IRQF_TRIGGER_FALLING;
2123 else if (st->irq_trigger & IRQF_TRIGGER_FALLING)
2124 st->inv_irq_trigger = IRQF_TRIGGER_RISING;
2125 else
2126 return dev_err_probe(dev, -EINVAL, "Invalid irq flags: %u\n",
2127 st->irq_trigger);
2128
2129 return devm_iio_device_register(dev, indio_dev);
2130 }
2131
2132 static const struct of_device_id ad4130_of_match[] = {
2133 {
2134 .compatible = "adi,ad4130",
2135 },
2136 { }
2137 };
2138 MODULE_DEVICE_TABLE(of, ad4130_of_match);
2139
2140 static struct spi_driver ad4130_driver = {
2141 .driver = {
2142 .name = AD4130_NAME,
2143 .of_match_table = ad4130_of_match,
2144 },
2145 .probe = ad4130_probe,
2146 };
2147 module_spi_driver(ad4130_driver);
2148
2149 MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>");
2150 MODULE_DESCRIPTION("Analog Devices AD4130 SPI driver");
2151 MODULE_LICENSE("GPL");
2152