1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qobject/qnum.h"
26 #include "acpi-build.h"
27 #include "acpi-common.h"
28 #include "qemu/bitmap.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci_bridge.h"
31 #include "hw/cxl/cxl.h"
32 #include "hw/core/cpu.h"
33 #include "target/i386/cpu.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/acpi/cpu.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/acpi/acpi_aml_interface.h"
41 #include "hw/input/i8042.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "system/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "hw/acpi/vmgenid.h"
46 #include "hw/acpi/vmclock.h"
47 #include "hw/acpi/erst.h"
48 #include "hw/acpi/piix4.h"
49 #include "system/tpm_backend.h"
50 #include "hw/rtc/mc146818rtc_regs.h"
51 #include "migration/vmstate.h"
52 #include "hw/mem/memory-device.h"
53 #include "hw/mem/nvdimm.h"
54 #include "system/numa.h"
55 #include "system/reset.h"
56 #include "hw/hyperv/vmbus-bridge.h"
57
58 /* Supported chipsets: */
59 #include "hw/southbridge/ich9.h"
60 #include "hw/acpi/pcihp.h"
61 #include "hw/i386/fw_cfg.h"
62 #include "hw/i386/pc.h"
63 #include "hw/pci/pci_bus.h"
64 #include "hw/pci-host/i440fx.h"
65 #include "hw/pci-host/q35.h"
66 #include "hw/i386/x86-iommu.h"
67
68 #include "hw/acpi/aml-build.h"
69 #include "hw/acpi/utils.h"
70 #include "hw/acpi/pci.h"
71 #include "hw/acpi/cxl.h"
72
73 #include "qom/qom-qobject.h"
74 #include "hw/i386/amd_iommu.h"
75 #include "hw/i386/intel_iommu.h"
76 #include "hw/virtio/virtio-iommu.h"
77
78 #include "hw/acpi/hmat.h"
79 #include "hw/acpi/viot.h"
80
81 #include CONFIG_DEVICES
82
83 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
84 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
85 * a little bit, there should be plenty of free space since the DSDT
86 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
87 */
88 #define ACPI_BUILD_ALIGN_SIZE 0x1000
89
90 #define ACPI_BUILD_TABLE_SIZE 0x20000
91
92 /* #define DEBUG_ACPI_BUILD */
93 #ifdef DEBUG_ACPI_BUILD
94 #define ACPI_BUILD_DPRINTF(fmt, ...) \
95 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
96 #else
97 #define ACPI_BUILD_DPRINTF(fmt, ...)
98 #endif
99
100 typedef struct AcpiPmInfo {
101 bool s3_disabled;
102 bool s4_disabled;
103 bool pcihp_bridge_en;
104 bool smi_on_cpuhp;
105 bool smi_on_cpu_unplug;
106 bool pcihp_root_en;
107 uint8_t s4_val;
108 AcpiFadtData fadt;
109 uint16_t cpu_hp_io_base;
110 uint16_t pcihp_io_base;
111 uint16_t pcihp_io_len;
112 } AcpiPmInfo;
113
114 typedef struct AcpiMiscInfo {
115 bool has_hpet;
116 #ifdef CONFIG_TPM
117 TPMVersion tpm_version;
118 #endif
119 } AcpiMiscInfo;
120
121 typedef struct FwCfgTPMConfig {
122 uint32_t tpmppi_address;
123 uint8_t tpm_version;
124 uint8_t tpmppi_version;
125 } QEMU_PACKED FwCfgTPMConfig;
126
127 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg);
128
129 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = {
130 .space_id = AML_AS_SYSTEM_IO,
131 .address = NVDIMM_ACPI_IO_BASE,
132 .bit_width = NVDIMM_ACPI_IO_LEN << 3
133 };
134
init_common_fadt_data(MachineState * ms,Object * o,AcpiFadtData * data)135 static void init_common_fadt_data(MachineState *ms, Object *o,
136 AcpiFadtData *data)
137 {
138 X86MachineState *x86ms = X86_MACHINE(ms);
139 /*
140 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old
141 * behavior for compatibility irrelevant to smm_enabled, which doesn't
142 * conform to the ACPI spec.
143 */
144 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ?
145 true : x86_machine_is_smm_enabled(x86ms);
146 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
147 AmlAddressSpace as = AML_AS_SYSTEM_IO;
148 AcpiFadtData fadt = {
149 .rev = 3,
150 .flags =
151 (1 << ACPI_FADT_F_WBINVD) |
152 (1 << ACPI_FADT_F_PROC_C1) |
153 (1 << ACPI_FADT_F_SLP_BUTTON) |
154 (1 << ACPI_FADT_F_RTC_S4) |
155 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
156 /* APIC destination mode ("Flat Logical") has an upper limit of 8
157 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
158 * used
159 */
160 ((ms->smp.max_cpus > 8) ?
161 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
162 .int_model = 1 /* Multiple APIC */,
163 .rtc_century = RTC_CENTURY,
164 .plvl2_lat = 0xfff /* C2 state not supported */,
165 .plvl3_lat = 0xfff /* C3 state not supported */,
166 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0,
167 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
168 .acpi_enable_cmd =
169 smm_enabled ?
170 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) :
171 0,
172 .acpi_disable_cmd =
173 smm_enabled ?
174 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) :
175 0,
176 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
177 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
178 .address = io + 0x04 },
179 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
180 .gpe0_blk = { .space_id = as, .bit_width =
181 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
182 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
183 },
184 };
185
186 /*
187 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture
188 * Flags, bit offset 1 - 8042.
189 */
190 fadt.iapc_boot_arch = iapc_boot_arch_8042();
191
192 *data = fadt;
193 }
194
acpi_get_pm_info(MachineState * machine,AcpiPmInfo * pm)195 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
196 {
197 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM, NULL);
198 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE, NULL);
199 Object *obj = piix ? piix : lpc;
200 QObject *o;
201 pm->cpu_hp_io_base = 0;
202 pm->pcihp_io_base = 0;
203 pm->pcihp_io_len = 0;
204 pm->smi_on_cpuhp = false;
205 pm->smi_on_cpu_unplug = false;
206
207 assert(obj);
208 init_common_fadt_data(machine, obj, &pm->fadt);
209 if (piix) {
210 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
211 pm->fadt.rev = 1;
212 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
213 }
214 if (lpc) {
215 uint64_t smi_features = object_property_get_uint(lpc,
216 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL);
217 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
218 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
219 pm->fadt.reset_reg = r;
220 pm->fadt.reset_val = 0xf;
221 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
222 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
223 pm->smi_on_cpuhp =
224 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT));
225 pm->smi_on_cpu_unplug =
226 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT));
227 }
228 pm->pcihp_io_base =
229 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
230 pm->pcihp_io_len =
231 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
232
233 /* Fill in optional s3/s4 related properties */
234 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
235 if (o) {
236 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o));
237 } else {
238 pm->s3_disabled = false;
239 }
240 qobject_unref(o);
241 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
242 if (o) {
243 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o));
244 } else {
245 pm->s4_disabled = false;
246 }
247 qobject_unref(o);
248 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
249 if (o) {
250 pm->s4_val = qnum_get_uint(qobject_to(QNum, o));
251 } else {
252 pm->s4_val = false;
253 }
254 qobject_unref(o);
255
256 pm->pcihp_bridge_en =
257 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE,
258 NULL);
259 pm->pcihp_root_en =
260 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP,
261 NULL);
262 }
263
acpi_get_misc_info(AcpiMiscInfo * info)264 static void acpi_get_misc_info(AcpiMiscInfo *info)
265 {
266 info->has_hpet = hpet_find();
267 #ifdef CONFIG_TPM
268 info->tpm_version = tpm_get_version(tpm_find());
269 #endif
270 }
271
272 /*
273 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
274 * On i386 arch we only have two pci hosts, so we can look only for them.
275 */
acpi_get_i386_pci_host(void)276 Object *acpi_get_i386_pci_host(void)
277 {
278 PCIHostState *host;
279
280 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL));
281 if (!host) {
282 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL));
283 }
284
285 return OBJECT(host);
286 }
287
acpi_get_pci_holes(Range * hole,Range * hole64)288 static void acpi_get_pci_holes(Range *hole, Range *hole64)
289 {
290 Object *pci_host;
291
292 pci_host = acpi_get_i386_pci_host();
293
294 if (!pci_host) {
295 return;
296 }
297
298 range_set_bounds1(hole,
299 object_property_get_uint(pci_host,
300 PCI_HOST_PROP_PCI_HOLE_START,
301 NULL),
302 object_property_get_uint(pci_host,
303 PCI_HOST_PROP_PCI_HOLE_END,
304 NULL));
305 range_set_bounds1(hole64,
306 object_property_get_uint(pci_host,
307 PCI_HOST_PROP_PCI_HOLE64_START,
308 NULL),
309 object_property_get_uint(pci_host,
310 PCI_HOST_PROP_PCI_HOLE64_END,
311 NULL));
312 }
313
acpi_align_size(GArray * blob,unsigned align)314 static void acpi_align_size(GArray *blob, unsigned align)
315 {
316 /* Align size to multiple of given size. This reduces the chance
317 * we need to change size in the future (breaking cross version migration).
318 */
319 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
320 }
321
322 /*
323 * ACPI spec 1.0b,
324 * 5.2.6 Firmware ACPI Control Structure
325 */
326 static void
build_facs(GArray * table_data)327 build_facs(GArray *table_data)
328 {
329 const char *sig = "FACS";
330 const uint8_t reserved[40] = {};
331
332 g_array_append_vals(table_data, sig, 4); /* Signature */
333 build_append_int_noprefix(table_data, 64, 4); /* Length */
334 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */
335 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */
336 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */
337 build_append_int_noprefix(table_data, 0, 4); /* Flags */
338 g_array_append_vals(table_data, reserved, 40); /* Reserved */
339 }
340
341 /*
342 * build_prt - Define interrupt routing rules
343 *
344 * Returns an array of 128 routes, one for each device,
345 * based on device location.
346 * The main goal is to equally distribute the interrupts
347 * over the 4 existing ACPI links (works only for i440fx).
348 * The hash function is: (slot + pin) & 3 -> "LNK[D|A|B|C]".
349 *
350 */
build_prt(bool is_pci0_prt)351 static Aml *build_prt(bool is_pci0_prt)
352 {
353 const int nroutes = 128;
354 Aml *rt_pkg, *method;
355 int pin;
356
357 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
358 assert(nroutes < 256);
359 rt_pkg = aml_package(nroutes);
360
361 for (pin = 0; pin < nroutes; pin++) {
362 Aml *pkg = aml_package(4);
363 int slot = pin >> 2;
364
365 aml_append(pkg, aml_int((slot << 16) | 0xFFFF));
366 aml_append(pkg, aml_int(pin & 3));
367 /* device 1 is the power-management device, needs SCI */
368 if (is_pci0_prt && pin == 4) {
369 aml_append(pkg, aml_name("%s", "LNKS"));
370 } else {
371 static const char link_name[][5] = {"LNKD", "LNKA", "LNKB", "LNKC"};
372 int hash = (slot + pin) & 3;
373 aml_append(pkg, aml_name("%s", link_name[hash]));
374 }
375 aml_append(pkg, aml_int(0));
376 aml_append(rt_pkg, pkg);
377 }
378
379 aml_append(method, aml_return(rt_pkg));
380
381 return method;
382 }
383
build_hpet_aml(Aml * table)384 static void build_hpet_aml(Aml *table)
385 {
386 Aml *crs;
387 Aml *field;
388 Aml *method;
389 Aml *if_ctx;
390 Aml *scope = aml_scope("_SB");
391 Aml *dev = aml_device("HPET");
392 Aml *zero = aml_int(0);
393 Aml *id = aml_local(0);
394 Aml *period = aml_local(1);
395
396 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
397 aml_append(dev, aml_name_decl("_UID", zero));
398
399 aml_append(dev,
400 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
401 HPET_LEN));
402 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
403 aml_append(field, aml_named_field("VEND", 32));
404 aml_append(field, aml_named_field("PRD", 32));
405 aml_append(dev, field);
406
407 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
408 aml_append(method, aml_store(aml_name("VEND"), id));
409 aml_append(method, aml_store(aml_name("PRD"), period));
410 aml_append(method, aml_shiftright(id, aml_int(16), id));
411 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
412 aml_equal(id, aml_int(0xffff))));
413 {
414 aml_append(if_ctx, aml_return(zero));
415 }
416 aml_append(method, if_ctx);
417
418 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
419 aml_lgreater(period, aml_int(100000000))));
420 {
421 aml_append(if_ctx, aml_return(zero));
422 }
423 aml_append(method, if_ctx);
424
425 aml_append(method, aml_return(aml_int(0x0F)));
426 aml_append(dev, method);
427
428 crs = aml_resource_template();
429 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
430 aml_append(dev, aml_name_decl("_CRS", crs));
431
432 aml_append(scope, dev);
433 aml_append(table, scope);
434 }
435
build_vmbus_device_aml(VMBusBridge * vmbus_bridge)436 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge)
437 {
438 Aml *dev;
439 Aml *method;
440 Aml *crs;
441
442 dev = aml_device("VMBS");
443 aml_append(dev, aml_name_decl("STA", aml_int(0xF)));
444 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus")));
445 aml_append(dev, aml_name_decl("_UID", aml_int(0x0)));
446 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS")));
447
448 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
449 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL),
450 aml_name("STA")));
451 aml_append(dev, method);
452
453 method = aml_method("_PS0", 0, AML_NOTSERIALIZED);
454 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL),
455 aml_name("STA")));
456 aml_append(dev, method);
457
458 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
459 aml_append(method, aml_return(aml_name("STA")));
460 aml_append(dev, method);
461
462 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0)));
463
464 crs = aml_resource_template();
465 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq));
466 aml_append(dev, aml_name_decl("_CRS", crs));
467
468 return dev;
469 }
470
build_dbg_aml(Aml * table)471 static void build_dbg_aml(Aml *table)
472 {
473 Aml *field;
474 Aml *method;
475 Aml *while_ctx;
476 Aml *scope = aml_scope("\\");
477 Aml *buf = aml_local(0);
478 Aml *len = aml_local(1);
479 Aml *idx = aml_local(2);
480
481 aml_append(scope,
482 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
483 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
484 aml_append(field, aml_named_field("DBGB", 8));
485 aml_append(scope, field);
486
487 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
488
489 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
490 aml_append(method, aml_to_buffer(buf, buf));
491 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
492 aml_append(method, aml_store(aml_int(0), idx));
493
494 while_ctx = aml_while(aml_lless(idx, len));
495 aml_append(while_ctx,
496 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
497 aml_append(while_ctx, aml_increment(idx));
498 aml_append(method, while_ctx);
499
500 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
501 aml_append(scope, method);
502
503 aml_append(table, scope);
504 }
505
build_link_dev(const char * name,uint8_t uid,Aml * reg)506 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
507 {
508 Aml *dev;
509 Aml *crs;
510 Aml *method;
511 uint32_t irqs[] = {5, 10, 11};
512
513 dev = aml_device("%s", name);
514 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
515 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
516
517 crs = aml_resource_template();
518 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
519 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
520 aml_append(dev, aml_name_decl("_PRS", crs));
521
522 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
523 aml_append(method, aml_return(aml_call1("IQST", reg)));
524 aml_append(dev, method);
525
526 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
527 aml_append(method, aml_or(reg, aml_int(0x80), reg));
528 aml_append(dev, method);
529
530 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
531 aml_append(method, aml_return(aml_call1("IQCR", reg)));
532 aml_append(dev, method);
533
534 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
535 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
536 aml_append(method, aml_store(aml_name("PRRI"), reg));
537 aml_append(dev, method);
538
539 return dev;
540 }
541
build_gsi_link_dev(const char * name,uint8_t uid,uint8_t gsi)542 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
543 {
544 Aml *dev;
545 Aml *crs;
546 Aml *method;
547 uint32_t irqs;
548
549 dev = aml_device("%s", name);
550 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
551 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
552
553 crs = aml_resource_template();
554 irqs = gsi;
555 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
556 AML_SHARED, &irqs, 1));
557 aml_append(dev, aml_name_decl("_PRS", crs));
558
559 aml_append(dev, aml_name_decl("_CRS", crs));
560
561 /*
562 * _DIS can be no-op because the interrupt cannot be disabled.
563 */
564 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
565 aml_append(dev, method);
566
567 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
568 aml_append(dev, method);
569
570 return dev;
571 }
572
573 /* _CRS method - get current settings */
build_iqcr_method(bool is_piix4)574 static Aml *build_iqcr_method(bool is_piix4)
575 {
576 Aml *if_ctx;
577 uint32_t irqs;
578 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
579 Aml *crs = aml_resource_template();
580
581 irqs = 0;
582 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
583 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
584 aml_append(method, aml_name_decl("PRR0", crs));
585
586 aml_append(method,
587 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
588
589 if (is_piix4) {
590 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
591 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
592 aml_append(method, if_ctx);
593 } else {
594 aml_append(method,
595 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
596 aml_name("PRRI")));
597 }
598
599 aml_append(method, aml_return(aml_name("PRR0")));
600 return method;
601 }
602
603 /* _STA method - get status */
build_irq_status_method(void)604 static Aml *build_irq_status_method(void)
605 {
606 Aml *if_ctx;
607 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
608
609 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
610 aml_append(if_ctx, aml_return(aml_int(0x09)));
611 aml_append(method, if_ctx);
612 aml_append(method, aml_return(aml_int(0x0B)));
613 return method;
614 }
615
build_piix4_pci0_int(Aml * table)616 static void build_piix4_pci0_int(Aml *table)
617 {
618 Aml *dev;
619 Aml *crs;
620 Aml *method;
621 uint32_t irqs;
622 Aml *sb_scope = aml_scope("_SB");
623 Aml *pci0_scope = aml_scope("PCI0");
624
625 aml_append(pci0_scope, build_prt(true));
626 aml_append(sb_scope, pci0_scope);
627
628 aml_append(sb_scope, build_irq_status_method());
629 aml_append(sb_scope, build_iqcr_method(true));
630
631 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
632 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
633 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
634 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
635
636 dev = aml_device("LNKS");
637 {
638 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
639 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
640
641 crs = aml_resource_template();
642 irqs = 9;
643 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
644 AML_ACTIVE_HIGH, AML_SHARED,
645 &irqs, 1));
646 aml_append(dev, aml_name_decl("_PRS", crs));
647
648 /* The SCI cannot be disabled and is always attached to GSI 9,
649 * so these are no-ops. We only need this link to override the
650 * polarity to active high and match the content of the MADT.
651 */
652 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
653 aml_append(method, aml_return(aml_int(0x0b)));
654 aml_append(dev, method);
655
656 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
657 aml_append(dev, method);
658
659 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
660 aml_append(method, aml_return(aml_name("_PRS")));
661 aml_append(dev, method);
662
663 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
664 aml_append(dev, method);
665 }
666 aml_append(sb_scope, dev);
667
668 aml_append(table, sb_scope);
669 }
670
append_q35_prt_entry(Aml * ctx,uint32_t nr,const char * name)671 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
672 {
673 int i;
674 int head;
675 Aml *pkg;
676 char base = name[3] < 'E' ? 'A' : 'E';
677 char *s = g_strdup(name);
678 Aml *a_nr = aml_int((nr << 16) | 0xffff);
679
680 assert(strlen(s) == 4);
681
682 head = name[3] - base;
683 for (i = 0; i < 4; i++) {
684 if (head + i > 3) {
685 head = i * -1;
686 }
687 s[3] = base + head + i;
688 pkg = aml_package(4);
689 aml_append(pkg, a_nr);
690 aml_append(pkg, aml_int(i));
691 aml_append(pkg, aml_name("%s", s));
692 aml_append(pkg, aml_int(0));
693 aml_append(ctx, pkg);
694 }
695 g_free(s);
696 }
697
build_q35_routing_table(const char * str)698 static Aml *build_q35_routing_table(const char *str)
699 {
700 int i;
701 Aml *pkg;
702 char *name = g_strdup_printf("%s ", str);
703
704 pkg = aml_package(128);
705 for (i = 0; i < 0x18; i++) {
706 name[3] = 'E' + (i & 0x3);
707 append_q35_prt_entry(pkg, i, name);
708 }
709
710 name[3] = 'E';
711 append_q35_prt_entry(pkg, 0x18, name);
712
713 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
714 for (i = 0x0019; i < 0x1e; i++) {
715 name[3] = 'A';
716 append_q35_prt_entry(pkg, i, name);
717 }
718
719 /* PCIe->PCI bridge. use PIRQ[E-H] */
720 name[3] = 'E';
721 append_q35_prt_entry(pkg, 0x1e, name);
722 name[3] = 'A';
723 append_q35_prt_entry(pkg, 0x1f, name);
724
725 g_free(name);
726 return pkg;
727 }
728
build_q35_pci0_int(Aml * table)729 static void build_q35_pci0_int(Aml *table)
730 {
731 Aml *method;
732 Aml *sb_scope = aml_scope("_SB");
733 Aml *pci0_scope = aml_scope("PCI0");
734
735 /* Zero => PIC mode, One => APIC Mode */
736 aml_append(table, aml_name_decl("PICF", aml_int(0)));
737 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
738 {
739 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
740 }
741 aml_append(table, method);
742
743 aml_append(pci0_scope,
744 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
745 aml_append(pci0_scope,
746 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
747
748 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
749 {
750 Aml *if_ctx;
751 Aml *else_ctx;
752
753 /* PCI IRQ routing table, example from ACPI 2.0a specification,
754 section 6.2.8.1 */
755 /* Note: we provide the same info as the PCI routing
756 table of the Bochs BIOS */
757 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
758 aml_append(if_ctx, aml_return(aml_name("PRTP")));
759 aml_append(method, if_ctx);
760 else_ctx = aml_else();
761 aml_append(else_ctx, aml_return(aml_name("PRTA")));
762 aml_append(method, else_ctx);
763 }
764 aml_append(pci0_scope, method);
765 aml_append(sb_scope, pci0_scope);
766
767 aml_append(sb_scope, build_irq_status_method());
768 aml_append(sb_scope, build_iqcr_method(false));
769
770 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
771 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
772 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
773 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
774 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
775 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
776 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
777 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
778
779 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
780 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
781 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
782 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
783 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
784 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
785 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
786 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
787
788 aml_append(table, sb_scope);
789 }
790
build_q35_dram_controller(const AcpiMcfgInfo * mcfg)791 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg)
792 {
793 Aml *dev;
794 Aml *resource_template;
795
796 /* DRAM controller */
797 dev = aml_device("DRAC");
798 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01")));
799
800 resource_template = aml_resource_template();
801 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) {
802 aml_append(resource_template,
803 aml_qword_memory(AML_POS_DECODE,
804 AML_MIN_FIXED,
805 AML_MAX_FIXED,
806 AML_NON_CACHEABLE,
807 AML_READ_WRITE,
808 0x0000000000000000,
809 mcfg->base,
810 mcfg->base + mcfg->size - 1,
811 0x0000000000000000,
812 mcfg->size));
813 } else {
814 aml_append(resource_template,
815 aml_dword_memory(AML_POS_DECODE,
816 AML_MIN_FIXED,
817 AML_MAX_FIXED,
818 AML_NON_CACHEABLE,
819 AML_READ_WRITE,
820 0x0000000000000000,
821 mcfg->base,
822 mcfg->base + mcfg->size - 1,
823 0x0000000000000000,
824 mcfg->size));
825 }
826 aml_append(dev, aml_name_decl("_CRS", resource_template));
827
828 return dev;
829 }
830
build_acpi0017(Aml * table)831 static void build_acpi0017(Aml *table)
832 {
833 Aml *dev, *scope, *method;
834
835 scope = aml_scope("_SB");
836 dev = aml_device("CXLM");
837 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017")));
838
839 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
840 aml_append(method, aml_return(aml_int(0x0B)));
841 aml_append(dev, method);
842 build_cxl_dsm_method(dev);
843
844 aml_append(scope, dev);
845 aml_append(table, scope);
846 }
847
848 static void
build_dsdt(GArray * table_data,BIOSLinker * linker,AcpiPmInfo * pm,AcpiMiscInfo * misc,Range * pci_hole,Range * pci_hole64,MachineState * machine)849 build_dsdt(GArray *table_data, BIOSLinker *linker,
850 AcpiPmInfo *pm, AcpiMiscInfo *misc,
851 Range *pci_hole, Range *pci_hole64, MachineState *machine)
852 {
853 Object *i440fx = object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE,
854 NULL);
855 Object *q35 = object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE, NULL);
856 CrsRangeEntry *entry;
857 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
858 CrsRangeSet crs_range_set;
859 PCMachineState *pcms = PC_MACHINE(machine);
860 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
861 X86MachineState *x86ms = X86_MACHINE(machine);
862 AcpiMcfgInfo mcfg;
863 bool mcfg_valid = !!acpi_get_mcfg(&mcfg);
864 uint32_t nr_mem = machine->ram_slots;
865 int root_bus_limit = 0xFF;
866 PCIBus *bus = NULL;
867 #ifdef CONFIG_TPM
868 TPMIf *tpm = tpm_find();
869 #endif
870 bool cxl_present = false;
871 int i;
872 VMBusBridge *vmbus_bridge = vmbus_bridge_find();
873 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id,
874 .oem_table_id = x86ms->oem_table_id };
875
876 assert(!!i440fx != !!q35);
877
878 acpi_table_begin(&table, table_data);
879 dsdt = init_aml_allocator();
880
881 build_dbg_aml(dsdt);
882 if (i440fx) {
883 sb_scope = aml_scope("_SB");
884 dev = aml_device("PCI0");
885 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
886 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
887 aml_append(dev, build_pci_bridge_edsm());
888 aml_append(sb_scope, dev);
889 aml_append(dsdt, sb_scope);
890
891 if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
892 build_acpi_pci_hotplug(dsdt, AML_SYSTEM_IO, pm->pcihp_io_base);
893 }
894 build_piix4_pci0_int(dsdt);
895 } else if (q35) {
896 sb_scope = aml_scope("_SB");
897 dev = aml_device("PCI0");
898 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
899 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
900 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
901 aml_append(dev, build_pci_host_bridge_osc_method(!pm->pcihp_bridge_en));
902 aml_append(dev, build_pci_bridge_edsm());
903 aml_append(sb_scope, dev);
904 if (mcfg_valid) {
905 aml_append(sb_scope, build_q35_dram_controller(&mcfg));
906 }
907
908 if (pm->smi_on_cpuhp) {
909 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */
910 dev = aml_device("PCI0.SMI0");
911 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
912 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources")));
913 crs = aml_resource_template();
914 aml_append(crs,
915 aml_io(
916 AML_DECODE16,
917 pm->fadt.smi_cmd,
918 pm->fadt.smi_cmd,
919 1,
920 2)
921 );
922 aml_append(dev, aml_name_decl("_CRS", crs));
923 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO,
924 aml_int(pm->fadt.smi_cmd), 2));
925 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK,
926 AML_WRITE_AS_ZEROS);
927 aml_append(field, aml_named_field("SMIC", 8));
928 aml_append(field, aml_reserved_field(8));
929 aml_append(dev, field);
930 aml_append(sb_scope, dev);
931 }
932
933 aml_append(dsdt, sb_scope);
934
935 if (pm->pcihp_bridge_en) {
936 build_acpi_pci_hotplug(dsdt, AML_SYSTEM_IO, pm->pcihp_io_base);
937 }
938 build_q35_pci0_int(dsdt);
939 }
940
941 if (misc->has_hpet) {
942 build_hpet_aml(dsdt);
943 }
944
945 if (vmbus_bridge) {
946 sb_scope = aml_scope("_SB");
947 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge));
948 aml_append(dsdt, sb_scope);
949 }
950
951 scope = aml_scope("_GPE");
952 {
953 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
954 if (machine->nvdimms_state->is_enabled) {
955 method = aml_method("_E04", 0, AML_NOTSERIALIZED);
956 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
957 aml_int(0x80)));
958 aml_append(scope, method);
959 }
960 }
961 aml_append(dsdt, scope);
962
963 if (pcmc->legacy_cpu_hotplug) {
964 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
965 } else {
966 CPUHotplugFeatures opts = {
967 .acpi_1_compatible = true, .has_legacy_cphp = true,
968 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL,
969 .fw_unplugs_cpu = pm->smi_on_cpu_unplug,
970 };
971 build_cpus_aml(dsdt, machine, opts, pc_madt_cpu_entry,
972 pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02",
973 AML_SYSTEM_IO);
974 }
975
976 if (pcms->memhp_io_base && nr_mem) {
977 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0",
978 "\\_GPE._E03", AML_SYSTEM_IO,
979 pcms->memhp_io_base);
980 }
981
982 crs_range_set_init(&crs_range_set);
983 bus = PC_MACHINE(machine)->pcibus;
984 if (bus) {
985 QLIST_FOREACH(bus, &bus->child, sibling) {
986 uint8_t bus_num = pci_bus_num(bus);
987 uint8_t numa_node = pci_bus_numa_node(bus);
988 uint32_t uid;
989
990 /* look only for expander root buses */
991 if (!pci_bus_is_root(bus)) {
992 continue;
993 }
994
995 if (bus_num < root_bus_limit) {
996 root_bus_limit = bus_num - 1;
997 }
998
999 uid = object_property_get_uint(OBJECT(bus), "acpi_uid",
1000 &error_fatal);
1001 scope = aml_scope("\\_SB");
1002
1003 if (pci_bus_is_cxl(bus)) {
1004 dev = aml_device("CL%.02X", bus_num);
1005 } else {
1006 dev = aml_device("PC%.02X", bus_num);
1007 }
1008 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1009 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1010 if (pci_bus_is_cxl(bus)) {
1011 struct Aml *aml_pkg = aml_package(2);
1012
1013 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016")));
1014 aml_append(aml_pkg, aml_eisaid("PNP0A08"));
1015 aml_append(aml_pkg, aml_eisaid("PNP0A03"));
1016 aml_append(dev, aml_name_decl("_CID", aml_pkg));
1017 build_cxl_osc_method(dev);
1018 } else if (pci_bus_is_express(bus)) {
1019 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1020 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1021
1022 /* Expander bridges do not have ACPI PCI Hot-plug enabled */
1023 aml_append(dev, build_pci_host_bridge_osc_method(true));
1024 } else {
1025 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1026 }
1027
1028 if (numa_node != NUMA_NODE_UNASSIGNED) {
1029 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1030 }
1031
1032 aml_append(dev, build_prt(false));
1033 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set,
1034 0, 0, 0, 0);
1035 aml_append(dev, aml_name_decl("_CRS", crs));
1036 aml_append(scope, dev);
1037 aml_append(dsdt, scope);
1038
1039 /* Handle the ranges for the PXB expanders */
1040 if (pci_bus_is_cxl(bus)) {
1041 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
1042 uint64_t base = mr->addr;
1043
1044 cxl_present = true;
1045 crs_range_insert(crs_range_set.mem_ranges, base,
1046 base + memory_region_size(mr) - 1);
1047 }
1048 }
1049 }
1050
1051 if (cxl_present) {
1052 build_acpi0017(dsdt);
1053 }
1054
1055 /*
1056 * At this point crs_range_set has all the ranges used by pci
1057 * busses *other* than PCI0. These ranges will be excluded from
1058 * the PCI0._CRS. Add mmconfig to the set so it will be excluded
1059 * too.
1060 */
1061 if (mcfg_valid) {
1062 crs_range_insert(crs_range_set.mem_ranges,
1063 mcfg.base, mcfg.base + mcfg.size - 1);
1064 }
1065
1066 scope = aml_scope("\\_SB.PCI0");
1067 /* build PCI0._CRS */
1068 crs = aml_resource_template();
1069 aml_append(crs,
1070 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1071 0x0000, 0x0, root_bus_limit,
1072 0x0000, root_bus_limit + 1));
1073 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1074
1075 aml_append(crs,
1076 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1077 AML_POS_DECODE, AML_ENTIRE_RANGE,
1078 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1079
1080 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
1081 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
1082 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
1083 aml_append(crs,
1084 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1085 AML_POS_DECODE, AML_ENTIRE_RANGE,
1086 0x0000, entry->base, entry->limit,
1087 0x0000, entry->limit - entry->base + 1));
1088 }
1089
1090 aml_append(crs,
1091 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1092 AML_CACHEABLE, AML_READ_WRITE,
1093 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1094
1095 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
1096 range_lob(pci_hole),
1097 range_upb(pci_hole));
1098 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
1099 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
1100 aml_append(crs,
1101 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1102 AML_NON_CACHEABLE, AML_READ_WRITE,
1103 0, entry->base, entry->limit,
1104 0, entry->limit - entry->base + 1));
1105 }
1106
1107 if (!range_is_empty(pci_hole64)) {
1108 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
1109 range_lob(pci_hole64),
1110 range_upb(pci_hole64));
1111 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
1112 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
1113 aml_append(crs,
1114 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1115 AML_MAX_FIXED,
1116 AML_CACHEABLE, AML_READ_WRITE,
1117 0, entry->base, entry->limit,
1118 0, entry->limit - entry->base + 1));
1119 }
1120 }
1121
1122 #ifdef CONFIG_TPM
1123 if (TPM_IS_TIS_ISA(tpm_find())) {
1124 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1125 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1126 }
1127 #endif
1128 aml_append(scope, aml_name_decl("_CRS", crs));
1129
1130 /* reserve GPE0 block resources */
1131 dev = aml_device("GPE0");
1132 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1133 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1134 /* device present, functioning, decoding, not shown in UI */
1135 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1136 crs = aml_resource_template();
1137 aml_append(crs,
1138 aml_io(
1139 AML_DECODE16,
1140 pm->fadt.gpe0_blk.address,
1141 pm->fadt.gpe0_blk.address,
1142 1,
1143 pm->fadt.gpe0_blk.bit_width / 8)
1144 );
1145 aml_append(dev, aml_name_decl("_CRS", crs));
1146 aml_append(scope, dev);
1147
1148 crs_range_set_free(&crs_range_set);
1149
1150 /* reserve PCIHP resources */
1151 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) {
1152 build_append_pcihp_resources(scope,
1153 pm->pcihp_io_base, pm->pcihp_io_len);
1154 }
1155 aml_append(dsdt, scope);
1156
1157 /* create S3_ / S4_ / S5_ packages if necessary */
1158 scope = aml_scope("\\");
1159 if (!pm->s3_disabled) {
1160 pkg = aml_package(4);
1161 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1162 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1163 aml_append(pkg, aml_int(0)); /* reserved */
1164 aml_append(pkg, aml_int(0)); /* reserved */
1165 aml_append(scope, aml_name_decl("_S3", pkg));
1166 }
1167
1168 if (!pm->s4_disabled) {
1169 pkg = aml_package(4);
1170 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
1171 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1172 aml_append(pkg, aml_int(pm->s4_val));
1173 aml_append(pkg, aml_int(0)); /* reserved */
1174 aml_append(pkg, aml_int(0)); /* reserved */
1175 aml_append(scope, aml_name_decl("_S4", pkg));
1176 }
1177
1178 pkg = aml_package(4);
1179 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1180 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1181 aml_append(pkg, aml_int(0)); /* reserved */
1182 aml_append(pkg, aml_int(0)); /* reserved */
1183 aml_append(scope, aml_name_decl("_S5", pkg));
1184 aml_append(dsdt, scope);
1185
1186 /* create fw_cfg node, unconditionally */
1187 {
1188 scope = aml_scope("\\_SB.PCI0");
1189 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg);
1190 aml_append(dsdt, scope);
1191 }
1192
1193 sb_scope = aml_scope("\\_SB");
1194 {
1195 Object *pci_host = acpi_get_i386_pci_host();
1196
1197 if (pci_host) {
1198 PCIBus *pbus = PCI_HOST_BRIDGE(pci_host)->bus;
1199 Aml *ascope = aml_scope("PCI0");
1200 /* Scan all PCI buses. Generate tables to support hotplug. */
1201 build_append_pci_bus_devices(ascope, pbus);
1202 if (object_property_find(OBJECT(pbus), ACPI_PCIHP_PROP_BSEL)) {
1203 build_append_pcihp_slots(ascope, pbus);
1204 }
1205 aml_append(sb_scope, ascope);
1206 }
1207 }
1208
1209 #ifdef CONFIG_TPM
1210 if (TPM_IS_CRB(tpm)) {
1211 dev = aml_device("TPM");
1212 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
1213 aml_append(dev, aml_name_decl("_STR",
1214 aml_string("TPM 2.0 Device")));
1215 crs = aml_resource_template();
1216 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE,
1217 TPM_CRB_ADDR_SIZE, AML_READ_WRITE));
1218 aml_append(dev, aml_name_decl("_CRS", crs));
1219
1220 aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
1221 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1222
1223 tpm_build_ppi_acpi(tpm, dev);
1224
1225 aml_append(sb_scope, dev);
1226 }
1227 #endif
1228
1229 if (pcms->sgx_epc.size != 0) {
1230 uint64_t epc_base = pcms->sgx_epc.base;
1231 uint64_t epc_size = pcms->sgx_epc.size;
1232
1233 dev = aml_device("EPC");
1234 aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C")));
1235 aml_append(dev, aml_name_decl("_STR",
1236 aml_unicode("Enclave Page Cache 1.0")));
1237 crs = aml_resource_template();
1238 aml_append(crs,
1239 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1240 AML_MAX_FIXED, AML_NON_CACHEABLE,
1241 AML_READ_WRITE, 0, epc_base,
1242 epc_base + epc_size - 1, 0, epc_size));
1243 aml_append(dev, aml_name_decl("_CRS", crs));
1244
1245 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1246 aml_append(method, aml_return(aml_int(0x0f)));
1247 aml_append(dev, method);
1248
1249 aml_append(sb_scope, dev);
1250 }
1251 aml_append(dsdt, sb_scope);
1252
1253 if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
1254 bool has_pcnt;
1255
1256 Object *pci_host = acpi_get_i386_pci_host();
1257 PCIBus *b = PCI_HOST_BRIDGE(pci_host)->bus;
1258
1259 scope = aml_scope("\\_SB.PCI0");
1260 has_pcnt = build_append_notification_callback(scope, b);
1261 if (has_pcnt) {
1262 aml_append(dsdt, scope);
1263 }
1264
1265 scope = aml_scope("_GPE");
1266 {
1267 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1268 if (has_pcnt) {
1269 aml_append(method,
1270 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1271 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1272 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1273 }
1274 aml_append(scope, method);
1275 }
1276 aml_append(dsdt, scope);
1277 }
1278
1279 /* copy AML table into ACPI tables blob and patch header there */
1280 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
1281 acpi_table_end(linker, &table);
1282 free_aml_allocator();
1283 }
1284
1285 /*
1286 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a)
1287 * 3.2.4The ACPI 2.0 HPET Description Table (HPET)
1288 */
1289 static void
build_hpet(GArray * table_data,BIOSLinker * linker,const char * oem_id,const char * oem_table_id)1290 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
1291 const char *oem_table_id)
1292 {
1293 AcpiTable table = { .sig = "HPET", .rev = 1,
1294 .oem_id = oem_id, .oem_table_id = oem_table_id };
1295
1296 acpi_table_begin(&table, table_data);
1297 /* Note timer_block_id value must be kept in sync with value advertised by
1298 * emulated hpet
1299 */
1300 /* Event Timer Block ID */
1301 build_append_int_noprefix(table_data, 0x8086a201, 4);
1302 /* BASE_ADDRESS */
1303 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE);
1304 /* HPET Number */
1305 build_append_int_noprefix(table_data, 0, 1);
1306 /* Main Counter Minimum Clock_tick in Periodic Mode */
1307 build_append_int_noprefix(table_data, 0, 2);
1308 /* Page Protection And OEM Attribute */
1309 build_append_int_noprefix(table_data, 0, 1);
1310 acpi_table_end(linker, &table);
1311 }
1312
1313 #ifdef CONFIG_TPM
1314 /*
1315 * TCPA Description Table
1316 *
1317 * Following Level 00, Rev 00.37 of specs:
1318 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification
1319 * 7.1.2 ACPI Table Layout
1320 */
1321 static void
build_tpm_tcpa(GArray * table_data,BIOSLinker * linker,GArray * tcpalog,const char * oem_id,const char * oem_table_id)1322 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog,
1323 const char *oem_id, const char *oem_table_id)
1324 {
1325 unsigned log_addr_offset;
1326 AcpiTable table = { .sig = "TCPA", .rev = 2,
1327 .oem_id = oem_id, .oem_table_id = oem_table_id };
1328
1329 acpi_table_begin(&table, table_data);
1330 /* Platform Class */
1331 build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2);
1332 /* Log Area Minimum Length (LAML) */
1333 build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4);
1334 /* Log Area Start Address (LASA) */
1335 log_addr_offset = table_data->len;
1336 build_append_int_noprefix(table_data, 0, 8);
1337
1338 /* allocate/reserve space for TPM log area */
1339 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
1340 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
1341 false /* high memory */);
1342 /* log area start address to be filled by Guest linker */
1343 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
1344 log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0);
1345
1346 acpi_table_end(linker, &table);
1347 }
1348 #endif
1349
1350 #define HOLE_640K_START (640 * KiB)
1351 #define HOLE_640K_END (1 * MiB)
1352
1353 /*
1354 * ACPI spec, Revision 3.0
1355 * 5.2.15 System Resource Affinity Table (SRAT)
1356 */
1357 static void
build_srat(GArray * table_data,BIOSLinker * linker,MachineState * machine)1358 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
1359 {
1360 int i;
1361 int numa_mem_start, slots;
1362 uint64_t mem_len, mem_base, next_base;
1363 MachineClass *mc = MACHINE_GET_CLASS(machine);
1364 X86MachineState *x86ms = X86_MACHINE(machine);
1365 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
1366 int nb_numa_nodes = machine->numa_state->num_nodes;
1367 NodeInfo *numa_info = machine->numa_state->nodes;
1368 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id,
1369 .oem_table_id = x86ms->oem_table_id };
1370
1371 acpi_table_begin(&table, table_data);
1372 build_append_int_noprefix(table_data, 1, 4); /* Reserved */
1373 build_append_int_noprefix(table_data, 0, 8); /* Reserved */
1374
1375 for (i = 0; i < apic_ids->len; i++) {
1376 int node_id = apic_ids->cpus[i].props.node_id;
1377 uint32_t apic_id = apic_ids->cpus[i].arch_id;
1378
1379 if (apic_id < 255) {
1380 /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */
1381 build_append_int_noprefix(table_data, 0, 1); /* Type */
1382 build_append_int_noprefix(table_data, 16, 1); /* Length */
1383 /* Proximity Domain [7:0] */
1384 build_append_int_noprefix(table_data, node_id, 1);
1385 build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */
1386 /* Flags, Table 5-36 */
1387 build_append_int_noprefix(table_data, 1, 4);
1388 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */
1389 /* Proximity Domain [31:8] */
1390 build_append_int_noprefix(table_data, 0, 3);
1391 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
1392 } else {
1393 /*
1394 * ACPI spec, Revision 4.0
1395 * 5.2.16.3 Processor Local x2APIC Affinity Structure
1396 */
1397 build_append_int_noprefix(table_data, 2, 1); /* Type */
1398 build_append_int_noprefix(table_data, 24, 1); /* Length */
1399 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
1400 /* Proximity Domain */
1401 build_append_int_noprefix(table_data, node_id, 4);
1402 build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */
1403 /* Flags, Table 5-39 */
1404 build_append_int_noprefix(table_data, 1 /* Enabled */, 4);
1405 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */
1406 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
1407 }
1408 }
1409
1410 /* the memory map is a bit tricky, it contains at least one hole
1411 * from 640k-1M and possibly another one from 3.5G-4G.
1412 */
1413 next_base = 0;
1414 numa_mem_start = table_data->len;
1415
1416 for (i = 1; i < nb_numa_nodes + 1; ++i) {
1417 mem_base = next_base;
1418 mem_len = numa_info[i - 1].node_mem;
1419 next_base = mem_base + mem_len;
1420
1421 /* Cut out the 640K hole */
1422 if (mem_base <= HOLE_640K_START &&
1423 next_base > HOLE_640K_START) {
1424 mem_len -= next_base - HOLE_640K_START;
1425 if (mem_len > 0) {
1426 build_srat_memory(table_data, mem_base, mem_len, i - 1,
1427 MEM_AFFINITY_ENABLED);
1428 }
1429
1430 /* Check for the rare case: 640K < RAM < 1M */
1431 if (next_base <= HOLE_640K_END) {
1432 next_base = HOLE_640K_END;
1433 continue;
1434 }
1435 mem_base = HOLE_640K_END;
1436 mem_len = next_base - HOLE_640K_END;
1437 }
1438
1439 /* Cut out the ACPI_PCI hole */
1440 if (mem_base <= x86ms->below_4g_mem_size &&
1441 next_base > x86ms->below_4g_mem_size) {
1442 mem_len -= next_base - x86ms->below_4g_mem_size;
1443 if (mem_len > 0) {
1444 build_srat_memory(table_data, mem_base, mem_len, i - 1,
1445 MEM_AFFINITY_ENABLED);
1446 }
1447 mem_base = x86ms->above_4g_mem_start;
1448 mem_len = next_base - x86ms->below_4g_mem_size;
1449 next_base = mem_base + mem_len;
1450 }
1451
1452 if (mem_len > 0) {
1453 build_srat_memory(table_data, mem_base, mem_len, i - 1,
1454 MEM_AFFINITY_ENABLED);
1455 }
1456 }
1457
1458 if (machine->nvdimms_state->is_enabled) {
1459 nvdimm_build_srat(table_data);
1460 }
1461
1462 sgx_epc_build_srat(table_data);
1463
1464 /*
1465 * TODO: this part is not in ACPI spec and current linux kernel boots fine
1466 * without these entries. But I recall there were issues the last time I
1467 * tried to remove it with some ancient guest OS, however I can't remember
1468 * what that was so keep this around for now
1469 */
1470 slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */;
1471 for (; slots < nb_numa_nodes + 2; slots++) {
1472 build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
1473 }
1474
1475 build_srat_generic_affinity_structures(table_data);
1476
1477 /*
1478 * Entry is required for Windows to enable memory hotplug in OS
1479 * and for Linux to enable SWIOTLB when booted with less than
1480 * 4G of RAM. Windows works better if the entry sets proximity
1481 * to the highest NUMA node in the machine.
1482 * Memory devices may override proximity set by this entry,
1483 * providing _PXM method if necessary.
1484 */
1485 if (machine->device_memory) {
1486 build_srat_memory(table_data, machine->device_memory->base,
1487 memory_region_size(&machine->device_memory->mr),
1488 nb_numa_nodes - 1,
1489 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
1490 }
1491
1492 acpi_table_end(linker, &table);
1493 }
1494
1495 /*
1496 * Insert DMAR scope for PCI bridges and endpoint devices
1497 */
1498 static void
insert_scope(PCIBus * bus,PCIDevice * dev,void * opaque)1499 insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque)
1500 {
1501 const size_t device_scope_size = 6 /* device scope structure */ +
1502 2 /* 1 path entry */;
1503 GArray *scope_blob = opaque;
1504
1505 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
1506 /* Dmar Scope Type: 0x02 for PCI Bridge */
1507 build_append_int_noprefix(scope_blob, 0x02, 1);
1508 } else {
1509 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */
1510 build_append_int_noprefix(scope_blob, 0x01, 1);
1511 }
1512
1513 /* length */
1514 build_append_int_noprefix(scope_blob, device_scope_size, 1);
1515 /* reserved */
1516 build_append_int_noprefix(scope_blob, 0, 2);
1517 /* enumeration_id */
1518 build_append_int_noprefix(scope_blob, 0, 1);
1519 /* bus */
1520 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1);
1521 /* device */
1522 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1);
1523 /* function */
1524 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1);
1525 }
1526
1527 /* For a given PCI host bridge, walk and insert DMAR scope */
1528 static int
dmar_host_bridges(Object * obj,void * opaque)1529 dmar_host_bridges(Object *obj, void *opaque)
1530 {
1531 GArray *scope_blob = opaque;
1532
1533 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
1534 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
1535
1536 if (bus && !pci_bus_bypass_iommu(bus)) {
1537 pci_for_each_device_under_bus(bus, insert_scope, scope_blob);
1538 }
1539 }
1540
1541 return 0;
1542 }
1543
1544 /*
1545 * Intel ® Virtualization Technology for Directed I/O
1546 * Architecture Specification. Revision 3.3
1547 * 8.1 DMA Remapping Reporting Structure
1548 */
1549 static void
build_dmar_q35(GArray * table_data,BIOSLinker * linker,const char * oem_id,const char * oem_table_id)1550 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id,
1551 const char *oem_table_id)
1552 {
1553 uint8_t dmar_flags = 0;
1554 uint8_t rsvd10[10] = {};
1555 /* Root complex IOAPIC uses one path only */
1556 const size_t ioapic_scope_size = 6 /* device scope structure */ +
1557 2 /* 1 path entry */;
1558 X86IOMMUState *iommu = x86_iommu_get_default();
1559 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1560 GArray *scope_blob = g_array_new(false, true, 1);
1561
1562 AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id,
1563 .oem_table_id = oem_table_id };
1564
1565 /*
1566 * A PCI bus walk, for each PCI host bridge.
1567 * Insert scope for each PCI bridge and endpoint device which
1568 * is attached to a bus with iommu enabled.
1569 */
1570 object_child_foreach_recursive(object_get_root(),
1571 dmar_host_bridges, scope_blob);
1572
1573 assert(iommu);
1574 if (x86_iommu_ir_supported(iommu)) {
1575 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
1576 }
1577
1578 acpi_table_begin(&table, table_data);
1579 /* Host Address Width */
1580 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1);
1581 build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */
1582 g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */
1583
1584 /* 8.3 DMAR Remapping Hardware Unit Definition structure */
1585 build_append_int_noprefix(table_data, 0, 2); /* Type */
1586 /* Length */
1587 build_append_int_noprefix(table_data,
1588 16 + ioapic_scope_size + scope_blob->len, 2);
1589 /* Flags */
1590 build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ ,
1591 1);
1592 build_append_int_noprefix(table_data, 0 , 1); /* Reserved */
1593 build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */
1594 /* Register Base Address */
1595 build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8);
1596
1597 /* Scope definition for the root-complex IOAPIC. See VT-d spec
1598 * 8.3.1 (version Oct. 2014 or later). */
1599 build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */
1600 build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */
1601 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
1602 /* Enumeration ID */
1603 build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1);
1604 /* Start Bus Number */
1605 build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1);
1606 /* Path, {Device, Function} pair */
1607 build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1);
1608 build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1);
1609
1610 /* Add scope found above */
1611 g_array_append_vals(table_data, scope_blob->data, scope_blob->len);
1612 g_array_free(scope_blob, true);
1613
1614 if (iommu->dt_supported) {
1615 /* 8.5 Root Port ATS Capability Reporting Structure */
1616 build_append_int_noprefix(table_data, 2, 2); /* Type */
1617 build_append_int_noprefix(table_data, 8, 2); /* Length */
1618 build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */
1619 build_append_int_noprefix(table_data, 0, 1); /* Reserved */
1620 build_append_int_noprefix(table_data, 0, 2); /* Segment Number */
1621 }
1622
1623 acpi_table_end(linker, &table);
1624 }
1625
1626 /*
1627 * Windows ACPI Emulated Devices Table
1628 * (Version 1.0 - April 6, 2009)
1629 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx
1630 *
1631 * Helpful to speedup Windows guests and ignored by others.
1632 */
1633 static void
build_waet(GArray * table_data,BIOSLinker * linker,const char * oem_id,const char * oem_table_id)1634 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
1635 const char *oem_table_id)
1636 {
1637 AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id,
1638 .oem_table_id = oem_table_id };
1639
1640 acpi_table_begin(&table, table_data);
1641 /*
1642 * Set "ACPI PM timer good" flag.
1643 *
1644 * Tells Windows guests that our ACPI PM timer is reliable in the
1645 * sense that guest can read it only once to obtain a reliable value.
1646 * Which avoids costly VMExits caused by guest re-reading it unnecessarily.
1647 */
1648 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4);
1649 acpi_table_end(linker, &table);
1650 }
1651
1652 /*
1653 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
1654 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
1655 */
1656 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
1657
1658 /*
1659 * Insert IVHD entry for device and recurse, insert alias, or insert range as
1660 * necessary for the PCI topology.
1661 */
1662 static void
insert_ivhd(PCIBus * bus,PCIDevice * dev,void * opaque)1663 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque)
1664 {
1665 GArray *table_data = opaque;
1666 uint32_t entry;
1667
1668 /* "Select" IVHD entry, type 0x2 */
1669 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2;
1670 build_append_int_noprefix(table_data, entry, 4);
1671
1672 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
1673 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
1674 uint8_t sec = pci_bus_num(sec_bus);
1675 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS];
1676
1677 if (pci_bus_is_express(sec_bus)) {
1678 /*
1679 * Walk the bus if there are subordinates, otherwise use a range
1680 * to cover an entire leaf bus. We could potentially also use a
1681 * range for traversed buses, but we'd need to take care not to
1682 * create both Select and Range entries covering the same device.
1683 * This is easier and potentially more compact.
1684 *
1685 * An example bare metal system seems to use Select entries for
1686 * root ports without a slot (ie. built-ins) and Range entries
1687 * when there is a slot. The same system also only hard-codes
1688 * the alias range for an onboard PCIe-to-PCI bridge, apparently
1689 * making no effort to support nested bridges. We attempt to
1690 * be more thorough here.
1691 */
1692 if (sec == sub) { /* leaf bus */
1693 /* "Start of Range" IVHD entry, type 0x3 */
1694 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3;
1695 build_append_int_noprefix(table_data, entry, 4);
1696 /* "End of Range" IVHD entry, type 0x4 */
1697 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
1698 build_append_int_noprefix(table_data, entry, 4);
1699 } else {
1700 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data);
1701 }
1702 } else {
1703 /*
1704 * If the secondary bus is conventional, then we need to create an
1705 * Alias range for everything downstream. The range covers the
1706 * first devfn on the secondary bus to the last devfn on the
1707 * subordinate bus. The alias target depends on legacy versus
1708 * express bridges, just as in pci_device_iommu_address_space().
1709 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec.
1710 */
1711 uint16_t dev_id_a, dev_id_b;
1712
1713 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0));
1714
1715 if (pci_is_express(dev) &&
1716 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) {
1717 dev_id_b = dev_id_a;
1718 } else {
1719 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn);
1720 }
1721
1722 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */
1723 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4);
1724 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4);
1725
1726 /* "End of Range" IVHD entry, type 0x4 */
1727 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
1728 build_append_int_noprefix(table_data, entry, 4);
1729 }
1730 }
1731 }
1732
1733 /* For all PCI host bridges, walk and insert IVHD entries */
1734 static int
ivrs_host_bridges(Object * obj,void * opaque)1735 ivrs_host_bridges(Object *obj, void *opaque)
1736 {
1737 GArray *ivhd_blob = opaque;
1738
1739 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
1740 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
1741
1742 if (bus && !pci_bus_bypass_iommu(bus)) {
1743 pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob);
1744 }
1745 }
1746
1747 return 0;
1748 }
1749
1750 static void
build_amd_iommu(GArray * table_data,BIOSLinker * linker,const char * oem_id,const char * oem_table_id)1751 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id,
1752 const char *oem_table_id)
1753 {
1754 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
1755 GArray *ivhd_blob = g_array_new(false, true, 1);
1756 AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id,
1757 .oem_table_id = oem_table_id };
1758 uint64_t feature_report;
1759
1760 acpi_table_begin(&table, table_data);
1761 /* IVinfo - IO virtualization information common to all
1762 * IOMMU units in a system
1763 */
1764 build_append_int_noprefix(table_data,
1765 (1UL << 0) | /* EFRSup */
1766 (40UL << 8), /* PASize */
1767 4);
1768 /* reserved */
1769 build_append_int_noprefix(table_data, 0, 8);
1770
1771 /*
1772 * A PCI bus walk, for each PCI host bridge, is necessary to create a
1773 * complete set of IVHD entries. Do this into a separate blob so that we
1774 * can calculate the total IVRS table length here and then append the new
1775 * blob further below. Fall back to an entry covering all devices, which
1776 * is sufficient when no aliases are present.
1777 */
1778 object_child_foreach_recursive(object_get_root(),
1779 ivrs_host_bridges, ivhd_blob);
1780
1781 if (!ivhd_blob->len) {
1782 /*
1783 * Type 1 device entry reporting all devices
1784 * These are 4-byte device entries currently reporting the range of
1785 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
1786 */
1787 build_append_int_noprefix(ivhd_blob, 0x0000001, 4);
1788 }
1789
1790 /*
1791 * When interrupt remapping is supported, we add a special IVHD device
1792 * for type IO-APIC
1793 * Refer to spec - Table 95: IVHD device entry type codes
1794 *
1795 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
1796 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
1797 */
1798 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
1799 build_append_int_noprefix(ivhd_blob,
1800 (0x1ull << 56) | /* type IOAPIC */
1801 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */
1802 0x48, /* special device */
1803 8);
1804 }
1805
1806 /* IVHD definition - type 10h */
1807 build_append_int_noprefix(table_data, 0x10, 1);
1808 /* virtualization flags */
1809 build_append_int_noprefix(table_data,
1810 (1UL << 0) | /* HtTunEn */
1811 (1UL << 4) | /* iotblSup */
1812 (1UL << 6) | /* PrefSup */
1813 (1UL << 7), /* PPRSup */
1814 1);
1815
1816 /* IVHD length */
1817 build_append_int_noprefix(table_data, ivhd_blob->len + 24, 2);
1818 /* DeviceID */
1819 build_append_int_noprefix(table_data,
1820 object_property_get_int(OBJECT(s->pci), "addr",
1821 &error_abort), 2);
1822 /* Capability offset */
1823 build_append_int_noprefix(table_data, s->pci->capab_offset, 2);
1824 /* IOMMU base address */
1825 build_append_int_noprefix(table_data, s->mr_mmio.addr, 8);
1826 /* PCI Segment Group */
1827 build_append_int_noprefix(table_data, 0, 2);
1828 /* IOMMU info */
1829 build_append_int_noprefix(table_data, 0, 2);
1830 /* IOMMU Feature Reporting */
1831 feature_report = (48UL << 30) | /* HATS */
1832 (48UL << 28) | /* GATS */
1833 (1UL << 2) | /* GTSup */
1834 (1UL << 6); /* GASup */
1835 if (s->xtsup) {
1836 feature_report |= (1UL << 0); /* XTSup */
1837 }
1838 build_append_int_noprefix(table_data, feature_report, 4);
1839
1840 /* IVHD entries as found above */
1841 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
1842
1843 /* IVHD definition - type 11h */
1844 build_append_int_noprefix(table_data, 0x11, 1);
1845 /* virtualization flags */
1846 build_append_int_noprefix(table_data,
1847 (1UL << 0) | /* HtTunEn */
1848 (1UL << 4), /* iotblSup */
1849 1);
1850
1851 /* IVHD length */
1852 build_append_int_noprefix(table_data, ivhd_blob->len + 40, 2);
1853 /* DeviceID */
1854 build_append_int_noprefix(table_data,
1855 object_property_get_int(OBJECT(s->pci), "addr",
1856 &error_abort), 2);
1857 /* Capability offset */
1858 build_append_int_noprefix(table_data, s->pci->capab_offset, 2);
1859 /* IOMMU base address */
1860 build_append_int_noprefix(table_data, s->mr_mmio.addr, 8);
1861 /* PCI Segment Group */
1862 build_append_int_noprefix(table_data, 0, 2);
1863 /* IOMMU info */
1864 build_append_int_noprefix(table_data, 0, 2);
1865 /* IOMMU Attributes */
1866 build_append_int_noprefix(table_data, 0, 4);
1867 /* EFR Register Image */
1868 build_append_int_noprefix(table_data,
1869 amdvi_extended_feature_register(s),
1870 8);
1871 /* EFR Register Image 2 */
1872 build_append_int_noprefix(table_data, 0, 8);
1873
1874 /* IVHD entries as found above */
1875 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
1876
1877 g_array_free(ivhd_blob, TRUE);
1878 acpi_table_end(linker, &table);
1879 }
1880
1881 typedef
1882 struct AcpiBuildState {
1883 /* Copy of table in RAM (for patching). */
1884 MemoryRegion *table_mr;
1885 /* Is table patched? */
1886 uint8_t patched;
1887 MemoryRegion *rsdp_mr;
1888 MemoryRegion *linker_mr;
1889 } AcpiBuildState;
1890
acpi_get_mcfg(AcpiMcfgInfo * mcfg)1891 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
1892 {
1893 Object *pci_host;
1894 QObject *o;
1895
1896 pci_host = acpi_get_i386_pci_host();
1897 if (!pci_host) {
1898 return false;
1899 }
1900
1901 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
1902 if (!o) {
1903 return false;
1904 }
1905 mcfg->base = qnum_get_uint(qobject_to(QNum, o));
1906 qobject_unref(o);
1907 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) {
1908 return false;
1909 }
1910
1911 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
1912 assert(o);
1913 mcfg->size = qnum_get_uint(qobject_to(QNum, o));
1914 qobject_unref(o);
1915 return true;
1916 }
1917
1918 static
acpi_build(AcpiBuildTables * tables,MachineState * machine)1919 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
1920 {
1921 PCMachineState *pcms = PC_MACHINE(machine);
1922 X86MachineState *x86ms = X86_MACHINE(machine);
1923 DeviceState *iommu = pcms->iommu;
1924 GArray *table_offsets;
1925 unsigned facs, dsdt, rsdt;
1926 AcpiPmInfo pm;
1927 AcpiMiscInfo misc;
1928 AcpiMcfgInfo mcfg;
1929 Range pci_hole = {}, pci_hole64 = {};
1930 uint8_t *u;
1931 GArray *tables_blob = tables->table_data;
1932 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
1933 Object *vmgenid_dev, *vmclock_dev;
1934 char *oem_id;
1935 char *oem_table_id;
1936
1937 acpi_get_pm_info(machine, &pm);
1938 acpi_get_misc_info(&misc);
1939 acpi_get_pci_holes(&pci_hole, &pci_hole64);
1940 acpi_get_slic_oem(&slic_oem);
1941
1942 if (slic_oem.id) {
1943 oem_id = slic_oem.id;
1944 } else {
1945 oem_id = x86ms->oem_id;
1946 }
1947
1948 if (slic_oem.table_id) {
1949 oem_table_id = slic_oem.table_id;
1950 } else {
1951 oem_table_id = x86ms->oem_table_id;
1952 }
1953
1954 table_offsets = g_array_new(false, true /* clear */,
1955 sizeof(uint32_t));
1956 ACPI_BUILD_DPRINTF("init ACPI tables\n");
1957
1958 bios_linker_loader_alloc(tables->linker,
1959 ACPI_BUILD_TABLE_FILE, tables_blob,
1960 64 /* Ensure FACS is aligned */,
1961 false /* high memory */);
1962
1963 /*
1964 * FACS is pointed to by FADT.
1965 * We place it first since it's the only table that has alignment
1966 * requirements.
1967 */
1968 facs = tables_blob->len;
1969 build_facs(tables_blob);
1970
1971 /* DSDT is pointed to by FADT */
1972 dsdt = tables_blob->len;
1973 build_dsdt(tables_blob, tables->linker, &pm, &misc,
1974 &pci_hole, &pci_hole64, machine);
1975
1976 /* ACPI tables pointed to by RSDT */
1977 acpi_add_table(table_offsets, tables_blob);
1978 pm.fadt.facs_tbl_offset = &facs;
1979 pm.fadt.dsdt_tbl_offset = &dsdt;
1980 pm.fadt.xdsdt_tbl_offset = &dsdt;
1981 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id);
1982
1983 acpi_add_table(table_offsets, tables_blob);
1984 acpi_build_madt(tables_blob, tables->linker, x86ms,
1985 x86ms->oem_id, x86ms->oem_table_id);
1986
1987 #ifdef CONFIG_ACPI_ERST
1988 {
1989 Object *erst_dev;
1990 erst_dev = find_erst_dev();
1991 if (erst_dev) {
1992 acpi_add_table(table_offsets, tables_blob);
1993 build_erst(tables_blob, tables->linker, erst_dev,
1994 x86ms->oem_id, x86ms->oem_table_id);
1995 }
1996 }
1997 #endif
1998
1999 vmgenid_dev = find_vmgenid_dev();
2000 if (vmgenid_dev) {
2001 acpi_add_table(table_offsets, tables_blob);
2002 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
2003 tables->vmgenid, tables->linker, x86ms->oem_id);
2004 }
2005
2006 vmclock_dev = find_vmclock_dev();
2007 if (vmclock_dev) {
2008 acpi_add_table(table_offsets, tables_blob);
2009 vmclock_build_acpi(VMCLOCK(vmclock_dev), tables_blob, tables->linker,
2010 x86ms->oem_id);
2011 }
2012
2013 if (misc.has_hpet) {
2014 acpi_add_table(table_offsets, tables_blob);
2015 build_hpet(tables_blob, tables->linker, x86ms->oem_id,
2016 x86ms->oem_table_id);
2017 }
2018 #ifdef CONFIG_TPM
2019 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2020 if (misc.tpm_version == TPM_VERSION_1_2) {
2021 acpi_add_table(table_offsets, tables_blob);
2022 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog,
2023 x86ms->oem_id, x86ms->oem_table_id);
2024 } else { /* TPM_VERSION_2_0 */
2025 acpi_add_table(table_offsets, tables_blob);
2026 build_tpm2(tables_blob, tables->linker, tables->tcpalog,
2027 x86ms->oem_id, x86ms->oem_table_id);
2028 }
2029 }
2030 #endif
2031 if (machine->numa_state->num_nodes) {
2032 acpi_add_table(table_offsets, tables_blob);
2033 build_srat(tables_blob, tables->linker, machine);
2034 if (machine->numa_state->have_numa_distance) {
2035 acpi_add_table(table_offsets, tables_blob);
2036 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id,
2037 x86ms->oem_table_id);
2038 }
2039 if (machine->numa_state->hmat_enabled) {
2040 acpi_add_table(table_offsets, tables_blob);
2041 build_hmat(tables_blob, tables->linker, machine->numa_state,
2042 x86ms->oem_id, x86ms->oem_table_id);
2043 }
2044 }
2045 if (acpi_get_mcfg(&mcfg)) {
2046 acpi_add_table(table_offsets, tables_blob);
2047 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id,
2048 x86ms->oem_table_id);
2049 }
2050 if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) {
2051 acpi_add_table(table_offsets, tables_blob);
2052 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id,
2053 x86ms->oem_table_id);
2054 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) {
2055 acpi_add_table(table_offsets, tables_blob);
2056 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id,
2057 x86ms->oem_table_id);
2058 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) {
2059 PCIDevice *pdev = PCI_DEVICE(iommu);
2060
2061 acpi_add_table(table_offsets, tables_blob);
2062 build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev),
2063 x86ms->oem_id, x86ms->oem_table_id);
2064 }
2065 if (machine->nvdimms_state->is_enabled) {
2066 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2067 machine->nvdimms_state, machine->ram_slots,
2068 x86ms->oem_id, x86ms->oem_table_id);
2069 }
2070 if (pcms->cxl_devices_state.is_enabled) {
2071 cxl_build_cedt(table_offsets, tables_blob, tables->linker,
2072 x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state);
2073 }
2074
2075 acpi_add_table(table_offsets, tables_blob);
2076 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id);
2077
2078 /* Add tables supplied by user (if any) */
2079 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2080 unsigned len = acpi_table_len(u);
2081
2082 acpi_add_table(table_offsets, tables_blob);
2083 g_array_append_vals(tables_blob, u, len);
2084 }
2085
2086 /* RSDT is pointed to by RSDP */
2087 rsdt = tables_blob->len;
2088 build_rsdt(tables_blob, tables->linker, table_offsets,
2089 oem_id, oem_table_id);
2090
2091 /* RSDP is in FSEG memory, so allocate it separately */
2092 {
2093 AcpiRsdpData rsdp_data = {
2094 .revision = 0,
2095 .oem_id = x86ms->oem_id,
2096 .xsdt_tbl_offset = NULL,
2097 .rsdt_tbl_offset = &rsdt,
2098 };
2099 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
2100 }
2101
2102 /* We'll expose it all to Guest so we want to reduce
2103 * chance of size changes.
2104 *
2105 * We used to align the tables to 4k, but of course this would
2106 * too simple to be enough. 4k turned out to be too small an
2107 * alignment very soon, and in fact it is almost impossible to
2108 * keep the table size stable for all (max_cpus, max_memory_slots)
2109 * combinations.
2110 */
2111 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2112
2113 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2114
2115 /* Cleanup memory that's no longer used. */
2116 g_array_free(table_offsets, true);
2117 g_free(slic_oem.id);
2118 g_free(slic_oem.table_id);
2119 }
2120
acpi_ram_update(MemoryRegion * mr,GArray * data)2121 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2122 {
2123 uint32_t size = acpi_data_len(data);
2124
2125 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2126 memory_region_ram_resize(mr, size, &error_abort);
2127
2128 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2129 memory_region_set_dirty(mr, 0, size);
2130 }
2131
acpi_build_update(void * build_opaque)2132 static void acpi_build_update(void *build_opaque)
2133 {
2134 AcpiBuildState *build_state = build_opaque;
2135 AcpiBuildTables tables;
2136
2137 /* No state to update or already patched? Nothing to do. */
2138 if (!build_state || build_state->patched) {
2139 return;
2140 }
2141 build_state->patched = 1;
2142
2143 acpi_build_tables_init(&tables);
2144
2145 acpi_build(&tables, MACHINE(qdev_get_machine()));
2146
2147 acpi_ram_update(build_state->table_mr, tables.table_data);
2148
2149 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2150
2151 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2152 acpi_build_tables_cleanup(&tables, true);
2153 }
2154
acpi_build_reset(void * build_opaque)2155 static void acpi_build_reset(void *build_opaque)
2156 {
2157 AcpiBuildState *build_state = build_opaque;
2158 build_state->patched = 0;
2159 }
2160
2161 static const VMStateDescription vmstate_acpi_build = {
2162 .name = "acpi_build",
2163 .version_id = 1,
2164 .minimum_version_id = 1,
2165 .fields = (const VMStateField[]) {
2166 VMSTATE_UINT8(patched, AcpiBuildState),
2167 VMSTATE_END_OF_LIST()
2168 },
2169 };
2170
acpi_setup(void)2171 void acpi_setup(void)
2172 {
2173 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2174 X86MachineState *x86ms = X86_MACHINE(pcms);
2175 AcpiBuildTables tables;
2176 AcpiBuildState *build_state;
2177 Object *vmgenid_dev;
2178 #ifdef CONFIG_TPM
2179 TPMIf *tpm;
2180 static FwCfgTPMConfig tpm_config;
2181 #endif
2182
2183 if (!x86ms->fw_cfg) {
2184 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2185 return;
2186 }
2187
2188 if (!pcms->acpi_build_enabled) {
2189 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2190 return;
2191 }
2192
2193 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
2194 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2195 return;
2196 }
2197
2198 build_state = g_malloc0(sizeof *build_state);
2199
2200 acpi_build_tables_init(&tables);
2201 acpi_build(&tables, MACHINE(pcms));
2202
2203 /* Now expose it all to Guest */
2204 build_state->table_mr = acpi_add_rom_blob(acpi_build_update,
2205 build_state, tables.table_data,
2206 ACPI_BUILD_TABLE_FILE);
2207 assert(build_state->table_mr != NULL);
2208
2209 build_state->linker_mr =
2210 acpi_add_rom_blob(acpi_build_update, build_state,
2211 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE);
2212
2213 #ifdef CONFIG_TPM
2214 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2215 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2216
2217 tpm = tpm_find();
2218 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) {
2219 tpm_config = (FwCfgTPMConfig) {
2220 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE),
2221 .tpm_version = tpm_get_version(tpm),
2222 .tpmppi_version = TPM_PPI_VERSION_1_30
2223 };
2224 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config",
2225 &tpm_config, sizeof tpm_config);
2226 }
2227 #endif
2228
2229 vmgenid_dev = find_vmgenid_dev();
2230 if (vmgenid_dev) {
2231 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg,
2232 tables.vmgenid);
2233 }
2234
2235 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update,
2236 build_state, tables.rsdp,
2237 ACPI_BUILD_RSDP_FILE);
2238
2239 qemu_register_reset(acpi_build_reset, build_state);
2240 acpi_build_reset(build_state);
2241 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2242
2243 /* Cleanup tables but don't free the memory: we track it
2244 * in build_state.
2245 */
2246 acpi_build_tables_cleanup(&tables, false);
2247 }
2248