1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
5 //
6 // Copyright(c) 2021 Advanced Micro Devices, Inc.
7 //
8 // Authors: Balakishore Pati <Balakishore.pati@amd.com>
9 // Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
10
11 /* ACP-specific SOF IPC code */
12
13 #include <linux/module.h>
14 #include "../ops.h"
15 #include "acp.h"
16 #include "acp-dsp-offset.h"
17
acp_mailbox_write(struct snd_sof_dev * sdev,u32 offset,void * message,size_t bytes)18 void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes)
19 {
20 memcpy_to_scratch(sdev, offset, message, bytes);
21 }
22 EXPORT_SYMBOL_NS(acp_mailbox_write, SND_SOC_SOF_AMD_COMMON);
23
acp_mailbox_read(struct snd_sof_dev * sdev,u32 offset,void * message,size_t bytes)24 void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes)
25 {
26 memcpy_from_scratch(sdev, offset, message, bytes);
27 }
28 EXPORT_SYMBOL_NS(acp_mailbox_read, SND_SOC_SOF_AMD_COMMON);
29
acpbus_trigger_host_to_dsp_swintr(struct acp_dev_data * adata)30 static void acpbus_trigger_host_to_dsp_swintr(struct acp_dev_data *adata)
31 {
32 struct snd_sof_dev *sdev = adata->dev;
33 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
34 u32 swintr_trigger;
35
36 swintr_trigger = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->dsp_intr_base +
37 DSP_SW_INTR_TRIG_OFFSET);
38 swintr_trigger |= 0x01;
39 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->dsp_intr_base + DSP_SW_INTR_TRIG_OFFSET,
40 swintr_trigger);
41 }
42
acp_ipc_host_msg_set(struct snd_sof_dev * sdev)43 static void acp_ipc_host_msg_set(struct snd_sof_dev *sdev)
44 {
45 unsigned int host_msg = sdev->debug_box.offset +
46 offsetof(struct scratch_ipc_conf, sof_host_msg_write);
47
48 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + host_msg, 1);
49 }
50
acp_dsp_ipc_host_done(struct snd_sof_dev * sdev)51 static void acp_dsp_ipc_host_done(struct snd_sof_dev *sdev)
52 {
53 unsigned int dsp_msg = sdev->debug_box.offset +
54 offsetof(struct scratch_ipc_conf, sof_dsp_msg_write);
55
56 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_msg, 0);
57 }
58
acp_dsp_ipc_dsp_done(struct snd_sof_dev * sdev)59 static void acp_dsp_ipc_dsp_done(struct snd_sof_dev *sdev)
60 {
61 unsigned int dsp_ack = sdev->debug_box.offset +
62 offsetof(struct scratch_ipc_conf, sof_dsp_ack_write);
63
64 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_ack, 0);
65 }
66
acp_sof_ipc_send_msg(struct snd_sof_dev * sdev,struct snd_sof_ipc_msg * msg)67 int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
68 {
69 struct acp_dev_data *adata = sdev->pdata->hw_pdata;
70 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
71 unsigned int offset = sdev->host_box.offset;
72 unsigned int count = ACP_HW_SEM_RETRY_COUNT;
73
74 while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset)) {
75 /* Wait until acquired HW Semaphore Lock or timeout*/
76 count--;
77 if (!count) {
78 dev_err(sdev->dev, "%s: Failed to acquire HW lock\n", __func__);
79 return -EINVAL;
80 }
81 }
82
83 acp_mailbox_write(sdev, offset, msg->msg_data, msg->msg_size);
84 acp_ipc_host_msg_set(sdev);
85
86 /* Trigger host to dsp interrupt for the msg */
87 acpbus_trigger_host_to_dsp_swintr(adata);
88
89 /* Unlock or Release HW Semaphore */
90 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset, 0x0);
91
92 return 0;
93 }
94 EXPORT_SYMBOL_NS(acp_sof_ipc_send_msg, SND_SOC_SOF_AMD_COMMON);
95
acp_dsp_ipc_get_reply(struct snd_sof_dev * sdev)96 static void acp_dsp_ipc_get_reply(struct snd_sof_dev *sdev)
97 {
98 struct snd_sof_ipc_msg *msg = sdev->msg;
99 struct sof_ipc_reply reply;
100 struct sof_ipc_cmd_hdr *hdr;
101 unsigned int offset = sdev->host_box.offset;
102 int ret = 0;
103
104 /*
105 * Sometimes, there is unexpected reply ipc arriving. The reply
106 * ipc belongs to none of the ipcs sent from driver.
107 * In this case, the driver must ignore the ipc.
108 */
109 if (!msg) {
110 dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n");
111 return;
112 }
113 hdr = msg->msg_data;
114 if (hdr->cmd == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CTX_SAVE) ||
115 hdr->cmd == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE)) {
116 /*
117 * memory windows are powered off before sending IPC reply,
118 * so we can't read the mailbox for CTX_SAVE and PM_GATE
119 * replies.
120 */
121 reply.error = 0;
122 reply.hdr.cmd = SOF_IPC_GLB_REPLY;
123 reply.hdr.size = sizeof(reply);
124 memcpy(msg->reply_data, &reply, sizeof(reply));
125 goto out;
126 }
127 /* get IPC reply from DSP in the mailbox */
128 acp_mailbox_read(sdev, offset, &reply, sizeof(reply));
129 if (reply.error < 0) {
130 memcpy(msg->reply_data, &reply, sizeof(reply));
131 ret = reply.error;
132 } else {
133 /*
134 * To support an IPC tx_message with a
135 * reply_size set to zero.
136 */
137 if (!msg->reply_size)
138 goto out;
139
140 /* reply correct size ? */
141 if (reply.hdr.size != msg->reply_size &&
142 !(reply.hdr.cmd & SOF_IPC_GLB_PROBE)) {
143 dev_err(sdev->dev, "reply expected %zu got %u bytes\n",
144 msg->reply_size, reply.hdr.size);
145 ret = -EINVAL;
146 }
147 /* read the message */
148 if (msg->reply_size > 0)
149 acp_mailbox_read(sdev, offset, msg->reply_data, msg->reply_size);
150 }
151 out:
152 msg->reply_error = ret;
153 }
154
acp_sof_ipc_irq_thread(int irq,void * context)155 irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context)
156 {
157 struct snd_sof_dev *sdev = context;
158 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
159 struct acp_dev_data *adata = sdev->pdata->hw_pdata;
160 unsigned int dsp_msg_write = sdev->debug_box.offset +
161 offsetof(struct scratch_ipc_conf, sof_dsp_msg_write);
162 unsigned int dsp_ack_write = sdev->debug_box.offset +
163 offsetof(struct scratch_ipc_conf, sof_dsp_ack_write);
164 bool ipc_irq = false;
165 int dsp_msg, dsp_ack;
166 unsigned int status;
167
168 if (sdev->first_boot && sdev->fw_state != SOF_FW_BOOT_COMPLETE) {
169 acp_mailbox_read(sdev, sdev->dsp_box.offset, &status, sizeof(status));
170 if ((status & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
171 snd_sof_dsp_panic(sdev, sdev->dsp_box.offset + sizeof(status),
172 true);
173 status = 0;
174 acp_mailbox_write(sdev, sdev->dsp_box.offset, &status, sizeof(status));
175 return IRQ_HANDLED;
176 }
177 snd_sof_ipc_msgs_rx(sdev);
178 acp_dsp_ipc_host_done(sdev);
179 return IRQ_HANDLED;
180 }
181
182 dsp_msg = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_msg_write);
183 if (dsp_msg) {
184 snd_sof_ipc_msgs_rx(sdev);
185 acp_dsp_ipc_host_done(sdev);
186 ipc_irq = true;
187 }
188
189 dsp_ack = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_ack_write);
190 if (dsp_ack) {
191 spin_lock_irq(&sdev->ipc_lock);
192 /* handle immediate reply from DSP core */
193 acp_dsp_ipc_get_reply(sdev);
194 snd_sof_ipc_reply(sdev, 0);
195 /* set the done bit */
196 acp_dsp_ipc_dsp_done(sdev);
197 spin_unlock_irq(&sdev->ipc_lock);
198 ipc_irq = true;
199 }
200
201 acp_mailbox_read(sdev, sdev->debug_box.offset, &status, sizeof(u32));
202 if ((status & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
203 snd_sof_dsp_panic(sdev, sdev->dsp_oops_offset, true);
204 status = 0;
205 acp_mailbox_write(sdev, sdev->debug_box.offset, &status, sizeof(status));
206 return IRQ_HANDLED;
207 }
208
209 if (desc->probe_reg_offset) {
210 u32 val;
211 u32 posn;
212
213 /* Probe register consists of two parts
214 * (0-30) bit has cumulative position value
215 * 31 bit is a synchronization flag between DSP and CPU
216 * for the position update
217 */
218 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->probe_reg_offset);
219 if (val & PROBE_STATUS_BIT) {
220 posn = val & ~PROBE_STATUS_BIT;
221 if (adata->probe_stream) {
222 /* Probe related posn value is of 31 bits limited to 2GB
223 * once wrapped DSP won't send posn interrupt.
224 */
225 adata->probe_stream->cstream_posn = posn;
226 snd_compr_fragment_elapsed(adata->probe_stream->cstream);
227 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->probe_reg_offset, posn);
228 ipc_irq = true;
229 }
230 }
231 }
232
233 if (!ipc_irq)
234 dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n");
235
236 return IRQ_HANDLED;
237 }
238 EXPORT_SYMBOL_NS(acp_sof_ipc_irq_thread, SND_SOC_SOF_AMD_COMMON);
239
acp_sof_ipc_msg_data(struct snd_sof_dev * sdev,struct snd_sof_pcm_stream * sps,void * p,size_t sz)240 int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_sof_pcm_stream *sps,
241 void *p, size_t sz)
242 {
243 unsigned int offset = sdev->dsp_box.offset;
244
245 if (!sps || !sdev->stream_box.size) {
246 acp_mailbox_read(sdev, offset, p, sz);
247 } else {
248 struct snd_pcm_substream *substream = sps->substream;
249 struct acp_dsp_stream *stream;
250
251 if (!substream || !substream->runtime)
252 return -ESTRPIPE;
253
254 stream = substream->runtime->private_data;
255
256 if (!stream)
257 return -ESTRPIPE;
258
259 acp_mailbox_read(sdev, stream->posn_offset, p, sz);
260 }
261
262 return 0;
263 }
264 EXPORT_SYMBOL_NS(acp_sof_ipc_msg_data, SND_SOC_SOF_AMD_COMMON);
265
acp_set_stream_data_offset(struct snd_sof_dev * sdev,struct snd_sof_pcm_stream * sps,size_t posn_offset)266 int acp_set_stream_data_offset(struct snd_sof_dev *sdev,
267 struct snd_sof_pcm_stream *sps,
268 size_t posn_offset)
269 {
270 struct snd_pcm_substream *substream = sps->substream;
271 struct acp_dsp_stream *stream = substream->runtime->private_data;
272
273 /* check for unaligned offset or overflow */
274 if (posn_offset > sdev->stream_box.size ||
275 posn_offset % sizeof(struct sof_ipc_stream_posn) != 0)
276 return -EINVAL;
277
278 stream->posn_offset = sdev->stream_box.offset + posn_offset;
279
280 dev_dbg(sdev->dev, "pcm: stream dir %d, posn mailbox offset is %zu",
281 substream->stream, stream->posn_offset);
282
283 return 0;
284 }
285 EXPORT_SYMBOL_NS(acp_set_stream_data_offset, SND_SOC_SOF_AMD_COMMON);
286
acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev * sdev)287 int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev)
288 {
289 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
290
291 return desc->sram_pte_offset;
292 }
293 EXPORT_SYMBOL_NS(acp_sof_ipc_get_mailbox_offset, SND_SOC_SOF_AMD_COMMON);
294
acp_sof_ipc_get_window_offset(struct snd_sof_dev * sdev,u32 id)295 int acp_sof_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id)
296 {
297 return 0;
298 }
299 EXPORT_SYMBOL_NS(acp_sof_ipc_get_window_offset, SND_SOC_SOF_AMD_COMMON);
300
301 MODULE_DESCRIPTION("AMD ACP sof-ipc driver");
302