1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 Huawei Ltd.
4 * Author: Jiang Liu <liuj97@gmail.com>
5 *
6 * Copyright (C) 2014-2016 Zi Shen Lim <zlim.lnx@gmail.com>
7 */
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/bug.h>
11 #include <linux/printk.h>
12 #include <linux/sizes.h>
13 #include <linux/types.h>
14
15 #include <asm/debug-monitors.h>
16 #include <asm/errno.h>
17 #include <asm/insn.h>
18 #include <asm/kprobes.h>
19
20 #define AARCH64_INSN_SF_BIT BIT(31)
21 #define AARCH64_INSN_N_BIT BIT(22)
22 #define AARCH64_INSN_LSL_12 BIT(22)
23
aarch64_get_imm_shift_mask(enum aarch64_insn_imm_type type,u32 * maskp,int * shiftp)24 static int __kprobes aarch64_get_imm_shift_mask(enum aarch64_insn_imm_type type,
25 u32 *maskp, int *shiftp)
26 {
27 u32 mask;
28 int shift;
29
30 switch (type) {
31 case AARCH64_INSN_IMM_26:
32 mask = BIT(26) - 1;
33 shift = 0;
34 break;
35 case AARCH64_INSN_IMM_19:
36 mask = BIT(19) - 1;
37 shift = 5;
38 break;
39 case AARCH64_INSN_IMM_16:
40 mask = BIT(16) - 1;
41 shift = 5;
42 break;
43 case AARCH64_INSN_IMM_14:
44 mask = BIT(14) - 1;
45 shift = 5;
46 break;
47 case AARCH64_INSN_IMM_12:
48 mask = BIT(12) - 1;
49 shift = 10;
50 break;
51 case AARCH64_INSN_IMM_9:
52 mask = BIT(9) - 1;
53 shift = 12;
54 break;
55 case AARCH64_INSN_IMM_7:
56 mask = BIT(7) - 1;
57 shift = 15;
58 break;
59 case AARCH64_INSN_IMM_6:
60 case AARCH64_INSN_IMM_S:
61 mask = BIT(6) - 1;
62 shift = 10;
63 break;
64 case AARCH64_INSN_IMM_R:
65 mask = BIT(6) - 1;
66 shift = 16;
67 break;
68 case AARCH64_INSN_IMM_N:
69 mask = 1;
70 shift = 22;
71 break;
72 default:
73 return -EINVAL;
74 }
75
76 *maskp = mask;
77 *shiftp = shift;
78
79 return 0;
80 }
81
82 #define ADR_IMM_HILOSPLIT 2
83 #define ADR_IMM_SIZE SZ_2M
84 #define ADR_IMM_LOMASK ((1 << ADR_IMM_HILOSPLIT) - 1)
85 #define ADR_IMM_HIMASK ((ADR_IMM_SIZE >> ADR_IMM_HILOSPLIT) - 1)
86 #define ADR_IMM_LOSHIFT 29
87 #define ADR_IMM_HISHIFT 5
88
aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type,u32 insn)89 u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn)
90 {
91 u32 immlo, immhi, mask;
92 int shift;
93
94 switch (type) {
95 case AARCH64_INSN_IMM_ADR:
96 shift = 0;
97 immlo = (insn >> ADR_IMM_LOSHIFT) & ADR_IMM_LOMASK;
98 immhi = (insn >> ADR_IMM_HISHIFT) & ADR_IMM_HIMASK;
99 insn = (immhi << ADR_IMM_HILOSPLIT) | immlo;
100 mask = ADR_IMM_SIZE - 1;
101 break;
102 default:
103 if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) {
104 pr_err("%s: unknown immediate encoding %d\n", __func__,
105 type);
106 return 0;
107 }
108 }
109
110 return (insn >> shift) & mask;
111 }
112
aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,u32 insn,u64 imm)113 u32 __kprobes aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
114 u32 insn, u64 imm)
115 {
116 u32 immlo, immhi, mask;
117 int shift;
118
119 if (insn == AARCH64_BREAK_FAULT)
120 return AARCH64_BREAK_FAULT;
121
122 switch (type) {
123 case AARCH64_INSN_IMM_ADR:
124 shift = 0;
125 immlo = (imm & ADR_IMM_LOMASK) << ADR_IMM_LOSHIFT;
126 imm >>= ADR_IMM_HILOSPLIT;
127 immhi = (imm & ADR_IMM_HIMASK) << ADR_IMM_HISHIFT;
128 imm = immlo | immhi;
129 mask = ((ADR_IMM_LOMASK << ADR_IMM_LOSHIFT) |
130 (ADR_IMM_HIMASK << ADR_IMM_HISHIFT));
131 break;
132 default:
133 if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) {
134 pr_err("%s: unknown immediate encoding %d\n", __func__,
135 type);
136 return AARCH64_BREAK_FAULT;
137 }
138 }
139
140 /* Update the immediate field. */
141 insn &= ~(mask << shift);
142 insn |= (imm & mask) << shift;
143
144 return insn;
145 }
146
aarch64_insn_decode_register(enum aarch64_insn_register_type type,u32 insn)147 u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,
148 u32 insn)
149 {
150 int shift;
151
152 switch (type) {
153 case AARCH64_INSN_REGTYPE_RT:
154 case AARCH64_INSN_REGTYPE_RD:
155 shift = 0;
156 break;
157 case AARCH64_INSN_REGTYPE_RN:
158 shift = 5;
159 break;
160 case AARCH64_INSN_REGTYPE_RT2:
161 case AARCH64_INSN_REGTYPE_RA:
162 shift = 10;
163 break;
164 case AARCH64_INSN_REGTYPE_RM:
165 shift = 16;
166 break;
167 default:
168 pr_err("%s: unknown register type encoding %d\n", __func__,
169 type);
170 return 0;
171 }
172
173 return (insn >> shift) & GENMASK(4, 0);
174 }
175
aarch64_insn_encode_register(enum aarch64_insn_register_type type,u32 insn,enum aarch64_insn_register reg)176 static u32 aarch64_insn_encode_register(enum aarch64_insn_register_type type,
177 u32 insn,
178 enum aarch64_insn_register reg)
179 {
180 int shift;
181
182 if (insn == AARCH64_BREAK_FAULT)
183 return AARCH64_BREAK_FAULT;
184
185 if (reg < AARCH64_INSN_REG_0 || reg > AARCH64_INSN_REG_SP) {
186 pr_err("%s: unknown register encoding %d\n", __func__, reg);
187 return AARCH64_BREAK_FAULT;
188 }
189
190 switch (type) {
191 case AARCH64_INSN_REGTYPE_RT:
192 case AARCH64_INSN_REGTYPE_RD:
193 shift = 0;
194 break;
195 case AARCH64_INSN_REGTYPE_RN:
196 shift = 5;
197 break;
198 case AARCH64_INSN_REGTYPE_RT2:
199 case AARCH64_INSN_REGTYPE_RA:
200 shift = 10;
201 break;
202 case AARCH64_INSN_REGTYPE_RM:
203 case AARCH64_INSN_REGTYPE_RS:
204 shift = 16;
205 break;
206 default:
207 pr_err("%s: unknown register type encoding %d\n", __func__,
208 type);
209 return AARCH64_BREAK_FAULT;
210 }
211
212 insn &= ~(GENMASK(4, 0) << shift);
213 insn |= reg << shift;
214
215 return insn;
216 }
217
218 static const u32 aarch64_insn_ldst_size[] = {
219 [AARCH64_INSN_SIZE_8] = 0,
220 [AARCH64_INSN_SIZE_16] = 1,
221 [AARCH64_INSN_SIZE_32] = 2,
222 [AARCH64_INSN_SIZE_64] = 3,
223 };
224
aarch64_insn_encode_ldst_size(enum aarch64_insn_size_type type,u32 insn)225 static u32 aarch64_insn_encode_ldst_size(enum aarch64_insn_size_type type,
226 u32 insn)
227 {
228 u32 size;
229
230 if (type < AARCH64_INSN_SIZE_8 || type > AARCH64_INSN_SIZE_64) {
231 pr_err("%s: unknown size encoding %d\n", __func__, type);
232 return AARCH64_BREAK_FAULT;
233 }
234
235 size = aarch64_insn_ldst_size[type];
236 insn &= ~GENMASK(31, 30);
237 insn |= size << 30;
238
239 return insn;
240 }
241
label_imm_common(unsigned long pc,unsigned long addr,long range)242 static inline long label_imm_common(unsigned long pc, unsigned long addr,
243 long range)
244 {
245 long offset;
246
247 if ((pc & 0x3) || (addr & 0x3)) {
248 pr_err("%s: A64 instructions must be word aligned\n", __func__);
249 return range;
250 }
251
252 offset = ((long)addr - (long)pc);
253
254 if (offset < -range || offset >= range) {
255 pr_err("%s: offset out of range\n", __func__);
256 return range;
257 }
258
259 return offset;
260 }
261
aarch64_insn_gen_branch_imm(unsigned long pc,unsigned long addr,enum aarch64_insn_branch_type type)262 u32 __kprobes aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
263 enum aarch64_insn_branch_type type)
264 {
265 u32 insn;
266 long offset;
267
268 /*
269 * B/BL support [-128M, 128M) offset
270 * ARM64 virtual address arrangement guarantees all kernel and module
271 * texts are within +/-128M.
272 */
273 offset = label_imm_common(pc, addr, SZ_128M);
274 if (offset >= SZ_128M)
275 return AARCH64_BREAK_FAULT;
276
277 switch (type) {
278 case AARCH64_INSN_BRANCH_LINK:
279 insn = aarch64_insn_get_bl_value();
280 break;
281 case AARCH64_INSN_BRANCH_NOLINK:
282 insn = aarch64_insn_get_b_value();
283 break;
284 default:
285 pr_err("%s: unknown branch encoding %d\n", __func__, type);
286 return AARCH64_BREAK_FAULT;
287 }
288
289 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_26, insn,
290 offset >> 2);
291 }
292
aarch64_insn_gen_comp_branch_imm(unsigned long pc,unsigned long addr,enum aarch64_insn_register reg,enum aarch64_insn_variant variant,enum aarch64_insn_branch_type type)293 u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
294 enum aarch64_insn_register reg,
295 enum aarch64_insn_variant variant,
296 enum aarch64_insn_branch_type type)
297 {
298 u32 insn;
299 long offset;
300
301 offset = label_imm_common(pc, addr, SZ_1M);
302 if (offset >= SZ_1M)
303 return AARCH64_BREAK_FAULT;
304
305 switch (type) {
306 case AARCH64_INSN_BRANCH_COMP_ZERO:
307 insn = aarch64_insn_get_cbz_value();
308 break;
309 case AARCH64_INSN_BRANCH_COMP_NONZERO:
310 insn = aarch64_insn_get_cbnz_value();
311 break;
312 default:
313 pr_err("%s: unknown branch encoding %d\n", __func__, type);
314 return AARCH64_BREAK_FAULT;
315 }
316
317 switch (variant) {
318 case AARCH64_INSN_VARIANT_32BIT:
319 break;
320 case AARCH64_INSN_VARIANT_64BIT:
321 insn |= AARCH64_INSN_SF_BIT;
322 break;
323 default:
324 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
325 return AARCH64_BREAK_FAULT;
326 }
327
328 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
329
330 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
331 offset >> 2);
332 }
333
aarch64_insn_gen_cond_branch_imm(unsigned long pc,unsigned long addr,enum aarch64_insn_condition cond)334 u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
335 enum aarch64_insn_condition cond)
336 {
337 u32 insn;
338 long offset;
339
340 offset = label_imm_common(pc, addr, SZ_1M);
341
342 insn = aarch64_insn_get_bcond_value();
343
344 if (cond < AARCH64_INSN_COND_EQ || cond > AARCH64_INSN_COND_AL) {
345 pr_err("%s: unknown condition encoding %d\n", __func__, cond);
346 return AARCH64_BREAK_FAULT;
347 }
348 insn |= cond;
349
350 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
351 offset >> 2);
352 }
353
aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,enum aarch64_insn_branch_type type)354 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
355 enum aarch64_insn_branch_type type)
356 {
357 u32 insn;
358
359 switch (type) {
360 case AARCH64_INSN_BRANCH_NOLINK:
361 insn = aarch64_insn_get_br_value();
362 break;
363 case AARCH64_INSN_BRANCH_LINK:
364 insn = aarch64_insn_get_blr_value();
365 break;
366 case AARCH64_INSN_BRANCH_RETURN:
367 insn = aarch64_insn_get_ret_value();
368 break;
369 default:
370 pr_err("%s: unknown branch encoding %d\n", __func__, type);
371 return AARCH64_BREAK_FAULT;
372 }
373
374 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, reg);
375 }
376
aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,enum aarch64_insn_register base,enum aarch64_insn_register offset,enum aarch64_insn_size_type size,enum aarch64_insn_ldst_type type)377 u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
378 enum aarch64_insn_register base,
379 enum aarch64_insn_register offset,
380 enum aarch64_insn_size_type size,
381 enum aarch64_insn_ldst_type type)
382 {
383 u32 insn;
384
385 switch (type) {
386 case AARCH64_INSN_LDST_LOAD_REG_OFFSET:
387 insn = aarch64_insn_get_ldr_reg_value();
388 break;
389 case AARCH64_INSN_LDST_SIGNED_LOAD_REG_OFFSET:
390 insn = aarch64_insn_get_signed_ldr_reg_value();
391 break;
392 case AARCH64_INSN_LDST_STORE_REG_OFFSET:
393 insn = aarch64_insn_get_str_reg_value();
394 break;
395 default:
396 pr_err("%s: unknown load/store encoding %d\n", __func__, type);
397 return AARCH64_BREAK_FAULT;
398 }
399
400 insn = aarch64_insn_encode_ldst_size(size, insn);
401
402 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
403
404 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
405 base);
406
407 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
408 offset);
409 }
410
aarch64_insn_gen_load_store_imm(enum aarch64_insn_register reg,enum aarch64_insn_register base,unsigned int imm,enum aarch64_insn_size_type size,enum aarch64_insn_ldst_type type)411 u32 aarch64_insn_gen_load_store_imm(enum aarch64_insn_register reg,
412 enum aarch64_insn_register base,
413 unsigned int imm,
414 enum aarch64_insn_size_type size,
415 enum aarch64_insn_ldst_type type)
416 {
417 u32 insn;
418 u32 shift;
419
420 if (size < AARCH64_INSN_SIZE_8 || size > AARCH64_INSN_SIZE_64) {
421 pr_err("%s: unknown size encoding %d\n", __func__, type);
422 return AARCH64_BREAK_FAULT;
423 }
424
425 shift = aarch64_insn_ldst_size[size];
426 if (imm & ~(BIT(12 + shift) - BIT(shift))) {
427 pr_err("%s: invalid imm: %d\n", __func__, imm);
428 return AARCH64_BREAK_FAULT;
429 }
430
431 imm >>= shift;
432
433 switch (type) {
434 case AARCH64_INSN_LDST_LOAD_IMM_OFFSET:
435 insn = aarch64_insn_get_ldr_imm_value();
436 break;
437 case AARCH64_INSN_LDST_SIGNED_LOAD_IMM_OFFSET:
438 insn = aarch64_insn_get_signed_load_imm_value();
439 break;
440 case AARCH64_INSN_LDST_STORE_IMM_OFFSET:
441 insn = aarch64_insn_get_str_imm_value();
442 break;
443 default:
444 pr_err("%s: unknown load/store encoding %d\n", __func__, type);
445 return AARCH64_BREAK_FAULT;
446 }
447
448 insn = aarch64_insn_encode_ldst_size(size, insn);
449
450 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
451
452 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
453 base);
454
455 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_12, insn, imm);
456 }
457
aarch64_insn_gen_load_literal(unsigned long pc,unsigned long addr,enum aarch64_insn_register reg,bool is64bit)458 u32 aarch64_insn_gen_load_literal(unsigned long pc, unsigned long addr,
459 enum aarch64_insn_register reg,
460 bool is64bit)
461 {
462 u32 insn;
463 long offset;
464
465 offset = label_imm_common(pc, addr, SZ_1M);
466 if (offset >= SZ_1M)
467 return AARCH64_BREAK_FAULT;
468
469 insn = aarch64_insn_get_ldr_lit_value();
470
471 if (is64bit)
472 insn |= BIT(30);
473
474 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
475
476 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
477 offset >> 2);
478 }
479
aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,enum aarch64_insn_register reg2,enum aarch64_insn_register base,int offset,enum aarch64_insn_variant variant,enum aarch64_insn_ldst_type type)480 u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
481 enum aarch64_insn_register reg2,
482 enum aarch64_insn_register base,
483 int offset,
484 enum aarch64_insn_variant variant,
485 enum aarch64_insn_ldst_type type)
486 {
487 u32 insn;
488 int shift;
489
490 switch (type) {
491 case AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX:
492 insn = aarch64_insn_get_ldp_pre_value();
493 break;
494 case AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX:
495 insn = aarch64_insn_get_stp_pre_value();
496 break;
497 case AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX:
498 insn = aarch64_insn_get_ldp_post_value();
499 break;
500 case AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX:
501 insn = aarch64_insn_get_stp_post_value();
502 break;
503 default:
504 pr_err("%s: unknown load/store encoding %d\n", __func__, type);
505 return AARCH64_BREAK_FAULT;
506 }
507
508 switch (variant) {
509 case AARCH64_INSN_VARIANT_32BIT:
510 if ((offset & 0x3) || (offset < -256) || (offset > 252)) {
511 pr_err("%s: offset must be multiples of 4 in the range of [-256, 252] %d\n",
512 __func__, offset);
513 return AARCH64_BREAK_FAULT;
514 }
515 shift = 2;
516 break;
517 case AARCH64_INSN_VARIANT_64BIT:
518 if ((offset & 0x7) || (offset < -512) || (offset > 504)) {
519 pr_err("%s: offset must be multiples of 8 in the range of [-512, 504] %d\n",
520 __func__, offset);
521 return AARCH64_BREAK_FAULT;
522 }
523 shift = 3;
524 insn |= AARCH64_INSN_SF_BIT;
525 break;
526 default:
527 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
528 return AARCH64_BREAK_FAULT;
529 }
530
531 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
532 reg1);
533
534 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT2, insn,
535 reg2);
536
537 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
538 base);
539
540 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_7, insn,
541 offset >> shift);
542 }
543
aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,enum aarch64_insn_register base,enum aarch64_insn_register state,enum aarch64_insn_size_type size,enum aarch64_insn_ldst_type type)544 u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,
545 enum aarch64_insn_register base,
546 enum aarch64_insn_register state,
547 enum aarch64_insn_size_type size,
548 enum aarch64_insn_ldst_type type)
549 {
550 u32 insn;
551
552 switch (type) {
553 case AARCH64_INSN_LDST_LOAD_EX:
554 case AARCH64_INSN_LDST_LOAD_ACQ_EX:
555 insn = aarch64_insn_get_load_ex_value();
556 if (type == AARCH64_INSN_LDST_LOAD_ACQ_EX)
557 insn |= BIT(15);
558 break;
559 case AARCH64_INSN_LDST_STORE_EX:
560 case AARCH64_INSN_LDST_STORE_REL_EX:
561 insn = aarch64_insn_get_store_ex_value();
562 if (type == AARCH64_INSN_LDST_STORE_REL_EX)
563 insn |= BIT(15);
564 break;
565 default:
566 pr_err("%s: unknown load/store exclusive encoding %d\n", __func__, type);
567 return AARCH64_BREAK_FAULT;
568 }
569
570 insn = aarch64_insn_encode_ldst_size(size, insn);
571
572 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
573 reg);
574
575 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
576 base);
577
578 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT2, insn,
579 AARCH64_INSN_REG_ZR);
580
581 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RS, insn,
582 state);
583 }
584
585 #ifdef CONFIG_ARM64_LSE_ATOMICS
aarch64_insn_encode_ldst_order(enum aarch64_insn_mem_order_type type,u32 insn)586 static u32 aarch64_insn_encode_ldst_order(enum aarch64_insn_mem_order_type type,
587 u32 insn)
588 {
589 u32 order;
590
591 switch (type) {
592 case AARCH64_INSN_MEM_ORDER_NONE:
593 order = 0;
594 break;
595 case AARCH64_INSN_MEM_ORDER_ACQ:
596 order = 2;
597 break;
598 case AARCH64_INSN_MEM_ORDER_REL:
599 order = 1;
600 break;
601 case AARCH64_INSN_MEM_ORDER_ACQREL:
602 order = 3;
603 break;
604 default:
605 pr_err("%s: unknown mem order %d\n", __func__, type);
606 return AARCH64_BREAK_FAULT;
607 }
608
609 insn &= ~GENMASK(23, 22);
610 insn |= order << 22;
611
612 return insn;
613 }
614
aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result,enum aarch64_insn_register address,enum aarch64_insn_register value,enum aarch64_insn_size_type size,enum aarch64_insn_mem_atomic_op op,enum aarch64_insn_mem_order_type order)615 u32 aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result,
616 enum aarch64_insn_register address,
617 enum aarch64_insn_register value,
618 enum aarch64_insn_size_type size,
619 enum aarch64_insn_mem_atomic_op op,
620 enum aarch64_insn_mem_order_type order)
621 {
622 u32 insn;
623
624 switch (op) {
625 case AARCH64_INSN_MEM_ATOMIC_ADD:
626 insn = aarch64_insn_get_ldadd_value();
627 break;
628 case AARCH64_INSN_MEM_ATOMIC_CLR:
629 insn = aarch64_insn_get_ldclr_value();
630 break;
631 case AARCH64_INSN_MEM_ATOMIC_EOR:
632 insn = aarch64_insn_get_ldeor_value();
633 break;
634 case AARCH64_INSN_MEM_ATOMIC_SET:
635 insn = aarch64_insn_get_ldset_value();
636 break;
637 case AARCH64_INSN_MEM_ATOMIC_SWP:
638 insn = aarch64_insn_get_swp_value();
639 break;
640 default:
641 pr_err("%s: unimplemented mem atomic op %d\n", __func__, op);
642 return AARCH64_BREAK_FAULT;
643 }
644
645 switch (size) {
646 case AARCH64_INSN_SIZE_32:
647 case AARCH64_INSN_SIZE_64:
648 break;
649 default:
650 pr_err("%s: unimplemented size encoding %d\n", __func__, size);
651 return AARCH64_BREAK_FAULT;
652 }
653
654 insn = aarch64_insn_encode_ldst_size(size, insn);
655
656 insn = aarch64_insn_encode_ldst_order(order, insn);
657
658 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
659 result);
660
661 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
662 address);
663
664 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RS, insn,
665 value);
666 }
667
aarch64_insn_encode_cas_order(enum aarch64_insn_mem_order_type type,u32 insn)668 static u32 aarch64_insn_encode_cas_order(enum aarch64_insn_mem_order_type type,
669 u32 insn)
670 {
671 u32 order;
672
673 switch (type) {
674 case AARCH64_INSN_MEM_ORDER_NONE:
675 order = 0;
676 break;
677 case AARCH64_INSN_MEM_ORDER_ACQ:
678 order = BIT(22);
679 break;
680 case AARCH64_INSN_MEM_ORDER_REL:
681 order = BIT(15);
682 break;
683 case AARCH64_INSN_MEM_ORDER_ACQREL:
684 order = BIT(15) | BIT(22);
685 break;
686 default:
687 pr_err("%s: unknown mem order %d\n", __func__, type);
688 return AARCH64_BREAK_FAULT;
689 }
690
691 insn &= ~(BIT(15) | BIT(22));
692 insn |= order;
693
694 return insn;
695 }
696
aarch64_insn_gen_cas(enum aarch64_insn_register result,enum aarch64_insn_register address,enum aarch64_insn_register value,enum aarch64_insn_size_type size,enum aarch64_insn_mem_order_type order)697 u32 aarch64_insn_gen_cas(enum aarch64_insn_register result,
698 enum aarch64_insn_register address,
699 enum aarch64_insn_register value,
700 enum aarch64_insn_size_type size,
701 enum aarch64_insn_mem_order_type order)
702 {
703 u32 insn;
704
705 switch (size) {
706 case AARCH64_INSN_SIZE_32:
707 case AARCH64_INSN_SIZE_64:
708 break;
709 default:
710 pr_err("%s: unimplemented size encoding %d\n", __func__, size);
711 return AARCH64_BREAK_FAULT;
712 }
713
714 insn = aarch64_insn_get_cas_value();
715
716 insn = aarch64_insn_encode_ldst_size(size, insn);
717
718 insn = aarch64_insn_encode_cas_order(order, insn);
719
720 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
721 result);
722
723 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
724 address);
725
726 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RS, insn,
727 value);
728 }
729 #endif
730
aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,enum aarch64_insn_register src,int imm,enum aarch64_insn_variant variant,enum aarch64_insn_adsb_type type)731 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
732 enum aarch64_insn_register src,
733 int imm, enum aarch64_insn_variant variant,
734 enum aarch64_insn_adsb_type type)
735 {
736 u32 insn;
737
738 switch (type) {
739 case AARCH64_INSN_ADSB_ADD:
740 insn = aarch64_insn_get_add_imm_value();
741 break;
742 case AARCH64_INSN_ADSB_SUB:
743 insn = aarch64_insn_get_sub_imm_value();
744 break;
745 case AARCH64_INSN_ADSB_ADD_SETFLAGS:
746 insn = aarch64_insn_get_adds_imm_value();
747 break;
748 case AARCH64_INSN_ADSB_SUB_SETFLAGS:
749 insn = aarch64_insn_get_subs_imm_value();
750 break;
751 default:
752 pr_err("%s: unknown add/sub encoding %d\n", __func__, type);
753 return AARCH64_BREAK_FAULT;
754 }
755
756 switch (variant) {
757 case AARCH64_INSN_VARIANT_32BIT:
758 break;
759 case AARCH64_INSN_VARIANT_64BIT:
760 insn |= AARCH64_INSN_SF_BIT;
761 break;
762 default:
763 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
764 return AARCH64_BREAK_FAULT;
765 }
766
767 /* We can't encode more than a 24bit value (12bit + 12bit shift) */
768 if (imm & ~(BIT(24) - 1))
769 goto out;
770
771 /* If we have something in the top 12 bits... */
772 if (imm & ~(SZ_4K - 1)) {
773 /* ... and in the low 12 bits -> error */
774 if (imm & (SZ_4K - 1))
775 goto out;
776
777 imm >>= 12;
778 insn |= AARCH64_INSN_LSL_12;
779 }
780
781 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
782
783 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
784
785 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_12, insn, imm);
786
787 out:
788 pr_err("%s: invalid immediate encoding %d\n", __func__, imm);
789 return AARCH64_BREAK_FAULT;
790 }
791
aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,enum aarch64_insn_register src,int immr,int imms,enum aarch64_insn_variant variant,enum aarch64_insn_bitfield_type type)792 u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
793 enum aarch64_insn_register src,
794 int immr, int imms,
795 enum aarch64_insn_variant variant,
796 enum aarch64_insn_bitfield_type type)
797 {
798 u32 insn;
799 u32 mask;
800
801 switch (type) {
802 case AARCH64_INSN_BITFIELD_MOVE:
803 insn = aarch64_insn_get_bfm_value();
804 break;
805 case AARCH64_INSN_BITFIELD_MOVE_UNSIGNED:
806 insn = aarch64_insn_get_ubfm_value();
807 break;
808 case AARCH64_INSN_BITFIELD_MOVE_SIGNED:
809 insn = aarch64_insn_get_sbfm_value();
810 break;
811 default:
812 pr_err("%s: unknown bitfield encoding %d\n", __func__, type);
813 return AARCH64_BREAK_FAULT;
814 }
815
816 switch (variant) {
817 case AARCH64_INSN_VARIANT_32BIT:
818 mask = GENMASK(4, 0);
819 break;
820 case AARCH64_INSN_VARIANT_64BIT:
821 insn |= AARCH64_INSN_SF_BIT | AARCH64_INSN_N_BIT;
822 mask = GENMASK(5, 0);
823 break;
824 default:
825 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
826 return AARCH64_BREAK_FAULT;
827 }
828
829 if (immr & ~mask) {
830 pr_err("%s: invalid immr encoding %d\n", __func__, immr);
831 return AARCH64_BREAK_FAULT;
832 }
833 if (imms & ~mask) {
834 pr_err("%s: invalid imms encoding %d\n", __func__, imms);
835 return AARCH64_BREAK_FAULT;
836 }
837
838 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
839
840 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
841
842 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_R, insn, immr);
843
844 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_S, insn, imms);
845 }
846
aarch64_insn_gen_movewide(enum aarch64_insn_register dst,int imm,int shift,enum aarch64_insn_variant variant,enum aarch64_insn_movewide_type type)847 u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
848 int imm, int shift,
849 enum aarch64_insn_variant variant,
850 enum aarch64_insn_movewide_type type)
851 {
852 u32 insn;
853
854 switch (type) {
855 case AARCH64_INSN_MOVEWIDE_ZERO:
856 insn = aarch64_insn_get_movz_value();
857 break;
858 case AARCH64_INSN_MOVEWIDE_KEEP:
859 insn = aarch64_insn_get_movk_value();
860 break;
861 case AARCH64_INSN_MOVEWIDE_INVERSE:
862 insn = aarch64_insn_get_movn_value();
863 break;
864 default:
865 pr_err("%s: unknown movewide encoding %d\n", __func__, type);
866 return AARCH64_BREAK_FAULT;
867 }
868
869 if (imm & ~(SZ_64K - 1)) {
870 pr_err("%s: invalid immediate encoding %d\n", __func__, imm);
871 return AARCH64_BREAK_FAULT;
872 }
873
874 switch (variant) {
875 case AARCH64_INSN_VARIANT_32BIT:
876 if (shift != 0 && shift != 16) {
877 pr_err("%s: invalid shift encoding %d\n", __func__,
878 shift);
879 return AARCH64_BREAK_FAULT;
880 }
881 break;
882 case AARCH64_INSN_VARIANT_64BIT:
883 insn |= AARCH64_INSN_SF_BIT;
884 if (shift != 0 && shift != 16 && shift != 32 && shift != 48) {
885 pr_err("%s: invalid shift encoding %d\n", __func__,
886 shift);
887 return AARCH64_BREAK_FAULT;
888 }
889 break;
890 default:
891 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
892 return AARCH64_BREAK_FAULT;
893 }
894
895 insn |= (shift >> 4) << 21;
896
897 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
898
899 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm);
900 }
901
aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,enum aarch64_insn_register src,enum aarch64_insn_register reg,int shift,enum aarch64_insn_variant variant,enum aarch64_insn_adsb_type type)902 u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
903 enum aarch64_insn_register src,
904 enum aarch64_insn_register reg,
905 int shift,
906 enum aarch64_insn_variant variant,
907 enum aarch64_insn_adsb_type type)
908 {
909 u32 insn;
910
911 switch (type) {
912 case AARCH64_INSN_ADSB_ADD:
913 insn = aarch64_insn_get_add_value();
914 break;
915 case AARCH64_INSN_ADSB_SUB:
916 insn = aarch64_insn_get_sub_value();
917 break;
918 case AARCH64_INSN_ADSB_ADD_SETFLAGS:
919 insn = aarch64_insn_get_adds_value();
920 break;
921 case AARCH64_INSN_ADSB_SUB_SETFLAGS:
922 insn = aarch64_insn_get_subs_value();
923 break;
924 default:
925 pr_err("%s: unknown add/sub encoding %d\n", __func__, type);
926 return AARCH64_BREAK_FAULT;
927 }
928
929 switch (variant) {
930 case AARCH64_INSN_VARIANT_32BIT:
931 if (shift & ~(SZ_32 - 1)) {
932 pr_err("%s: invalid shift encoding %d\n", __func__,
933 shift);
934 return AARCH64_BREAK_FAULT;
935 }
936 break;
937 case AARCH64_INSN_VARIANT_64BIT:
938 insn |= AARCH64_INSN_SF_BIT;
939 if (shift & ~(SZ_64 - 1)) {
940 pr_err("%s: invalid shift encoding %d\n", __func__,
941 shift);
942 return AARCH64_BREAK_FAULT;
943 }
944 break;
945 default:
946 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
947 return AARCH64_BREAK_FAULT;
948 }
949
950
951 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
952
953 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
954
955 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
956
957 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);
958 }
959
aarch64_insn_gen_data1(enum aarch64_insn_register dst,enum aarch64_insn_register src,enum aarch64_insn_variant variant,enum aarch64_insn_data1_type type)960 u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
961 enum aarch64_insn_register src,
962 enum aarch64_insn_variant variant,
963 enum aarch64_insn_data1_type type)
964 {
965 u32 insn;
966
967 switch (type) {
968 case AARCH64_INSN_DATA1_REVERSE_16:
969 insn = aarch64_insn_get_rev16_value();
970 break;
971 case AARCH64_INSN_DATA1_REVERSE_32:
972 insn = aarch64_insn_get_rev32_value();
973 break;
974 case AARCH64_INSN_DATA1_REVERSE_64:
975 if (variant != AARCH64_INSN_VARIANT_64BIT) {
976 pr_err("%s: invalid variant for reverse64 %d\n",
977 __func__, variant);
978 return AARCH64_BREAK_FAULT;
979 }
980 insn = aarch64_insn_get_rev64_value();
981 break;
982 default:
983 pr_err("%s: unknown data1 encoding %d\n", __func__, type);
984 return AARCH64_BREAK_FAULT;
985 }
986
987 switch (variant) {
988 case AARCH64_INSN_VARIANT_32BIT:
989 break;
990 case AARCH64_INSN_VARIANT_64BIT:
991 insn |= AARCH64_INSN_SF_BIT;
992 break;
993 default:
994 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
995 return AARCH64_BREAK_FAULT;
996 }
997
998 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
999
1000 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
1001 }
1002
aarch64_insn_gen_data2(enum aarch64_insn_register dst,enum aarch64_insn_register src,enum aarch64_insn_register reg,enum aarch64_insn_variant variant,enum aarch64_insn_data2_type type)1003 u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
1004 enum aarch64_insn_register src,
1005 enum aarch64_insn_register reg,
1006 enum aarch64_insn_variant variant,
1007 enum aarch64_insn_data2_type type)
1008 {
1009 u32 insn;
1010
1011 switch (type) {
1012 case AARCH64_INSN_DATA2_UDIV:
1013 insn = aarch64_insn_get_udiv_value();
1014 break;
1015 case AARCH64_INSN_DATA2_SDIV:
1016 insn = aarch64_insn_get_sdiv_value();
1017 break;
1018 case AARCH64_INSN_DATA2_LSLV:
1019 insn = aarch64_insn_get_lslv_value();
1020 break;
1021 case AARCH64_INSN_DATA2_LSRV:
1022 insn = aarch64_insn_get_lsrv_value();
1023 break;
1024 case AARCH64_INSN_DATA2_ASRV:
1025 insn = aarch64_insn_get_asrv_value();
1026 break;
1027 case AARCH64_INSN_DATA2_RORV:
1028 insn = aarch64_insn_get_rorv_value();
1029 break;
1030 default:
1031 pr_err("%s: unknown data2 encoding %d\n", __func__, type);
1032 return AARCH64_BREAK_FAULT;
1033 }
1034
1035 switch (variant) {
1036 case AARCH64_INSN_VARIANT_32BIT:
1037 break;
1038 case AARCH64_INSN_VARIANT_64BIT:
1039 insn |= AARCH64_INSN_SF_BIT;
1040 break;
1041 default:
1042 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1043 return AARCH64_BREAK_FAULT;
1044 }
1045
1046 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1047
1048 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
1049
1050 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
1051 }
1052
aarch64_insn_gen_data3(enum aarch64_insn_register dst,enum aarch64_insn_register src,enum aarch64_insn_register reg1,enum aarch64_insn_register reg2,enum aarch64_insn_variant variant,enum aarch64_insn_data3_type type)1053 u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
1054 enum aarch64_insn_register src,
1055 enum aarch64_insn_register reg1,
1056 enum aarch64_insn_register reg2,
1057 enum aarch64_insn_variant variant,
1058 enum aarch64_insn_data3_type type)
1059 {
1060 u32 insn;
1061
1062 switch (type) {
1063 case AARCH64_INSN_DATA3_MADD:
1064 insn = aarch64_insn_get_madd_value();
1065 break;
1066 case AARCH64_INSN_DATA3_MSUB:
1067 insn = aarch64_insn_get_msub_value();
1068 break;
1069 default:
1070 pr_err("%s: unknown data3 encoding %d\n", __func__, type);
1071 return AARCH64_BREAK_FAULT;
1072 }
1073
1074 switch (variant) {
1075 case AARCH64_INSN_VARIANT_32BIT:
1076 break;
1077 case AARCH64_INSN_VARIANT_64BIT:
1078 insn |= AARCH64_INSN_SF_BIT;
1079 break;
1080 default:
1081 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1082 return AARCH64_BREAK_FAULT;
1083 }
1084
1085 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1086
1087 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RA, insn, src);
1088
1089 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
1090 reg1);
1091
1092 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
1093 reg2);
1094 }
1095
aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,enum aarch64_insn_register src,enum aarch64_insn_register reg,int shift,enum aarch64_insn_variant variant,enum aarch64_insn_logic_type type)1096 u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
1097 enum aarch64_insn_register src,
1098 enum aarch64_insn_register reg,
1099 int shift,
1100 enum aarch64_insn_variant variant,
1101 enum aarch64_insn_logic_type type)
1102 {
1103 u32 insn;
1104
1105 switch (type) {
1106 case AARCH64_INSN_LOGIC_AND:
1107 insn = aarch64_insn_get_and_value();
1108 break;
1109 case AARCH64_INSN_LOGIC_BIC:
1110 insn = aarch64_insn_get_bic_value();
1111 break;
1112 case AARCH64_INSN_LOGIC_ORR:
1113 insn = aarch64_insn_get_orr_value();
1114 break;
1115 case AARCH64_INSN_LOGIC_ORN:
1116 insn = aarch64_insn_get_orn_value();
1117 break;
1118 case AARCH64_INSN_LOGIC_EOR:
1119 insn = aarch64_insn_get_eor_value();
1120 break;
1121 case AARCH64_INSN_LOGIC_EON:
1122 insn = aarch64_insn_get_eon_value();
1123 break;
1124 case AARCH64_INSN_LOGIC_AND_SETFLAGS:
1125 insn = aarch64_insn_get_ands_value();
1126 break;
1127 case AARCH64_INSN_LOGIC_BIC_SETFLAGS:
1128 insn = aarch64_insn_get_bics_value();
1129 break;
1130 default:
1131 pr_err("%s: unknown logical encoding %d\n", __func__, type);
1132 return AARCH64_BREAK_FAULT;
1133 }
1134
1135 switch (variant) {
1136 case AARCH64_INSN_VARIANT_32BIT:
1137 if (shift & ~(SZ_32 - 1)) {
1138 pr_err("%s: invalid shift encoding %d\n", __func__,
1139 shift);
1140 return AARCH64_BREAK_FAULT;
1141 }
1142 break;
1143 case AARCH64_INSN_VARIANT_64BIT:
1144 insn |= AARCH64_INSN_SF_BIT;
1145 if (shift & ~(SZ_64 - 1)) {
1146 pr_err("%s: invalid shift encoding %d\n", __func__,
1147 shift);
1148 return AARCH64_BREAK_FAULT;
1149 }
1150 break;
1151 default:
1152 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1153 return AARCH64_BREAK_FAULT;
1154 }
1155
1156
1157 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1158
1159 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
1160
1161 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
1162
1163 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);
1164 }
1165
1166 /*
1167 * MOV (register) is architecturally an alias of ORR (shifted register) where
1168 * MOV <*d>, <*m> is equivalent to ORR <*d>, <*ZR>, <*m>
1169 */
aarch64_insn_gen_move_reg(enum aarch64_insn_register dst,enum aarch64_insn_register src,enum aarch64_insn_variant variant)1170 u32 aarch64_insn_gen_move_reg(enum aarch64_insn_register dst,
1171 enum aarch64_insn_register src,
1172 enum aarch64_insn_variant variant)
1173 {
1174 return aarch64_insn_gen_logical_shifted_reg(dst, AARCH64_INSN_REG_ZR,
1175 src, 0, variant,
1176 AARCH64_INSN_LOGIC_ORR);
1177 }
1178
aarch64_insn_gen_adr(unsigned long pc,unsigned long addr,enum aarch64_insn_register reg,enum aarch64_insn_adr_type type)1179 u32 aarch64_insn_gen_adr(unsigned long pc, unsigned long addr,
1180 enum aarch64_insn_register reg,
1181 enum aarch64_insn_adr_type type)
1182 {
1183 u32 insn;
1184 s32 offset;
1185
1186 switch (type) {
1187 case AARCH64_INSN_ADR_TYPE_ADR:
1188 insn = aarch64_insn_get_adr_value();
1189 offset = addr - pc;
1190 break;
1191 case AARCH64_INSN_ADR_TYPE_ADRP:
1192 insn = aarch64_insn_get_adrp_value();
1193 offset = (addr - ALIGN_DOWN(pc, SZ_4K)) >> 12;
1194 break;
1195 default:
1196 pr_err("%s: unknown adr encoding %d\n", __func__, type);
1197 return AARCH64_BREAK_FAULT;
1198 }
1199
1200 if (offset < -SZ_1M || offset >= SZ_1M)
1201 return AARCH64_BREAK_FAULT;
1202
1203 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, reg);
1204
1205 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_ADR, insn, offset);
1206 }
1207
1208 /*
1209 * Decode the imm field of a branch, and return the byte offset as a
1210 * signed value (so it can be used when computing a new branch
1211 * target).
1212 */
aarch64_get_branch_offset(u32 insn)1213 s32 aarch64_get_branch_offset(u32 insn)
1214 {
1215 s32 imm;
1216
1217 if (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn)) {
1218 imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_26, insn);
1219 return (imm << 6) >> 4;
1220 }
1221
1222 if (aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) ||
1223 aarch64_insn_is_bcond(insn)) {
1224 imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_19, insn);
1225 return (imm << 13) >> 11;
1226 }
1227
1228 if (aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn)) {
1229 imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_14, insn);
1230 return (imm << 18) >> 16;
1231 }
1232
1233 /* Unhandled instruction */
1234 BUG();
1235 }
1236
1237 /*
1238 * Encode the displacement of a branch in the imm field and return the
1239 * updated instruction.
1240 */
aarch64_set_branch_offset(u32 insn,s32 offset)1241 u32 aarch64_set_branch_offset(u32 insn, s32 offset)
1242 {
1243 if (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn))
1244 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_26, insn,
1245 offset >> 2);
1246
1247 if (aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) ||
1248 aarch64_insn_is_bcond(insn))
1249 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
1250 offset >> 2);
1251
1252 if (aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn))
1253 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_14, insn,
1254 offset >> 2);
1255
1256 /* Unhandled instruction */
1257 BUG();
1258 }
1259
aarch64_insn_adrp_get_offset(u32 insn)1260 s32 aarch64_insn_adrp_get_offset(u32 insn)
1261 {
1262 BUG_ON(!aarch64_insn_is_adrp(insn));
1263 return aarch64_insn_decode_immediate(AARCH64_INSN_IMM_ADR, insn) << 12;
1264 }
1265
aarch64_insn_adrp_set_offset(u32 insn,s32 offset)1266 u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset)
1267 {
1268 BUG_ON(!aarch64_insn_is_adrp(insn));
1269 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_ADR, insn,
1270 offset >> 12);
1271 }
1272
1273 /*
1274 * Extract the Op/CR data from a msr/mrs instruction.
1275 */
aarch64_insn_extract_system_reg(u32 insn)1276 u32 aarch64_insn_extract_system_reg(u32 insn)
1277 {
1278 return (insn & 0x1FFFE0) >> 5;
1279 }
1280
aarch32_insn_is_wide(u32 insn)1281 bool aarch32_insn_is_wide(u32 insn)
1282 {
1283 return insn >= 0xe800;
1284 }
1285
1286 /*
1287 * Macros/defines for extracting register numbers from instruction.
1288 */
aarch32_insn_extract_reg_num(u32 insn,int offset)1289 u32 aarch32_insn_extract_reg_num(u32 insn, int offset)
1290 {
1291 return (insn & (0xf << offset)) >> offset;
1292 }
1293
1294 #define OPC2_MASK 0x7
1295 #define OPC2_OFFSET 5
aarch32_insn_mcr_extract_opc2(u32 insn)1296 u32 aarch32_insn_mcr_extract_opc2(u32 insn)
1297 {
1298 return (insn & (OPC2_MASK << OPC2_OFFSET)) >> OPC2_OFFSET;
1299 }
1300
1301 #define CRM_MASK 0xf
aarch32_insn_mcr_extract_crm(u32 insn)1302 u32 aarch32_insn_mcr_extract_crm(u32 insn)
1303 {
1304 return insn & CRM_MASK;
1305 }
1306
range_of_ones(u64 val)1307 static bool range_of_ones(u64 val)
1308 {
1309 /* Doesn't handle full ones or full zeroes */
1310 u64 sval = val >> __ffs64(val);
1311
1312 /* One of Sean Eron Anderson's bithack tricks */
1313 return ((sval + 1) & (sval)) == 0;
1314 }
1315
aarch64_encode_immediate(u64 imm,enum aarch64_insn_variant variant,u32 insn)1316 static u32 aarch64_encode_immediate(u64 imm,
1317 enum aarch64_insn_variant variant,
1318 u32 insn)
1319 {
1320 unsigned int immr, imms, n, ones, ror, esz, tmp;
1321 u64 mask;
1322
1323 switch (variant) {
1324 case AARCH64_INSN_VARIANT_32BIT:
1325 esz = 32;
1326 break;
1327 case AARCH64_INSN_VARIANT_64BIT:
1328 insn |= AARCH64_INSN_SF_BIT;
1329 esz = 64;
1330 break;
1331 default:
1332 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1333 return AARCH64_BREAK_FAULT;
1334 }
1335
1336 mask = GENMASK(esz - 1, 0);
1337
1338 /* Can't encode full zeroes, full ones, or value wider than the mask */
1339 if (!imm || imm == mask || imm & ~mask)
1340 return AARCH64_BREAK_FAULT;
1341
1342 /*
1343 * Inverse of Replicate(). Try to spot a repeating pattern
1344 * with a pow2 stride.
1345 */
1346 for (tmp = esz / 2; tmp >= 2; tmp /= 2) {
1347 u64 emask = BIT(tmp) - 1;
1348
1349 if ((imm & emask) != ((imm >> tmp) & emask))
1350 break;
1351
1352 esz = tmp;
1353 mask = emask;
1354 }
1355
1356 /* N is only set if we're encoding a 64bit value */
1357 n = esz == 64;
1358
1359 /* Trim imm to the element size */
1360 imm &= mask;
1361
1362 /* That's how many ones we need to encode */
1363 ones = hweight64(imm);
1364
1365 /*
1366 * imms is set to (ones - 1), prefixed with a string of ones
1367 * and a zero if they fit. Cap it to 6 bits.
1368 */
1369 imms = ones - 1;
1370 imms |= 0xf << ffs(esz);
1371 imms &= BIT(6) - 1;
1372
1373 /* Compute the rotation */
1374 if (range_of_ones(imm)) {
1375 /*
1376 * Pattern: 0..01..10..0
1377 *
1378 * Compute how many rotate we need to align it right
1379 */
1380 ror = __ffs64(imm);
1381 } else {
1382 /*
1383 * Pattern: 0..01..10..01..1
1384 *
1385 * Fill the unused top bits with ones, and check if
1386 * the result is a valid immediate (all ones with a
1387 * contiguous ranges of zeroes).
1388 */
1389 imm |= ~mask;
1390 if (!range_of_ones(~imm))
1391 return AARCH64_BREAK_FAULT;
1392
1393 /*
1394 * Compute the rotation to get a continuous set of
1395 * ones, with the first bit set at position 0
1396 */
1397 ror = fls64(~imm);
1398 }
1399
1400 /*
1401 * immr is the number of bits we need to rotate back to the
1402 * original set of ones. Note that this is relative to the
1403 * element size...
1404 */
1405 immr = (esz - ror) % esz;
1406
1407 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_N, insn, n);
1408 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_R, insn, immr);
1409 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_S, insn, imms);
1410 }
1411
aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type,enum aarch64_insn_variant variant,enum aarch64_insn_register Rn,enum aarch64_insn_register Rd,u64 imm)1412 u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type,
1413 enum aarch64_insn_variant variant,
1414 enum aarch64_insn_register Rn,
1415 enum aarch64_insn_register Rd,
1416 u64 imm)
1417 {
1418 u32 insn;
1419
1420 switch (type) {
1421 case AARCH64_INSN_LOGIC_AND:
1422 insn = aarch64_insn_get_and_imm_value();
1423 break;
1424 case AARCH64_INSN_LOGIC_ORR:
1425 insn = aarch64_insn_get_orr_imm_value();
1426 break;
1427 case AARCH64_INSN_LOGIC_EOR:
1428 insn = aarch64_insn_get_eor_imm_value();
1429 break;
1430 case AARCH64_INSN_LOGIC_AND_SETFLAGS:
1431 insn = aarch64_insn_get_ands_imm_value();
1432 break;
1433 default:
1434 pr_err("%s: unknown logical encoding %d\n", __func__, type);
1435 return AARCH64_BREAK_FAULT;
1436 }
1437
1438 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, Rd);
1439 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, Rn);
1440 return aarch64_encode_immediate(imm, variant, insn);
1441 }
1442
aarch64_insn_gen_extr(enum aarch64_insn_variant variant,enum aarch64_insn_register Rm,enum aarch64_insn_register Rn,enum aarch64_insn_register Rd,u8 lsb)1443 u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant,
1444 enum aarch64_insn_register Rm,
1445 enum aarch64_insn_register Rn,
1446 enum aarch64_insn_register Rd,
1447 u8 lsb)
1448 {
1449 u32 insn;
1450
1451 insn = aarch64_insn_get_extr_value();
1452
1453 switch (variant) {
1454 case AARCH64_INSN_VARIANT_32BIT:
1455 if (lsb > 31)
1456 return AARCH64_BREAK_FAULT;
1457 break;
1458 case AARCH64_INSN_VARIANT_64BIT:
1459 if (lsb > 63)
1460 return AARCH64_BREAK_FAULT;
1461 insn |= AARCH64_INSN_SF_BIT;
1462 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_N, insn, 1);
1463 break;
1464 default:
1465 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1466 return AARCH64_BREAK_FAULT;
1467 }
1468
1469 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_S, insn, lsb);
1470 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, Rd);
1471 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, Rn);
1472 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, Rm);
1473 }
1474
__get_barrier_crm_val(enum aarch64_insn_mb_type type)1475 static u32 __get_barrier_crm_val(enum aarch64_insn_mb_type type)
1476 {
1477 switch (type) {
1478 case AARCH64_INSN_MB_SY:
1479 return 0xf;
1480 case AARCH64_INSN_MB_ST:
1481 return 0xe;
1482 case AARCH64_INSN_MB_LD:
1483 return 0xd;
1484 case AARCH64_INSN_MB_ISH:
1485 return 0xb;
1486 case AARCH64_INSN_MB_ISHST:
1487 return 0xa;
1488 case AARCH64_INSN_MB_ISHLD:
1489 return 0x9;
1490 case AARCH64_INSN_MB_NSH:
1491 return 0x7;
1492 case AARCH64_INSN_MB_NSHST:
1493 return 0x6;
1494 case AARCH64_INSN_MB_NSHLD:
1495 return 0x5;
1496 default:
1497 pr_err("%s: unknown barrier type %d\n", __func__, type);
1498 return AARCH64_BREAK_FAULT;
1499 }
1500 }
1501
aarch64_insn_gen_dmb(enum aarch64_insn_mb_type type)1502 u32 aarch64_insn_gen_dmb(enum aarch64_insn_mb_type type)
1503 {
1504 u32 opt;
1505 u32 insn;
1506
1507 opt = __get_barrier_crm_val(type);
1508 if (opt == AARCH64_BREAK_FAULT)
1509 return AARCH64_BREAK_FAULT;
1510
1511 insn = aarch64_insn_get_dmb_value();
1512 insn &= ~GENMASK(11, 8);
1513 insn |= (opt << 8);
1514
1515 return insn;
1516 }
1517
aarch64_insn_gen_dsb(enum aarch64_insn_mb_type type)1518 u32 aarch64_insn_gen_dsb(enum aarch64_insn_mb_type type)
1519 {
1520 u32 opt, insn;
1521
1522 opt = __get_barrier_crm_val(type);
1523 if (opt == AARCH64_BREAK_FAULT)
1524 return AARCH64_BREAK_FAULT;
1525
1526 insn = aarch64_insn_get_dsb_base_value();
1527 insn &= ~GENMASK(11, 8);
1528 insn |= (opt << 8);
1529
1530 return insn;
1531 }
1532