1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2016-2019 Intel Corporation
4 */
5
6 #include <linux/string_helpers.h>
7
8 #include "gt/intel_gt.h"
9 #include "gt/intel_gt_print.h"
10 #include "gt/intel_reset.h"
11 #include "intel_gsc_fw.h"
12 #include "intel_gsc_uc.h"
13 #include "intel_guc.h"
14 #include "intel_guc_ads.h"
15 #include "intel_guc_print.h"
16 #include "intel_guc_submission.h"
17 #include "gt/intel_rps.h"
18 #include "intel_uc.h"
19
20 #include "i915_drv.h"
21 #include "i915_hwmon.h"
22
23 static const struct intel_uc_ops uc_ops_off;
24 static const struct intel_uc_ops uc_ops_on;
25
uc_expand_default_options(struct intel_uc * uc)26 static void uc_expand_default_options(struct intel_uc *uc)
27 {
28 struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
29
30 if (i915->params.enable_guc != -1)
31 return;
32
33 /* Don't enable GuC/HuC on pre-Gen12 */
34 if (GRAPHICS_VER(i915) < 12) {
35 i915->params.enable_guc = 0;
36 return;
37 }
38
39 /* Don't enable GuC/HuC on older Gen12 platforms */
40 if (IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915)) {
41 i915->params.enable_guc = 0;
42 return;
43 }
44
45 /* Intermediate platforms are HuC authentication only */
46 if (IS_ALDERLAKE_S(i915) && !IS_RAPTORLAKE_S(i915)) {
47 i915->params.enable_guc = ENABLE_GUC_LOAD_HUC;
48 return;
49 }
50
51 /* Default: enable HuC authentication and GuC submission */
52 i915->params.enable_guc = ENABLE_GUC_LOAD_HUC | ENABLE_GUC_SUBMISSION;
53
54 /* XEHPSDV and PVC do not use HuC */
55 if (IS_XEHPSDV(i915) || IS_PONTEVECCHIO(i915))
56 i915->params.enable_guc &= ~ENABLE_GUC_LOAD_HUC;
57 }
58
59 /* Reset GuC providing us with fresh state for both GuC and HuC.
60 */
__intel_uc_reset_hw(struct intel_uc * uc)61 static int __intel_uc_reset_hw(struct intel_uc *uc)
62 {
63 struct intel_gt *gt = uc_to_gt(uc);
64 int ret;
65 u32 guc_status;
66
67 ret = i915_inject_probe_error(gt->i915, -ENXIO);
68 if (ret)
69 return ret;
70
71 ret = intel_reset_guc(gt);
72 if (ret) {
73 gt_err(gt, "Failed to reset GuC, ret = %d\n", ret);
74 return ret;
75 }
76
77 guc_status = intel_uncore_read(gt->uncore, GUC_STATUS);
78 gt_WARN(gt, !(guc_status & GS_MIA_IN_RESET),
79 "GuC status: 0x%x, MIA core expected to be in reset\n",
80 guc_status);
81
82 return ret;
83 }
84
__confirm_options(struct intel_uc * uc)85 static void __confirm_options(struct intel_uc *uc)
86 {
87 struct intel_gt *gt = uc_to_gt(uc);
88 struct drm_i915_private *i915 = gt->i915;
89
90 gt_dbg(gt, "enable_guc=%d (guc:%s submission:%s huc:%s slpc:%s)\n",
91 i915->params.enable_guc,
92 str_yes_no(intel_uc_wants_guc(uc)),
93 str_yes_no(intel_uc_wants_guc_submission(uc)),
94 str_yes_no(intel_uc_wants_huc(uc)),
95 str_yes_no(intel_uc_wants_guc_slpc(uc)));
96
97 if (i915->params.enable_guc == 0) {
98 GEM_BUG_ON(intel_uc_wants_guc(uc));
99 GEM_BUG_ON(intel_uc_wants_guc_submission(uc));
100 GEM_BUG_ON(intel_uc_wants_huc(uc));
101 GEM_BUG_ON(intel_uc_wants_guc_slpc(uc));
102 return;
103 }
104
105 if (!intel_uc_supports_guc(uc))
106 gt_info(gt, "Incompatible option enable_guc=%d - %s\n",
107 i915->params.enable_guc, "GuC is not supported!");
108
109 if (i915->params.enable_guc & ENABLE_GUC_LOAD_HUC &&
110 !intel_uc_supports_huc(uc))
111 gt_info(gt, "Incompatible option enable_guc=%d - %s\n",
112 i915->params.enable_guc, "HuC is not supported!");
113
114 if (i915->params.enable_guc & ENABLE_GUC_SUBMISSION &&
115 !intel_uc_supports_guc_submission(uc))
116 gt_info(gt, "Incompatible option enable_guc=%d - %s\n",
117 i915->params.enable_guc, "GuC submission is N/A");
118
119 if (i915->params.enable_guc & ~ENABLE_GUC_MASK)
120 gt_info(gt, "Incompatible option enable_guc=%d - %s\n",
121 i915->params.enable_guc, "undocumented flag");
122 }
123
intel_uc_init_early(struct intel_uc * uc)124 void intel_uc_init_early(struct intel_uc *uc)
125 {
126 uc_expand_default_options(uc);
127
128 intel_guc_init_early(&uc->guc);
129 intel_huc_init_early(&uc->huc);
130 intel_gsc_uc_init_early(&uc->gsc);
131
132 __confirm_options(uc);
133
134 if (intel_uc_wants_guc(uc))
135 uc->ops = &uc_ops_on;
136 else
137 uc->ops = &uc_ops_off;
138 }
139
intel_uc_init_late(struct intel_uc * uc)140 void intel_uc_init_late(struct intel_uc *uc)
141 {
142 intel_guc_init_late(&uc->guc);
143 intel_gsc_uc_load_start(&uc->gsc);
144 }
145
intel_uc_driver_late_release(struct intel_uc * uc)146 void intel_uc_driver_late_release(struct intel_uc *uc)
147 {
148 intel_huc_fini_late(&uc->huc);
149 }
150
151 /**
152 * intel_uc_init_mmio - setup uC MMIO access
153 * @uc: the intel_uc structure
154 *
155 * Setup minimal state necessary for MMIO accesses later in the
156 * initialization sequence.
157 */
intel_uc_init_mmio(struct intel_uc * uc)158 void intel_uc_init_mmio(struct intel_uc *uc)
159 {
160 intel_guc_init_send_regs(&uc->guc);
161 }
162
__uc_capture_load_err_log(struct intel_uc * uc)163 static void __uc_capture_load_err_log(struct intel_uc *uc)
164 {
165 struct intel_guc *guc = &uc->guc;
166
167 if (guc->log.vma && !uc->load_err_log)
168 uc->load_err_log = i915_gem_object_get(guc->log.vma->obj);
169 }
170
__uc_free_load_err_log(struct intel_uc * uc)171 static void __uc_free_load_err_log(struct intel_uc *uc)
172 {
173 struct drm_i915_gem_object *log = fetch_and_zero(&uc->load_err_log);
174
175 if (log)
176 i915_gem_object_put(log);
177 }
178
intel_uc_driver_remove(struct intel_uc * uc)179 void intel_uc_driver_remove(struct intel_uc *uc)
180 {
181 intel_uc_fini_hw(uc);
182 intel_uc_fini(uc);
183 __uc_free_load_err_log(uc);
184 }
185
186 /*
187 * Events triggered while CT buffers are disabled are logged in the SCRATCH_15
188 * register using the same bits used in the CT message payload. Since our
189 * communication channel with guc is turned off at this point, we can save the
190 * message and handle it after we turn it back on.
191 */
guc_clear_mmio_msg(struct intel_guc * guc)192 static void guc_clear_mmio_msg(struct intel_guc *guc)
193 {
194 intel_uncore_write(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15), 0);
195 }
196
guc_get_mmio_msg(struct intel_guc * guc)197 static void guc_get_mmio_msg(struct intel_guc *guc)
198 {
199 u32 val;
200
201 spin_lock_irq(&guc->irq_lock);
202
203 val = intel_uncore_read(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15));
204 guc->mmio_msg |= val & guc->msg_enabled_mask;
205
206 /*
207 * clear all events, including the ones we're not currently servicing,
208 * to make sure we don't try to process a stale message if we enable
209 * handling of more events later.
210 */
211 guc_clear_mmio_msg(guc);
212
213 spin_unlock_irq(&guc->irq_lock);
214 }
215
guc_handle_mmio_msg(struct intel_guc * guc)216 static void guc_handle_mmio_msg(struct intel_guc *guc)
217 {
218 /* we need communication to be enabled to reply to GuC */
219 GEM_BUG_ON(!intel_guc_ct_enabled(&guc->ct));
220
221 spin_lock_irq(&guc->irq_lock);
222 if (guc->mmio_msg) {
223 intel_guc_to_host_process_recv_msg(guc, &guc->mmio_msg, 1);
224 guc->mmio_msg = 0;
225 }
226 spin_unlock_irq(&guc->irq_lock);
227 }
228
guc_enable_communication(struct intel_guc * guc)229 static int guc_enable_communication(struct intel_guc *guc)
230 {
231 struct intel_gt *gt = guc_to_gt(guc);
232 struct drm_i915_private *i915 = gt->i915;
233 int ret;
234
235 GEM_BUG_ON(intel_guc_ct_enabled(&guc->ct));
236
237 ret = i915_inject_probe_error(i915, -ENXIO);
238 if (ret)
239 return ret;
240
241 ret = intel_guc_ct_enable(&guc->ct);
242 if (ret)
243 return ret;
244
245 /* check for mmio messages received before/during the CT enable */
246 guc_get_mmio_msg(guc);
247 guc_handle_mmio_msg(guc);
248
249 intel_guc_enable_interrupts(guc);
250
251 /* check for CT messages received before we enabled interrupts */
252 spin_lock_irq(gt->irq_lock);
253 intel_guc_ct_event_handler(&guc->ct);
254 spin_unlock_irq(gt->irq_lock);
255
256 guc_dbg(guc, "communication enabled\n");
257
258 return 0;
259 }
260
guc_disable_communication(struct intel_guc * guc)261 static void guc_disable_communication(struct intel_guc *guc)
262 {
263 /*
264 * Events generated during or after CT disable are logged by guc in
265 * via mmio. Make sure the register is clear before disabling CT since
266 * all events we cared about have already been processed via CT.
267 */
268 guc_clear_mmio_msg(guc);
269
270 intel_guc_disable_interrupts(guc);
271
272 intel_guc_ct_disable(&guc->ct);
273
274 /*
275 * Check for messages received during/after the CT disable. We do not
276 * expect any messages to have arrived via CT between the interrupt
277 * disable and the CT disable because GuC should've been idle until we
278 * triggered the CT disable protocol.
279 */
280 guc_get_mmio_msg(guc);
281
282 guc_dbg(guc, "communication disabled\n");
283 }
284
__uc_fetch_firmwares(struct intel_uc * uc)285 static void __uc_fetch_firmwares(struct intel_uc *uc)
286 {
287 struct intel_gt *gt = uc_to_gt(uc);
288 int err;
289
290 GEM_BUG_ON(!intel_uc_wants_guc(uc));
291
292 err = intel_uc_fw_fetch(&uc->guc.fw);
293 if (err) {
294 /* Make sure we transition out of transient "SELECTED" state */
295 if (intel_uc_wants_huc(uc)) {
296 gt_dbg(gt, "Failed to fetch GuC fw (%pe) disabling HuC\n", ERR_PTR(err));
297 intel_uc_fw_change_status(&uc->huc.fw,
298 INTEL_UC_FIRMWARE_ERROR);
299 }
300
301 if (intel_uc_wants_gsc_uc(uc)) {
302 gt_dbg(gt, "Failed to fetch GuC fw (%pe) disabling GSC\n", ERR_PTR(err));
303 intel_uc_fw_change_status(&uc->gsc.fw,
304 INTEL_UC_FIRMWARE_ERROR);
305 }
306
307 return;
308 }
309
310 if (intel_uc_wants_huc(uc))
311 intel_uc_fw_fetch(&uc->huc.fw);
312
313 if (intel_uc_wants_gsc_uc(uc))
314 intel_uc_fw_fetch(&uc->gsc.fw);
315 }
316
__uc_cleanup_firmwares(struct intel_uc * uc)317 static void __uc_cleanup_firmwares(struct intel_uc *uc)
318 {
319 intel_uc_fw_cleanup_fetch(&uc->gsc.fw);
320 intel_uc_fw_cleanup_fetch(&uc->huc.fw);
321 intel_uc_fw_cleanup_fetch(&uc->guc.fw);
322 }
323
__uc_init(struct intel_uc * uc)324 static int __uc_init(struct intel_uc *uc)
325 {
326 struct intel_guc *guc = &uc->guc;
327 struct intel_huc *huc = &uc->huc;
328 int ret;
329
330 GEM_BUG_ON(!intel_uc_wants_guc(uc));
331
332 if (!intel_uc_uses_guc(uc))
333 return 0;
334
335 if (i915_inject_probe_failure(uc_to_gt(uc)->i915))
336 return -ENOMEM;
337
338 ret = intel_guc_init(guc);
339 if (ret)
340 return ret;
341
342 if (intel_uc_uses_huc(uc))
343 intel_huc_init(huc);
344
345 if (intel_uc_uses_gsc_uc(uc))
346 intel_gsc_uc_init(&uc->gsc);
347
348 return 0;
349 }
350
__uc_fini(struct intel_uc * uc)351 static void __uc_fini(struct intel_uc *uc)
352 {
353 intel_gsc_uc_fini(&uc->gsc);
354 intel_huc_fini(&uc->huc);
355 intel_guc_fini(&uc->guc);
356 }
357
__uc_sanitize(struct intel_uc * uc)358 static int __uc_sanitize(struct intel_uc *uc)
359 {
360 struct intel_guc *guc = &uc->guc;
361 struct intel_huc *huc = &uc->huc;
362
363 GEM_BUG_ON(!intel_uc_supports_guc(uc));
364
365 intel_huc_sanitize(huc);
366 intel_guc_sanitize(guc);
367
368 return __intel_uc_reset_hw(uc);
369 }
370
371 /* Initialize and verify the uC regs related to uC positioning in WOPCM */
uc_init_wopcm(struct intel_uc * uc)372 static int uc_init_wopcm(struct intel_uc *uc)
373 {
374 struct intel_gt *gt = uc_to_gt(uc);
375 struct intel_uncore *uncore = gt->uncore;
376 u32 base = intel_wopcm_guc_base(>->wopcm);
377 u32 size = intel_wopcm_guc_size(>->wopcm);
378 u32 huc_agent = intel_uc_uses_huc(uc) ? HUC_LOADING_AGENT_GUC : 0;
379 u32 mask;
380 int err;
381
382 if (unlikely(!base || !size)) {
383 gt_probe_error(gt, "Unsuccessful WOPCM partitioning\n");
384 return -E2BIG;
385 }
386
387 GEM_BUG_ON(!intel_uc_supports_guc(uc));
388 GEM_BUG_ON(!(base & GUC_WOPCM_OFFSET_MASK));
389 GEM_BUG_ON(base & ~GUC_WOPCM_OFFSET_MASK);
390 GEM_BUG_ON(!(size & GUC_WOPCM_SIZE_MASK));
391 GEM_BUG_ON(size & ~GUC_WOPCM_SIZE_MASK);
392
393 err = i915_inject_probe_error(gt->i915, -ENXIO);
394 if (err)
395 return err;
396
397 mask = GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED;
398 err = intel_uncore_write_and_verify(uncore, GUC_WOPCM_SIZE, size, mask,
399 size | GUC_WOPCM_SIZE_LOCKED);
400 if (err)
401 goto err_out;
402
403 mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent;
404 err = intel_uncore_write_and_verify(uncore, DMA_GUC_WOPCM_OFFSET,
405 base | huc_agent, mask,
406 base | huc_agent |
407 GUC_WOPCM_OFFSET_VALID);
408 if (err)
409 goto err_out;
410
411 return 0;
412
413 err_out:
414 gt_probe_error(gt, "Failed to init uC WOPCM registers!\n");
415 gt_probe_error(gt, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSET",
416 i915_mmio_reg_offset(DMA_GUC_WOPCM_OFFSET),
417 intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET));
418 gt_probe_error(gt, "%s(%#x)=%#x\n", "GUC_WOPCM_SIZE",
419 i915_mmio_reg_offset(GUC_WOPCM_SIZE),
420 intel_uncore_read(uncore, GUC_WOPCM_SIZE));
421
422 return err;
423 }
424
uc_is_wopcm_locked(struct intel_uc * uc)425 static bool uc_is_wopcm_locked(struct intel_uc *uc)
426 {
427 struct intel_gt *gt = uc_to_gt(uc);
428 struct intel_uncore *uncore = gt->uncore;
429
430 return (intel_uncore_read(uncore, GUC_WOPCM_SIZE) & GUC_WOPCM_SIZE_LOCKED) ||
431 (intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET) & GUC_WOPCM_OFFSET_VALID);
432 }
433
__uc_check_hw(struct intel_uc * uc)434 static int __uc_check_hw(struct intel_uc *uc)
435 {
436 if (uc->fw_table_invalid)
437 return -EIO;
438
439 if (!intel_uc_supports_guc(uc))
440 return 0;
441
442 /*
443 * We can silently continue without GuC only if it was never enabled
444 * before on this system after reboot, otherwise we risk GPU hangs.
445 * To check if GuC was loaded before we look at WOPCM registers.
446 */
447 if (uc_is_wopcm_locked(uc))
448 return -EIO;
449
450 return 0;
451 }
452
print_fw_ver(struct intel_gt * gt,struct intel_uc_fw * fw)453 static void print_fw_ver(struct intel_gt *gt, struct intel_uc_fw *fw)
454 {
455 gt_info(gt, "%s firmware %s version %u.%u.%u\n",
456 intel_uc_fw_type_repr(fw->type), fw->file_selected.path,
457 fw->file_selected.ver.major,
458 fw->file_selected.ver.minor,
459 fw->file_selected.ver.patch);
460 }
461
__uc_init_hw(struct intel_uc * uc)462 static int __uc_init_hw(struct intel_uc *uc)
463 {
464 struct intel_gt *gt = uc_to_gt(uc);
465 struct drm_i915_private *i915 = gt->i915;
466 struct intel_guc *guc = &uc->guc;
467 struct intel_huc *huc = &uc->huc;
468 int ret, attempts;
469 bool pl1en = false;
470
471 GEM_BUG_ON(!intel_uc_supports_guc(uc));
472 GEM_BUG_ON(!intel_uc_wants_guc(uc));
473
474 print_fw_ver(gt, &guc->fw);
475
476 if (intel_uc_uses_huc(uc))
477 print_fw_ver(gt, &huc->fw);
478
479 if (!intel_uc_fw_is_loadable(&guc->fw)) {
480 ret = __uc_check_hw(uc) ||
481 intel_uc_fw_is_overridden(&guc->fw) ||
482 intel_uc_wants_guc_submission(uc) ?
483 intel_uc_fw_status_to_error(guc->fw.status) : 0;
484 goto err_out;
485 }
486
487 ret = uc_init_wopcm(uc);
488 if (ret)
489 goto err_out;
490
491 intel_guc_reset_interrupts(guc);
492
493 /* WaEnableuKernelHeaderValidFix:skl */
494 /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
495 if (GRAPHICS_VER(i915) == 9)
496 attempts = 3;
497 else
498 attempts = 1;
499
500 /* Disable a potentially low PL1 power limit to allow freq to be raised */
501 i915_hwmon_power_max_disable(gt->i915, &pl1en);
502
503 intel_rps_raise_unslice(&uc_to_gt(uc)->rps);
504
505 while (attempts--) {
506 /*
507 * Always reset the GuC just before (re)loading, so
508 * that the state and timing are fairly predictable
509 */
510 ret = __uc_sanitize(uc);
511 if (ret)
512 goto err_rps;
513
514 intel_huc_fw_upload(huc);
515 intel_guc_ads_reset(guc);
516 intel_guc_write_params(guc);
517 ret = intel_guc_fw_upload(guc);
518 if (ret == 0)
519 break;
520
521 gt_dbg(gt, "GuC fw load failed (%pe) will reset and retry %d more time(s)\n",
522 ERR_PTR(ret), attempts);
523 }
524
525 /* Did we succeded or run out of retries? */
526 if (ret)
527 goto err_log_capture;
528
529 ret = guc_enable_communication(guc);
530 if (ret)
531 goto err_log_capture;
532
533 /*
534 * GSC-loaded HuC is authenticated by the GSC, so we don't need to
535 * trigger the auth here. However, given that the HuC loaded this way
536 * survive GT reset, we still need to update our SW bookkeeping to make
537 * sure it reflects the correct HW status.
538 */
539 if (intel_huc_is_loaded_by_gsc(huc))
540 intel_huc_update_auth_status(huc);
541 else
542 intel_huc_auth(huc, INTEL_HUC_AUTH_BY_GUC);
543
544 if (intel_uc_uses_guc_submission(uc)) {
545 ret = intel_guc_submission_enable(guc);
546 if (ret)
547 goto err_log_capture;
548 }
549
550 if (intel_uc_uses_guc_slpc(uc)) {
551 ret = intel_guc_slpc_enable(&guc->slpc);
552 if (ret)
553 goto err_submission;
554 } else {
555 /* Restore GT back to RPn for non-SLPC path */
556 intel_rps_lower_unslice(&uc_to_gt(uc)->rps);
557 }
558
559 i915_hwmon_power_max_restore(gt->i915, pl1en);
560
561 guc_info(guc, "submission %s\n", str_enabled_disabled(intel_uc_uses_guc_submission(uc)));
562 guc_info(guc, "SLPC %s\n", str_enabled_disabled(intel_uc_uses_guc_slpc(uc)));
563
564 return 0;
565
566 /*
567 * We've failed to load the firmware :(
568 */
569 err_submission:
570 intel_guc_submission_disable(guc);
571 err_log_capture:
572 __uc_capture_load_err_log(uc);
573 err_rps:
574 /* Return GT back to RPn */
575 intel_rps_lower_unslice(&uc_to_gt(uc)->rps);
576
577 i915_hwmon_power_max_restore(gt->i915, pl1en);
578 err_out:
579 __uc_sanitize(uc);
580
581 if (!ret) {
582 gt_notice(gt, "GuC is uninitialized\n");
583 /* We want to run without GuC submission */
584 return 0;
585 }
586
587 gt_probe_error(gt, "GuC initialization failed %pe\n", ERR_PTR(ret));
588
589 /* We want to keep KMS alive */
590 return -EIO;
591 }
592
__uc_fini_hw(struct intel_uc * uc)593 static void __uc_fini_hw(struct intel_uc *uc)
594 {
595 struct intel_guc *guc = &uc->guc;
596
597 if (!intel_guc_is_fw_running(guc))
598 return;
599
600 if (intel_uc_uses_guc_submission(uc))
601 intel_guc_submission_disable(guc);
602
603 __uc_sanitize(uc);
604 }
605
606 /**
607 * intel_uc_reset_prepare - Prepare for reset
608 * @uc: the intel_uc structure
609 *
610 * Preparing for full gpu reset.
611 */
intel_uc_reset_prepare(struct intel_uc * uc)612 void intel_uc_reset_prepare(struct intel_uc *uc)
613 {
614 struct intel_guc *guc = &uc->guc;
615
616 uc->reset_in_progress = true;
617
618 /* Nothing to do if GuC isn't supported */
619 if (!intel_uc_supports_guc(uc))
620 return;
621
622 /* Firmware expected to be running when this function is called */
623 if (!intel_guc_is_ready(guc))
624 goto sanitize;
625
626 if (intel_uc_uses_guc_submission(uc))
627 intel_guc_submission_reset_prepare(guc);
628
629 sanitize:
630 __uc_sanitize(uc);
631 }
632
intel_uc_reset(struct intel_uc * uc,intel_engine_mask_t stalled)633 void intel_uc_reset(struct intel_uc *uc, intel_engine_mask_t stalled)
634 {
635 struct intel_guc *guc = &uc->guc;
636
637 /* Firmware can not be running when this function is called */
638 if (intel_uc_uses_guc_submission(uc))
639 intel_guc_submission_reset(guc, stalled);
640 }
641
intel_uc_reset_finish(struct intel_uc * uc)642 void intel_uc_reset_finish(struct intel_uc *uc)
643 {
644 struct intel_guc *guc = &uc->guc;
645
646 uc->reset_in_progress = false;
647
648 /* Firmware expected to be running when this function is called */
649 if (intel_guc_is_fw_running(guc) && intel_uc_uses_guc_submission(uc))
650 intel_guc_submission_reset_finish(guc);
651 }
652
intel_uc_cancel_requests(struct intel_uc * uc)653 void intel_uc_cancel_requests(struct intel_uc *uc)
654 {
655 struct intel_guc *guc = &uc->guc;
656
657 /* Firmware can not be running when this function is called */
658 if (intel_uc_uses_guc_submission(uc))
659 intel_guc_submission_cancel_requests(guc);
660 }
661
intel_uc_runtime_suspend(struct intel_uc * uc)662 void intel_uc_runtime_suspend(struct intel_uc *uc)
663 {
664 struct intel_guc *guc = &uc->guc;
665
666 if (!intel_guc_is_ready(guc)) {
667 guc->interrupts.enabled = false;
668 return;
669 }
670
671 /*
672 * Wait for any outstanding CTB before tearing down communication /w the
673 * GuC.
674 */
675 #define OUTSTANDING_CTB_TIMEOUT_PERIOD (HZ / 5)
676 intel_guc_wait_for_pending_msg(guc, &guc->outstanding_submission_g2h,
677 false, OUTSTANDING_CTB_TIMEOUT_PERIOD);
678 GEM_WARN_ON(atomic_read(&guc->outstanding_submission_g2h));
679
680 guc_disable_communication(guc);
681 }
682
intel_uc_suspend(struct intel_uc * uc)683 void intel_uc_suspend(struct intel_uc *uc)
684 {
685 struct intel_guc *guc = &uc->guc;
686 intel_wakeref_t wakeref;
687 int err;
688
689 /* flush the GSC worker */
690 intel_gsc_uc_flush_work(&uc->gsc);
691
692 if (!intel_guc_is_ready(guc)) {
693 guc->interrupts.enabled = false;
694 return;
695 }
696
697 with_intel_runtime_pm(&uc_to_gt(uc)->i915->runtime_pm, wakeref) {
698 err = intel_guc_suspend(guc);
699 if (err)
700 guc_dbg(guc, "Failed to suspend, %pe", ERR_PTR(err));
701 }
702 }
703
__uc_resume_mappings(struct intel_uc * uc)704 static void __uc_resume_mappings(struct intel_uc *uc)
705 {
706 intel_uc_fw_resume_mapping(&uc->guc.fw);
707 intel_uc_fw_resume_mapping(&uc->huc.fw);
708 }
709
__uc_resume(struct intel_uc * uc,bool enable_communication)710 static int __uc_resume(struct intel_uc *uc, bool enable_communication)
711 {
712 struct intel_guc *guc = &uc->guc;
713 struct intel_gt *gt = guc_to_gt(guc);
714 int err;
715
716 if (!intel_guc_is_fw_running(guc))
717 return 0;
718
719 /* Make sure we enable communication if and only if it's disabled */
720 GEM_BUG_ON(enable_communication == intel_guc_ct_enabled(&guc->ct));
721
722 if (enable_communication)
723 guc_enable_communication(guc);
724
725 /* If we are only resuming GuC communication but not reloading
726 * GuC, we need to ensure the ARAT timer interrupt is enabled
727 * again. In case of GuC reload, it is enabled during SLPC enable.
728 */
729 if (enable_communication && intel_uc_uses_guc_slpc(uc))
730 intel_guc_pm_intrmsk_enable(gt);
731
732 err = intel_guc_resume(guc);
733 if (err) {
734 guc_dbg(guc, "Failed to resume, %pe", ERR_PTR(err));
735 return err;
736 }
737
738 intel_gsc_uc_resume(&uc->gsc);
739
740 return 0;
741 }
742
intel_uc_resume(struct intel_uc * uc)743 int intel_uc_resume(struct intel_uc *uc)
744 {
745 /*
746 * When coming out of S3/S4 we sanitize and re-init the HW, so
747 * communication is already re-enabled at this point.
748 */
749 return __uc_resume(uc, false);
750 }
751
intel_uc_runtime_resume(struct intel_uc * uc)752 int intel_uc_runtime_resume(struct intel_uc *uc)
753 {
754 /*
755 * During runtime resume we don't sanitize, so we need to re-init
756 * communication as well.
757 */
758 return __uc_resume(uc, true);
759 }
760
761 static const struct intel_uc_ops uc_ops_off = {
762 .init_hw = __uc_check_hw,
763 .fini = __uc_fini, /* to clean-up the init_early initialization */
764 };
765
766 static const struct intel_uc_ops uc_ops_on = {
767 .sanitize = __uc_sanitize,
768
769 .init_fw = __uc_fetch_firmwares,
770 .fini_fw = __uc_cleanup_firmwares,
771
772 .init = __uc_init,
773 .fini = __uc_fini,
774
775 .init_hw = __uc_init_hw,
776 .fini_hw = __uc_fini_hw,
777
778 .resume_mappings = __uc_resume_mappings,
779 };
780