1 /* 2 * Copyright 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef DRM_FOURCC_H 25 #define DRM_FOURCC_H 26 27 28 #if defined(__cplusplus) 29 extern "C" { 30 #endif 31 32 /** 33 * DOC: overview 34 * 35 * In the DRM subsystem, framebuffer pixel formats are described using the 36 * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the 37 * fourcc code, a Format Modifier may optionally be provided, in order to 38 * further describe the buffer's format - for example tiling or compression. 39 * 40 * Format Modifiers 41 * ---------------- 42 * 43 * Format modifiers are used in conjunction with a fourcc code, forming a 44 * unique fourcc:modifier pair. This format:modifier pair must fully define the 45 * format and data layout of the buffer, and should be the only way to describe 46 * that particular buffer. 47 * 48 * Having multiple fourcc:modifier pairs which describe the same layout should 49 * be avoided, as such aliases run the risk of different drivers exposing 50 * different names for the same data format, forcing userspace to understand 51 * that they are aliases. 52 * 53 * Format modifiers may change any property of the buffer, including the number 54 * of planes and/or the required allocation size. Format modifiers are 55 * vendor-namespaced, and as such the relationship between a fourcc code and a 56 * modifier is specific to the modifier being used. For example, some modifiers 57 * may preserve meaning - such as number of planes - from the fourcc code, 58 * whereas others may not. 59 * 60 * Modifiers must uniquely encode buffer layout. In other words, a buffer must 61 * match only a single modifier. A modifier must not be a subset of layouts of 62 * another modifier. For instance, it's incorrect to encode pitch alignment in 63 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel 64 * aligned modifier. That said, modifiers can have implicit minimal 65 * requirements. 66 * 67 * For modifiers where the combination of fourcc code and modifier can alias, 68 * a canonical pair needs to be defined and used by all drivers. Preferred 69 * combinations are also encouraged where all combinations might lead to 70 * confusion and unnecessarily reduced interoperability. An example for the 71 * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts. 72 * 73 * There are two kinds of modifier users: 74 * 75 * - Kernel and user-space drivers: for drivers it's important that modifiers 76 * don't alias, otherwise two drivers might support the same format but use 77 * different aliases, preventing them from sharing buffers in an efficient 78 * format. 79 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users 80 * see modifiers as opaque tokens they can check for equality and intersect. 81 * These users mustn't need to know to reason about the modifier value 82 * (i.e. they are not expected to extract information out of the modifier). 83 * 84 * Vendors should document their modifier usage in as much detail as 85 * possible, to ensure maximum compatibility across devices, drivers and 86 * applications. 87 * 88 * The authoritative list of format modifier codes is found in 89 * `include/uapi/drm/drm_fourcc.h` 90 * 91 * Open Source User Waiver 92 * ----------------------- 93 * 94 * Because this is the authoritative source for pixel formats and modifiers 95 * referenced by GL, Vulkan extensions and other standards and hence used both 96 * by open source and closed source driver stacks, the usual requirement for an 97 * upstream in-kernel or open source userspace user does not apply. 98 * 99 * To ensure, as much as feasible, compatibility across stacks and avoid 100 * confusion with incompatible enumerations stakeholders for all relevant driver 101 * stacks should approve additions. 102 */ 103 104 #define fourcc_code(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \ 105 ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24)) 106 107 #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */ 108 109 /* Reserve 0 for the invalid format specifier */ 110 #define DRM_FORMAT_INVALID 0 111 112 /* color index */ 113 #define DRM_FORMAT_C1 fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */ 114 #define DRM_FORMAT_C2 fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */ 115 #define DRM_FORMAT_C4 fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */ 116 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ 117 118 /* 1 bpp Darkness (inverse relationship between channel value and brightness) */ 119 #define DRM_FORMAT_D1 fourcc_code('D', '1', ' ', ' ') /* [7:0] D0:D1:D2:D3:D4:D5:D6:D7 1:1:1:1:1:1:1:1 eight pixels/byte */ 120 121 /* 2 bpp Darkness (inverse relationship between channel value and brightness) */ 122 #define DRM_FORMAT_D2 fourcc_code('D', '2', ' ', ' ') /* [7:0] D0:D1:D2:D3 2:2:2:2 four pixels/byte */ 123 124 /* 4 bpp Darkness (inverse relationship between channel value and brightness) */ 125 #define DRM_FORMAT_D4 fourcc_code('D', '4', ' ', ' ') /* [7:0] D0:D1 4:4 two pixels/byte */ 126 127 /* 8 bpp Darkness (inverse relationship between channel value and brightness) */ 128 #define DRM_FORMAT_D8 fourcc_code('D', '8', ' ', ' ') /* [7:0] D */ 129 130 /* 1 bpp Red (direct relationship between channel value and brightness) */ 131 #define DRM_FORMAT_R1 fourcc_code('R', '1', ' ', ' ') /* [7:0] R0:R1:R2:R3:R4:R5:R6:R7 1:1:1:1:1:1:1:1 eight pixels/byte */ 132 133 /* 2 bpp Red (direct relationship between channel value and brightness) */ 134 #define DRM_FORMAT_R2 fourcc_code('R', '2', ' ', ' ') /* [7:0] R0:R1:R2:R3 2:2:2:2 four pixels/byte */ 135 136 /* 4 bpp Red (direct relationship between channel value and brightness) */ 137 #define DRM_FORMAT_R4 fourcc_code('R', '4', ' ', ' ') /* [7:0] R0:R1 4:4 two pixels/byte */ 138 139 /* 8 bpp Red (direct relationship between channel value and brightness) */ 140 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ 141 142 /* 10 bpp Red (direct relationship between channel value and brightness) */ 143 #define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */ 144 145 /* 12 bpp Red (direct relationship between channel value and brightness) */ 146 #define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */ 147 148 /* 16 bpp Red (direct relationship between channel value and brightness) */ 149 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ 150 151 /* 16 bpp RG */ 152 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ 153 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ 154 155 /* 32 bpp RG */ 156 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */ 157 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */ 158 159 /* 8 bpp RGB */ 160 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ 161 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ 162 163 /* 16 bpp RGB */ 164 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */ 165 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */ 166 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */ 167 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */ 168 169 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */ 170 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */ 171 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */ 172 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */ 173 174 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */ 175 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */ 176 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */ 177 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */ 178 179 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */ 180 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */ 181 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */ 182 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */ 183 184 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ 185 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ 186 187 /* 24 bpp RGB */ 188 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ 189 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ 190 191 /* 32 bpp RGB */ 192 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */ 193 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */ 194 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */ 195 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */ 196 197 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */ 198 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */ 199 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */ 200 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */ 201 202 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */ 203 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */ 204 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */ 205 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */ 206 207 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */ 208 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */ 209 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ 210 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ 211 212 /* 48 bpp RGB */ 213 #define DRM_FORMAT_RGB161616 fourcc_code('R', 'G', '4', '8') /* [47:0] R:G:B 16:16:16 little endian */ 214 #define DRM_FORMAT_BGR161616 fourcc_code('B', 'G', '4', '8') /* [47:0] B:G:R 16:16:16 little endian */ 215 216 /* 64 bpp RGB */ 217 #define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */ 218 #define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */ 219 220 #define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */ 221 #define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */ 222 223 /* 224 * Half-Floating point - 16b/component 225 * IEEE 754-2008 binary16 half-precision float 226 * [15:0] sign:exponent:mantissa 1:5:10 227 */ 228 #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */ 229 #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */ 230 231 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ 232 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ 233 234 #define DRM_FORMAT_R16F fourcc_code('R', ' ', ' ', 'H') /* [15:0] R 16 little endian */ 235 #define DRM_FORMAT_GR1616F fourcc_code('G', 'R', ' ', 'H') /* [31:0] G:R 16:16 little endian */ 236 #define DRM_FORMAT_BGR161616F fourcc_code('B', 'G', 'R', 'H') /* [47:0] B:G:R 16:16:16 little endian */ 237 238 /* 239 * Floating point - 32b/component 240 * IEEE 754-2008 binary32 float 241 * [31:0] sign:exponent:mantissa 1:8:23 242 */ 243 #define DRM_FORMAT_R32F fourcc_code('R', ' ', ' ', 'F') /* [31:0] R 32 little endian */ 244 #define DRM_FORMAT_GR3232F fourcc_code('G', 'R', ' ', 'F') /* [63:0] R:G 32:32 little endian */ 245 #define DRM_FORMAT_BGR323232F fourcc_code('B', 'G', 'R', 'F') /* [95:0] R:G:B 32:32:32 little endian */ 246 #define DRM_FORMAT_ABGR32323232F fourcc_code('A', 'B', '8', 'F') /* [127:0] R:G:B:A 32:32:32:32 little endian */ 247 248 /* 249 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits 250 * of unused padding per component: 251 */ 252 #define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */ 253 254 /* packed YCbCr */ 255 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ 256 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ 257 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */ 258 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ 259 260 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ 261 #define DRM_FORMAT_AVUY8888 fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endian */ 262 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ 263 #define DRM_FORMAT_XVUY8888 fourcc_code('X', 'V', 'U', 'Y') /* [31:0] X:Cr:Cb:Y 8:8:8:8 little endian */ 264 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */ 265 #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */ 266 267 /* 268 * packed Y2xx indicate for each component, xx valid data occupy msb 269 * 16-xx padding occupy lsb 270 */ 271 #define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */ 272 #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */ 273 #define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */ 274 275 /* 276 * packed Y4xx indicate for each component, xx valid data occupy msb 277 * 16-xx padding occupy lsb except Y410 278 */ 279 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */ 280 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 281 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */ 282 283 #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */ 284 #define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 285 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */ 286 287 /* 288 * packed YCbCr420 2x2 tiled formats 289 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile 290 */ 291 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 292 #define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0') 293 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 294 #define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0') 295 296 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 297 #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2') 298 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 299 #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2') 300 301 /* 302 * 1-plane YUV 4:2:0 303 * In these formats, the component ordering is specified (Y, followed by U 304 * then V), but the exact Linear layout is undefined. 305 * These formats can only be used with a non-Linear modifier. 306 */ 307 #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8') 308 #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0') 309 310 /* 311 * 2 plane RGB + A 312 * index 0 = RGB plane, same format as the corresponding non _A8 format has 313 * index 1 = A plane, [7:0] A 314 */ 315 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8') 316 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8') 317 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8') 318 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8') 319 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8') 320 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8') 321 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8') 322 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8') 323 324 /* 325 * 2 plane YCbCr 326 * index 0 = Y plane, [7:0] Y 327 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian 328 * or 329 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian 330 */ 331 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ 332 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ 333 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ 334 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ 335 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ 336 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ 337 /* 338 * 2 plane YCbCr 339 * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian 340 * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian 341 */ 342 #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */ 343 #define DRM_FORMAT_NV20 fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */ 344 #define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */ 345 346 /* 347 * 2 plane YCbCr MSB aligned 348 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 349 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 350 */ 351 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */ 352 353 /* 354 * 2 plane YCbCr MSB aligned 355 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 356 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 357 */ 358 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */ 359 360 /* 361 * 2 plane YCbCr MSB aligned 362 * index 0 = Y plane, [15:0] Y:x [12:4] little endian 363 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian 364 */ 365 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */ 366 367 /* 368 * 2 plane YCbCr MSB aligned 369 * index 0 = Y plane, [15:0] Y little endian 370 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian 371 */ 372 #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */ 373 374 /* 2 plane YCbCr420. 375 * 3 10 bit components and 2 padding bits packed into 4 bytes. 376 * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian 377 * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian 378 */ 379 #define DRM_FORMAT_P030 fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel packed */ 380 381 /* 3 plane non-subsampled (444) YCbCr 382 * 16 bits per component, but only 10 bits are used and 6 bits are padded 383 * index 0: Y plane, [15:0] Y:x [10:6] little endian 384 * index 1: Cb plane, [15:0] Cb:x [10:6] little endian 385 * index 2: Cr plane, [15:0] Cr:x [10:6] little endian 386 */ 387 #define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0') 388 389 /* 3 plane non-subsampled (444) YCrCb 390 * 16 bits per component, but only 10 bits are used and 6 bits are padded 391 * index 0: Y plane, [15:0] Y:x [10:6] little endian 392 * index 1: Cr plane, [15:0] Cr:x [10:6] little endian 393 * index 2: Cb plane, [15:0] Cb:x [10:6] little endian 394 */ 395 #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1') 396 397 /* 398 * 3 plane YCbCr LSB aligned 399 * In order to use these formats in a similar fashion to MSB aligned ones 400 * implementation can multiply the values by 2^6=64. For that reason the padding 401 * must only contain zeros. 402 * index 0 = Y plane, [15:0] z:Y [6:10] little endian 403 * index 1 = Cr plane, [15:0] z:Cr [6:10] little endian 404 * index 2 = Cb plane, [15:0] z:Cb [6:10] little endian 405 */ 406 #define DRM_FORMAT_S010 fourcc_code('S', '0', '1', '0') /* 2x2 subsampled Cb (1) and Cr (2) planes 10 bits per channel */ 407 #define DRM_FORMAT_S210 fourcc_code('S', '2', '1', '0') /* 2x1 subsampled Cb (1) and Cr (2) planes 10 bits per channel */ 408 #define DRM_FORMAT_S410 fourcc_code('S', '4', '1', '0') /* non-subsampled Cb (1) and Cr (2) planes 10 bits per channel */ 409 410 /* 411 * 3 plane YCbCr LSB aligned 412 * In order to use these formats in a similar fashion to MSB aligned ones 413 * implementation can multiply the values by 2^4=16. For that reason the padding 414 * must only contain zeros. 415 * index 0 = Y plane, [15:0] z:Y [4:12] little endian 416 * index 1 = Cr plane, [15:0] z:Cr [4:12] little endian 417 * index 2 = Cb plane, [15:0] z:Cb [4:12] little endian 418 */ 419 #define DRM_FORMAT_S012 fourcc_code('S', '0', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes 12 bits per channel */ 420 #define DRM_FORMAT_S212 fourcc_code('S', '2', '1', '2') /* 2x1 subsampled Cb (1) and Cr (2) planes 12 bits per channel */ 421 #define DRM_FORMAT_S412 fourcc_code('S', '4', '1', '2') /* non-subsampled Cb (1) and Cr (2) planes 12 bits per channel */ 422 423 /* 424 * 3 plane YCbCr 425 * index 0 = Y plane, [15:0] Y little endian 426 * index 1 = Cr plane, [15:0] Cr little endian 427 * index 2 = Cb plane, [15:0] Cb little endian 428 */ 429 #define DRM_FORMAT_S016 fourcc_code('S', '0', '1', '6') /* 2x2 subsampled Cb (1) and Cr (2) planes 16 bits per channel */ 430 #define DRM_FORMAT_S216 fourcc_code('S', '2', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes 16 bits per channel */ 431 #define DRM_FORMAT_S416 fourcc_code('S', '4', '1', '6') /* non-subsampled Cb (1) and Cr (2) planes 16 bits per channel */ 432 433 /* 434 * 3 plane YCbCr 435 * index 0: Y plane, [7:0] Y 436 * index 1: Cb plane, [7:0] Cb 437 * index 2: Cr plane, [7:0] Cr 438 * or 439 * index 1: Cr plane, [7:0] Cr 440 * index 2: Cb plane, [7:0] Cb 441 */ 442 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */ 443 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */ 444 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */ 445 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */ 446 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ 447 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */ 448 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */ 449 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */ 450 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ 451 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ 452 453 454 /* 455 * Format Modifiers: 456 * 457 * Format modifiers describe, typically, a re-ordering or modification 458 * of the data in a plane of an FB. This can be used to express tiled/ 459 * swizzled formats, or compression, or a combination of the two. 460 * 461 * The upper 8 bits of the format modifier are a vendor-id as assigned 462 * below. The lower 56 bits are assigned as vendor sees fit. 463 */ 464 465 /* Vendor Ids: */ 466 #define DRM_FORMAT_MOD_VENDOR_NONE 0 467 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 468 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 469 #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03 470 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 471 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 472 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 473 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 474 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 475 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 476 #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a 477 #define DRM_FORMAT_MOD_VENDOR_MTK 0x0b 478 #define DRM_FORMAT_MOD_VENDOR_APPLE 0x0c 479 480 /* add more to the end as needed */ 481 482 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) 483 484 #define fourcc_mod_get_vendor(modifier) \ 485 (((modifier) >> 56) & 0xff) 486 487 #define fourcc_mod_is_vendor(modifier, vendor) \ 488 (fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_## vendor) 489 490 #define fourcc_mod_code(vendor, val) \ 491 ((((uint64_t)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) 492 493 /* 494 * Format Modifier tokens: 495 * 496 * When adding a new token please document the layout with a code comment, 497 * similar to the fourcc codes above. drm_fourcc.h is considered the 498 * authoritative source for all of these. 499 * 500 * Generic modifier names: 501 * 502 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names 503 * for layouts which are common across multiple vendors. To preserve 504 * compatibility, in cases where a vendor-specific definition already exists and 505 * a generic name for it is desired, the common name is a purely symbolic alias 506 * and must use the same numerical value as the original definition. 507 * 508 * Note that generic names should only be used for modifiers which describe 509 * generic layouts (such as pixel re-ordering), which may have 510 * independently-developed support across multiple vendors. 511 * 512 * In future cases where a generic layout is identified before merging with a 513 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor 514 * 'NONE' could be considered. This should only be for obvious, exceptional 515 * cases to avoid polluting the 'GENERIC' namespace with modifiers which only 516 * apply to a single vendor. 517 * 518 * Generic names should not be used for cases where multiple hardware vendors 519 * have implementations of the same standardised compression scheme (such as 520 * AFBC). In those cases, all implementations should use the same format 521 * modifier(s), reflecting the vendor of the standard. 522 */ 523 524 #define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE 525 526 /* 527 * Invalid Modifier 528 * 529 * This modifier can be used as a sentinel to terminate the format modifiers 530 * list, or to initialize a variable with an invalid modifier. It might also be 531 * used to report an error back to userspace for certain APIs. 532 */ 533 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) 534 535 /* 536 * Linear Layout 537 * 538 * Just plain linear layout. Note that this is different from no specifying any 539 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl), 540 * which tells the driver to also take driver-internal information into account 541 * and so might actually result in a tiled framebuffer. 542 */ 543 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) 544 545 /* 546 * Deprecated: use DRM_FORMAT_MOD_LINEAR instead 547 * 548 * The "none" format modifier doesn't actually mean that the modifier is 549 * implicit, instead it means that the layout is linear. Whether modifiers are 550 * used is out-of-band information carried in an API-specific way (e.g. in a 551 * flag for drm_mode_fb_cmd2). 552 */ 553 #define DRM_FORMAT_MOD_NONE 0 554 555 /* Intel framebuffer modifiers */ 556 557 /* 558 * Intel X-tiling layout 559 * 560 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 561 * in row-major layout. Within the tile bytes are laid out row-major, with 562 * a platform-dependent stride. On top of that the memory can apply 563 * platform-depending swizzling of some higher address bits into bit6. 564 * 565 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 566 * On earlier platforms the is highly platforms specific and not useful for 567 * cross-driver sharing. It exists since on a given platform it does uniquely 568 * identify the layout in a simple way for i915-specific userspace, which 569 * facilitated conversion of userspace to modifiers. Additionally the exact 570 * format on some really old platforms is not known. 571 */ 572 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) 573 574 /* 575 * Intel Y-tiling layout 576 * 577 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 578 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) 579 * chunks column-major, with a platform-dependent height. On top of that the 580 * memory can apply platform-depending swizzling of some higher address bits 581 * into bit6. 582 * 583 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 584 * On earlier platforms the is highly platforms specific and not useful for 585 * cross-driver sharing. It exists since on a given platform it does uniquely 586 * identify the layout in a simple way for i915-specific userspace, which 587 * facilitated conversion of userspace to modifiers. Additionally the exact 588 * format on some really old platforms is not known. 589 */ 590 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) 591 592 /* 593 * Intel Yf-tiling layout 594 * 595 * This is a tiled layout using 4Kb tiles in row-major layout. 596 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which 597 * are arranged in four groups (two wide, two high) with column-major layout. 598 * Each group therefore consists out of four 256 byte units, which are also laid 599 * out as 2x2 column-major. 600 * 256 byte units are made out of four 64 byte blocks of pixels, producing 601 * either a square block or a 2:1 unit. 602 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width 603 * in pixel depends on the pixel depth. 604 */ 605 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) 606 607 /* 608 * Intel color control surface (CCS) for render compression 609 * 610 * The framebuffer format must be one of the 8:8:8:8 RGB formats. 611 * The main surface will be plane index 0 and must be Y/Yf-tiled, 612 * the CCS will be plane index 1. 613 * 614 * Each CCS tile matches a 1024x512 pixel area of the main surface. 615 * To match certain aspects of the 3D hardware the CCS is 616 * considered to be made up of normal 128Bx32 Y tiles, Thus 617 * the CCS pitch must be specified in multiples of 128 bytes. 618 * 619 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed 620 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks. 621 * But that fact is not relevant unless the memory is accessed 622 * directly. 623 */ 624 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) 625 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) 626 627 /* 628 * Intel color control surfaces (CCS) for Gen-12 render compression. 629 * 630 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 631 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 632 * main surface. In other words, 4 bits in CCS map to a main surface cache 633 * line pair. The main surface pitch is required to be a multiple of four 634 * Y-tile widths. 635 */ 636 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) 637 638 /* 639 * Intel color control surfaces (CCS) for Gen-12 media compression 640 * 641 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 642 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 643 * main surface. In other words, 4 bits in CCS map to a main surface cache 644 * line pair. The main surface pitch is required to be a multiple of four 645 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the 646 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, 647 * planes 2 and 3 for the respective CCS. 648 */ 649 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) 650 651 /* 652 * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render 653 * compression. 654 * 655 * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear 656 * and at index 1. The clear color is stored at index 2, and the pitch should 657 * be 64 bytes aligned. The clear color structure is 256 bits. The first 128 bits 658 * represents Raw Clear Color Red, Green, Blue and Alpha color each represented 659 * by 32 bits. The raw clear color is consumed by the 3d engine and generates 660 * the converted clear color of size 64 bits. The first 32 bits store the Lower 661 * Converted Clear Color value and the next 32 bits store the Higher Converted 662 * Clear Color value when applicable. The Converted Clear Color values are 663 * consumed by the DE. The last 64 bits are used to store Color Discard Enable 664 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line 665 * corresponds to an area of 4x1 tiles in the main surface. The main surface 666 * pitch is required to be a multiple of 4 tile widths. 667 */ 668 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8) 669 670 /* 671 * Intel Tile 4 layout 672 * 673 * This is a tiled layout using 4KB tiles in a row-major layout. It has the same 674 * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It 675 * only differs from Tile Y at the 256B granularity in between. At this 676 * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape 677 * of 64B x 8 rows. 678 */ 679 #define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9) 680 681 /* 682 * Intel color control surfaces (CCS) for DG2 render compression. 683 * 684 * The main surface is Tile 4 and at plane index 0. The CCS data is stored 685 * outside of the GEM object in a reserved memory area dedicated for the 686 * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The 687 * main surface pitch is required to be a multiple of four Tile 4 widths. 688 */ 689 #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10) 690 691 /* 692 * Intel color control surfaces (CCS) for DG2 media compression. 693 * 694 * The main surface is Tile 4 and at plane index 0. For semi-planar formats 695 * like NV12, the Y and UV planes are Tile 4 and are located at plane indices 696 * 0 and 1, respectively. The CCS for all planes are stored outside of the 697 * GEM object in a reserved memory area dedicated for the storage of the 698 * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface 699 * pitch is required to be a multiple of four Tile 4 widths. 700 */ 701 #define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11) 702 703 /* 704 * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression. 705 * 706 * The main surface is Tile 4 and at plane index 0. The CCS data is stored 707 * outside of the GEM object in a reserved memory area dedicated for the 708 * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The 709 * main surface pitch is required to be a multiple of four Tile 4 widths. The 710 * clear color is stored at plane index 1 and the pitch should be 64 bytes 711 * aligned. The format of the 256 bits of clear color data matches the one used 712 * for the I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description 713 * for details. 714 */ 715 #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12) 716 717 /* 718 * Intel Color Control Surfaces (CCS) for display ver. 14 render compression. 719 * 720 * The main surface is tile4 and at plane index 0, the CCS is linear and 721 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 722 * main surface. In other words, 4 bits in CCS map to a main surface cache 723 * line pair. The main surface pitch is required to be a multiple of four 724 * tile4 widths. 725 */ 726 #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS fourcc_mod_code(INTEL, 13) 727 728 /* 729 * Intel Color Control Surfaces (CCS) for display ver. 14 media compression 730 * 731 * The main surface is tile4 and at plane index 0, the CCS is linear and 732 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 733 * main surface. In other words, 4 bits in CCS map to a main surface cache 734 * line pair. The main surface pitch is required to be a multiple of four 735 * tile4 widths. For semi-planar formats like NV12, CCS planes follow the 736 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, 737 * planes 2 and 3 for the respective CCS. 738 */ 739 #define I915_FORMAT_MOD_4_TILED_MTL_MC_CCS fourcc_mod_code(INTEL, 14) 740 741 /* 742 * Intel Color Control Surface with Clear Color (CCS) for display ver. 14 render 743 * compression. 744 * 745 * The main surface is tile4 and is at plane index 0 whereas CCS is linear 746 * and at index 1. The clear color is stored at index 2, and the pitch should 747 * be ignored. The clear color structure is 256 bits. The first 128 bits 748 * represents Raw Clear Color Red, Green, Blue and Alpha color each represented 749 * by 32 bits. The raw clear color is consumed by the 3d engine and generates 750 * the converted clear color of size 64 bits. The first 32 bits store the Lower 751 * Converted Clear Color value and the next 32 bits store the Higher Converted 752 * Clear Color value when applicable. The Converted Clear Color values are 753 * consumed by the DE. The last 64 bits are used to store Color Discard Enable 754 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line 755 * corresponds to an area of 4x1 tiles in the main surface. The main surface 756 * pitch is required to be a multiple of 4 tile widths. 757 */ 758 #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15) 759 760 /* 761 * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression 762 * on integrated graphics 763 * 764 * The main surface is Tile 4 and at plane index 0. For semi-planar formats 765 * like NV12, the Y and UV planes are Tile 4 and are located at plane indices 766 * 0 and 1, respectively. The CCS for all planes are stored outside of the 767 * GEM object in a reserved memory area dedicated for the storage of the 768 * CCS data for all compressible GEM objects. 769 */ 770 #define I915_FORMAT_MOD_4_TILED_LNL_CCS fourcc_mod_code(INTEL, 16) 771 772 /* 773 * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression 774 * on discrete graphics 775 * 776 * The main surface is Tile 4 and at plane index 0. For semi-planar formats 777 * like NV12, the Y and UV planes are Tile 4 and are located at plane indices 778 * 0 and 1, respectively. The CCS for all planes are stored outside of the 779 * GEM object in a reserved memory area dedicated for the storage of the 780 * CCS data for all compressible GEM objects. The GEM object must be stored in 781 * contiguous memory with a size aligned to 64KB 782 */ 783 #define I915_FORMAT_MOD_4_TILED_BMG_CCS fourcc_mod_code(INTEL, 17) 784 785 /* 786 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks 787 * 788 * Macroblocks are laid in a Z-shape, and each pixel data is following the 789 * standard NV12 style. 790 * As for NV12, an image is the result of two frame buffers: one for Y, 791 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). 792 * Alignment requirements are (for each buffer): 793 * - multiple of 128 pixels for the width 794 * - multiple of 32 pixels for the height 795 * 796 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html 797 */ 798 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) 799 800 /* 801 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks 802 * 803 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major 804 * layout. For YCbCr formats Cb/Cr components are taken in such a way that 805 * they correspond to their 16x16 luma block. 806 */ 807 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2) 808 809 /* 810 * Qualcomm Compressed Format 811 * 812 * Refers to a compressed variant of the base format that is compressed. 813 * Implementation may be platform and base-format specific. 814 * 815 * Each macrotile consists of m x n (mostly 4 x 4) tiles. 816 * Pixel data pitch/stride is aligned with macrotile width. 817 * Pixel data height is aligned with macrotile height. 818 * Entire pixel data buffer is aligned with 4k(bytes). 819 */ 820 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1) 821 822 /* 823 * Qualcomm Tiled Format 824 * 825 * Similar to DRM_FORMAT_MOD_QCOM_COMPRESSED but not compressed. 826 * Implementation may be platform and base-format specific. 827 * 828 * Each macrotile consists of m x n (mostly 4 x 4) tiles. 829 * Pixel data pitch/stride is aligned with macrotile width. 830 * Pixel data height is aligned with macrotile height. 831 * Entire pixel data buffer is aligned with 4k(bytes). 832 */ 833 #define DRM_FORMAT_MOD_QCOM_TILED3 fourcc_mod_code(QCOM, 3) 834 835 /* 836 * Qualcomm Alternate Tiled Format 837 * 838 * Alternate tiled format typically only used within GMEM. 839 * Implementation may be platform and base-format specific. 840 */ 841 #define DRM_FORMAT_MOD_QCOM_TILED2 fourcc_mod_code(QCOM, 2) 842 843 844 /* Vivante framebuffer modifiers */ 845 846 /* 847 * Vivante 4x4 tiling layout 848 * 849 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major 850 * layout. 851 */ 852 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) 853 854 /* 855 * Vivante 64x64 super-tiling layout 856 * 857 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile 858 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- 859 * major layout. 860 * 861 * For more information: see 862 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling 863 */ 864 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) 865 866 /* 867 * Vivante 4x4 tiling layout for dual-pipe 868 * 869 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a 870 * different base address. Offsets from the base addresses are therefore halved 871 * compared to the non-split tiled layout. 872 */ 873 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) 874 875 /* 876 * Vivante 64x64 super-tiling layout for dual-pipe 877 * 878 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile 879 * starts at a different base address. Offsets from the base addresses are 880 * therefore halved compared to the non-split super-tiled layout. 881 */ 882 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) 883 884 /* 885 * Vivante TS (tile-status) buffer modifiers. They can be combined with all of 886 * the color buffer tiling modifiers defined above. When TS is present it's a 887 * separate buffer containing the clear/compression status of each tile. The 888 * modifiers are defined as VIVANTE_MOD_TS_c_s, where c is the color buffer 889 * tile size in bytes covered by one entry in the status buffer and s is the 890 * number of status bits per entry. 891 * We reserve the top 8 bits of the Vivante modifier space for tile status 892 * clear/compression modifiers, as future cores might add some more TS layout 893 * variations. 894 */ 895 #define VIVANTE_MOD_TS_64_4 (1ULL << 48) 896 #define VIVANTE_MOD_TS_64_2 (2ULL << 48) 897 #define VIVANTE_MOD_TS_128_4 (3ULL << 48) 898 #define VIVANTE_MOD_TS_256_4 (4ULL << 48) 899 #define VIVANTE_MOD_TS_MASK (0xfULL << 48) 900 901 /* 902 * Vivante compression modifiers. Those depend on a TS modifier being present 903 * as the TS bits get reinterpreted as compression tags instead of simple 904 * clear markers when compression is enabled. 905 */ 906 #define VIVANTE_MOD_COMP_DEC400 (1ULL << 52) 907 #define VIVANTE_MOD_COMP_MASK (0xfULL << 52) 908 909 /* Masking out the extension bits will yield the base modifier. */ 910 #define VIVANTE_MOD_EXT_MASK (VIVANTE_MOD_TS_MASK | \ 911 VIVANTE_MOD_COMP_MASK) 912 913 /* NVIDIA frame buffer modifiers */ 914 915 /* 916 * Tegra Tiled Layout, used by Tegra 2, 3 and 4. 917 * 918 * Pixels are arranged in simple tiles of 16 x 16 bytes. 919 */ 920 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) 921 922 /* 923 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80, 924 * and Tegra GPUs starting with Tegra K1. 925 * 926 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies 927 * based on the architecture generation. GOBs themselves are then arranged in 928 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power 929 * of two, and hence expressible as their log2 equivalent (E.g., "2" represents 930 * a block depth or height of "4"). 931 * 932 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 933 * in full detail. 934 * 935 * Macro 936 * Bits Param Description 937 * ---- ----- ----------------------------------------------------------------- 938 * 939 * 3:0 h log2(height) of each block, in GOBs. Placed here for 940 * compatibility with the existing 941 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 942 * 943 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for 944 * compatibility with the existing 945 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 946 * 947 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block 948 * size). Must be zero. 949 * 950 * Note there is no log2(width) parameter. Some portions of the 951 * hardware support a block width of two gobs, but it is impractical 952 * to use due to lack of support elsewhere, and has no known 953 * benefits. 954 * 955 * 11:9 - Reserved (To support 2D-array textures with variable array stride 956 * in blocks, specified via log2(tile width in blocks)). Must be 957 * zero. 958 * 959 * 19:12 k Page Kind. This value directly maps to a field in the page 960 * tables of all GPUs >= NV50. It affects the exact layout of bits 961 * in memory and can be derived from the tuple 962 * 963 * (format, GPU model, compression type, samples per pixel) 964 * 965 * Where compression type is defined below. If GPU model were 966 * implied by the format modifier, format, or memory buffer, page 967 * kind would not need to be included in the modifier itself, but 968 * since the modifier should define the layout of the associated 969 * memory buffer independent from any device or other context, it 970 * must be included here. 971 * 972 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed 973 * starting with Fermi GPUs. Additionally, the mapping between page 974 * kind and bit layout has changed at various points. 975 * 976 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping 977 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping 978 * 2 = Gob Height 8, Turing+ Page Kind mapping 979 * 3 = Reserved for future use. 980 * 981 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further 982 * bit remapping step that occurs at an even lower level than the 983 * page kind and block linear swizzles. This causes the layout of 984 * surfaces mapped in those SOC's GPUs to be incompatible with the 985 * equivalent mapping on other GPUs in the same system. 986 * 987 * 0 = Tegra K1 - Tegra Parker/TX2 Layout. 988 * 1 = Desktop GPU and Tegra Xavier+ Layout 989 * 990 * 25:23 c Lossless Framebuffer Compression type. 991 * 992 * 0 = none 993 * 1 = ROP/3D, layout 1, exact compression format implied by Page 994 * Kind field 995 * 2 = ROP/3D, layout 2, exact compression format implied by Page 996 * Kind field 997 * 3 = CDE horizontal 998 * 4 = CDE vertical 999 * 5 = Reserved for future use 1000 * 6 = Reserved for future use 1001 * 7 = Reserved for future use 1002 * 1003 * 55:25 - Reserved for future use. Must be zero. 1004 */ 1005 #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ 1006 fourcc_mod_code(NVIDIA, (0x10 | \ 1007 ((h) & 0xf) | \ 1008 (((k) & 0xff) << 12) | \ 1009 (((g) & 0x3) << 20) | \ 1010 (((s) & 0x1) << 22) | \ 1011 (((c) & 0x7) << 23))) 1012 1013 /* To grandfather in prior block linear format modifiers to the above layout, 1014 * the page kind "0", which corresponds to "pitch/linear" and hence is unusable 1015 * with block-linear layouts, is remapped within drivers to the value 0xfe, 1016 * which corresponds to the "generic" kind used for simple single-sample 1017 * uncompressed color formats on Fermi - Volta GPUs. 1018 */ 1019 static inline uint64_t 1020 drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier) 1021 { 1022 if (!(modifier & 0x10) || (modifier & (0xff << 12))) 1023 return modifier; 1024 else 1025 return modifier | (0xfe << 12); 1026 } 1027 1028 /* 1029 * 16Bx2 Block Linear layout, used by Tegra K1 and later 1030 * 1031 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked 1032 * vertically by a power of 2 (1 to 32 GOBs) to form a block. 1033 * 1034 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape. 1035 * 1036 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically. 1037 * Valid values are: 1038 * 1039 * 0 == ONE_GOB 1040 * 1 == TWO_GOBS 1041 * 2 == FOUR_GOBS 1042 * 3 == EIGHT_GOBS 1043 * 4 == SIXTEEN_GOBS 1044 * 5 == THIRTYTWO_GOBS 1045 * 1046 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 1047 * in full detail. 1048 */ 1049 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ 1050 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v)) 1051 1052 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ 1053 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0) 1054 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ 1055 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1) 1056 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ 1057 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2) 1058 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ 1059 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3) 1060 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ 1061 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4) 1062 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ 1063 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5) 1064 1065 /* 1066 * Some Broadcom modifiers take parameters, for example the number of 1067 * vertical lines in the image. Reserve the lower 32 bits for modifier 1068 * type, and the next 24 bits for parameters. Top 8 bits are the 1069 * vendor code. 1070 */ 1071 #define __fourcc_mod_broadcom_param_shift 8 1072 #define __fourcc_mod_broadcom_param_bits 48 1073 #define fourcc_mod_broadcom_code(val, params) \ 1074 fourcc_mod_code(BROADCOM, ((((uint64_t)params) << __fourcc_mod_broadcom_param_shift) | val)) 1075 #define fourcc_mod_broadcom_param(m) \ 1076 ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \ 1077 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1))) 1078 #define fourcc_mod_broadcom_mod(m) \ 1079 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \ 1080 __fourcc_mod_broadcom_param_shift)) 1081 1082 /* 1083 * Broadcom VC4 "T" format 1084 * 1085 * This is the primary layout that the V3D GPU can texture from (it 1086 * can't do linear). The T format has: 1087 * 1088 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4 1089 * pixels at 32 bit depth. 1090 * 1091 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually 1092 * 16x16 pixels). 1093 * 1094 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On 1095 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows 1096 * they're (TR, BR, BL, TL), where bottom left is start of memory. 1097 * 1098 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k 1099 * tiles) or right-to-left (odd rows of 4k tiles). 1100 */ 1101 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1) 1102 1103 /* 1104 * Broadcom SAND format 1105 * 1106 * This is the native format that the H.264 codec block uses. For VC4 1107 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes. 1108 * 1109 * The image can be considered to be split into columns, and the 1110 * columns are placed consecutively into memory. The width of those 1111 * columns can be either 32, 64, 128, or 256 pixels, but in practice 1112 * only 128 pixel columns are used. 1113 * 1114 * The pitch between the start of each column is set to optimally 1115 * switch between SDRAM banks. This is passed as the number of lines 1116 * of column width in the modifier (we can't use the stride value due 1117 * to various core checks that look at it , so you should set the 1118 * stride to width*cpp). 1119 * 1120 * Note that the column height for this format modifier is the same 1121 * for all of the planes, assuming that each column contains both Y 1122 * and UV. Some SAND-using hardware stores UV in a separate tiled 1123 * image from Y to reduce the column height, which is not supported 1124 * with these modifiers. 1125 * 1126 * The DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT modifier is also 1127 * supported for DRM_FORMAT_P030 where the columns remain as 128 bytes 1128 * wide, but as this is a 10 bpp format that translates to 96 pixels. 1129 */ 1130 1131 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \ 1132 fourcc_mod_broadcom_code(2, v) 1133 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \ 1134 fourcc_mod_broadcom_code(3, v) 1135 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \ 1136 fourcc_mod_broadcom_code(4, v) 1137 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \ 1138 fourcc_mod_broadcom_code(5, v) 1139 1140 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \ 1141 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0) 1142 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \ 1143 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0) 1144 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \ 1145 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0) 1146 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \ 1147 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0) 1148 1149 /* Broadcom UIF format 1150 * 1151 * This is the common format for the current Broadcom multimedia 1152 * blocks, including V3D 3.x and newer, newer video codecs, and 1153 * displays. 1154 * 1155 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles), 1156 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are 1157 * stored in columns, with padding between the columns to ensure that 1158 * moving from one column to the next doesn't hit the same SDRAM page 1159 * bank. 1160 * 1161 * To calculate the padding, it is assumed that each hardware block 1162 * and the software driving it knows the platform's SDRAM page size, 1163 * number of banks, and XOR address, and that it's identical between 1164 * all blocks using the format. This tiling modifier will use XOR as 1165 * necessary to reduce the padding. If a hardware block can't do XOR, 1166 * the assumption is that a no-XOR tiling modifier will be created. 1167 */ 1168 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6) 1169 1170 /* 1171 * Arm Framebuffer Compression (AFBC) modifiers 1172 * 1173 * AFBC is a proprietary lossless image compression protocol and format. 1174 * It provides fine-grained random access and minimizes the amount of data 1175 * transferred between IP blocks. 1176 * 1177 * AFBC has several features which may be supported and/or used, which are 1178 * represented using bits in the modifier. Not all combinations are valid, 1179 * and different devices or use-cases may support different combinations. 1180 * 1181 * Further information on the use of AFBC modifiers can be found in 1182 * Documentation/gpu/afbc.rst 1183 */ 1184 1185 /* 1186 * The top 4 bits (out of the 56 bits allotted for specifying vendor specific 1187 * modifiers) denote the category for modifiers. Currently we have three 1188 * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of 1189 * sixteen different categories. 1190 */ 1191 #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \ 1192 fourcc_mod_code(ARM, ((uint64_t)(__type) << 52) | ((__val) & 0x000fffffffffffffULL)) 1193 1194 #define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00 1195 #define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01 1196 1197 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \ 1198 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode) 1199 1200 /* 1201 * AFBC superblock size 1202 * 1203 * Indicates the superblock size(s) used for the AFBC buffer. The buffer 1204 * size (in pixels) must be aligned to a multiple of the superblock size. 1205 * Four lowest significant bits(LSBs) are reserved for block size. 1206 * 1207 * Where one superblock size is specified, it applies to all planes of the 1208 * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified, 1209 * the first applies to the Luma plane and the second applies to the Chroma 1210 * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma). 1211 * Multiple superblock sizes are only valid for multi-plane YCbCr formats. 1212 */ 1213 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf 1214 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL) 1215 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL) 1216 #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL) 1217 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL) 1218 1219 /* 1220 * AFBC lossless colorspace transform 1221 * 1222 * Indicates that the buffer makes use of the AFBC lossless colorspace 1223 * transform. 1224 */ 1225 #define AFBC_FORMAT_MOD_YTR (1ULL << 4) 1226 1227 /* 1228 * AFBC block-split 1229 * 1230 * Indicates that the payload of each superblock is split. The second 1231 * half of the payload is positioned at a predefined offset from the start 1232 * of the superblock payload. 1233 */ 1234 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5) 1235 1236 /* 1237 * AFBC sparse layout 1238 * 1239 * This flag indicates that the payload of each superblock must be stored at a 1240 * predefined position relative to the other superblocks in the same AFBC 1241 * buffer. This order is the same order used by the header buffer. In this mode 1242 * each superblock is given the same amount of space as an uncompressed 1243 * superblock of the particular format would require, rounding up to the next 1244 * multiple of 128 bytes in size. 1245 */ 1246 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6) 1247 1248 /* 1249 * AFBC copy-block restrict 1250 * 1251 * Buffers with this flag must obey the copy-block restriction. The restriction 1252 * is such that there are no copy-blocks referring across the border of 8x8 1253 * blocks. For the subsampled data the 8x8 limitation is also subsampled. 1254 */ 1255 #define AFBC_FORMAT_MOD_CBR (1ULL << 7) 1256 1257 /* 1258 * AFBC tiled layout 1259 * 1260 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all 1261 * superblocks inside a tile are stored together in memory. 8x8 tiles are used 1262 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for 1263 * larger bpp formats. The order between the tiles is scan line. 1264 * When the tiled layout is used, the buffer size (in pixels) must be aligned 1265 * to the tile size. 1266 */ 1267 #define AFBC_FORMAT_MOD_TILED (1ULL << 8) 1268 1269 /* 1270 * AFBC solid color blocks 1271 * 1272 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth 1273 * can be reduced if a whole superblock is a single color. 1274 */ 1275 #define AFBC_FORMAT_MOD_SC (1ULL << 9) 1276 1277 /* 1278 * AFBC double-buffer 1279 * 1280 * Indicates that the buffer is allocated in a layout safe for front-buffer 1281 * rendering. 1282 */ 1283 #define AFBC_FORMAT_MOD_DB (1ULL << 10) 1284 1285 /* 1286 * AFBC buffer content hints 1287 * 1288 * Indicates that the buffer includes per-superblock content hints. 1289 */ 1290 #define AFBC_FORMAT_MOD_BCH (1ULL << 11) 1291 1292 /* AFBC uncompressed storage mode 1293 * 1294 * Indicates that the buffer is using AFBC uncompressed storage mode. 1295 * In this mode all superblock payloads in the buffer use the uncompressed 1296 * storage mode, which is usually only used for data which cannot be compressed. 1297 * The buffer layout is the same as for AFBC buffers without USM set, this only 1298 * affects the storage mode of the individual superblocks. Note that even a 1299 * buffer without USM set may use uncompressed storage mode for some or all 1300 * superblocks, USM just guarantees it for all. 1301 */ 1302 #define AFBC_FORMAT_MOD_USM (1ULL << 12) 1303 1304 /* 1305 * Arm Fixed-Rate Compression (AFRC) modifiers 1306 * 1307 * AFRC is a proprietary fixed rate image compression protocol and format, 1308 * designed to provide guaranteed bandwidth and memory footprint 1309 * reductions in graphics and media use-cases. 1310 * 1311 * AFRC buffers consist of one or more planes, with the same components 1312 * and meaning as an uncompressed buffer using the same pixel format. 1313 * 1314 * Within each plane, the pixel/luma/chroma values are grouped into 1315 * "coding unit" blocks which are individually compressed to a 1316 * fixed size (in bytes). All coding units within a given plane of a buffer 1317 * store the same number of values, and have the same compressed size. 1318 * 1319 * The coding unit size is configurable, allowing different rates of compression. 1320 * 1321 * The start of each AFRC buffer plane must be aligned to an alignment granule which 1322 * depends on the coding unit size. 1323 * 1324 * Coding Unit Size Plane Alignment 1325 * ---------------- --------------- 1326 * 16 bytes 1024 bytes 1327 * 24 bytes 512 bytes 1328 * 32 bytes 2048 bytes 1329 * 1330 * Coding units are grouped into paging tiles. AFRC buffer dimensions must be aligned 1331 * to a multiple of the paging tile dimensions. 1332 * The dimensions of each paging tile depend on whether the buffer is optimised for 1333 * scanline (SCAN layout) or rotated (ROT layout) access. 1334 * 1335 * Layout Paging Tile Width Paging Tile Height 1336 * ------ ----------------- ------------------ 1337 * SCAN 16 coding units 4 coding units 1338 * ROT 8 coding units 8 coding units 1339 * 1340 * The dimensions of each coding unit depend on the number of components 1341 * in the compressed plane and whether the buffer is optimised for 1342 * scanline (SCAN layout) or rotated (ROT layout) access. 1343 * 1344 * Number of Components in Plane Layout Coding Unit Width Coding Unit Height 1345 * ----------------------------- --------- ----------------- ------------------ 1346 * 1 SCAN 16 samples 4 samples 1347 * Example: 16x4 luma samples in a 'Y' plane 1348 * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer 1349 * ----------------------------- --------- ----------------- ------------------ 1350 * 1 ROT 8 samples 8 samples 1351 * Example: 8x8 luma samples in a 'Y' plane 1352 * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer 1353 * ----------------------------- --------- ----------------- ------------------ 1354 * 2 DONT CARE 8 samples 4 samples 1355 * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer 1356 * ----------------------------- --------- ----------------- ------------------ 1357 * 3 DONT CARE 4 samples 4 samples 1358 * Example: 4x4 pixels in an RGB buffer without alpha 1359 * ----------------------------- --------- ----------------- ------------------ 1360 * 4 DONT CARE 4 samples 4 samples 1361 * Example: 4x4 pixels in an RGB buffer with alpha 1362 */ 1363 1364 #define DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02 1365 1366 #define DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) \ 1367 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode) 1368 1369 /* 1370 * AFRC coding unit size modifier. 1371 * 1372 * Indicates the number of bytes used to store each compressed coding unit for 1373 * one or more planes in an AFRC encoded buffer. The coding unit size for chrominance 1374 * is the same for both Cb and Cr, which may be stored in separate planes. 1375 * 1376 * AFRC_FORMAT_MOD_CU_SIZE_P0 indicates the number of bytes used to store 1377 * each compressed coding unit in the first plane of the buffer. For RGBA buffers 1378 * this is the only plane, while for semi-planar and fully-planar YUV buffers, 1379 * this corresponds to the luma plane. 1380 * 1381 * AFRC_FORMAT_MOD_CU_SIZE_P12 indicates the number of bytes used to store 1382 * each compressed coding unit in the second and third planes in the buffer. 1383 * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s). 1384 * 1385 * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified 1386 * and AFRC_FORMAT_MOD_CU_SIZE_P12 must be zero. 1387 * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and 1388 * AFRC_FORMAT_MOD_CU_SIZE_P12 must be specified. 1389 */ 1390 #define AFRC_FORMAT_MOD_CU_SIZE_MASK 0xf 1391 #define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL) 1392 #define AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL) 1393 #define AFRC_FORMAT_MOD_CU_SIZE_32 (3ULL) 1394 1395 #define AFRC_FORMAT_MOD_CU_SIZE_P0(__afrc_cu_size) (__afrc_cu_size) 1396 #define AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4) 1397 1398 /* 1399 * AFRC scanline memory layout. 1400 * 1401 * Indicates if the buffer uses the scanline-optimised layout 1402 * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout. 1403 * The memory layout is the same for all planes. 1404 */ 1405 #define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8) 1406 1407 /* 1408 * Arm 16x16 Block U-Interleaved modifier 1409 * 1410 * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image 1411 * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels 1412 * in the block are reordered. 1413 */ 1414 #define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \ 1415 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL) 1416 1417 /* 1418 * Allwinner tiled modifier 1419 * 1420 * This tiling mode is implemented by the VPU found on all Allwinner platforms, 1421 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3 1422 * planes. 1423 * 1424 * With this tiling, the luminance samples are disposed in tiles representing 1425 * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels. 1426 * The pixel order in each tile is linear and the tiles are disposed linearly, 1427 * both in row-major order. 1428 */ 1429 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1) 1430 1431 /* 1432 * Amlogic Video Framebuffer Compression modifiers 1433 * 1434 * Amlogic uses a proprietary lossless image compression protocol and format 1435 * for their hardware video codec accelerators, either video decoders or 1436 * video input encoders. 1437 * 1438 * It considerably reduces memory bandwidth while writing and reading 1439 * frames in memory. 1440 * 1441 * The underlying storage is considered to be 3 components, 8bit or 10-bit 1442 * per component YCbCr 420, single plane : 1443 * - DRM_FORMAT_YUV420_8BIT 1444 * - DRM_FORMAT_YUV420_10BIT 1445 * 1446 * The first 8 bits of the mode defines the layout, then the following 8 bits 1447 * defines the options changing the layout. 1448 * 1449 * Not all combinations are valid, and different SoCs may support different 1450 * combinations of layout and options. 1451 */ 1452 #define __fourcc_mod_amlogic_layout_mask 0xff 1453 #define __fourcc_mod_amlogic_options_shift 8 1454 #define __fourcc_mod_amlogic_options_mask 0xff 1455 1456 #define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \ 1457 fourcc_mod_code(AMLOGIC, \ 1458 ((__layout) & __fourcc_mod_amlogic_layout_mask) | \ 1459 (((__options) & __fourcc_mod_amlogic_options_mask) \ 1460 << __fourcc_mod_amlogic_options_shift)) 1461 1462 /* Amlogic FBC Layouts */ 1463 1464 /* 1465 * Amlogic FBC Basic Layout 1466 * 1467 * The basic layout is composed of: 1468 * - a body content organized in 64x32 superblocks with 4096 bytes per 1469 * superblock in default mode. 1470 * - a 32 bytes per 128x64 header block 1471 * 1472 * This layout is transferrable between Amlogic SoCs supporting this modifier. 1473 */ 1474 #define AMLOGIC_FBC_LAYOUT_BASIC (1ULL) 1475 1476 /* 1477 * Amlogic FBC Scatter Memory layout 1478 * 1479 * Indicates the header contains IOMMU references to the compressed 1480 * frames content to optimize memory access and layout. 1481 * 1482 * In this mode, only the header memory address is needed, thus the 1483 * content memory organization is tied to the current producer 1484 * execution and cannot be saved/dumped neither transferrable between 1485 * Amlogic SoCs supporting this modifier. 1486 * 1487 * Due to the nature of the layout, these buffers are not expected to 1488 * be accessible by the user-space clients, but only accessible by the 1489 * hardware producers and consumers. 1490 * 1491 * The user-space clients should expect a failure while trying to mmap 1492 * the DMA-BUF handle returned by the producer. 1493 */ 1494 #define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL) 1495 1496 /* Amlogic FBC Layout Options Bit Mask */ 1497 1498 /* 1499 * Amlogic FBC Memory Saving mode 1500 * 1501 * Indicates the storage is packed when pixel size is multiple of word 1502 * boundaries, i.e. 8bit should be stored in this mode to save allocation 1503 * memory. 1504 * 1505 * This mode reduces body layout to 3072 bytes per 64x32 superblock with 1506 * the basic layout and 3200 bytes per 64x32 superblock combined with 1507 * the scatter layout. 1508 */ 1509 #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) 1510 1511 /* MediaTek modifiers 1512 * Bits Parameter Notes 1513 * ----- ------------------------ --------------------------------------------- 1514 * 7: 0 TILE LAYOUT Values are MTK_FMT_MOD_TILE_* 1515 * 15: 8 COMPRESSION Values are MTK_FMT_MOD_COMPRESS_* 1516 * 23:16 10 BIT LAYOUT Values are MTK_FMT_MOD_10BIT_LAYOUT_* 1517 * 1518 */ 1519 1520 #define DRM_FORMAT_MOD_MTK(__flags) fourcc_mod_code(MTK, __flags) 1521 1522 /* 1523 * MediaTek Tiled Modifier 1524 * The lowest 8 bits of the modifier is used to specify the tiling 1525 * layout. Only the 16L_32S tiling is used for now, but we define an 1526 * "untiled" version and leave room for future expansion. 1527 */ 1528 #define MTK_FMT_MOD_TILE_MASK 0xf 1529 #define MTK_FMT_MOD_TILE_NONE 0x0 1530 #define MTK_FMT_MOD_TILE_16L32S 0x1 1531 1532 /* 1533 * Bits 8-15 specify compression options 1534 */ 1535 #define MTK_FMT_MOD_COMPRESS_MASK (0xf << 8) 1536 #define MTK_FMT_MOD_COMPRESS_NONE (0x0 << 8) 1537 #define MTK_FMT_MOD_COMPRESS_V1 (0x1 << 8) 1538 1539 /* 1540 * Bits 16-23 specify how the bits of 10 bit formats are 1541 * stored out in memory 1542 */ 1543 #define MTK_FMT_MOD_10BIT_LAYOUT_MASK (0xf << 16) 1544 #define MTK_FMT_MOD_10BIT_LAYOUT_PACKED (0x0 << 16) 1545 #define MTK_FMT_MOD_10BIT_LAYOUT_LSBTILED (0x1 << 16) 1546 #define MTK_FMT_MOD_10BIT_LAYOUT_LSBRASTER (0x2 << 16) 1547 1548 /* alias for the most common tiling format */ 1549 #define DRM_FORMAT_MOD_MTK_16L_32S_TILE DRM_FORMAT_MOD_MTK(MTK_FMT_MOD_TILE_16L32S) 1550 1551 /* 1552 * Apple GPU-tiled layouts. 1553 * 1554 * Apple GPUs support nonlinear tilings with optional lossless compression. 1555 * 1556 * GPU-tiled images are divided into 16KiB tiles: 1557 * 1558 * Bytes per pixel Tile size 1559 * --------------- --------- 1560 * 1 128x128 1561 * 2 128x64 1562 * 4 64x64 1563 * 8 64x32 1564 * 16 32x32 1565 * 1566 * Tiles are raster-order. Pixels within a tile are interleaved (Morton order). 1567 * 1568 * Compressed images pad the body to 128-bytes and are immediately followed by a 1569 * metadata section. The metadata section rounds the image dimensions to 1570 * powers-of-two and contains 8 bytes for each 16x16 compression subtile. 1571 * Subtiles are interleaved (Morton order). 1572 * 1573 * All images are 128-byte aligned. 1574 * 1575 * These layouts fundamentally do not have meaningful strides. No matter how we 1576 * specify strides for these layouts, userspace unaware of Apple image layouts 1577 * will be unable to use correctly the specified stride for any purpose. 1578 * Userspace aware of the image layouts do not use strides. The most "correct" 1579 * convention would be setting the image stride to 0. Unfortunately, some 1580 * software assumes the stride is at least (width * bytes per pixel). We 1581 * therefore require that stride equals (width * bytes per pixel). Since the 1582 * stride is arbitrary here, we pick the simplest convention. 1583 * 1584 * Although containing two sections, compressed image layouts are treated in 1585 * software as a single plane. This is modelled after AFBC, a similar 1586 * scheme. Attempting to separate the sections to be "explicit" in DRM would 1587 * only generate more confusion, as software does not treat the image this way. 1588 * 1589 * For detailed information on the hardware image layouts, see 1590 * https://docs.mesa3d.org/drivers/asahi.html#image-layouts 1591 */ 1592 #define DRM_FORMAT_MOD_APPLE_GPU_TILED fourcc_mod_code(APPLE, 1) 1593 #define DRM_FORMAT_MOD_APPLE_GPU_TILED_COMPRESSED fourcc_mod_code(APPLE, 2) 1594 1595 /* 1596 * AMD modifiers 1597 * 1598 * Memory layout: 1599 * 1600 * without DCC: 1601 * - main surface 1602 * 1603 * with DCC & without DCC_RETILE: 1604 * - main surface in plane 0 1605 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set) 1606 * 1607 * with DCC & DCC_RETILE: 1608 * - main surface in plane 0 1609 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned) 1610 * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned) 1611 * 1612 * For multi-plane formats the above surfaces get merged into one plane for 1613 * each format plane, based on the required alignment only. 1614 * 1615 * Bits Parameter Notes 1616 * ----- ------------------------ --------------------------------------------- 1617 * 1618 * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_* 1619 * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_* 1620 * 13 DCC 1621 * 14 DCC_RETILE 1622 * 15 DCC_PIPE_ALIGN 1623 * 16 DCC_INDEPENDENT_64B 1624 * 17 DCC_INDEPENDENT_128B 1625 * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_* 1626 * 20 DCC_CONSTANT_ENCODE 1627 * 23:21 PIPE_XOR_BITS Only for some chips 1628 * 26:24 BANK_XOR_BITS Only for some chips 1629 * 29:27 PACKERS Only for some chips 1630 * 32:30 RB Only for some chips 1631 * 35:33 PIPE Only for some chips 1632 * 55:36 - Reserved for future use, must be zero 1633 */ 1634 #define AMD_FMT_MOD fourcc_mod_code(AMD, 0) 1635 1636 #define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD) 1637 1638 /* Reserve 0 for GFX8 and older */ 1639 #define AMD_FMT_MOD_TILE_VER_GFX9 1 1640 #define AMD_FMT_MOD_TILE_VER_GFX10 2 1641 #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3 1642 #define AMD_FMT_MOD_TILE_VER_GFX11 4 1643 #define AMD_FMT_MOD_TILE_VER_GFX12 5 1644 1645 /* 1646 * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical 1647 * version. 1648 */ 1649 #define AMD_FMT_MOD_TILE_GFX9_64K_S 9 1650 1651 /* 1652 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has 1653 * GFX9 as canonical version. 1654 * 1655 * 64K_D_2D on GFX12 is identical to 64K_D on GFX11. 1656 */ 1657 #define AMD_FMT_MOD_TILE_GFX9_64K_D 10 1658 #define AMD_FMT_MOD_TILE_GFX9_4K_D_X 22 1659 #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 1660 #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 1661 #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27 1662 #define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31 1663 1664 /* Gfx12 swizzle modes: 1665 * 0 - LINEAR 1666 * 1 - 256B_2D - 2D block dimensions 1667 * 2 - 4KB_2D 1668 * 3 - 64KB_2D 1669 * 4 - 256KB_2D 1670 * 5 - 4KB_3D - 3D block dimensions 1671 * 6 - 64KB_3D 1672 * 7 - 256KB_3D 1673 */ 1674 #define AMD_FMT_MOD_TILE_GFX12_256B_2D 1 1675 #define AMD_FMT_MOD_TILE_GFX12_4K_2D 2 1676 #define AMD_FMT_MOD_TILE_GFX12_64K_2D 3 1677 #define AMD_FMT_MOD_TILE_GFX12_256K_2D 4 1678 1679 #define AMD_FMT_MOD_DCC_BLOCK_64B 0 1680 #define AMD_FMT_MOD_DCC_BLOCK_128B 1 1681 #define AMD_FMT_MOD_DCC_BLOCK_256B 2 1682 1683 #define AMD_FMT_MOD_TILE_VERSION_SHIFT 0 1684 #define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF 1685 #define AMD_FMT_MOD_TILE_SHIFT 8 1686 #define AMD_FMT_MOD_TILE_MASK 0x1F 1687 1688 /* Whether DCC compression is enabled. */ 1689 #define AMD_FMT_MOD_DCC_SHIFT 13 1690 #define AMD_FMT_MOD_DCC_MASK 0x1 1691 1692 /* 1693 * Whether to include two DCC surfaces, one which is rb & pipe aligned, and 1694 * one which is not-aligned. 1695 */ 1696 #define AMD_FMT_MOD_DCC_RETILE_SHIFT 14 1697 #define AMD_FMT_MOD_DCC_RETILE_MASK 0x1 1698 1699 /* Only set if DCC_RETILE = false */ 1700 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15 1701 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1 1702 1703 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16 1704 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1 1705 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17 1706 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1 1707 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 1708 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 1709 1710 /* 1711 * DCC supports embedding some clear colors directly in the DCC surface. 1712 * However, on older GPUs the rendering HW ignores the embedded clear color 1713 * and prefers the driver provided color. This necessitates doing a fastclear 1714 * eliminate operation before a process transfers control. 1715 * 1716 * If this bit is set that means the fastclear eliminate is not needed for these 1717 * embeddable colors. 1718 */ 1719 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20 1720 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1 1721 1722 /* 1723 * The below fields are for accounting for per GPU differences. These are only 1724 * relevant for GFX9 and later and if the tile field is *_X/_T. 1725 * 1726 * PIPE_XOR_BITS = always needed 1727 * BANK_XOR_BITS = only for TILE_VER_GFX9 1728 * PACKERS = only for TILE_VER_GFX10_RBPLUS 1729 * RB = only for TILE_VER_GFX9 & DCC 1730 * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN) 1731 */ 1732 #define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21 1733 #define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7 1734 #define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24 1735 #define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7 1736 #define AMD_FMT_MOD_PACKERS_SHIFT 27 1737 #define AMD_FMT_MOD_PACKERS_MASK 0x7 1738 #define AMD_FMT_MOD_RB_SHIFT 30 1739 #define AMD_FMT_MOD_RB_MASK 0x7 1740 #define AMD_FMT_MOD_PIPE_SHIFT 33 1741 #define AMD_FMT_MOD_PIPE_MASK 0x7 1742 1743 #define AMD_FMT_MOD_SET(field, value) \ 1744 ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT) 1745 #define AMD_FMT_MOD_GET(field, value) \ 1746 (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK) 1747 #define AMD_FMT_MOD_CLEAR(field) \ 1748 (~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) 1749 1750 #if defined(__cplusplus) 1751 } 1752 #endif 1753 1754 #endif /* DRM_FOURCC_H */ 1755