1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * BPF JIT compiler
4 *
5 * Copyright (C) 2011-2013 Eric Dumazet (eric.dumazet@gmail.com)
6 * Copyright (c) 2011-2014 PLUMgrid, http://plumgrid.com
7 */
8 #include <linux/netdevice.h>
9 #include <linux/filter.h>
10 #include <linux/if_vlan.h>
11 #include <linux/bpf.h>
12 #include <linux/memory.h>
13 #include <linux/sort.h>
14 #include <asm/extable.h>
15 #include <asm/ftrace.h>
16 #include <asm/set_memory.h>
17 #include <asm/nospec-branch.h>
18 #include <asm/text-patching.h>
19
emit_code(u8 * ptr,u32 bytes,unsigned int len)20 static u8 *emit_code(u8 *ptr, u32 bytes, unsigned int len)
21 {
22 if (len == 1)
23 *ptr = bytes;
24 else if (len == 2)
25 *(u16 *)ptr = bytes;
26 else {
27 *(u32 *)ptr = bytes;
28 barrier();
29 }
30 return ptr + len;
31 }
32
33 #define EMIT(bytes, len) \
34 do { prog = emit_code(prog, bytes, len); } while (0)
35
36 #define EMIT1(b1) EMIT(b1, 1)
37 #define EMIT2(b1, b2) EMIT((b1) + ((b2) << 8), 2)
38 #define EMIT3(b1, b2, b3) EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3)
39 #define EMIT4(b1, b2, b3, b4) EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4)
40
41 #define EMIT1_off32(b1, off) \
42 do { EMIT1(b1); EMIT(off, 4); } while (0)
43 #define EMIT2_off32(b1, b2, off) \
44 do { EMIT2(b1, b2); EMIT(off, 4); } while (0)
45 #define EMIT3_off32(b1, b2, b3, off) \
46 do { EMIT3(b1, b2, b3); EMIT(off, 4); } while (0)
47 #define EMIT4_off32(b1, b2, b3, b4, off) \
48 do { EMIT4(b1, b2, b3, b4); EMIT(off, 4); } while (0)
49
50 #ifdef CONFIG_X86_KERNEL_IBT
51 #define EMIT_ENDBR() EMIT(gen_endbr(), 4)
52 #else
53 #define EMIT_ENDBR()
54 #endif
55
is_imm8(int value)56 static bool is_imm8(int value)
57 {
58 return value <= 127 && value >= -128;
59 }
60
is_simm32(s64 value)61 static bool is_simm32(s64 value)
62 {
63 return value == (s64)(s32)value;
64 }
65
is_uimm32(u64 value)66 static bool is_uimm32(u64 value)
67 {
68 return value == (u64)(u32)value;
69 }
70
71 /* mov dst, src */
72 #define EMIT_mov(DST, SRC) \
73 do { \
74 if (DST != SRC) \
75 EMIT3(add_2mod(0x48, DST, SRC), 0x89, add_2reg(0xC0, DST, SRC)); \
76 } while (0)
77
bpf_size_to_x86_bytes(int bpf_size)78 static int bpf_size_to_x86_bytes(int bpf_size)
79 {
80 if (bpf_size == BPF_W)
81 return 4;
82 else if (bpf_size == BPF_H)
83 return 2;
84 else if (bpf_size == BPF_B)
85 return 1;
86 else if (bpf_size == BPF_DW)
87 return 4; /* imm32 */
88 else
89 return 0;
90 }
91
92 /*
93 * List of x86 cond jumps opcodes (. + s8)
94 * Add 0x10 (and an extra 0x0f) to generate far jumps (. + s32)
95 */
96 #define X86_JB 0x72
97 #define X86_JAE 0x73
98 #define X86_JE 0x74
99 #define X86_JNE 0x75
100 #define X86_JBE 0x76
101 #define X86_JA 0x77
102 #define X86_JL 0x7C
103 #define X86_JGE 0x7D
104 #define X86_JLE 0x7E
105 #define X86_JG 0x7F
106
107 /* Pick a register outside of BPF range for JIT internal work */
108 #define AUX_REG (MAX_BPF_JIT_REG + 1)
109 #define X86_REG_R9 (MAX_BPF_JIT_REG + 2)
110
111 /*
112 * The following table maps BPF registers to x86-64 registers.
113 *
114 * x86-64 register R12 is unused, since if used as base address
115 * register in load/store instructions, it always needs an
116 * extra byte of encoding and is callee saved.
117 *
118 * x86-64 register R9 is not used by BPF programs, but can be used by BPF
119 * trampoline. x86-64 register R10 is used for blinding (if enabled).
120 */
121 static const int reg2hex[] = {
122 [BPF_REG_0] = 0, /* RAX */
123 [BPF_REG_1] = 7, /* RDI */
124 [BPF_REG_2] = 6, /* RSI */
125 [BPF_REG_3] = 2, /* RDX */
126 [BPF_REG_4] = 1, /* RCX */
127 [BPF_REG_5] = 0, /* R8 */
128 [BPF_REG_6] = 3, /* RBX callee saved */
129 [BPF_REG_7] = 5, /* R13 callee saved */
130 [BPF_REG_8] = 6, /* R14 callee saved */
131 [BPF_REG_9] = 7, /* R15 callee saved */
132 [BPF_REG_FP] = 5, /* RBP readonly */
133 [BPF_REG_AX] = 2, /* R10 temp register */
134 [AUX_REG] = 3, /* R11 temp register */
135 [X86_REG_R9] = 1, /* R9 register, 6th function argument */
136 };
137
138 static const int reg2pt_regs[] = {
139 [BPF_REG_0] = offsetof(struct pt_regs, ax),
140 [BPF_REG_1] = offsetof(struct pt_regs, di),
141 [BPF_REG_2] = offsetof(struct pt_regs, si),
142 [BPF_REG_3] = offsetof(struct pt_regs, dx),
143 [BPF_REG_4] = offsetof(struct pt_regs, cx),
144 [BPF_REG_5] = offsetof(struct pt_regs, r8),
145 [BPF_REG_6] = offsetof(struct pt_regs, bx),
146 [BPF_REG_7] = offsetof(struct pt_regs, r13),
147 [BPF_REG_8] = offsetof(struct pt_regs, r14),
148 [BPF_REG_9] = offsetof(struct pt_regs, r15),
149 };
150
151 /*
152 * is_ereg() == true if BPF register 'reg' maps to x86-64 r8..r15
153 * which need extra byte of encoding.
154 * rax,rcx,...,rbp have simpler encoding
155 */
is_ereg(u32 reg)156 static bool is_ereg(u32 reg)
157 {
158 return (1 << reg) & (BIT(BPF_REG_5) |
159 BIT(AUX_REG) |
160 BIT(BPF_REG_7) |
161 BIT(BPF_REG_8) |
162 BIT(BPF_REG_9) |
163 BIT(X86_REG_R9) |
164 BIT(BPF_REG_AX));
165 }
166
167 /*
168 * is_ereg_8l() == true if BPF register 'reg' is mapped to access x86-64
169 * lower 8-bit registers dil,sil,bpl,spl,r8b..r15b, which need extra byte
170 * of encoding. al,cl,dl,bl have simpler encoding.
171 */
is_ereg_8l(u32 reg)172 static bool is_ereg_8l(u32 reg)
173 {
174 return is_ereg(reg) ||
175 (1 << reg) & (BIT(BPF_REG_1) |
176 BIT(BPF_REG_2) |
177 BIT(BPF_REG_FP));
178 }
179
is_axreg(u32 reg)180 static bool is_axreg(u32 reg)
181 {
182 return reg == BPF_REG_0;
183 }
184
185 /* Add modifiers if 'reg' maps to x86-64 registers R8..R15 */
add_1mod(u8 byte,u32 reg)186 static u8 add_1mod(u8 byte, u32 reg)
187 {
188 if (is_ereg(reg))
189 byte |= 1;
190 return byte;
191 }
192
add_2mod(u8 byte,u32 r1,u32 r2)193 static u8 add_2mod(u8 byte, u32 r1, u32 r2)
194 {
195 if (is_ereg(r1))
196 byte |= 1;
197 if (is_ereg(r2))
198 byte |= 4;
199 return byte;
200 }
201
202 /* Encode 'dst_reg' register into x86-64 opcode 'byte' */
add_1reg(u8 byte,u32 dst_reg)203 static u8 add_1reg(u8 byte, u32 dst_reg)
204 {
205 return byte + reg2hex[dst_reg];
206 }
207
208 /* Encode 'dst_reg' and 'src_reg' registers into x86-64 opcode 'byte' */
add_2reg(u8 byte,u32 dst_reg,u32 src_reg)209 static u8 add_2reg(u8 byte, u32 dst_reg, u32 src_reg)
210 {
211 return byte + reg2hex[dst_reg] + (reg2hex[src_reg] << 3);
212 }
213
214 /* Some 1-byte opcodes for binary ALU operations */
215 static u8 simple_alu_opcodes[] = {
216 [BPF_ADD] = 0x01,
217 [BPF_SUB] = 0x29,
218 [BPF_AND] = 0x21,
219 [BPF_OR] = 0x09,
220 [BPF_XOR] = 0x31,
221 [BPF_LSH] = 0xE0,
222 [BPF_RSH] = 0xE8,
223 [BPF_ARSH] = 0xF8,
224 };
225
jit_fill_hole(void * area,unsigned int size)226 static void jit_fill_hole(void *area, unsigned int size)
227 {
228 /* Fill whole space with INT3 instructions */
229 memset(area, 0xcc, size);
230 }
231
bpf_arch_text_invalidate(void * dst,size_t len)232 int bpf_arch_text_invalidate(void *dst, size_t len)
233 {
234 return IS_ERR_OR_NULL(text_poke_set(dst, 0xcc, len));
235 }
236
237 struct jit_context {
238 int cleanup_addr; /* Epilogue code offset */
239
240 /*
241 * Program specific offsets of labels in the code; these rely on the
242 * JIT doing at least 2 passes, recording the position on the first
243 * pass, only to generate the correct offset on the second pass.
244 */
245 int tail_call_direct_label;
246 int tail_call_indirect_label;
247 };
248
249 /* Maximum number of bytes emitted while JITing one eBPF insn */
250 #define BPF_MAX_INSN_SIZE 128
251 #define BPF_INSN_SAFETY 64
252
253 /* Number of bytes emit_patch() needs to generate instructions */
254 #define X86_PATCH_SIZE 5
255 /* Number of bytes that will be skipped on tailcall */
256 #define X86_TAIL_CALL_OFFSET (11 + ENDBR_INSN_SIZE)
257
push_callee_regs(u8 ** pprog,bool * callee_regs_used)258 static void push_callee_regs(u8 **pprog, bool *callee_regs_used)
259 {
260 u8 *prog = *pprog;
261
262 if (callee_regs_used[0])
263 EMIT1(0x53); /* push rbx */
264 if (callee_regs_used[1])
265 EMIT2(0x41, 0x55); /* push r13 */
266 if (callee_regs_used[2])
267 EMIT2(0x41, 0x56); /* push r14 */
268 if (callee_regs_used[3])
269 EMIT2(0x41, 0x57); /* push r15 */
270 *pprog = prog;
271 }
272
pop_callee_regs(u8 ** pprog,bool * callee_regs_used)273 static void pop_callee_regs(u8 **pprog, bool *callee_regs_used)
274 {
275 u8 *prog = *pprog;
276
277 if (callee_regs_used[3])
278 EMIT2(0x41, 0x5F); /* pop r15 */
279 if (callee_regs_used[2])
280 EMIT2(0x41, 0x5E); /* pop r14 */
281 if (callee_regs_used[1])
282 EMIT2(0x41, 0x5D); /* pop r13 */
283 if (callee_regs_used[0])
284 EMIT1(0x5B); /* pop rbx */
285 *pprog = prog;
286 }
287
288 /*
289 * Emit x86-64 prologue code for BPF program.
290 * bpf_tail_call helper will skip the first X86_TAIL_CALL_OFFSET bytes
291 * while jumping to another program
292 */
emit_prologue(u8 ** pprog,u32 stack_depth,bool ebpf_from_cbpf,bool tail_call_reachable,bool is_subprog)293 static void emit_prologue(u8 **pprog, u32 stack_depth, bool ebpf_from_cbpf,
294 bool tail_call_reachable, bool is_subprog)
295 {
296 u8 *prog = *pprog;
297
298 /* BPF trampoline can be made to work without these nops,
299 * but let's waste 5 bytes for now and optimize later
300 */
301 EMIT_ENDBR();
302 memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
303 prog += X86_PATCH_SIZE;
304 if (!ebpf_from_cbpf) {
305 if (tail_call_reachable && !is_subprog)
306 EMIT2(0x31, 0xC0); /* xor eax, eax */
307 else
308 EMIT2(0x66, 0x90); /* nop2 */
309 }
310 EMIT1(0x55); /* push rbp */
311 EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */
312
313 /* X86_TAIL_CALL_OFFSET is here */
314 EMIT_ENDBR();
315
316 /* sub rsp, rounded_stack_depth */
317 if (stack_depth)
318 EMIT3_off32(0x48, 0x81, 0xEC, round_up(stack_depth, 8));
319 if (tail_call_reachable)
320 EMIT1(0x50); /* push rax */
321 *pprog = prog;
322 }
323
emit_patch(u8 ** pprog,void * func,void * ip,u8 opcode)324 static int emit_patch(u8 **pprog, void *func, void *ip, u8 opcode)
325 {
326 u8 *prog = *pprog;
327 s64 offset;
328
329 offset = func - (ip + X86_PATCH_SIZE);
330 if (!is_simm32(offset)) {
331 pr_err("Target call %p is out of range\n", func);
332 return -ERANGE;
333 }
334 EMIT1_off32(opcode, offset);
335 *pprog = prog;
336 return 0;
337 }
338
emit_call(u8 ** pprog,void * func,void * ip)339 static int emit_call(u8 **pprog, void *func, void *ip)
340 {
341 return emit_patch(pprog, func, ip, 0xE8);
342 }
343
emit_rsb_call(u8 ** pprog,void * func,void * ip)344 static int emit_rsb_call(u8 **pprog, void *func, void *ip)
345 {
346 OPTIMIZER_HIDE_VAR(func);
347 ip += x86_call_depth_emit_accounting(pprog, func);
348 return emit_patch(pprog, func, ip, 0xE8);
349 }
350
emit_jump(u8 ** pprog,void * func,void * ip)351 static int emit_jump(u8 **pprog, void *func, void *ip)
352 {
353 return emit_patch(pprog, func, ip, 0xE9);
354 }
355
__bpf_arch_text_poke(void * ip,enum bpf_text_poke_type t,void * old_addr,void * new_addr)356 static int __bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t,
357 void *old_addr, void *new_addr)
358 {
359 const u8 *nop_insn = x86_nops[5];
360 u8 old_insn[X86_PATCH_SIZE];
361 u8 new_insn[X86_PATCH_SIZE];
362 u8 *prog;
363 int ret;
364
365 memcpy(old_insn, nop_insn, X86_PATCH_SIZE);
366 if (old_addr) {
367 prog = old_insn;
368 ret = t == BPF_MOD_CALL ?
369 emit_call(&prog, old_addr, ip) :
370 emit_jump(&prog, old_addr, ip);
371 if (ret)
372 return ret;
373 }
374
375 memcpy(new_insn, nop_insn, X86_PATCH_SIZE);
376 if (new_addr) {
377 prog = new_insn;
378 ret = t == BPF_MOD_CALL ?
379 emit_call(&prog, new_addr, ip) :
380 emit_jump(&prog, new_addr, ip);
381 if (ret)
382 return ret;
383 }
384
385 ret = -EBUSY;
386 mutex_lock(&text_mutex);
387 if (memcmp(ip, old_insn, X86_PATCH_SIZE))
388 goto out;
389 ret = 1;
390 if (memcmp(ip, new_insn, X86_PATCH_SIZE)) {
391 text_poke_bp(ip, new_insn, X86_PATCH_SIZE, NULL);
392 ret = 0;
393 }
394 out:
395 mutex_unlock(&text_mutex);
396 return ret;
397 }
398
bpf_arch_text_poke(void * ip,enum bpf_text_poke_type t,void * old_addr,void * new_addr)399 int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t,
400 void *old_addr, void *new_addr)
401 {
402 if (!is_kernel_text((long)ip) &&
403 !is_bpf_text_address((long)ip))
404 /* BPF poking in modules is not supported */
405 return -EINVAL;
406
407 /*
408 * See emit_prologue(), for IBT builds the trampoline hook is preceded
409 * with an ENDBR instruction.
410 */
411 if (is_endbr(*(u32 *)ip))
412 ip += ENDBR_INSN_SIZE;
413
414 return __bpf_arch_text_poke(ip, t, old_addr, new_addr);
415 }
416
417 #define EMIT_LFENCE() EMIT3(0x0F, 0xAE, 0xE8)
418
emit_indirect_jump(u8 ** pprog,int reg,u8 * ip)419 static void emit_indirect_jump(u8 **pprog, int reg, u8 *ip)
420 {
421 u8 *prog = *pprog;
422
423 if (cpu_feature_enabled(X86_FEATURE_RETPOLINE_LFENCE)) {
424 EMIT_LFENCE();
425 EMIT2(0xFF, 0xE0 + reg);
426 } else if (cpu_feature_enabled(X86_FEATURE_RETPOLINE)) {
427 OPTIMIZER_HIDE_VAR(reg);
428 if (cpu_feature_enabled(X86_FEATURE_CALL_DEPTH))
429 emit_jump(&prog, &__x86_indirect_jump_thunk_array[reg], ip);
430 else
431 emit_jump(&prog, &__x86_indirect_thunk_array[reg], ip);
432 } else {
433 EMIT2(0xFF, 0xE0 + reg); /* jmp *%\reg */
434 if (IS_ENABLED(CONFIG_RETPOLINE) || IS_ENABLED(CONFIG_SLS))
435 EMIT1(0xCC); /* int3 */
436 }
437
438 *pprog = prog;
439 }
440
emit_return(u8 ** pprog,u8 * ip)441 static void emit_return(u8 **pprog, u8 *ip)
442 {
443 u8 *prog = *pprog;
444
445 if (cpu_feature_enabled(X86_FEATURE_RETHUNK)) {
446 emit_jump(&prog, x86_return_thunk, ip);
447 } else {
448 EMIT1(0xC3); /* ret */
449 if (IS_ENABLED(CONFIG_SLS))
450 EMIT1(0xCC); /* int3 */
451 }
452
453 *pprog = prog;
454 }
455
456 /*
457 * Generate the following code:
458 *
459 * ... bpf_tail_call(void *ctx, struct bpf_array *array, u64 index) ...
460 * if (index >= array->map.max_entries)
461 * goto out;
462 * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT)
463 * goto out;
464 * prog = array->ptrs[index];
465 * if (prog == NULL)
466 * goto out;
467 * goto *(prog->bpf_func + prologue_size);
468 * out:
469 */
emit_bpf_tail_call_indirect(u8 ** pprog,bool * callee_regs_used,u32 stack_depth,u8 * ip,struct jit_context * ctx)470 static void emit_bpf_tail_call_indirect(u8 **pprog, bool *callee_regs_used,
471 u32 stack_depth, u8 *ip,
472 struct jit_context *ctx)
473 {
474 int tcc_off = -4 - round_up(stack_depth, 8);
475 u8 *prog = *pprog, *start = *pprog;
476 int offset;
477
478 /*
479 * rdi - pointer to ctx
480 * rsi - pointer to bpf_array
481 * rdx - index in bpf_array
482 */
483
484 /*
485 * if (index >= array->map.max_entries)
486 * goto out;
487 */
488 EMIT2(0x89, 0xD2); /* mov edx, edx */
489 EMIT3(0x39, 0x56, /* cmp dword ptr [rsi + 16], edx */
490 offsetof(struct bpf_array, map.max_entries));
491
492 offset = ctx->tail_call_indirect_label - (prog + 2 - start);
493 EMIT2(X86_JBE, offset); /* jbe out */
494
495 /*
496 * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT)
497 * goto out;
498 */
499 EMIT2_off32(0x8B, 0x85, tcc_off); /* mov eax, dword ptr [rbp - tcc_off] */
500 EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT); /* cmp eax, MAX_TAIL_CALL_CNT */
501
502 offset = ctx->tail_call_indirect_label - (prog + 2 - start);
503 EMIT2(X86_JAE, offset); /* jae out */
504 EMIT3(0x83, 0xC0, 0x01); /* add eax, 1 */
505 EMIT2_off32(0x89, 0x85, tcc_off); /* mov dword ptr [rbp - tcc_off], eax */
506
507 /* prog = array->ptrs[index]; */
508 EMIT4_off32(0x48, 0x8B, 0x8C, 0xD6, /* mov rcx, [rsi + rdx * 8 + offsetof(...)] */
509 offsetof(struct bpf_array, ptrs));
510
511 /*
512 * if (prog == NULL)
513 * goto out;
514 */
515 EMIT3(0x48, 0x85, 0xC9); /* test rcx,rcx */
516
517 offset = ctx->tail_call_indirect_label - (prog + 2 - start);
518 EMIT2(X86_JE, offset); /* je out */
519
520 pop_callee_regs(&prog, callee_regs_used);
521
522 EMIT1(0x58); /* pop rax */
523 if (stack_depth)
524 EMIT3_off32(0x48, 0x81, 0xC4, /* add rsp, sd */
525 round_up(stack_depth, 8));
526
527 /* goto *(prog->bpf_func + X86_TAIL_CALL_OFFSET); */
528 EMIT4(0x48, 0x8B, 0x49, /* mov rcx, qword ptr [rcx + 32] */
529 offsetof(struct bpf_prog, bpf_func));
530 EMIT4(0x48, 0x83, 0xC1, /* add rcx, X86_TAIL_CALL_OFFSET */
531 X86_TAIL_CALL_OFFSET);
532 /*
533 * Now we're ready to jump into next BPF program
534 * rdi == ctx (1st arg)
535 * rcx == prog->bpf_func + X86_TAIL_CALL_OFFSET
536 */
537 emit_indirect_jump(&prog, 1 /* rcx */, ip + (prog - start));
538
539 /* out: */
540 ctx->tail_call_indirect_label = prog - start;
541 *pprog = prog;
542 }
543
emit_bpf_tail_call_direct(struct bpf_jit_poke_descriptor * poke,u8 ** pprog,u8 * ip,bool * callee_regs_used,u32 stack_depth,struct jit_context * ctx)544 static void emit_bpf_tail_call_direct(struct bpf_jit_poke_descriptor *poke,
545 u8 **pprog, u8 *ip,
546 bool *callee_regs_used, u32 stack_depth,
547 struct jit_context *ctx)
548 {
549 int tcc_off = -4 - round_up(stack_depth, 8);
550 u8 *prog = *pprog, *start = *pprog;
551 int offset;
552
553 /*
554 * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT)
555 * goto out;
556 */
557 EMIT2_off32(0x8B, 0x85, tcc_off); /* mov eax, dword ptr [rbp - tcc_off] */
558 EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT); /* cmp eax, MAX_TAIL_CALL_CNT */
559
560 offset = ctx->tail_call_direct_label - (prog + 2 - start);
561 EMIT2(X86_JAE, offset); /* jae out */
562 EMIT3(0x83, 0xC0, 0x01); /* add eax, 1 */
563 EMIT2_off32(0x89, 0x85, tcc_off); /* mov dword ptr [rbp - tcc_off], eax */
564
565 poke->tailcall_bypass = ip + (prog - start);
566 poke->adj_off = X86_TAIL_CALL_OFFSET;
567 poke->tailcall_target = ip + ctx->tail_call_direct_label - X86_PATCH_SIZE;
568 poke->bypass_addr = (u8 *)poke->tailcall_target + X86_PATCH_SIZE;
569
570 emit_jump(&prog, (u8 *)poke->tailcall_target + X86_PATCH_SIZE,
571 poke->tailcall_bypass);
572
573 pop_callee_regs(&prog, callee_regs_used);
574 EMIT1(0x58); /* pop rax */
575 if (stack_depth)
576 EMIT3_off32(0x48, 0x81, 0xC4, round_up(stack_depth, 8));
577
578 memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
579 prog += X86_PATCH_SIZE;
580
581 /* out: */
582 ctx->tail_call_direct_label = prog - start;
583
584 *pprog = prog;
585 }
586
bpf_tail_call_direct_fixup(struct bpf_prog * prog)587 static void bpf_tail_call_direct_fixup(struct bpf_prog *prog)
588 {
589 struct bpf_jit_poke_descriptor *poke;
590 struct bpf_array *array;
591 struct bpf_prog *target;
592 int i, ret;
593
594 for (i = 0; i < prog->aux->size_poke_tab; i++) {
595 poke = &prog->aux->poke_tab[i];
596 if (poke->aux && poke->aux != prog->aux)
597 continue;
598
599 WARN_ON_ONCE(READ_ONCE(poke->tailcall_target_stable));
600
601 if (poke->reason != BPF_POKE_REASON_TAIL_CALL)
602 continue;
603
604 array = container_of(poke->tail_call.map, struct bpf_array, map);
605 mutex_lock(&array->aux->poke_mutex);
606 target = array->ptrs[poke->tail_call.key];
607 if (target) {
608 ret = __bpf_arch_text_poke(poke->tailcall_target,
609 BPF_MOD_JUMP, NULL,
610 (u8 *)target->bpf_func +
611 poke->adj_off);
612 BUG_ON(ret < 0);
613 ret = __bpf_arch_text_poke(poke->tailcall_bypass,
614 BPF_MOD_JUMP,
615 (u8 *)poke->tailcall_target +
616 X86_PATCH_SIZE, NULL);
617 BUG_ON(ret < 0);
618 }
619 WRITE_ONCE(poke->tailcall_target_stable, true);
620 mutex_unlock(&array->aux->poke_mutex);
621 }
622 }
623
emit_mov_imm32(u8 ** pprog,bool sign_propagate,u32 dst_reg,const u32 imm32)624 static void emit_mov_imm32(u8 **pprog, bool sign_propagate,
625 u32 dst_reg, const u32 imm32)
626 {
627 u8 *prog = *pprog;
628 u8 b1, b2, b3;
629
630 /*
631 * Optimization: if imm32 is positive, use 'mov %eax, imm32'
632 * (which zero-extends imm32) to save 2 bytes.
633 */
634 if (sign_propagate && (s32)imm32 < 0) {
635 /* 'mov %rax, imm32' sign extends imm32 */
636 b1 = add_1mod(0x48, dst_reg);
637 b2 = 0xC7;
638 b3 = 0xC0;
639 EMIT3_off32(b1, b2, add_1reg(b3, dst_reg), imm32);
640 goto done;
641 }
642
643 /*
644 * Optimization: if imm32 is zero, use 'xor %eax, %eax'
645 * to save 3 bytes.
646 */
647 if (imm32 == 0) {
648 if (is_ereg(dst_reg))
649 EMIT1(add_2mod(0x40, dst_reg, dst_reg));
650 b2 = 0x31; /* xor */
651 b3 = 0xC0;
652 EMIT2(b2, add_2reg(b3, dst_reg, dst_reg));
653 goto done;
654 }
655
656 /* mov %eax, imm32 */
657 if (is_ereg(dst_reg))
658 EMIT1(add_1mod(0x40, dst_reg));
659 EMIT1_off32(add_1reg(0xB8, dst_reg), imm32);
660 done:
661 *pprog = prog;
662 }
663
emit_mov_imm64(u8 ** pprog,u32 dst_reg,const u32 imm32_hi,const u32 imm32_lo)664 static void emit_mov_imm64(u8 **pprog, u32 dst_reg,
665 const u32 imm32_hi, const u32 imm32_lo)
666 {
667 u8 *prog = *pprog;
668
669 if (is_uimm32(((u64)imm32_hi << 32) | (u32)imm32_lo)) {
670 /*
671 * For emitting plain u32, where sign bit must not be
672 * propagated LLVM tends to load imm64 over mov32
673 * directly, so save couple of bytes by just doing
674 * 'mov %eax, imm32' instead.
675 */
676 emit_mov_imm32(&prog, false, dst_reg, imm32_lo);
677 } else {
678 /* movabsq rax, imm64 */
679 EMIT2(add_1mod(0x48, dst_reg), add_1reg(0xB8, dst_reg));
680 EMIT(imm32_lo, 4);
681 EMIT(imm32_hi, 4);
682 }
683
684 *pprog = prog;
685 }
686
emit_mov_reg(u8 ** pprog,bool is64,u32 dst_reg,u32 src_reg)687 static void emit_mov_reg(u8 **pprog, bool is64, u32 dst_reg, u32 src_reg)
688 {
689 u8 *prog = *pprog;
690
691 if (is64) {
692 /* mov dst, src */
693 EMIT_mov(dst_reg, src_reg);
694 } else {
695 /* mov32 dst, src */
696 if (is_ereg(dst_reg) || is_ereg(src_reg))
697 EMIT1(add_2mod(0x40, dst_reg, src_reg));
698 EMIT2(0x89, add_2reg(0xC0, dst_reg, src_reg));
699 }
700
701 *pprog = prog;
702 }
703
emit_movsx_reg(u8 ** pprog,int num_bits,bool is64,u32 dst_reg,u32 src_reg)704 static void emit_movsx_reg(u8 **pprog, int num_bits, bool is64, u32 dst_reg,
705 u32 src_reg)
706 {
707 u8 *prog = *pprog;
708
709 if (is64) {
710 /* movs[b,w,l]q dst, src */
711 if (num_bits == 8)
712 EMIT4(add_2mod(0x48, src_reg, dst_reg), 0x0f, 0xbe,
713 add_2reg(0xC0, src_reg, dst_reg));
714 else if (num_bits == 16)
715 EMIT4(add_2mod(0x48, src_reg, dst_reg), 0x0f, 0xbf,
716 add_2reg(0xC0, src_reg, dst_reg));
717 else if (num_bits == 32)
718 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x63,
719 add_2reg(0xC0, src_reg, dst_reg));
720 } else {
721 /* movs[b,w]l dst, src */
722 if (num_bits == 8) {
723 EMIT4(add_2mod(0x40, src_reg, dst_reg), 0x0f, 0xbe,
724 add_2reg(0xC0, src_reg, dst_reg));
725 } else if (num_bits == 16) {
726 if (is_ereg(dst_reg) || is_ereg(src_reg))
727 EMIT1(add_2mod(0x40, src_reg, dst_reg));
728 EMIT3(add_2mod(0x0f, src_reg, dst_reg), 0xbf,
729 add_2reg(0xC0, src_reg, dst_reg));
730 }
731 }
732
733 *pprog = prog;
734 }
735
736 /* Emit the suffix (ModR/M etc) for addressing *(ptr_reg + off) and val_reg */
emit_insn_suffix(u8 ** pprog,u32 ptr_reg,u32 val_reg,int off)737 static void emit_insn_suffix(u8 **pprog, u32 ptr_reg, u32 val_reg, int off)
738 {
739 u8 *prog = *pprog;
740
741 if (is_imm8(off)) {
742 /* 1-byte signed displacement.
743 *
744 * If off == 0 we could skip this and save one extra byte, but
745 * special case of x86 R13 which always needs an offset is not
746 * worth the hassle
747 */
748 EMIT2(add_2reg(0x40, ptr_reg, val_reg), off);
749 } else {
750 /* 4-byte signed displacement */
751 EMIT1_off32(add_2reg(0x80, ptr_reg, val_reg), off);
752 }
753 *pprog = prog;
754 }
755
756 /*
757 * Emit a REX byte if it will be necessary to address these registers
758 */
maybe_emit_mod(u8 ** pprog,u32 dst_reg,u32 src_reg,bool is64)759 static void maybe_emit_mod(u8 **pprog, u32 dst_reg, u32 src_reg, bool is64)
760 {
761 u8 *prog = *pprog;
762
763 if (is64)
764 EMIT1(add_2mod(0x48, dst_reg, src_reg));
765 else if (is_ereg(dst_reg) || is_ereg(src_reg))
766 EMIT1(add_2mod(0x40, dst_reg, src_reg));
767 *pprog = prog;
768 }
769
770 /*
771 * Similar version of maybe_emit_mod() for a single register
772 */
maybe_emit_1mod(u8 ** pprog,u32 reg,bool is64)773 static void maybe_emit_1mod(u8 **pprog, u32 reg, bool is64)
774 {
775 u8 *prog = *pprog;
776
777 if (is64)
778 EMIT1(add_1mod(0x48, reg));
779 else if (is_ereg(reg))
780 EMIT1(add_1mod(0x40, reg));
781 *pprog = prog;
782 }
783
784 /* LDX: dst_reg = *(u8*)(src_reg + off) */
emit_ldx(u8 ** pprog,u32 size,u32 dst_reg,u32 src_reg,int off)785 static void emit_ldx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
786 {
787 u8 *prog = *pprog;
788
789 switch (size) {
790 case BPF_B:
791 /* Emit 'movzx rax, byte ptr [rax + off]' */
792 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB6);
793 break;
794 case BPF_H:
795 /* Emit 'movzx rax, word ptr [rax + off]' */
796 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB7);
797 break;
798 case BPF_W:
799 /* Emit 'mov eax, dword ptr [rax+0x14]' */
800 if (is_ereg(dst_reg) || is_ereg(src_reg))
801 EMIT2(add_2mod(0x40, src_reg, dst_reg), 0x8B);
802 else
803 EMIT1(0x8B);
804 break;
805 case BPF_DW:
806 /* Emit 'mov rax, qword ptr [rax+0x14]' */
807 EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x8B);
808 break;
809 }
810 emit_insn_suffix(&prog, src_reg, dst_reg, off);
811 *pprog = prog;
812 }
813
814 /* LDSX: dst_reg = *(s8*)(src_reg + off) */
emit_ldsx(u8 ** pprog,u32 size,u32 dst_reg,u32 src_reg,int off)815 static void emit_ldsx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
816 {
817 u8 *prog = *pprog;
818
819 switch (size) {
820 case BPF_B:
821 /* Emit 'movsx rax, byte ptr [rax + off]' */
822 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xBE);
823 break;
824 case BPF_H:
825 /* Emit 'movsx rax, word ptr [rax + off]' */
826 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xBF);
827 break;
828 case BPF_W:
829 /* Emit 'movsx rax, dword ptr [rax+0x14]' */
830 EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x63);
831 break;
832 }
833 emit_insn_suffix(&prog, src_reg, dst_reg, off);
834 *pprog = prog;
835 }
836
837 /* STX: *(u8*)(dst_reg + off) = src_reg */
emit_stx(u8 ** pprog,u32 size,u32 dst_reg,u32 src_reg,int off)838 static void emit_stx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
839 {
840 u8 *prog = *pprog;
841
842 switch (size) {
843 case BPF_B:
844 /* Emit 'mov byte ptr [rax + off], al' */
845 if (is_ereg(dst_reg) || is_ereg_8l(src_reg))
846 /* Add extra byte for eregs or SIL,DIL,BPL in src_reg */
847 EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x88);
848 else
849 EMIT1(0x88);
850 break;
851 case BPF_H:
852 if (is_ereg(dst_reg) || is_ereg(src_reg))
853 EMIT3(0x66, add_2mod(0x40, dst_reg, src_reg), 0x89);
854 else
855 EMIT2(0x66, 0x89);
856 break;
857 case BPF_W:
858 if (is_ereg(dst_reg) || is_ereg(src_reg))
859 EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x89);
860 else
861 EMIT1(0x89);
862 break;
863 case BPF_DW:
864 EMIT2(add_2mod(0x48, dst_reg, src_reg), 0x89);
865 break;
866 }
867 emit_insn_suffix(&prog, dst_reg, src_reg, off);
868 *pprog = prog;
869 }
870
emit_atomic(u8 ** pprog,u8 atomic_op,u32 dst_reg,u32 src_reg,s16 off,u8 bpf_size)871 static int emit_atomic(u8 **pprog, u8 atomic_op,
872 u32 dst_reg, u32 src_reg, s16 off, u8 bpf_size)
873 {
874 u8 *prog = *pprog;
875
876 EMIT1(0xF0); /* lock prefix */
877
878 maybe_emit_mod(&prog, dst_reg, src_reg, bpf_size == BPF_DW);
879
880 /* emit opcode */
881 switch (atomic_op) {
882 case BPF_ADD:
883 case BPF_AND:
884 case BPF_OR:
885 case BPF_XOR:
886 /* lock *(u32/u64*)(dst_reg + off) <op>= src_reg */
887 EMIT1(simple_alu_opcodes[atomic_op]);
888 break;
889 case BPF_ADD | BPF_FETCH:
890 /* src_reg = atomic_fetch_add(dst_reg + off, src_reg); */
891 EMIT2(0x0F, 0xC1);
892 break;
893 case BPF_XCHG:
894 /* src_reg = atomic_xchg(dst_reg + off, src_reg); */
895 EMIT1(0x87);
896 break;
897 case BPF_CMPXCHG:
898 /* r0 = atomic_cmpxchg(dst_reg + off, r0, src_reg); */
899 EMIT2(0x0F, 0xB1);
900 break;
901 default:
902 pr_err("bpf_jit: unknown atomic opcode %02x\n", atomic_op);
903 return -EFAULT;
904 }
905
906 emit_insn_suffix(&prog, dst_reg, src_reg, off);
907
908 *pprog = prog;
909 return 0;
910 }
911
ex_handler_bpf(const struct exception_table_entry * x,struct pt_regs * regs)912 bool ex_handler_bpf(const struct exception_table_entry *x, struct pt_regs *regs)
913 {
914 u32 reg = x->fixup >> 8;
915
916 /* jump over faulting load and clear dest register */
917 *(unsigned long *)((void *)regs + reg) = 0;
918 regs->ip += x->fixup & 0xff;
919 return true;
920 }
921
detect_reg_usage(struct bpf_insn * insn,int insn_cnt,bool * regs_used,bool * tail_call_seen)922 static void detect_reg_usage(struct bpf_insn *insn, int insn_cnt,
923 bool *regs_used, bool *tail_call_seen)
924 {
925 int i;
926
927 for (i = 1; i <= insn_cnt; i++, insn++) {
928 if (insn->code == (BPF_JMP | BPF_TAIL_CALL))
929 *tail_call_seen = true;
930 if (insn->dst_reg == BPF_REG_6 || insn->src_reg == BPF_REG_6)
931 regs_used[0] = true;
932 if (insn->dst_reg == BPF_REG_7 || insn->src_reg == BPF_REG_7)
933 regs_used[1] = true;
934 if (insn->dst_reg == BPF_REG_8 || insn->src_reg == BPF_REG_8)
935 regs_used[2] = true;
936 if (insn->dst_reg == BPF_REG_9 || insn->src_reg == BPF_REG_9)
937 regs_used[3] = true;
938 }
939 }
940
emit_nops(u8 ** pprog,int len)941 static void emit_nops(u8 **pprog, int len)
942 {
943 u8 *prog = *pprog;
944 int i, noplen;
945
946 while (len > 0) {
947 noplen = len;
948
949 if (noplen > ASM_NOP_MAX)
950 noplen = ASM_NOP_MAX;
951
952 for (i = 0; i < noplen; i++)
953 EMIT1(x86_nops[noplen][i]);
954 len -= noplen;
955 }
956
957 *pprog = prog;
958 }
959
960 /* emit the 3-byte VEX prefix
961 *
962 * r: same as rex.r, extra bit for ModRM reg field
963 * x: same as rex.x, extra bit for SIB index field
964 * b: same as rex.b, extra bit for ModRM r/m, or SIB base
965 * m: opcode map select, encoding escape bytes e.g. 0x0f38
966 * w: same as rex.w (32 bit or 64 bit) or opcode specific
967 * src_reg2: additional source reg (encoded as BPF reg)
968 * l: vector length (128 bit or 256 bit) or reserved
969 * pp: opcode prefix (none, 0x66, 0xf2 or 0xf3)
970 */
emit_3vex(u8 ** pprog,bool r,bool x,bool b,u8 m,bool w,u8 src_reg2,bool l,u8 pp)971 static void emit_3vex(u8 **pprog, bool r, bool x, bool b, u8 m,
972 bool w, u8 src_reg2, bool l, u8 pp)
973 {
974 u8 *prog = *pprog;
975 const u8 b0 = 0xc4; /* first byte of 3-byte VEX prefix */
976 u8 b1, b2;
977 u8 vvvv = reg2hex[src_reg2];
978
979 /* reg2hex gives only the lower 3 bit of vvvv */
980 if (is_ereg(src_reg2))
981 vvvv |= 1 << 3;
982
983 /*
984 * 2nd byte of 3-byte VEX prefix
985 * ~ means bit inverted encoding
986 *
987 * 7 0
988 * +---+---+---+---+---+---+---+---+
989 * |~R |~X |~B | m |
990 * +---+---+---+---+---+---+---+---+
991 */
992 b1 = (!r << 7) | (!x << 6) | (!b << 5) | (m & 0x1f);
993 /*
994 * 3rd byte of 3-byte VEX prefix
995 *
996 * 7 0
997 * +---+---+---+---+---+---+---+---+
998 * | W | ~vvvv | L | pp |
999 * +---+---+---+---+---+---+---+---+
1000 */
1001 b2 = (w << 7) | ((~vvvv & 0xf) << 3) | (l << 2) | (pp & 3);
1002
1003 EMIT3(b0, b1, b2);
1004 *pprog = prog;
1005 }
1006
1007 /* emit BMI2 shift instruction */
emit_shiftx(u8 ** pprog,u32 dst_reg,u8 src_reg,bool is64,u8 op)1008 static void emit_shiftx(u8 **pprog, u32 dst_reg, u8 src_reg, bool is64, u8 op)
1009 {
1010 u8 *prog = *pprog;
1011 bool r = is_ereg(dst_reg);
1012 u8 m = 2; /* escape code 0f38 */
1013
1014 emit_3vex(&prog, r, false, r, m, is64, src_reg, false, op);
1015 EMIT2(0xf7, add_2reg(0xC0, dst_reg, dst_reg));
1016 *pprog = prog;
1017 }
1018
1019 #define INSN_SZ_DIFF (((addrs[i] - addrs[i - 1]) - (prog - temp)))
1020
1021 /* mov rax, qword ptr [rbp - rounded_stack_depth - 8] */
1022 #define RESTORE_TAIL_CALL_CNT(stack) \
1023 EMIT3_off32(0x48, 0x8B, 0x85, -round_up(stack, 8) - 8)
1024
do_jit(struct bpf_prog * bpf_prog,int * addrs,u8 * image,u8 * rw_image,int oldproglen,struct jit_context * ctx,bool jmp_padding)1025 static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, u8 *rw_image,
1026 int oldproglen, struct jit_context *ctx, bool jmp_padding)
1027 {
1028 bool tail_call_reachable = bpf_prog->aux->tail_call_reachable;
1029 struct bpf_insn *insn = bpf_prog->insnsi;
1030 bool callee_regs_used[4] = {};
1031 int insn_cnt = bpf_prog->len;
1032 bool tail_call_seen = false;
1033 bool seen_exit = false;
1034 u8 temp[BPF_MAX_INSN_SIZE + BPF_INSN_SAFETY];
1035 int i, excnt = 0;
1036 int ilen, proglen = 0;
1037 u8 *prog = temp;
1038 int err;
1039
1040 detect_reg_usage(insn, insn_cnt, callee_regs_used,
1041 &tail_call_seen);
1042
1043 /* tail call's presence in current prog implies it is reachable */
1044 tail_call_reachable |= tail_call_seen;
1045
1046 emit_prologue(&prog, bpf_prog->aux->stack_depth,
1047 bpf_prog_was_classic(bpf_prog), tail_call_reachable,
1048 bpf_prog->aux->func_idx != 0);
1049 push_callee_regs(&prog, callee_regs_used);
1050
1051 ilen = prog - temp;
1052 if (rw_image)
1053 memcpy(rw_image + proglen, temp, ilen);
1054 proglen += ilen;
1055 addrs[0] = proglen;
1056 prog = temp;
1057
1058 for (i = 1; i <= insn_cnt; i++, insn++) {
1059 const s32 imm32 = insn->imm;
1060 u32 dst_reg = insn->dst_reg;
1061 u32 src_reg = insn->src_reg;
1062 u8 b2 = 0, b3 = 0;
1063 u8 *start_of_ldx;
1064 s64 jmp_offset;
1065 s16 insn_off;
1066 u8 jmp_cond;
1067 u8 *func;
1068 int nops;
1069
1070 switch (insn->code) {
1071 /* ALU */
1072 case BPF_ALU | BPF_ADD | BPF_X:
1073 case BPF_ALU | BPF_SUB | BPF_X:
1074 case BPF_ALU | BPF_AND | BPF_X:
1075 case BPF_ALU | BPF_OR | BPF_X:
1076 case BPF_ALU | BPF_XOR | BPF_X:
1077 case BPF_ALU64 | BPF_ADD | BPF_X:
1078 case BPF_ALU64 | BPF_SUB | BPF_X:
1079 case BPF_ALU64 | BPF_AND | BPF_X:
1080 case BPF_ALU64 | BPF_OR | BPF_X:
1081 case BPF_ALU64 | BPF_XOR | BPF_X:
1082 maybe_emit_mod(&prog, dst_reg, src_reg,
1083 BPF_CLASS(insn->code) == BPF_ALU64);
1084 b2 = simple_alu_opcodes[BPF_OP(insn->code)];
1085 EMIT2(b2, add_2reg(0xC0, dst_reg, src_reg));
1086 break;
1087
1088 case BPF_ALU64 | BPF_MOV | BPF_X:
1089 case BPF_ALU | BPF_MOV | BPF_X:
1090 if (insn->off == 0)
1091 emit_mov_reg(&prog,
1092 BPF_CLASS(insn->code) == BPF_ALU64,
1093 dst_reg, src_reg);
1094 else
1095 emit_movsx_reg(&prog, insn->off,
1096 BPF_CLASS(insn->code) == BPF_ALU64,
1097 dst_reg, src_reg);
1098 break;
1099
1100 /* neg dst */
1101 case BPF_ALU | BPF_NEG:
1102 case BPF_ALU64 | BPF_NEG:
1103 maybe_emit_1mod(&prog, dst_reg,
1104 BPF_CLASS(insn->code) == BPF_ALU64);
1105 EMIT2(0xF7, add_1reg(0xD8, dst_reg));
1106 break;
1107
1108 case BPF_ALU | BPF_ADD | BPF_K:
1109 case BPF_ALU | BPF_SUB | BPF_K:
1110 case BPF_ALU | BPF_AND | BPF_K:
1111 case BPF_ALU | BPF_OR | BPF_K:
1112 case BPF_ALU | BPF_XOR | BPF_K:
1113 case BPF_ALU64 | BPF_ADD | BPF_K:
1114 case BPF_ALU64 | BPF_SUB | BPF_K:
1115 case BPF_ALU64 | BPF_AND | BPF_K:
1116 case BPF_ALU64 | BPF_OR | BPF_K:
1117 case BPF_ALU64 | BPF_XOR | BPF_K:
1118 maybe_emit_1mod(&prog, dst_reg,
1119 BPF_CLASS(insn->code) == BPF_ALU64);
1120
1121 /*
1122 * b3 holds 'normal' opcode, b2 short form only valid
1123 * in case dst is eax/rax.
1124 */
1125 switch (BPF_OP(insn->code)) {
1126 case BPF_ADD:
1127 b3 = 0xC0;
1128 b2 = 0x05;
1129 break;
1130 case BPF_SUB:
1131 b3 = 0xE8;
1132 b2 = 0x2D;
1133 break;
1134 case BPF_AND:
1135 b3 = 0xE0;
1136 b2 = 0x25;
1137 break;
1138 case BPF_OR:
1139 b3 = 0xC8;
1140 b2 = 0x0D;
1141 break;
1142 case BPF_XOR:
1143 b3 = 0xF0;
1144 b2 = 0x35;
1145 break;
1146 }
1147
1148 if (is_imm8(imm32))
1149 EMIT3(0x83, add_1reg(b3, dst_reg), imm32);
1150 else if (is_axreg(dst_reg))
1151 EMIT1_off32(b2, imm32);
1152 else
1153 EMIT2_off32(0x81, add_1reg(b3, dst_reg), imm32);
1154 break;
1155
1156 case BPF_ALU64 | BPF_MOV | BPF_K:
1157 case BPF_ALU | BPF_MOV | BPF_K:
1158 emit_mov_imm32(&prog, BPF_CLASS(insn->code) == BPF_ALU64,
1159 dst_reg, imm32);
1160 break;
1161
1162 case BPF_LD | BPF_IMM | BPF_DW:
1163 emit_mov_imm64(&prog, dst_reg, insn[1].imm, insn[0].imm);
1164 insn++;
1165 i++;
1166 break;
1167
1168 /* dst %= src, dst /= src, dst %= imm32, dst /= imm32 */
1169 case BPF_ALU | BPF_MOD | BPF_X:
1170 case BPF_ALU | BPF_DIV | BPF_X:
1171 case BPF_ALU | BPF_MOD | BPF_K:
1172 case BPF_ALU | BPF_DIV | BPF_K:
1173 case BPF_ALU64 | BPF_MOD | BPF_X:
1174 case BPF_ALU64 | BPF_DIV | BPF_X:
1175 case BPF_ALU64 | BPF_MOD | BPF_K:
1176 case BPF_ALU64 | BPF_DIV | BPF_K: {
1177 bool is64 = BPF_CLASS(insn->code) == BPF_ALU64;
1178
1179 if (dst_reg != BPF_REG_0)
1180 EMIT1(0x50); /* push rax */
1181 if (dst_reg != BPF_REG_3)
1182 EMIT1(0x52); /* push rdx */
1183
1184 if (BPF_SRC(insn->code) == BPF_X) {
1185 if (src_reg == BPF_REG_0 ||
1186 src_reg == BPF_REG_3) {
1187 /* mov r11, src_reg */
1188 EMIT_mov(AUX_REG, src_reg);
1189 src_reg = AUX_REG;
1190 }
1191 } else {
1192 /* mov r11, imm32 */
1193 EMIT3_off32(0x49, 0xC7, 0xC3, imm32);
1194 src_reg = AUX_REG;
1195 }
1196
1197 if (dst_reg != BPF_REG_0)
1198 /* mov rax, dst_reg */
1199 emit_mov_reg(&prog, is64, BPF_REG_0, dst_reg);
1200
1201 if (insn->off == 0) {
1202 /*
1203 * xor edx, edx
1204 * equivalent to 'xor rdx, rdx', but one byte less
1205 */
1206 EMIT2(0x31, 0xd2);
1207
1208 /* div src_reg */
1209 maybe_emit_1mod(&prog, src_reg, is64);
1210 EMIT2(0xF7, add_1reg(0xF0, src_reg));
1211 } else {
1212 if (BPF_CLASS(insn->code) == BPF_ALU)
1213 EMIT1(0x99); /* cdq */
1214 else
1215 EMIT2(0x48, 0x99); /* cqo */
1216
1217 /* idiv src_reg */
1218 maybe_emit_1mod(&prog, src_reg, is64);
1219 EMIT2(0xF7, add_1reg(0xF8, src_reg));
1220 }
1221
1222 if (BPF_OP(insn->code) == BPF_MOD &&
1223 dst_reg != BPF_REG_3)
1224 /* mov dst_reg, rdx */
1225 emit_mov_reg(&prog, is64, dst_reg, BPF_REG_3);
1226 else if (BPF_OP(insn->code) == BPF_DIV &&
1227 dst_reg != BPF_REG_0)
1228 /* mov dst_reg, rax */
1229 emit_mov_reg(&prog, is64, dst_reg, BPF_REG_0);
1230
1231 if (dst_reg != BPF_REG_3)
1232 EMIT1(0x5A); /* pop rdx */
1233 if (dst_reg != BPF_REG_0)
1234 EMIT1(0x58); /* pop rax */
1235 break;
1236 }
1237
1238 case BPF_ALU | BPF_MUL | BPF_K:
1239 case BPF_ALU64 | BPF_MUL | BPF_K:
1240 maybe_emit_mod(&prog, dst_reg, dst_reg,
1241 BPF_CLASS(insn->code) == BPF_ALU64);
1242
1243 if (is_imm8(imm32))
1244 /* imul dst_reg, dst_reg, imm8 */
1245 EMIT3(0x6B, add_2reg(0xC0, dst_reg, dst_reg),
1246 imm32);
1247 else
1248 /* imul dst_reg, dst_reg, imm32 */
1249 EMIT2_off32(0x69,
1250 add_2reg(0xC0, dst_reg, dst_reg),
1251 imm32);
1252 break;
1253
1254 case BPF_ALU | BPF_MUL | BPF_X:
1255 case BPF_ALU64 | BPF_MUL | BPF_X:
1256 maybe_emit_mod(&prog, src_reg, dst_reg,
1257 BPF_CLASS(insn->code) == BPF_ALU64);
1258
1259 /* imul dst_reg, src_reg */
1260 EMIT3(0x0F, 0xAF, add_2reg(0xC0, src_reg, dst_reg));
1261 break;
1262
1263 /* Shifts */
1264 case BPF_ALU | BPF_LSH | BPF_K:
1265 case BPF_ALU | BPF_RSH | BPF_K:
1266 case BPF_ALU | BPF_ARSH | BPF_K:
1267 case BPF_ALU64 | BPF_LSH | BPF_K:
1268 case BPF_ALU64 | BPF_RSH | BPF_K:
1269 case BPF_ALU64 | BPF_ARSH | BPF_K:
1270 maybe_emit_1mod(&prog, dst_reg,
1271 BPF_CLASS(insn->code) == BPF_ALU64);
1272
1273 b3 = simple_alu_opcodes[BPF_OP(insn->code)];
1274 if (imm32 == 1)
1275 EMIT2(0xD1, add_1reg(b3, dst_reg));
1276 else
1277 EMIT3(0xC1, add_1reg(b3, dst_reg), imm32);
1278 break;
1279
1280 case BPF_ALU | BPF_LSH | BPF_X:
1281 case BPF_ALU | BPF_RSH | BPF_X:
1282 case BPF_ALU | BPF_ARSH | BPF_X:
1283 case BPF_ALU64 | BPF_LSH | BPF_X:
1284 case BPF_ALU64 | BPF_RSH | BPF_X:
1285 case BPF_ALU64 | BPF_ARSH | BPF_X:
1286 /* BMI2 shifts aren't better when shift count is already in rcx */
1287 if (boot_cpu_has(X86_FEATURE_BMI2) && src_reg != BPF_REG_4) {
1288 /* shrx/sarx/shlx dst_reg, dst_reg, src_reg */
1289 bool w = (BPF_CLASS(insn->code) == BPF_ALU64);
1290 u8 op;
1291
1292 switch (BPF_OP(insn->code)) {
1293 case BPF_LSH:
1294 op = 1; /* prefix 0x66 */
1295 break;
1296 case BPF_RSH:
1297 op = 3; /* prefix 0xf2 */
1298 break;
1299 case BPF_ARSH:
1300 op = 2; /* prefix 0xf3 */
1301 break;
1302 }
1303
1304 emit_shiftx(&prog, dst_reg, src_reg, w, op);
1305
1306 break;
1307 }
1308
1309 if (src_reg != BPF_REG_4) { /* common case */
1310 /* Check for bad case when dst_reg == rcx */
1311 if (dst_reg == BPF_REG_4) {
1312 /* mov r11, dst_reg */
1313 EMIT_mov(AUX_REG, dst_reg);
1314 dst_reg = AUX_REG;
1315 } else {
1316 EMIT1(0x51); /* push rcx */
1317 }
1318 /* mov rcx, src_reg */
1319 EMIT_mov(BPF_REG_4, src_reg);
1320 }
1321
1322 /* shl %rax, %cl | shr %rax, %cl | sar %rax, %cl */
1323 maybe_emit_1mod(&prog, dst_reg,
1324 BPF_CLASS(insn->code) == BPF_ALU64);
1325
1326 b3 = simple_alu_opcodes[BPF_OP(insn->code)];
1327 EMIT2(0xD3, add_1reg(b3, dst_reg));
1328
1329 if (src_reg != BPF_REG_4) {
1330 if (insn->dst_reg == BPF_REG_4)
1331 /* mov dst_reg, r11 */
1332 EMIT_mov(insn->dst_reg, AUX_REG);
1333 else
1334 EMIT1(0x59); /* pop rcx */
1335 }
1336
1337 break;
1338
1339 case BPF_ALU | BPF_END | BPF_FROM_BE:
1340 case BPF_ALU64 | BPF_END | BPF_FROM_LE:
1341 switch (imm32) {
1342 case 16:
1343 /* Emit 'ror %ax, 8' to swap lower 2 bytes */
1344 EMIT1(0x66);
1345 if (is_ereg(dst_reg))
1346 EMIT1(0x41);
1347 EMIT3(0xC1, add_1reg(0xC8, dst_reg), 8);
1348
1349 /* Emit 'movzwl eax, ax' */
1350 if (is_ereg(dst_reg))
1351 EMIT3(0x45, 0x0F, 0xB7);
1352 else
1353 EMIT2(0x0F, 0xB7);
1354 EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
1355 break;
1356 case 32:
1357 /* Emit 'bswap eax' to swap lower 4 bytes */
1358 if (is_ereg(dst_reg))
1359 EMIT2(0x41, 0x0F);
1360 else
1361 EMIT1(0x0F);
1362 EMIT1(add_1reg(0xC8, dst_reg));
1363 break;
1364 case 64:
1365 /* Emit 'bswap rax' to swap 8 bytes */
1366 EMIT3(add_1mod(0x48, dst_reg), 0x0F,
1367 add_1reg(0xC8, dst_reg));
1368 break;
1369 }
1370 break;
1371
1372 case BPF_ALU | BPF_END | BPF_FROM_LE:
1373 switch (imm32) {
1374 case 16:
1375 /*
1376 * Emit 'movzwl eax, ax' to zero extend 16-bit
1377 * into 64 bit
1378 */
1379 if (is_ereg(dst_reg))
1380 EMIT3(0x45, 0x0F, 0xB7);
1381 else
1382 EMIT2(0x0F, 0xB7);
1383 EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
1384 break;
1385 case 32:
1386 /* Emit 'mov eax, eax' to clear upper 32-bits */
1387 if (is_ereg(dst_reg))
1388 EMIT1(0x45);
1389 EMIT2(0x89, add_2reg(0xC0, dst_reg, dst_reg));
1390 break;
1391 case 64:
1392 /* nop */
1393 break;
1394 }
1395 break;
1396
1397 /* speculation barrier */
1398 case BPF_ST | BPF_NOSPEC:
1399 EMIT_LFENCE();
1400 break;
1401
1402 /* ST: *(u8*)(dst_reg + off) = imm */
1403 case BPF_ST | BPF_MEM | BPF_B:
1404 if (is_ereg(dst_reg))
1405 EMIT2(0x41, 0xC6);
1406 else
1407 EMIT1(0xC6);
1408 goto st;
1409 case BPF_ST | BPF_MEM | BPF_H:
1410 if (is_ereg(dst_reg))
1411 EMIT3(0x66, 0x41, 0xC7);
1412 else
1413 EMIT2(0x66, 0xC7);
1414 goto st;
1415 case BPF_ST | BPF_MEM | BPF_W:
1416 if (is_ereg(dst_reg))
1417 EMIT2(0x41, 0xC7);
1418 else
1419 EMIT1(0xC7);
1420 goto st;
1421 case BPF_ST | BPF_MEM | BPF_DW:
1422 EMIT2(add_1mod(0x48, dst_reg), 0xC7);
1423
1424 st: if (is_imm8(insn->off))
1425 EMIT2(add_1reg(0x40, dst_reg), insn->off);
1426 else
1427 EMIT1_off32(add_1reg(0x80, dst_reg), insn->off);
1428
1429 EMIT(imm32, bpf_size_to_x86_bytes(BPF_SIZE(insn->code)));
1430 break;
1431
1432 /* STX: *(u8*)(dst_reg + off) = src_reg */
1433 case BPF_STX | BPF_MEM | BPF_B:
1434 case BPF_STX | BPF_MEM | BPF_H:
1435 case BPF_STX | BPF_MEM | BPF_W:
1436 case BPF_STX | BPF_MEM | BPF_DW:
1437 emit_stx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off);
1438 break;
1439
1440 /* LDX: dst_reg = *(u8*)(src_reg + off) */
1441 case BPF_LDX | BPF_MEM | BPF_B:
1442 case BPF_LDX | BPF_PROBE_MEM | BPF_B:
1443 case BPF_LDX | BPF_MEM | BPF_H:
1444 case BPF_LDX | BPF_PROBE_MEM | BPF_H:
1445 case BPF_LDX | BPF_MEM | BPF_W:
1446 case BPF_LDX | BPF_PROBE_MEM | BPF_W:
1447 case BPF_LDX | BPF_MEM | BPF_DW:
1448 case BPF_LDX | BPF_PROBE_MEM | BPF_DW:
1449 /* LDXS: dst_reg = *(s8*)(src_reg + off) */
1450 case BPF_LDX | BPF_MEMSX | BPF_B:
1451 case BPF_LDX | BPF_MEMSX | BPF_H:
1452 case BPF_LDX | BPF_MEMSX | BPF_W:
1453 case BPF_LDX | BPF_PROBE_MEMSX | BPF_B:
1454 case BPF_LDX | BPF_PROBE_MEMSX | BPF_H:
1455 case BPF_LDX | BPF_PROBE_MEMSX | BPF_W:
1456 insn_off = insn->off;
1457
1458 if (BPF_MODE(insn->code) == BPF_PROBE_MEM ||
1459 BPF_MODE(insn->code) == BPF_PROBE_MEMSX) {
1460 /* Conservatively check that src_reg + insn->off is a kernel address:
1461 * src_reg + insn->off > TASK_SIZE_MAX + PAGE_SIZE
1462 * and
1463 * src_reg + insn->off < VSYSCALL_ADDR
1464 */
1465
1466 u64 limit = TASK_SIZE_MAX + PAGE_SIZE - VSYSCALL_ADDR;
1467 u8 *end_of_jmp;
1468
1469 /* movabsq r10, VSYSCALL_ADDR */
1470 emit_mov_imm64(&prog, BPF_REG_AX, (long)VSYSCALL_ADDR >> 32,
1471 (u32)(long)VSYSCALL_ADDR);
1472
1473 /* mov src_reg, r11 */
1474 EMIT_mov(AUX_REG, src_reg);
1475
1476 if (insn->off) {
1477 /* add r11, insn->off */
1478 maybe_emit_1mod(&prog, AUX_REG, true);
1479 EMIT2_off32(0x81, add_1reg(0xC0, AUX_REG), insn->off);
1480 }
1481
1482 /* sub r11, r10 */
1483 maybe_emit_mod(&prog, AUX_REG, BPF_REG_AX, true);
1484 EMIT2(0x29, add_2reg(0xC0, AUX_REG, BPF_REG_AX));
1485
1486 /* movabsq r10, limit */
1487 emit_mov_imm64(&prog, BPF_REG_AX, (long)limit >> 32,
1488 (u32)(long)limit);
1489
1490 /* cmp r10, r11 */
1491 maybe_emit_mod(&prog, AUX_REG, BPF_REG_AX, true);
1492 EMIT2(0x39, add_2reg(0xC0, AUX_REG, BPF_REG_AX));
1493
1494 /* if unsigned '>', goto load */
1495 EMIT2(X86_JA, 0);
1496 end_of_jmp = prog;
1497
1498 /* xor dst_reg, dst_reg */
1499 emit_mov_imm32(&prog, false, dst_reg, 0);
1500 /* jmp byte_after_ldx */
1501 EMIT2(0xEB, 0);
1502
1503 /* populate jmp_offset for JAE above to jump to start_of_ldx */
1504 start_of_ldx = prog;
1505 end_of_jmp[-1] = start_of_ldx - end_of_jmp;
1506 }
1507 if (BPF_MODE(insn->code) == BPF_PROBE_MEMSX ||
1508 BPF_MODE(insn->code) == BPF_MEMSX)
1509 emit_ldsx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn_off);
1510 else
1511 emit_ldx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn_off);
1512 if (BPF_MODE(insn->code) == BPF_PROBE_MEM ||
1513 BPF_MODE(insn->code) == BPF_PROBE_MEMSX) {
1514 struct exception_table_entry *ex;
1515 u8 *_insn = image + proglen + (start_of_ldx - temp);
1516 s64 delta;
1517
1518 /* populate jmp_offset for JMP above */
1519 start_of_ldx[-1] = prog - start_of_ldx;
1520
1521 if (!bpf_prog->aux->extable)
1522 break;
1523
1524 if (excnt >= bpf_prog->aux->num_exentries) {
1525 pr_err("ex gen bug\n");
1526 return -EFAULT;
1527 }
1528 ex = &bpf_prog->aux->extable[excnt++];
1529
1530 delta = _insn - (u8 *)&ex->insn;
1531 if (!is_simm32(delta)) {
1532 pr_err("extable->insn doesn't fit into 32-bit\n");
1533 return -EFAULT;
1534 }
1535 /* switch ex to rw buffer for writes */
1536 ex = (void *)rw_image + ((void *)ex - (void *)image);
1537
1538 ex->insn = delta;
1539
1540 ex->data = EX_TYPE_BPF;
1541
1542 if (dst_reg > BPF_REG_9) {
1543 pr_err("verifier error\n");
1544 return -EFAULT;
1545 }
1546 /*
1547 * Compute size of x86 insn and its target dest x86 register.
1548 * ex_handler_bpf() will use lower 8 bits to adjust
1549 * pt_regs->ip to jump over this x86 instruction
1550 * and upper bits to figure out which pt_regs to zero out.
1551 * End result: x86 insn "mov rbx, qword ptr [rax+0x14]"
1552 * of 4 bytes will be ignored and rbx will be zero inited.
1553 */
1554 ex->fixup = (prog - start_of_ldx) | (reg2pt_regs[dst_reg] << 8);
1555 }
1556 break;
1557
1558 case BPF_STX | BPF_ATOMIC | BPF_W:
1559 case BPF_STX | BPF_ATOMIC | BPF_DW:
1560 if (insn->imm == (BPF_AND | BPF_FETCH) ||
1561 insn->imm == (BPF_OR | BPF_FETCH) ||
1562 insn->imm == (BPF_XOR | BPF_FETCH)) {
1563 bool is64 = BPF_SIZE(insn->code) == BPF_DW;
1564 u32 real_src_reg = src_reg;
1565 u32 real_dst_reg = dst_reg;
1566 u8 *branch_target;
1567
1568 /*
1569 * Can't be implemented with a single x86 insn.
1570 * Need to do a CMPXCHG loop.
1571 */
1572
1573 /* Will need RAX as a CMPXCHG operand so save R0 */
1574 emit_mov_reg(&prog, true, BPF_REG_AX, BPF_REG_0);
1575 if (src_reg == BPF_REG_0)
1576 real_src_reg = BPF_REG_AX;
1577 if (dst_reg == BPF_REG_0)
1578 real_dst_reg = BPF_REG_AX;
1579
1580 branch_target = prog;
1581 /* Load old value */
1582 emit_ldx(&prog, BPF_SIZE(insn->code),
1583 BPF_REG_0, real_dst_reg, insn->off);
1584 /*
1585 * Perform the (commutative) operation locally,
1586 * put the result in the AUX_REG.
1587 */
1588 emit_mov_reg(&prog, is64, AUX_REG, BPF_REG_0);
1589 maybe_emit_mod(&prog, AUX_REG, real_src_reg, is64);
1590 EMIT2(simple_alu_opcodes[BPF_OP(insn->imm)],
1591 add_2reg(0xC0, AUX_REG, real_src_reg));
1592 /* Attempt to swap in new value */
1593 err = emit_atomic(&prog, BPF_CMPXCHG,
1594 real_dst_reg, AUX_REG,
1595 insn->off,
1596 BPF_SIZE(insn->code));
1597 if (WARN_ON(err))
1598 return err;
1599 /*
1600 * ZF tells us whether we won the race. If it's
1601 * cleared we need to try again.
1602 */
1603 EMIT2(X86_JNE, -(prog - branch_target) - 2);
1604 /* Return the pre-modification value */
1605 emit_mov_reg(&prog, is64, real_src_reg, BPF_REG_0);
1606 /* Restore R0 after clobbering RAX */
1607 emit_mov_reg(&prog, true, BPF_REG_0, BPF_REG_AX);
1608 break;
1609 }
1610
1611 err = emit_atomic(&prog, insn->imm, dst_reg, src_reg,
1612 insn->off, BPF_SIZE(insn->code));
1613 if (err)
1614 return err;
1615 break;
1616
1617 /* call */
1618 case BPF_JMP | BPF_CALL: {
1619 int offs;
1620
1621 func = (u8 *) __bpf_call_base + imm32;
1622 if (tail_call_reachable) {
1623 RESTORE_TAIL_CALL_CNT(bpf_prog->aux->stack_depth);
1624 if (!imm32)
1625 return -EINVAL;
1626 offs = 7 + x86_call_depth_emit_accounting(&prog, func);
1627 } else {
1628 if (!imm32)
1629 return -EINVAL;
1630 offs = x86_call_depth_emit_accounting(&prog, func);
1631 }
1632 if (emit_call(&prog, func, image + addrs[i - 1] + offs))
1633 return -EINVAL;
1634 break;
1635 }
1636
1637 case BPF_JMP | BPF_TAIL_CALL:
1638 if (imm32)
1639 emit_bpf_tail_call_direct(&bpf_prog->aux->poke_tab[imm32 - 1],
1640 &prog, image + addrs[i - 1],
1641 callee_regs_used,
1642 bpf_prog->aux->stack_depth,
1643 ctx);
1644 else
1645 emit_bpf_tail_call_indirect(&prog,
1646 callee_regs_used,
1647 bpf_prog->aux->stack_depth,
1648 image + addrs[i - 1],
1649 ctx);
1650 break;
1651
1652 /* cond jump */
1653 case BPF_JMP | BPF_JEQ | BPF_X:
1654 case BPF_JMP | BPF_JNE | BPF_X:
1655 case BPF_JMP | BPF_JGT | BPF_X:
1656 case BPF_JMP | BPF_JLT | BPF_X:
1657 case BPF_JMP | BPF_JGE | BPF_X:
1658 case BPF_JMP | BPF_JLE | BPF_X:
1659 case BPF_JMP | BPF_JSGT | BPF_X:
1660 case BPF_JMP | BPF_JSLT | BPF_X:
1661 case BPF_JMP | BPF_JSGE | BPF_X:
1662 case BPF_JMP | BPF_JSLE | BPF_X:
1663 case BPF_JMP32 | BPF_JEQ | BPF_X:
1664 case BPF_JMP32 | BPF_JNE | BPF_X:
1665 case BPF_JMP32 | BPF_JGT | BPF_X:
1666 case BPF_JMP32 | BPF_JLT | BPF_X:
1667 case BPF_JMP32 | BPF_JGE | BPF_X:
1668 case BPF_JMP32 | BPF_JLE | BPF_X:
1669 case BPF_JMP32 | BPF_JSGT | BPF_X:
1670 case BPF_JMP32 | BPF_JSLT | BPF_X:
1671 case BPF_JMP32 | BPF_JSGE | BPF_X:
1672 case BPF_JMP32 | BPF_JSLE | BPF_X:
1673 /* cmp dst_reg, src_reg */
1674 maybe_emit_mod(&prog, dst_reg, src_reg,
1675 BPF_CLASS(insn->code) == BPF_JMP);
1676 EMIT2(0x39, add_2reg(0xC0, dst_reg, src_reg));
1677 goto emit_cond_jmp;
1678
1679 case BPF_JMP | BPF_JSET | BPF_X:
1680 case BPF_JMP32 | BPF_JSET | BPF_X:
1681 /* test dst_reg, src_reg */
1682 maybe_emit_mod(&prog, dst_reg, src_reg,
1683 BPF_CLASS(insn->code) == BPF_JMP);
1684 EMIT2(0x85, add_2reg(0xC0, dst_reg, src_reg));
1685 goto emit_cond_jmp;
1686
1687 case BPF_JMP | BPF_JSET | BPF_K:
1688 case BPF_JMP32 | BPF_JSET | BPF_K:
1689 /* test dst_reg, imm32 */
1690 maybe_emit_1mod(&prog, dst_reg,
1691 BPF_CLASS(insn->code) == BPF_JMP);
1692 EMIT2_off32(0xF7, add_1reg(0xC0, dst_reg), imm32);
1693 goto emit_cond_jmp;
1694
1695 case BPF_JMP | BPF_JEQ | BPF_K:
1696 case BPF_JMP | BPF_JNE | BPF_K:
1697 case BPF_JMP | BPF_JGT | BPF_K:
1698 case BPF_JMP | BPF_JLT | BPF_K:
1699 case BPF_JMP | BPF_JGE | BPF_K:
1700 case BPF_JMP | BPF_JLE | BPF_K:
1701 case BPF_JMP | BPF_JSGT | BPF_K:
1702 case BPF_JMP | BPF_JSLT | BPF_K:
1703 case BPF_JMP | BPF_JSGE | BPF_K:
1704 case BPF_JMP | BPF_JSLE | BPF_K:
1705 case BPF_JMP32 | BPF_JEQ | BPF_K:
1706 case BPF_JMP32 | BPF_JNE | BPF_K:
1707 case BPF_JMP32 | BPF_JGT | BPF_K:
1708 case BPF_JMP32 | BPF_JLT | BPF_K:
1709 case BPF_JMP32 | BPF_JGE | BPF_K:
1710 case BPF_JMP32 | BPF_JLE | BPF_K:
1711 case BPF_JMP32 | BPF_JSGT | BPF_K:
1712 case BPF_JMP32 | BPF_JSLT | BPF_K:
1713 case BPF_JMP32 | BPF_JSGE | BPF_K:
1714 case BPF_JMP32 | BPF_JSLE | BPF_K:
1715 /* test dst_reg, dst_reg to save one extra byte */
1716 if (imm32 == 0) {
1717 maybe_emit_mod(&prog, dst_reg, dst_reg,
1718 BPF_CLASS(insn->code) == BPF_JMP);
1719 EMIT2(0x85, add_2reg(0xC0, dst_reg, dst_reg));
1720 goto emit_cond_jmp;
1721 }
1722
1723 /* cmp dst_reg, imm8/32 */
1724 maybe_emit_1mod(&prog, dst_reg,
1725 BPF_CLASS(insn->code) == BPF_JMP);
1726
1727 if (is_imm8(imm32))
1728 EMIT3(0x83, add_1reg(0xF8, dst_reg), imm32);
1729 else
1730 EMIT2_off32(0x81, add_1reg(0xF8, dst_reg), imm32);
1731
1732 emit_cond_jmp: /* Convert BPF opcode to x86 */
1733 switch (BPF_OP(insn->code)) {
1734 case BPF_JEQ:
1735 jmp_cond = X86_JE;
1736 break;
1737 case BPF_JSET:
1738 case BPF_JNE:
1739 jmp_cond = X86_JNE;
1740 break;
1741 case BPF_JGT:
1742 /* GT is unsigned '>', JA in x86 */
1743 jmp_cond = X86_JA;
1744 break;
1745 case BPF_JLT:
1746 /* LT is unsigned '<', JB in x86 */
1747 jmp_cond = X86_JB;
1748 break;
1749 case BPF_JGE:
1750 /* GE is unsigned '>=', JAE in x86 */
1751 jmp_cond = X86_JAE;
1752 break;
1753 case BPF_JLE:
1754 /* LE is unsigned '<=', JBE in x86 */
1755 jmp_cond = X86_JBE;
1756 break;
1757 case BPF_JSGT:
1758 /* Signed '>', GT in x86 */
1759 jmp_cond = X86_JG;
1760 break;
1761 case BPF_JSLT:
1762 /* Signed '<', LT in x86 */
1763 jmp_cond = X86_JL;
1764 break;
1765 case BPF_JSGE:
1766 /* Signed '>=', GE in x86 */
1767 jmp_cond = X86_JGE;
1768 break;
1769 case BPF_JSLE:
1770 /* Signed '<=', LE in x86 */
1771 jmp_cond = X86_JLE;
1772 break;
1773 default: /* to silence GCC warning */
1774 return -EFAULT;
1775 }
1776 jmp_offset = addrs[i + insn->off] - addrs[i];
1777 if (is_imm8(jmp_offset)) {
1778 if (jmp_padding) {
1779 /* To keep the jmp_offset valid, the extra bytes are
1780 * padded before the jump insn, so we subtract the
1781 * 2 bytes of jmp_cond insn from INSN_SZ_DIFF.
1782 *
1783 * If the previous pass already emits an imm8
1784 * jmp_cond, then this BPF insn won't shrink, so
1785 * "nops" is 0.
1786 *
1787 * On the other hand, if the previous pass emits an
1788 * imm32 jmp_cond, the extra 4 bytes(*) is padded to
1789 * keep the image from shrinking further.
1790 *
1791 * (*) imm32 jmp_cond is 6 bytes, and imm8 jmp_cond
1792 * is 2 bytes, so the size difference is 4 bytes.
1793 */
1794 nops = INSN_SZ_DIFF - 2;
1795 if (nops != 0 && nops != 4) {
1796 pr_err("unexpected jmp_cond padding: %d bytes\n",
1797 nops);
1798 return -EFAULT;
1799 }
1800 emit_nops(&prog, nops);
1801 }
1802 EMIT2(jmp_cond, jmp_offset);
1803 } else if (is_simm32(jmp_offset)) {
1804 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset);
1805 } else {
1806 pr_err("cond_jmp gen bug %llx\n", jmp_offset);
1807 return -EFAULT;
1808 }
1809
1810 break;
1811
1812 case BPF_JMP | BPF_JA:
1813 case BPF_JMP32 | BPF_JA:
1814 if (BPF_CLASS(insn->code) == BPF_JMP) {
1815 if (insn->off == -1)
1816 /* -1 jmp instructions will always jump
1817 * backwards two bytes. Explicitly handling
1818 * this case avoids wasting too many passes
1819 * when there are long sequences of replaced
1820 * dead code.
1821 */
1822 jmp_offset = -2;
1823 else
1824 jmp_offset = addrs[i + insn->off] - addrs[i];
1825 } else {
1826 if (insn->imm == -1)
1827 jmp_offset = -2;
1828 else
1829 jmp_offset = addrs[i + insn->imm] - addrs[i];
1830 }
1831
1832 if (!jmp_offset) {
1833 /*
1834 * If jmp_padding is enabled, the extra nops will
1835 * be inserted. Otherwise, optimize out nop jumps.
1836 */
1837 if (jmp_padding) {
1838 /* There are 3 possible conditions.
1839 * (1) This BPF_JA is already optimized out in
1840 * the previous run, so there is no need
1841 * to pad any extra byte (0 byte).
1842 * (2) The previous pass emits an imm8 jmp,
1843 * so we pad 2 bytes to match the previous
1844 * insn size.
1845 * (3) Similarly, the previous pass emits an
1846 * imm32 jmp, and 5 bytes is padded.
1847 */
1848 nops = INSN_SZ_DIFF;
1849 if (nops != 0 && nops != 2 && nops != 5) {
1850 pr_err("unexpected nop jump padding: %d bytes\n",
1851 nops);
1852 return -EFAULT;
1853 }
1854 emit_nops(&prog, nops);
1855 }
1856 break;
1857 }
1858 emit_jmp:
1859 if (is_imm8(jmp_offset)) {
1860 if (jmp_padding) {
1861 /* To avoid breaking jmp_offset, the extra bytes
1862 * are padded before the actual jmp insn, so
1863 * 2 bytes is subtracted from INSN_SZ_DIFF.
1864 *
1865 * If the previous pass already emits an imm8
1866 * jmp, there is nothing to pad (0 byte).
1867 *
1868 * If it emits an imm32 jmp (5 bytes) previously
1869 * and now an imm8 jmp (2 bytes), then we pad
1870 * (5 - 2 = 3) bytes to stop the image from
1871 * shrinking further.
1872 */
1873 nops = INSN_SZ_DIFF - 2;
1874 if (nops != 0 && nops != 3) {
1875 pr_err("unexpected jump padding: %d bytes\n",
1876 nops);
1877 return -EFAULT;
1878 }
1879 emit_nops(&prog, INSN_SZ_DIFF - 2);
1880 }
1881 EMIT2(0xEB, jmp_offset);
1882 } else if (is_simm32(jmp_offset)) {
1883 EMIT1_off32(0xE9, jmp_offset);
1884 } else {
1885 pr_err("jmp gen bug %llx\n", jmp_offset);
1886 return -EFAULT;
1887 }
1888 break;
1889
1890 case BPF_JMP | BPF_EXIT:
1891 if (seen_exit) {
1892 jmp_offset = ctx->cleanup_addr - addrs[i];
1893 goto emit_jmp;
1894 }
1895 seen_exit = true;
1896 /* Update cleanup_addr */
1897 ctx->cleanup_addr = proglen;
1898 pop_callee_regs(&prog, callee_regs_used);
1899 EMIT1(0xC9); /* leave */
1900 emit_return(&prog, image + addrs[i - 1] + (prog - temp));
1901 break;
1902
1903 default:
1904 /*
1905 * By design x86-64 JIT should support all BPF instructions.
1906 * This error will be seen if new instruction was added
1907 * to the interpreter, but not to the JIT, or if there is
1908 * junk in bpf_prog.
1909 */
1910 pr_err("bpf_jit: unknown opcode %02x\n", insn->code);
1911 return -EINVAL;
1912 }
1913
1914 ilen = prog - temp;
1915 if (ilen > BPF_MAX_INSN_SIZE) {
1916 pr_err("bpf_jit: fatal insn size error\n");
1917 return -EFAULT;
1918 }
1919
1920 if (image) {
1921 /*
1922 * When populating the image, assert that:
1923 *
1924 * i) We do not write beyond the allocated space, and
1925 * ii) addrs[i] did not change from the prior run, in order
1926 * to validate assumptions made for computing branch
1927 * displacements.
1928 */
1929 if (unlikely(proglen + ilen > oldproglen ||
1930 proglen + ilen != addrs[i])) {
1931 pr_err("bpf_jit: fatal error\n");
1932 return -EFAULT;
1933 }
1934 memcpy(rw_image + proglen, temp, ilen);
1935 }
1936 proglen += ilen;
1937 addrs[i] = proglen;
1938 prog = temp;
1939 }
1940
1941 if (image && excnt != bpf_prog->aux->num_exentries) {
1942 pr_err("extable is not populated\n");
1943 return -EFAULT;
1944 }
1945 return proglen;
1946 }
1947
clean_stack_garbage(const struct btf_func_model * m,u8 ** pprog,int nr_stack_slots,int stack_size)1948 static void clean_stack_garbage(const struct btf_func_model *m,
1949 u8 **pprog, int nr_stack_slots,
1950 int stack_size)
1951 {
1952 int arg_size, off;
1953 u8 *prog;
1954
1955 /* Generally speaking, the compiler will pass the arguments
1956 * on-stack with "push" instruction, which will take 8-byte
1957 * on the stack. In this case, there won't be garbage values
1958 * while we copy the arguments from origin stack frame to current
1959 * in BPF_DW.
1960 *
1961 * However, sometimes the compiler will only allocate 4-byte on
1962 * the stack for the arguments. For now, this case will only
1963 * happen if there is only one argument on-stack and its size
1964 * not more than 4 byte. In this case, there will be garbage
1965 * values on the upper 4-byte where we store the argument on
1966 * current stack frame.
1967 *
1968 * arguments on origin stack:
1969 *
1970 * stack_arg_1(4-byte) xxx(4-byte)
1971 *
1972 * what we copy:
1973 *
1974 * stack_arg_1(8-byte): stack_arg_1(origin) xxx
1975 *
1976 * and the xxx is the garbage values which we should clean here.
1977 */
1978 if (nr_stack_slots != 1)
1979 return;
1980
1981 /* the size of the last argument */
1982 arg_size = m->arg_size[m->nr_args - 1];
1983 if (arg_size <= 4) {
1984 off = -(stack_size - 4);
1985 prog = *pprog;
1986 /* mov DWORD PTR [rbp + off], 0 */
1987 if (!is_imm8(off))
1988 EMIT2_off32(0xC7, 0x85, off);
1989 else
1990 EMIT3(0xC7, 0x45, off);
1991 EMIT(0, 4);
1992 *pprog = prog;
1993 }
1994 }
1995
1996 /* get the count of the regs that are used to pass arguments */
get_nr_used_regs(const struct btf_func_model * m)1997 static int get_nr_used_regs(const struct btf_func_model *m)
1998 {
1999 int i, arg_regs, nr_used_regs = 0;
2000
2001 for (i = 0; i < min_t(int, m->nr_args, MAX_BPF_FUNC_ARGS); i++) {
2002 arg_regs = (m->arg_size[i] + 7) / 8;
2003 if (nr_used_regs + arg_regs <= 6)
2004 nr_used_regs += arg_regs;
2005
2006 if (nr_used_regs >= 6)
2007 break;
2008 }
2009
2010 return nr_used_regs;
2011 }
2012
save_args(const struct btf_func_model * m,u8 ** prog,int stack_size,bool for_call_origin)2013 static void save_args(const struct btf_func_model *m, u8 **prog,
2014 int stack_size, bool for_call_origin)
2015 {
2016 int arg_regs, first_off = 0, nr_regs = 0, nr_stack_slots = 0;
2017 int i, j;
2018
2019 /* Store function arguments to stack.
2020 * For a function that accepts two pointers the sequence will be:
2021 * mov QWORD PTR [rbp-0x10],rdi
2022 * mov QWORD PTR [rbp-0x8],rsi
2023 */
2024 for (i = 0; i < min_t(int, m->nr_args, MAX_BPF_FUNC_ARGS); i++) {
2025 arg_regs = (m->arg_size[i] + 7) / 8;
2026
2027 /* According to the research of Yonghong, struct members
2028 * should be all in register or all on the stack.
2029 * Meanwhile, the compiler will pass the argument on regs
2030 * if the remaining regs can hold the argument.
2031 *
2032 * Disorder of the args can happen. For example:
2033 *
2034 * struct foo_struct {
2035 * long a;
2036 * int b;
2037 * };
2038 * int foo(char, char, char, char, char, struct foo_struct,
2039 * char);
2040 *
2041 * the arg1-5,arg7 will be passed by regs, and arg6 will
2042 * by stack.
2043 */
2044 if (nr_regs + arg_regs > 6) {
2045 /* copy function arguments from origin stack frame
2046 * into current stack frame.
2047 *
2048 * The starting address of the arguments on-stack
2049 * is:
2050 * rbp + 8(push rbp) +
2051 * 8(return addr of origin call) +
2052 * 8(return addr of the caller)
2053 * which means: rbp + 24
2054 */
2055 for (j = 0; j < arg_regs; j++) {
2056 emit_ldx(prog, BPF_DW, BPF_REG_0, BPF_REG_FP,
2057 nr_stack_slots * 8 + 0x18);
2058 emit_stx(prog, BPF_DW, BPF_REG_FP, BPF_REG_0,
2059 -stack_size);
2060
2061 if (!nr_stack_slots)
2062 first_off = stack_size;
2063 stack_size -= 8;
2064 nr_stack_slots++;
2065 }
2066 } else {
2067 /* Only copy the arguments on-stack to current
2068 * 'stack_size' and ignore the regs, used to
2069 * prepare the arguments on-stack for orign call.
2070 */
2071 if (for_call_origin) {
2072 nr_regs += arg_regs;
2073 continue;
2074 }
2075
2076 /* copy the arguments from regs into stack */
2077 for (j = 0; j < arg_regs; j++) {
2078 emit_stx(prog, BPF_DW, BPF_REG_FP,
2079 nr_regs == 5 ? X86_REG_R9 : BPF_REG_1 + nr_regs,
2080 -stack_size);
2081 stack_size -= 8;
2082 nr_regs++;
2083 }
2084 }
2085 }
2086
2087 clean_stack_garbage(m, prog, nr_stack_slots, first_off);
2088 }
2089
restore_regs(const struct btf_func_model * m,u8 ** prog,int stack_size)2090 static void restore_regs(const struct btf_func_model *m, u8 **prog,
2091 int stack_size)
2092 {
2093 int i, j, arg_regs, nr_regs = 0;
2094
2095 /* Restore function arguments from stack.
2096 * For a function that accepts two pointers the sequence will be:
2097 * EMIT4(0x48, 0x8B, 0x7D, 0xF0); mov rdi,QWORD PTR [rbp-0x10]
2098 * EMIT4(0x48, 0x8B, 0x75, 0xF8); mov rsi,QWORD PTR [rbp-0x8]
2099 *
2100 * The logic here is similar to what we do in save_args()
2101 */
2102 for (i = 0; i < min_t(int, m->nr_args, MAX_BPF_FUNC_ARGS); i++) {
2103 arg_regs = (m->arg_size[i] + 7) / 8;
2104 if (nr_regs + arg_regs <= 6) {
2105 for (j = 0; j < arg_regs; j++) {
2106 emit_ldx(prog, BPF_DW,
2107 nr_regs == 5 ? X86_REG_R9 : BPF_REG_1 + nr_regs,
2108 BPF_REG_FP,
2109 -stack_size);
2110 stack_size -= 8;
2111 nr_regs++;
2112 }
2113 } else {
2114 stack_size -= 8 * arg_regs;
2115 }
2116
2117 if (nr_regs >= 6)
2118 break;
2119 }
2120 }
2121
invoke_bpf_prog(const struct btf_func_model * m,u8 ** pprog,struct bpf_tramp_link * l,int stack_size,int run_ctx_off,bool save_ret)2122 static int invoke_bpf_prog(const struct btf_func_model *m, u8 **pprog,
2123 struct bpf_tramp_link *l, int stack_size,
2124 int run_ctx_off, bool save_ret)
2125 {
2126 u8 *prog = *pprog;
2127 u8 *jmp_insn;
2128 int ctx_cookie_off = offsetof(struct bpf_tramp_run_ctx, bpf_cookie);
2129 struct bpf_prog *p = l->link.prog;
2130 u64 cookie = l->cookie;
2131
2132 /* mov rdi, cookie */
2133 emit_mov_imm64(&prog, BPF_REG_1, (long) cookie >> 32, (u32) (long) cookie);
2134
2135 /* Prepare struct bpf_tramp_run_ctx.
2136 *
2137 * bpf_tramp_run_ctx is already preserved by
2138 * arch_prepare_bpf_trampoline().
2139 *
2140 * mov QWORD PTR [rbp - run_ctx_off + ctx_cookie_off], rdi
2141 */
2142 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_1, -run_ctx_off + ctx_cookie_off);
2143
2144 /* arg1: mov rdi, progs[i] */
2145 emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p);
2146 /* arg2: lea rsi, [rbp - ctx_cookie_off] */
2147 if (!is_imm8(-run_ctx_off))
2148 EMIT3_off32(0x48, 0x8D, 0xB5, -run_ctx_off);
2149 else
2150 EMIT4(0x48, 0x8D, 0x75, -run_ctx_off);
2151
2152 if (emit_rsb_call(&prog, bpf_trampoline_enter(p), prog))
2153 return -EINVAL;
2154 /* remember prog start time returned by __bpf_prog_enter */
2155 emit_mov_reg(&prog, true, BPF_REG_6, BPF_REG_0);
2156
2157 /* if (__bpf_prog_enter*(prog) == 0)
2158 * goto skip_exec_of_prog;
2159 */
2160 EMIT3(0x48, 0x85, 0xC0); /* test rax,rax */
2161 /* emit 2 nops that will be replaced with JE insn */
2162 jmp_insn = prog;
2163 emit_nops(&prog, 2);
2164
2165 /* arg1: lea rdi, [rbp - stack_size] */
2166 if (!is_imm8(-stack_size))
2167 EMIT3_off32(0x48, 0x8D, 0xBD, -stack_size);
2168 else
2169 EMIT4(0x48, 0x8D, 0x7D, -stack_size);
2170 /* arg2: progs[i]->insnsi for interpreter */
2171 if (!p->jited)
2172 emit_mov_imm64(&prog, BPF_REG_2,
2173 (long) p->insnsi >> 32,
2174 (u32) (long) p->insnsi);
2175 /* call JITed bpf program or interpreter */
2176 if (emit_rsb_call(&prog, p->bpf_func, prog))
2177 return -EINVAL;
2178
2179 /*
2180 * BPF_TRAMP_MODIFY_RETURN trampolines can modify the return
2181 * of the previous call which is then passed on the stack to
2182 * the next BPF program.
2183 *
2184 * BPF_TRAMP_FENTRY trampoline may need to return the return
2185 * value of BPF_PROG_TYPE_STRUCT_OPS prog.
2186 */
2187 if (save_ret)
2188 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
2189
2190 /* replace 2 nops with JE insn, since jmp target is known */
2191 jmp_insn[0] = X86_JE;
2192 jmp_insn[1] = prog - jmp_insn - 2;
2193
2194 /* arg1: mov rdi, progs[i] */
2195 emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p);
2196 /* arg2: mov rsi, rbx <- start time in nsec */
2197 emit_mov_reg(&prog, true, BPF_REG_2, BPF_REG_6);
2198 /* arg3: lea rdx, [rbp - run_ctx_off] */
2199 if (!is_imm8(-run_ctx_off))
2200 EMIT3_off32(0x48, 0x8D, 0x95, -run_ctx_off);
2201 else
2202 EMIT4(0x48, 0x8D, 0x55, -run_ctx_off);
2203 if (emit_rsb_call(&prog, bpf_trampoline_exit(p), prog))
2204 return -EINVAL;
2205
2206 *pprog = prog;
2207 return 0;
2208 }
2209
emit_align(u8 ** pprog,u32 align)2210 static void emit_align(u8 **pprog, u32 align)
2211 {
2212 u8 *target, *prog = *pprog;
2213
2214 target = PTR_ALIGN(prog, align);
2215 if (target != prog)
2216 emit_nops(&prog, target - prog);
2217
2218 *pprog = prog;
2219 }
2220
emit_cond_near_jump(u8 ** pprog,void * func,void * ip,u8 jmp_cond)2221 static int emit_cond_near_jump(u8 **pprog, void *func, void *ip, u8 jmp_cond)
2222 {
2223 u8 *prog = *pprog;
2224 s64 offset;
2225
2226 offset = func - (ip + 2 + 4);
2227 if (!is_simm32(offset)) {
2228 pr_err("Target %p is out of range\n", func);
2229 return -EINVAL;
2230 }
2231 EMIT2_off32(0x0F, jmp_cond + 0x10, offset);
2232 *pprog = prog;
2233 return 0;
2234 }
2235
invoke_bpf(const struct btf_func_model * m,u8 ** pprog,struct bpf_tramp_links * tl,int stack_size,int run_ctx_off,bool save_ret)2236 static int invoke_bpf(const struct btf_func_model *m, u8 **pprog,
2237 struct bpf_tramp_links *tl, int stack_size,
2238 int run_ctx_off, bool save_ret)
2239 {
2240 int i;
2241 u8 *prog = *pprog;
2242
2243 for (i = 0; i < tl->nr_links; i++) {
2244 if (invoke_bpf_prog(m, &prog, tl->links[i], stack_size,
2245 run_ctx_off, save_ret))
2246 return -EINVAL;
2247 }
2248 *pprog = prog;
2249 return 0;
2250 }
2251
invoke_bpf_mod_ret(const struct btf_func_model * m,u8 ** pprog,struct bpf_tramp_links * tl,int stack_size,int run_ctx_off,u8 ** branches)2252 static int invoke_bpf_mod_ret(const struct btf_func_model *m, u8 **pprog,
2253 struct bpf_tramp_links *tl, int stack_size,
2254 int run_ctx_off, u8 **branches)
2255 {
2256 u8 *prog = *pprog;
2257 int i;
2258
2259 /* The first fmod_ret program will receive a garbage return value.
2260 * Set this to 0 to avoid confusing the program.
2261 */
2262 emit_mov_imm32(&prog, false, BPF_REG_0, 0);
2263 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
2264 for (i = 0; i < tl->nr_links; i++) {
2265 if (invoke_bpf_prog(m, &prog, tl->links[i], stack_size, run_ctx_off, true))
2266 return -EINVAL;
2267
2268 /* mod_ret prog stored return value into [rbp - 8]. Emit:
2269 * if (*(u64 *)(rbp - 8) != 0)
2270 * goto do_fexit;
2271 */
2272 /* cmp QWORD PTR [rbp - 0x8], 0x0 */
2273 EMIT4(0x48, 0x83, 0x7d, 0xf8); EMIT1(0x00);
2274
2275 /* Save the location of the branch and Generate 6 nops
2276 * (4 bytes for an offset and 2 bytes for the jump) These nops
2277 * are replaced with a conditional jump once do_fexit (i.e. the
2278 * start of the fexit invocation) is finalized.
2279 */
2280 branches[i] = prog;
2281 emit_nops(&prog, 4 + 2);
2282 }
2283
2284 *pprog = prog;
2285 return 0;
2286 }
2287
2288 /* Example:
2289 * __be16 eth_type_trans(struct sk_buff *skb, struct net_device *dev);
2290 * its 'struct btf_func_model' will be nr_args=2
2291 * The assembly code when eth_type_trans is executing after trampoline:
2292 *
2293 * push rbp
2294 * mov rbp, rsp
2295 * sub rsp, 16 // space for skb and dev
2296 * push rbx // temp regs to pass start time
2297 * mov qword ptr [rbp - 16], rdi // save skb pointer to stack
2298 * mov qword ptr [rbp - 8], rsi // save dev pointer to stack
2299 * call __bpf_prog_enter // rcu_read_lock and preempt_disable
2300 * mov rbx, rax // remember start time in bpf stats are enabled
2301 * lea rdi, [rbp - 16] // R1==ctx of bpf prog
2302 * call addr_of_jited_FENTRY_prog
2303 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off
2304 * mov rsi, rbx // prog start time
2305 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math
2306 * mov rdi, qword ptr [rbp - 16] // restore skb pointer from stack
2307 * mov rsi, qword ptr [rbp - 8] // restore dev pointer from stack
2308 * pop rbx
2309 * leave
2310 * ret
2311 *
2312 * eth_type_trans has 5 byte nop at the beginning. These 5 bytes will be
2313 * replaced with 'call generated_bpf_trampoline'. When it returns
2314 * eth_type_trans will continue executing with original skb and dev pointers.
2315 *
2316 * The assembly code when eth_type_trans is called from trampoline:
2317 *
2318 * push rbp
2319 * mov rbp, rsp
2320 * sub rsp, 24 // space for skb, dev, return value
2321 * push rbx // temp regs to pass start time
2322 * mov qword ptr [rbp - 24], rdi // save skb pointer to stack
2323 * mov qword ptr [rbp - 16], rsi // save dev pointer to stack
2324 * call __bpf_prog_enter // rcu_read_lock and preempt_disable
2325 * mov rbx, rax // remember start time if bpf stats are enabled
2326 * lea rdi, [rbp - 24] // R1==ctx of bpf prog
2327 * call addr_of_jited_FENTRY_prog // bpf prog can access skb and dev
2328 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off
2329 * mov rsi, rbx // prog start time
2330 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math
2331 * mov rdi, qword ptr [rbp - 24] // restore skb pointer from stack
2332 * mov rsi, qword ptr [rbp - 16] // restore dev pointer from stack
2333 * call eth_type_trans+5 // execute body of eth_type_trans
2334 * mov qword ptr [rbp - 8], rax // save return value
2335 * call __bpf_prog_enter // rcu_read_lock and preempt_disable
2336 * mov rbx, rax // remember start time in bpf stats are enabled
2337 * lea rdi, [rbp - 24] // R1==ctx of bpf prog
2338 * call addr_of_jited_FEXIT_prog // bpf prog can access skb, dev, return value
2339 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off
2340 * mov rsi, rbx // prog start time
2341 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math
2342 * mov rax, qword ptr [rbp - 8] // restore eth_type_trans's return value
2343 * pop rbx
2344 * leave
2345 * add rsp, 8 // skip eth_type_trans's frame
2346 * ret // return to its caller
2347 */
arch_prepare_bpf_trampoline(struct bpf_tramp_image * im,void * image,void * image_end,const struct btf_func_model * m,u32 flags,struct bpf_tramp_links * tlinks,void * func_addr)2348 int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *image, void *image_end,
2349 const struct btf_func_model *m, u32 flags,
2350 struct bpf_tramp_links *tlinks,
2351 void *func_addr)
2352 {
2353 int i, ret, nr_regs = m->nr_args, stack_size = 0;
2354 int regs_off, nregs_off, ip_off, run_ctx_off, arg_stack_off, rbx_off;
2355 struct bpf_tramp_links *fentry = &tlinks[BPF_TRAMP_FENTRY];
2356 struct bpf_tramp_links *fexit = &tlinks[BPF_TRAMP_FEXIT];
2357 struct bpf_tramp_links *fmod_ret = &tlinks[BPF_TRAMP_MODIFY_RETURN];
2358 void *orig_call = func_addr;
2359 u8 **branches = NULL;
2360 u8 *prog;
2361 bool save_ret;
2362
2363 /* extra registers for struct arguments */
2364 for (i = 0; i < m->nr_args; i++)
2365 if (m->arg_flags[i] & BTF_FMODEL_STRUCT_ARG)
2366 nr_regs += (m->arg_size[i] + 7) / 8 - 1;
2367
2368 /* x86-64 supports up to MAX_BPF_FUNC_ARGS arguments. 1-6
2369 * are passed through regs, the remains are through stack.
2370 */
2371 if (nr_regs > MAX_BPF_FUNC_ARGS)
2372 return -ENOTSUPP;
2373
2374 /* Generated trampoline stack layout:
2375 *
2376 * RBP + 8 [ return address ]
2377 * RBP + 0 [ RBP ]
2378 *
2379 * RBP - 8 [ return value ] BPF_TRAMP_F_CALL_ORIG or
2380 * BPF_TRAMP_F_RET_FENTRY_RET flags
2381 *
2382 * [ reg_argN ] always
2383 * [ ... ]
2384 * RBP - regs_off [ reg_arg1 ] program's ctx pointer
2385 *
2386 * RBP - nregs_off [ regs count ] always
2387 *
2388 * RBP - ip_off [ traced function ] BPF_TRAMP_F_IP_ARG flag
2389 *
2390 * RBP - rbx_off [ rbx value ] always
2391 *
2392 * RBP - run_ctx_off [ bpf_tramp_run_ctx ]
2393 *
2394 * [ stack_argN ] BPF_TRAMP_F_CALL_ORIG
2395 * [ ... ]
2396 * [ stack_arg2 ]
2397 * RBP - arg_stack_off [ stack_arg1 ]
2398 * RSP [ tail_call_cnt ] BPF_TRAMP_F_TAIL_CALL_CTX
2399 */
2400
2401 /* room for return value of orig_call or fentry prog */
2402 save_ret = flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET);
2403 if (save_ret)
2404 stack_size += 8;
2405
2406 stack_size += nr_regs * 8;
2407 regs_off = stack_size;
2408
2409 /* regs count */
2410 stack_size += 8;
2411 nregs_off = stack_size;
2412
2413 if (flags & BPF_TRAMP_F_IP_ARG)
2414 stack_size += 8; /* room for IP address argument */
2415
2416 ip_off = stack_size;
2417
2418 stack_size += 8;
2419 rbx_off = stack_size;
2420
2421 stack_size += (sizeof(struct bpf_tramp_run_ctx) + 7) & ~0x7;
2422 run_ctx_off = stack_size;
2423
2424 if (nr_regs > 6 && (flags & BPF_TRAMP_F_CALL_ORIG)) {
2425 /* the space that used to pass arguments on-stack */
2426 stack_size += (nr_regs - get_nr_used_regs(m)) * 8;
2427 /* make sure the stack pointer is 16-byte aligned if we
2428 * need pass arguments on stack, which means
2429 * [stack_size + 8(rbp) + 8(rip) + 8(origin rip)]
2430 * should be 16-byte aligned. Following code depend on
2431 * that stack_size is already 8-byte aligned.
2432 */
2433 stack_size += (stack_size % 16) ? 0 : 8;
2434 }
2435
2436 arg_stack_off = stack_size;
2437
2438 if (flags & BPF_TRAMP_F_SKIP_FRAME) {
2439 /* skip patched call instruction and point orig_call to actual
2440 * body of the kernel function.
2441 */
2442 if (is_endbr(*(u32 *)orig_call))
2443 orig_call += ENDBR_INSN_SIZE;
2444 orig_call += X86_PATCH_SIZE;
2445 }
2446
2447 prog = image;
2448
2449 EMIT_ENDBR();
2450 /*
2451 * This is the direct-call trampoline, as such it needs accounting
2452 * for the __fentry__ call.
2453 */
2454 x86_call_depth_emit_accounting(&prog, NULL);
2455 EMIT1(0x55); /* push rbp */
2456 EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */
2457 if (!is_imm8(stack_size))
2458 /* sub rsp, stack_size */
2459 EMIT3_off32(0x48, 0x81, 0xEC, stack_size);
2460 else
2461 /* sub rsp, stack_size */
2462 EMIT4(0x48, 0x83, 0xEC, stack_size);
2463 if (flags & BPF_TRAMP_F_TAIL_CALL_CTX)
2464 EMIT1(0x50); /* push rax */
2465 /* mov QWORD PTR [rbp - rbx_off], rbx */
2466 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_6, -rbx_off);
2467
2468 /* Store number of argument registers of the traced function:
2469 * mov rax, nr_regs
2470 * mov QWORD PTR [rbp - nregs_off], rax
2471 */
2472 emit_mov_imm64(&prog, BPF_REG_0, 0, (u32) nr_regs);
2473 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -nregs_off);
2474
2475 if (flags & BPF_TRAMP_F_IP_ARG) {
2476 /* Store IP address of the traced function:
2477 * movabsq rax, func_addr
2478 * mov QWORD PTR [rbp - ip_off], rax
2479 */
2480 emit_mov_imm64(&prog, BPF_REG_0, (long) func_addr >> 32, (u32) (long) func_addr);
2481 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -ip_off);
2482 }
2483
2484 save_args(m, &prog, regs_off, false);
2485
2486 if (flags & BPF_TRAMP_F_CALL_ORIG) {
2487 /* arg1: mov rdi, im */
2488 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im);
2489 if (emit_rsb_call(&prog, __bpf_tramp_enter, prog)) {
2490 ret = -EINVAL;
2491 goto cleanup;
2492 }
2493 }
2494
2495 if (fentry->nr_links)
2496 if (invoke_bpf(m, &prog, fentry, regs_off, run_ctx_off,
2497 flags & BPF_TRAMP_F_RET_FENTRY_RET))
2498 return -EINVAL;
2499
2500 if (fmod_ret->nr_links) {
2501 branches = kcalloc(fmod_ret->nr_links, sizeof(u8 *),
2502 GFP_KERNEL);
2503 if (!branches)
2504 return -ENOMEM;
2505
2506 if (invoke_bpf_mod_ret(m, &prog, fmod_ret, regs_off,
2507 run_ctx_off, branches)) {
2508 ret = -EINVAL;
2509 goto cleanup;
2510 }
2511 }
2512
2513 if (flags & BPF_TRAMP_F_CALL_ORIG) {
2514 restore_regs(m, &prog, regs_off);
2515 save_args(m, &prog, arg_stack_off, true);
2516
2517 if (flags & BPF_TRAMP_F_TAIL_CALL_CTX)
2518 /* Before calling the original function, restore the
2519 * tail_call_cnt from stack to rax.
2520 */
2521 RESTORE_TAIL_CALL_CNT(stack_size);
2522
2523 if (flags & BPF_TRAMP_F_ORIG_STACK) {
2524 emit_ldx(&prog, BPF_DW, BPF_REG_6, BPF_REG_FP, 8);
2525 EMIT2(0xff, 0xd3); /* call *rbx */
2526 } else {
2527 /* call original function */
2528 if (emit_rsb_call(&prog, orig_call, prog)) {
2529 ret = -EINVAL;
2530 goto cleanup;
2531 }
2532 }
2533 /* remember return value in a stack for bpf prog to access */
2534 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
2535 im->ip_after_call = prog;
2536 memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
2537 prog += X86_PATCH_SIZE;
2538 }
2539
2540 if (fmod_ret->nr_links) {
2541 /* From Intel 64 and IA-32 Architectures Optimization
2542 * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler
2543 * Coding Rule 11: All branch targets should be 16-byte
2544 * aligned.
2545 */
2546 emit_align(&prog, 16);
2547 /* Update the branches saved in invoke_bpf_mod_ret with the
2548 * aligned address of do_fexit.
2549 */
2550 for (i = 0; i < fmod_ret->nr_links; i++)
2551 emit_cond_near_jump(&branches[i], prog, branches[i],
2552 X86_JNE);
2553 }
2554
2555 if (fexit->nr_links)
2556 if (invoke_bpf(m, &prog, fexit, regs_off, run_ctx_off, false)) {
2557 ret = -EINVAL;
2558 goto cleanup;
2559 }
2560
2561 if (flags & BPF_TRAMP_F_RESTORE_REGS)
2562 restore_regs(m, &prog, regs_off);
2563
2564 /* This needs to be done regardless. If there were fmod_ret programs,
2565 * the return value is only updated on the stack and still needs to be
2566 * restored to R0.
2567 */
2568 if (flags & BPF_TRAMP_F_CALL_ORIG) {
2569 im->ip_epilogue = prog;
2570 /* arg1: mov rdi, im */
2571 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im);
2572 if (emit_rsb_call(&prog, __bpf_tramp_exit, prog)) {
2573 ret = -EINVAL;
2574 goto cleanup;
2575 }
2576 } else if (flags & BPF_TRAMP_F_TAIL_CALL_CTX)
2577 /* Before running the original function, restore the
2578 * tail_call_cnt from stack to rax.
2579 */
2580 RESTORE_TAIL_CALL_CNT(stack_size);
2581
2582 /* restore return value of orig_call or fentry prog back into RAX */
2583 if (save_ret)
2584 emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, -8);
2585
2586 emit_ldx(&prog, BPF_DW, BPF_REG_6, BPF_REG_FP, -rbx_off);
2587 EMIT1(0xC9); /* leave */
2588 if (flags & BPF_TRAMP_F_SKIP_FRAME)
2589 /* skip our return address and return to parent */
2590 EMIT4(0x48, 0x83, 0xC4, 8); /* add rsp, 8 */
2591 emit_return(&prog, prog);
2592 /* Make sure the trampoline generation logic doesn't overflow */
2593 if (WARN_ON_ONCE(prog > (u8 *)image_end - BPF_INSN_SAFETY)) {
2594 ret = -EFAULT;
2595 goto cleanup;
2596 }
2597 ret = prog - (u8 *)image;
2598
2599 cleanup:
2600 kfree(branches);
2601 return ret;
2602 }
2603
emit_bpf_dispatcher(u8 ** pprog,int a,int b,s64 * progs,u8 * image,u8 * buf)2604 static int emit_bpf_dispatcher(u8 **pprog, int a, int b, s64 *progs, u8 *image, u8 *buf)
2605 {
2606 u8 *jg_reloc, *prog = *pprog;
2607 int pivot, err, jg_bytes = 1;
2608 s64 jg_offset;
2609
2610 if (a == b) {
2611 /* Leaf node of recursion, i.e. not a range of indices
2612 * anymore.
2613 */
2614 EMIT1(add_1mod(0x48, BPF_REG_3)); /* cmp rdx,func */
2615 if (!is_simm32(progs[a]))
2616 return -1;
2617 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3),
2618 progs[a]);
2619 err = emit_cond_near_jump(&prog, /* je func */
2620 (void *)progs[a], image + (prog - buf),
2621 X86_JE);
2622 if (err)
2623 return err;
2624
2625 emit_indirect_jump(&prog, 2 /* rdx */, image + (prog - buf));
2626
2627 *pprog = prog;
2628 return 0;
2629 }
2630
2631 /* Not a leaf node, so we pivot, and recursively descend into
2632 * the lower and upper ranges.
2633 */
2634 pivot = (b - a) / 2;
2635 EMIT1(add_1mod(0x48, BPF_REG_3)); /* cmp rdx,func */
2636 if (!is_simm32(progs[a + pivot]))
2637 return -1;
2638 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3), progs[a + pivot]);
2639
2640 if (pivot > 2) { /* jg upper_part */
2641 /* Require near jump. */
2642 jg_bytes = 4;
2643 EMIT2_off32(0x0F, X86_JG + 0x10, 0);
2644 } else {
2645 EMIT2(X86_JG, 0);
2646 }
2647 jg_reloc = prog;
2648
2649 err = emit_bpf_dispatcher(&prog, a, a + pivot, /* emit lower_part */
2650 progs, image, buf);
2651 if (err)
2652 return err;
2653
2654 /* From Intel 64 and IA-32 Architectures Optimization
2655 * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler
2656 * Coding Rule 11: All branch targets should be 16-byte
2657 * aligned.
2658 */
2659 emit_align(&prog, 16);
2660 jg_offset = prog - jg_reloc;
2661 emit_code(jg_reloc - jg_bytes, jg_offset, jg_bytes);
2662
2663 err = emit_bpf_dispatcher(&prog, a + pivot + 1, /* emit upper_part */
2664 b, progs, image, buf);
2665 if (err)
2666 return err;
2667
2668 *pprog = prog;
2669 return 0;
2670 }
2671
cmp_ips(const void * a,const void * b)2672 static int cmp_ips(const void *a, const void *b)
2673 {
2674 const s64 *ipa = a;
2675 const s64 *ipb = b;
2676
2677 if (*ipa > *ipb)
2678 return 1;
2679 if (*ipa < *ipb)
2680 return -1;
2681 return 0;
2682 }
2683
arch_prepare_bpf_dispatcher(void * image,void * buf,s64 * funcs,int num_funcs)2684 int arch_prepare_bpf_dispatcher(void *image, void *buf, s64 *funcs, int num_funcs)
2685 {
2686 u8 *prog = buf;
2687
2688 sort(funcs, num_funcs, sizeof(funcs[0]), cmp_ips, NULL);
2689 return emit_bpf_dispatcher(&prog, 0, num_funcs - 1, funcs, image, buf);
2690 }
2691
2692 struct x64_jit_data {
2693 struct bpf_binary_header *rw_header;
2694 struct bpf_binary_header *header;
2695 int *addrs;
2696 u8 *image;
2697 int proglen;
2698 struct jit_context ctx;
2699 };
2700
2701 #define MAX_PASSES 20
2702 #define PADDING_PASSES (MAX_PASSES - 5)
2703
bpf_int_jit_compile(struct bpf_prog * prog)2704 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
2705 {
2706 struct bpf_binary_header *rw_header = NULL;
2707 struct bpf_binary_header *header = NULL;
2708 struct bpf_prog *tmp, *orig_prog = prog;
2709 struct x64_jit_data *jit_data;
2710 int proglen, oldproglen = 0;
2711 struct jit_context ctx = {};
2712 bool tmp_blinded = false;
2713 bool extra_pass = false;
2714 bool padding = false;
2715 u8 *rw_image = NULL;
2716 u8 *image = NULL;
2717 int *addrs;
2718 int pass;
2719 int i;
2720
2721 if (!prog->jit_requested)
2722 return orig_prog;
2723
2724 tmp = bpf_jit_blind_constants(prog);
2725 /*
2726 * If blinding was requested and we failed during blinding,
2727 * we must fall back to the interpreter.
2728 */
2729 if (IS_ERR(tmp))
2730 return orig_prog;
2731 if (tmp != prog) {
2732 tmp_blinded = true;
2733 prog = tmp;
2734 }
2735
2736 jit_data = prog->aux->jit_data;
2737 if (!jit_data) {
2738 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL);
2739 if (!jit_data) {
2740 prog = orig_prog;
2741 goto out;
2742 }
2743 prog->aux->jit_data = jit_data;
2744 }
2745 addrs = jit_data->addrs;
2746 if (addrs) {
2747 ctx = jit_data->ctx;
2748 oldproglen = jit_data->proglen;
2749 image = jit_data->image;
2750 header = jit_data->header;
2751 rw_header = jit_data->rw_header;
2752 rw_image = (void *)rw_header + ((void *)image - (void *)header);
2753 extra_pass = true;
2754 padding = true;
2755 goto skip_init_addrs;
2756 }
2757 addrs = kvmalloc_array(prog->len + 1, sizeof(*addrs), GFP_KERNEL);
2758 if (!addrs) {
2759 prog = orig_prog;
2760 goto out_addrs;
2761 }
2762
2763 /*
2764 * Before first pass, make a rough estimation of addrs[]
2765 * each BPF instruction is translated to less than 64 bytes
2766 */
2767 for (proglen = 0, i = 0; i <= prog->len; i++) {
2768 proglen += 64;
2769 addrs[i] = proglen;
2770 }
2771 ctx.cleanup_addr = proglen;
2772 skip_init_addrs:
2773
2774 /*
2775 * JITed image shrinks with every pass and the loop iterates
2776 * until the image stops shrinking. Very large BPF programs
2777 * may converge on the last pass. In such case do one more
2778 * pass to emit the final image.
2779 */
2780 for (pass = 0; pass < MAX_PASSES || image; pass++) {
2781 if (!padding && pass >= PADDING_PASSES)
2782 padding = true;
2783 proglen = do_jit(prog, addrs, image, rw_image, oldproglen, &ctx, padding);
2784 if (proglen <= 0) {
2785 out_image:
2786 image = NULL;
2787 if (header) {
2788 bpf_arch_text_copy(&header->size, &rw_header->size,
2789 sizeof(rw_header->size));
2790 bpf_jit_binary_pack_free(header, rw_header);
2791 }
2792 /* Fall back to interpreter mode */
2793 prog = orig_prog;
2794 if (extra_pass) {
2795 prog->bpf_func = NULL;
2796 prog->jited = 0;
2797 prog->jited_len = 0;
2798 }
2799 goto out_addrs;
2800 }
2801 if (image) {
2802 if (proglen != oldproglen) {
2803 pr_err("bpf_jit: proglen=%d != oldproglen=%d\n",
2804 proglen, oldproglen);
2805 goto out_image;
2806 }
2807 break;
2808 }
2809 if (proglen == oldproglen) {
2810 /*
2811 * The number of entries in extable is the number of BPF_LDX
2812 * insns that access kernel memory via "pointer to BTF type".
2813 * The verifier changed their opcode from LDX|MEM|size
2814 * to LDX|PROBE_MEM|size to make JITing easier.
2815 */
2816 u32 align = __alignof__(struct exception_table_entry);
2817 u32 extable_size = prog->aux->num_exentries *
2818 sizeof(struct exception_table_entry);
2819
2820 /* allocate module memory for x86 insns and extable */
2821 header = bpf_jit_binary_pack_alloc(roundup(proglen, align) + extable_size,
2822 &image, align, &rw_header, &rw_image,
2823 jit_fill_hole);
2824 if (!header) {
2825 prog = orig_prog;
2826 goto out_addrs;
2827 }
2828 prog->aux->extable = (void *) image + roundup(proglen, align);
2829 }
2830 oldproglen = proglen;
2831 cond_resched();
2832 }
2833
2834 if (bpf_jit_enable > 1)
2835 bpf_jit_dump(prog->len, proglen, pass + 1, rw_image);
2836
2837 if (image) {
2838 if (!prog->is_func || extra_pass) {
2839 /*
2840 * bpf_jit_binary_pack_finalize fails in two scenarios:
2841 * 1) header is not pointing to proper module memory;
2842 * 2) the arch doesn't support bpf_arch_text_copy().
2843 *
2844 * Both cases are serious bugs and justify WARN_ON.
2845 */
2846 if (WARN_ON(bpf_jit_binary_pack_finalize(prog, header, rw_header))) {
2847 /* header has been freed */
2848 header = NULL;
2849 goto out_image;
2850 }
2851
2852 bpf_tail_call_direct_fixup(prog);
2853 } else {
2854 jit_data->addrs = addrs;
2855 jit_data->ctx = ctx;
2856 jit_data->proglen = proglen;
2857 jit_data->image = image;
2858 jit_data->header = header;
2859 jit_data->rw_header = rw_header;
2860 }
2861 prog->bpf_func = (void *)image;
2862 prog->jited = 1;
2863 prog->jited_len = proglen;
2864 } else {
2865 prog = orig_prog;
2866 }
2867
2868 if (!image || !prog->is_func || extra_pass) {
2869 if (image)
2870 bpf_prog_fill_jited_linfo(prog, addrs + 1);
2871 out_addrs:
2872 kvfree(addrs);
2873 kfree(jit_data);
2874 prog->aux->jit_data = NULL;
2875 }
2876 out:
2877 if (tmp_blinded)
2878 bpf_jit_prog_release_other(prog, prog == orig_prog ?
2879 tmp : orig_prog);
2880 return prog;
2881 }
2882
bpf_jit_supports_kfunc_call(void)2883 bool bpf_jit_supports_kfunc_call(void)
2884 {
2885 return true;
2886 }
2887
bpf_arch_text_copy(void * dst,void * src,size_t len)2888 void *bpf_arch_text_copy(void *dst, void *src, size_t len)
2889 {
2890 if (text_poke_copy(dst, src, len) == NULL)
2891 return ERR_PTR(-EINVAL);
2892 return dst;
2893 }
2894
2895 /* Indicate the JIT backend supports mixing bpf2bpf and tailcalls. */
bpf_jit_supports_subprog_tailcalls(void)2896 bool bpf_jit_supports_subprog_tailcalls(void)
2897 {
2898 return true;
2899 }
2900
bpf_jit_free(struct bpf_prog * prog)2901 void bpf_jit_free(struct bpf_prog *prog)
2902 {
2903 if (prog->jited) {
2904 struct x64_jit_data *jit_data = prog->aux->jit_data;
2905 struct bpf_binary_header *hdr;
2906
2907 /*
2908 * If we fail the final pass of JIT (from jit_subprogs),
2909 * the program may not be finalized yet. Call finalize here
2910 * before freeing it.
2911 */
2912 if (jit_data) {
2913 bpf_jit_binary_pack_finalize(prog, jit_data->header,
2914 jit_data->rw_header);
2915 kvfree(jit_data->addrs);
2916 kfree(jit_data);
2917 }
2918 hdr = bpf_jit_binary_pack_hdr(prog);
2919 bpf_jit_binary_pack_free(hdr, NULL);
2920 WARN_ON_ONCE(!bpf_prog_kallsyms_verify_off(prog));
2921 }
2922
2923 bpf_prog_unlock_free(prog);
2924 }
2925
bpf_arch_poke_desc_update(struct bpf_jit_poke_descriptor * poke,struct bpf_prog * new,struct bpf_prog * old)2926 void bpf_arch_poke_desc_update(struct bpf_jit_poke_descriptor *poke,
2927 struct bpf_prog *new, struct bpf_prog *old)
2928 {
2929 u8 *old_addr, *new_addr, *old_bypass_addr;
2930 int ret;
2931
2932 old_bypass_addr = old ? NULL : poke->bypass_addr;
2933 old_addr = old ? (u8 *)old->bpf_func + poke->adj_off : NULL;
2934 new_addr = new ? (u8 *)new->bpf_func + poke->adj_off : NULL;
2935
2936 /*
2937 * On program loading or teardown, the program's kallsym entry
2938 * might not be in place, so we use __bpf_arch_text_poke to skip
2939 * the kallsyms check.
2940 */
2941 if (new) {
2942 ret = __bpf_arch_text_poke(poke->tailcall_target,
2943 BPF_MOD_JUMP,
2944 old_addr, new_addr);
2945 BUG_ON(ret < 0);
2946 if (!old) {
2947 ret = __bpf_arch_text_poke(poke->tailcall_bypass,
2948 BPF_MOD_JUMP,
2949 poke->bypass_addr,
2950 NULL);
2951 BUG_ON(ret < 0);
2952 }
2953 } else {
2954 ret = __bpf_arch_text_poke(poke->tailcall_bypass,
2955 BPF_MOD_JUMP,
2956 old_bypass_addr,
2957 poke->bypass_addr);
2958 BUG_ON(ret < 0);
2959 /* let other CPUs finish the execution of program
2960 * so that it will not possible to expose them
2961 * to invalid nop, stack unwind, nop state
2962 */
2963 if (!ret)
2964 synchronize_rcu();
2965 ret = __bpf_arch_text_poke(poke->tailcall_target,
2966 BPF_MOD_JUMP,
2967 old_addr, NULL);
2968 BUG_ON(ret < 0);
2969 }
2970 }
2971