1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_PGTABLE_DEFS_H
3 #define _ASM_X86_PGTABLE_DEFS_H
4
5 #include <linux/const.h>
6 #include <linux/mem_encrypt.h>
7
8 #include <asm/page_types.h>
9
10 #define _PAGE_BIT_PRESENT 0 /* is present */
11 #define _PAGE_BIT_RW 1 /* writeable */
12 #define _PAGE_BIT_USER 2 /* userspace addressable */
13 #define _PAGE_BIT_PWT 3 /* page write through */
14 #define _PAGE_BIT_PCD 4 /* page cache disabled */
15 #define _PAGE_BIT_ACCESSED 5 /* was accessed (raised by CPU) */
16 #define _PAGE_BIT_DIRTY 6 /* was written to (raised by CPU) */
17 #define _PAGE_BIT_PSE 7 /* 4 MB (or 2MB) page */
18 #define _PAGE_BIT_PAT 7 /* on 4KB pages */
19 #define _PAGE_BIT_GLOBAL 8 /* Global TLB entry PPro+ */
20 #define _PAGE_BIT_SOFTW1 9 /* available for programmer */
21 #define _PAGE_BIT_SOFTW2 10 /* " */
22 #define _PAGE_BIT_SOFTW3 11 /* " */
23 #define _PAGE_BIT_PAT_LARGE 12 /* On 2MB or 1GB pages */
24 #define _PAGE_BIT_SOFTW4 57 /* available for programmer */
25 #define _PAGE_BIT_SOFTW5 58 /* available for programmer */
26 #define _PAGE_BIT_PKEY_BIT0 59 /* Protection Keys, bit 1/4 */
27 #define _PAGE_BIT_PKEY_BIT1 60 /* Protection Keys, bit 2/4 */
28 #define _PAGE_BIT_PKEY_BIT2 61 /* Protection Keys, bit 3/4 */
29 #define _PAGE_BIT_PKEY_BIT3 62 /* Protection Keys, bit 4/4 */
30 #define _PAGE_BIT_NX 63 /* No execute: only valid after cpuid check */
31
32 #define _PAGE_BIT_SPECIAL _PAGE_BIT_SOFTW1
33 #define _PAGE_BIT_CPA_TEST _PAGE_BIT_SOFTW1
34 #define _PAGE_BIT_UFFD_WP _PAGE_BIT_SOFTW2 /* userfaultfd wrprotected */
35 #define _PAGE_BIT_SOFT_DIRTY _PAGE_BIT_SOFTW3 /* software dirty tracking */
36 #define _PAGE_BIT_DEVMAP _PAGE_BIT_SOFTW4
37
38 #ifdef CONFIG_X86_64
39 #define _PAGE_BIT_SAVED_DIRTY _PAGE_BIT_SOFTW5 /* Saved Dirty bit (leaf) */
40 #define _PAGE_BIT_NOPTISHADOW _PAGE_BIT_SOFTW5 /* No PTI shadow (root PGD) */
41 #else
42 /* Shared with _PAGE_BIT_UFFD_WP which is not supported on 32 bit */
43 #define _PAGE_BIT_SAVED_DIRTY _PAGE_BIT_SOFTW2 /* Saved Dirty bit (leaf) */
44 #define _PAGE_BIT_NOPTISHADOW _PAGE_BIT_SOFTW2 /* No PTI shadow (root PGD) */
45 #endif
46
47 /* If _PAGE_BIT_PRESENT is clear, we use these: */
48 /* - if the user mapped it with PROT_NONE; pte_present gives true */
49 #define _PAGE_BIT_PROTNONE _PAGE_BIT_GLOBAL
50
51 #define _PAGE_PRESENT (_AT(pteval_t, 1) << _PAGE_BIT_PRESENT)
52 #define _PAGE_RW (_AT(pteval_t, 1) << _PAGE_BIT_RW)
53 #define _PAGE_USER (_AT(pteval_t, 1) << _PAGE_BIT_USER)
54 #define _PAGE_PWT (_AT(pteval_t, 1) << _PAGE_BIT_PWT)
55 #define _PAGE_PCD (_AT(pteval_t, 1) << _PAGE_BIT_PCD)
56 #define _PAGE_ACCESSED (_AT(pteval_t, 1) << _PAGE_BIT_ACCESSED)
57 #define _PAGE_DIRTY (_AT(pteval_t, 1) << _PAGE_BIT_DIRTY)
58 #define _PAGE_PSE (_AT(pteval_t, 1) << _PAGE_BIT_PSE)
59 #define _PAGE_GLOBAL (_AT(pteval_t, 1) << _PAGE_BIT_GLOBAL)
60 #define _PAGE_SOFTW1 (_AT(pteval_t, 1) << _PAGE_BIT_SOFTW1)
61 #define _PAGE_SOFTW2 (_AT(pteval_t, 1) << _PAGE_BIT_SOFTW2)
62 #define _PAGE_SOFTW3 (_AT(pteval_t, 1) << _PAGE_BIT_SOFTW3)
63 #define _PAGE_PAT (_AT(pteval_t, 1) << _PAGE_BIT_PAT)
64 #define _PAGE_PAT_LARGE (_AT(pteval_t, 1) << _PAGE_BIT_PAT_LARGE)
65 #define _PAGE_SPECIAL (_AT(pteval_t, 1) << _PAGE_BIT_SPECIAL)
66 #define _PAGE_CPA_TEST (_AT(pteval_t, 1) << _PAGE_BIT_CPA_TEST)
67 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
68 #define _PAGE_PKEY_BIT0 (_AT(pteval_t, 1) << _PAGE_BIT_PKEY_BIT0)
69 #define _PAGE_PKEY_BIT1 (_AT(pteval_t, 1) << _PAGE_BIT_PKEY_BIT1)
70 #define _PAGE_PKEY_BIT2 (_AT(pteval_t, 1) << _PAGE_BIT_PKEY_BIT2)
71 #define _PAGE_PKEY_BIT3 (_AT(pteval_t, 1) << _PAGE_BIT_PKEY_BIT3)
72 #else
73 #define _PAGE_PKEY_BIT0 (_AT(pteval_t, 0))
74 #define _PAGE_PKEY_BIT1 (_AT(pteval_t, 0))
75 #define _PAGE_PKEY_BIT2 (_AT(pteval_t, 0))
76 #define _PAGE_PKEY_BIT3 (_AT(pteval_t, 0))
77 #endif
78
79 #define _PAGE_PKEY_MASK (_PAGE_PKEY_BIT0 | \
80 _PAGE_PKEY_BIT1 | \
81 _PAGE_PKEY_BIT2 | \
82 _PAGE_PKEY_BIT3)
83
84 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
85 #define _PAGE_KNL_ERRATUM_MASK (_PAGE_DIRTY | _PAGE_ACCESSED)
86 #else
87 #define _PAGE_KNL_ERRATUM_MASK 0
88 #endif
89
90 #ifdef CONFIG_MEM_SOFT_DIRTY
91 #define _PAGE_SOFT_DIRTY (_AT(pteval_t, 1) << _PAGE_BIT_SOFT_DIRTY)
92 #else
93 #define _PAGE_SOFT_DIRTY (_AT(pteval_t, 0))
94 #endif
95
96 /*
97 * Tracking soft dirty bit when a page goes to a swap is tricky.
98 * We need a bit which can be stored in pte _and_ not conflict
99 * with swap entry format. On x86 bits 1-4 are *not* involved
100 * into swap entry computation, but bit 7 is used for thp migration,
101 * so we borrow bit 1 for soft dirty tracking.
102 *
103 * Please note that this bit must be treated as swap dirty page
104 * mark if and only if the PTE/PMD has present bit clear!
105 */
106 #ifdef CONFIG_MEM_SOFT_DIRTY
107 #define _PAGE_SWP_SOFT_DIRTY _PAGE_RW
108 #else
109 #define _PAGE_SWP_SOFT_DIRTY (_AT(pteval_t, 0))
110 #endif
111
112 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
113 #define _PAGE_UFFD_WP (_AT(pteval_t, 1) << _PAGE_BIT_UFFD_WP)
114 #define _PAGE_SWP_UFFD_WP _PAGE_USER
115 #else
116 #define _PAGE_UFFD_WP (_AT(pteval_t, 0))
117 #define _PAGE_SWP_UFFD_WP (_AT(pteval_t, 0))
118 #endif
119
120 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
121 #define _PAGE_NX (_AT(pteval_t, 1) << _PAGE_BIT_NX)
122 #define _PAGE_DEVMAP (_AT(u64, 1) << _PAGE_BIT_DEVMAP)
123 #define _PAGE_SOFTW4 (_AT(pteval_t, 1) << _PAGE_BIT_SOFTW4)
124 #else
125 #define _PAGE_NX (_AT(pteval_t, 0))
126 #define _PAGE_DEVMAP (_AT(pteval_t, 0))
127 #define _PAGE_SOFTW4 (_AT(pteval_t, 0))
128 #endif
129
130 /*
131 * The hardware requires shadow stack to be Write=0,Dirty=1. However,
132 * there are valid cases where the kernel might create read-only PTEs that
133 * are dirty (e.g., fork(), mprotect(), uffd-wp(), soft-dirty tracking). In
134 * this case, the _PAGE_SAVED_DIRTY bit is used instead of the HW-dirty bit,
135 * to avoid creating a wrong "shadow stack" PTEs. Such PTEs have
136 * (Write=0,SavedDirty=1,Dirty=0) set.
137 */
138 #define _PAGE_SAVED_DIRTY (_AT(pteval_t, 1) << _PAGE_BIT_SAVED_DIRTY)
139
140 #define _PAGE_DIRTY_BITS (_PAGE_DIRTY | _PAGE_SAVED_DIRTY)
141
142 #define _PAGE_PROTNONE (_AT(pteval_t, 1) << _PAGE_BIT_PROTNONE)
143
144 #define _PAGE_NOPTISHADOW (_AT(pteval_t, 1) << _PAGE_BIT_NOPTISHADOW)
145
146 /*
147 * Set of bits not changed in pte_modify. The pte's
148 * protection key is treated like _PAGE_RW, for
149 * instance, and is *not* included in this mask since
150 * pte_modify() does modify it.
151 */
152 #define _COMMON_PAGE_CHG_MASK (PTE_PFN_MASK | _PAGE_PCD | _PAGE_PWT | \
153 _PAGE_SPECIAL | _PAGE_ACCESSED | \
154 _PAGE_DIRTY_BITS | _PAGE_SOFT_DIRTY | \
155 _PAGE_DEVMAP | _PAGE_CC | _PAGE_UFFD_WP)
156 #define _PAGE_CHG_MASK (_COMMON_PAGE_CHG_MASK | _PAGE_PAT)
157 #define _HPAGE_CHG_MASK (_COMMON_PAGE_CHG_MASK | _PAGE_PSE | _PAGE_PAT_LARGE)
158
159 /*
160 * The cache modes defined here are used to translate between pure SW usage
161 * and the HW defined cache mode bits and/or PAT entries.
162 *
163 * The resulting bits for PWT, PCD and PAT should be chosen in a way
164 * to have the WB mode at index 0 (all bits clear). This is the default
165 * right now and likely would break too much if changed.
166 */
167 #ifndef __ASSEMBLY__
168 enum page_cache_mode {
169 _PAGE_CACHE_MODE_WB = 0,
170 _PAGE_CACHE_MODE_WC = 1,
171 _PAGE_CACHE_MODE_UC_MINUS = 2,
172 _PAGE_CACHE_MODE_UC = 3,
173 _PAGE_CACHE_MODE_WT = 4,
174 _PAGE_CACHE_MODE_WP = 5,
175
176 _PAGE_CACHE_MODE_NUM = 8
177 };
178 #endif
179
180 #define _PAGE_CC (_AT(pteval_t, cc_mask))
181 #define _PAGE_ENC (_AT(pteval_t, sme_me_mask))
182
183 #define _PAGE_CACHE_MASK (_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)
184 #define _PAGE_LARGE_CACHE_MASK (_PAGE_PWT | _PAGE_PCD | _PAGE_PAT_LARGE)
185
186 #define _PAGE_NOCACHE (cachemode2protval(_PAGE_CACHE_MODE_UC))
187 #define _PAGE_CACHE_WP (cachemode2protval(_PAGE_CACHE_MODE_WP))
188
189 #define __PP _PAGE_PRESENT
190 #define __RW _PAGE_RW
191 #define _USR _PAGE_USER
192 #define ___A _PAGE_ACCESSED
193 #define ___D _PAGE_DIRTY
194 #define ___G _PAGE_GLOBAL
195 #define __NX _PAGE_NX
196
197 #define _ENC _PAGE_ENC
198 #define __WP _PAGE_CACHE_WP
199 #define __NC _PAGE_NOCACHE
200 #define _PSE _PAGE_PSE
201
202 #define pgprot_val(x) ((x).pgprot)
203 #define __pgprot(x) ((pgprot_t) { (x) } )
204 #define __pg(x) __pgprot(x)
205
206 #define PAGE_NONE __pg( 0| 0| 0|___A| 0| 0| 0|___G)
207 #define PAGE_SHARED __pg(__PP|__RW|_USR|___A|__NX| 0| 0| 0)
208 #define PAGE_SHARED_EXEC __pg(__PP|__RW|_USR|___A| 0| 0| 0| 0)
209 #define PAGE_COPY_NOEXEC __pg(__PP| 0|_USR|___A|__NX| 0| 0| 0)
210 #define PAGE_COPY_EXEC __pg(__PP| 0|_USR|___A| 0| 0| 0| 0)
211 #define PAGE_COPY __pg(__PP| 0|_USR|___A|__NX| 0| 0| 0)
212 #define PAGE_READONLY __pg(__PP| 0|_USR|___A|__NX| 0| 0| 0)
213 #define PAGE_READONLY_EXEC __pg(__PP| 0|_USR|___A| 0| 0| 0| 0)
214
215 #define __PAGE_KERNEL (__PP|__RW| 0|___A|__NX|___D| 0|___G)
216 #define __PAGE_KERNEL_EXEC (__PP|__RW| 0|___A| 0|___D| 0|___G)
217
218 /*
219 * Page tables needs to have Write=1 in order for any lower PTEs to be
220 * writable. This includes shadow stack memory (Write=0, Dirty=1)
221 */
222 #define _KERNPG_TABLE_NOENC (__PP|__RW| 0|___A| 0|___D| 0| 0)
223 #define _KERNPG_TABLE (__PP|__RW| 0|___A| 0|___D| 0| 0| _ENC)
224 #define _PAGE_TABLE_NOENC (__PP|__RW|_USR|___A| 0|___D| 0| 0)
225 #define _PAGE_TABLE (__PP|__RW|_USR|___A| 0|___D| 0| 0| _ENC)
226
227 #define __PAGE_KERNEL_RO (__PP| 0| 0|___A|__NX| 0| 0|___G)
228 #define __PAGE_KERNEL_ROX (__PP| 0| 0|___A| 0| 0| 0|___G)
229 #define __PAGE_KERNEL (__PP|__RW| 0|___A|__NX|___D| 0|___G)
230 #define __PAGE_KERNEL_EXEC (__PP|__RW| 0|___A| 0|___D| 0|___G)
231 #define __PAGE_KERNEL_NOCACHE (__PP|__RW| 0|___A|__NX|___D| 0|___G| __NC)
232 #define __PAGE_KERNEL_VVAR (__PP| 0|_USR|___A|__NX| 0| 0|___G)
233 #define __PAGE_KERNEL_LARGE (__PP|__RW| 0|___A|__NX|___D|_PSE|___G)
234 #define __PAGE_KERNEL_LARGE_EXEC (__PP|__RW| 0|___A| 0|___D|_PSE|___G)
235 #define __PAGE_KERNEL_WP (__PP|__RW| 0|___A|__NX|___D| 0|___G| __WP)
236
237
238 #define __PAGE_KERNEL_IO __PAGE_KERNEL
239 #define __PAGE_KERNEL_IO_NOCACHE __PAGE_KERNEL_NOCACHE
240
241
242 #ifndef __ASSEMBLY__
243
244 #define __PAGE_KERNEL_ENC (__PAGE_KERNEL | _ENC)
245 #define __PAGE_KERNEL_ENC_WP (__PAGE_KERNEL_WP | _ENC)
246 #define __PAGE_KERNEL_NOENC (__PAGE_KERNEL | 0)
247 #define __PAGE_KERNEL_NOENC_WP (__PAGE_KERNEL_WP | 0)
248
249 #define __pgprot_mask(x) __pgprot((x) & __default_kernel_pte_mask)
250
251 #define PAGE_KERNEL __pgprot_mask(__PAGE_KERNEL | _ENC)
252 #define PAGE_KERNEL_NOENC __pgprot_mask(__PAGE_KERNEL | 0)
253 #define PAGE_KERNEL_RO __pgprot_mask(__PAGE_KERNEL_RO | _ENC)
254 #define PAGE_KERNEL_EXEC __pgprot_mask(__PAGE_KERNEL_EXEC | _ENC)
255 #define PAGE_KERNEL_EXEC_NOENC __pgprot_mask(__PAGE_KERNEL_EXEC | 0)
256 #define PAGE_KERNEL_ROX __pgprot_mask(__PAGE_KERNEL_ROX | _ENC)
257 #define PAGE_KERNEL_NOCACHE __pgprot_mask(__PAGE_KERNEL_NOCACHE | _ENC)
258 #define PAGE_KERNEL_LARGE __pgprot_mask(__PAGE_KERNEL_LARGE | _ENC)
259 #define PAGE_KERNEL_LARGE_EXEC __pgprot_mask(__PAGE_KERNEL_LARGE_EXEC | _ENC)
260 #define PAGE_KERNEL_VVAR __pgprot_mask(__PAGE_KERNEL_VVAR | _ENC)
261
262 #define PAGE_KERNEL_IO __pgprot_mask(__PAGE_KERNEL_IO)
263 #define PAGE_KERNEL_IO_NOCACHE __pgprot_mask(__PAGE_KERNEL_IO_NOCACHE)
264
265 #endif /* __ASSEMBLY__ */
266
267 /*
268 * early identity mapping pte attrib macros.
269 */
270 #ifdef CONFIG_X86_64
271 #define __PAGE_KERNEL_IDENT_LARGE_EXEC __PAGE_KERNEL_LARGE_EXEC
272 #else
273 #define PTE_IDENT_ATTR 0x003 /* PRESENT+RW */
274 #define PDE_IDENT_ATTR 0x063 /* PRESENT+RW+DIRTY+ACCESSED */
275 #define PGD_IDENT_ATTR 0x001 /* PRESENT (no other attributes) */
276 #endif
277
278 #ifdef CONFIG_X86_32
279 # include <asm/pgtable_32_types.h>
280 #else
281 # include <asm/pgtable_64_types.h>
282 #endif
283
284 #ifndef __ASSEMBLY__
285
286 #include <linux/types.h>
287
288 /* Extracts the PFN from a (pte|pmd|pud|pgd)val_t of a 4KB page */
289 #define PTE_PFN_MASK ((pteval_t)PHYSICAL_PAGE_MASK)
290
291 /*
292 * Extracts the flags from a (pte|pmd|pud|pgd)val_t
293 * This includes the protection key value.
294 */
295 #define PTE_FLAGS_MASK (~PTE_PFN_MASK)
296
297 typedef struct pgprot { pgprotval_t pgprot; } pgprot_t;
298
299 typedef struct { pgdval_t pgd; } pgd_t;
300
pgprot_nx(pgprot_t prot)301 static inline pgprot_t pgprot_nx(pgprot_t prot)
302 {
303 return __pgprot(pgprot_val(prot) | _PAGE_NX);
304 }
305 #define pgprot_nx pgprot_nx
306
307 #ifdef CONFIG_X86_PAE
308
309 /*
310 * PHYSICAL_PAGE_MASK might be non-constant when SME is compiled in, so we can't
311 * use it here.
312 */
313
314 #define PGD_PAE_PAGE_MASK ((signed long)PAGE_MASK)
315 #define PGD_PAE_PHYS_MASK (((1ULL << __PHYSICAL_MASK_SHIFT)-1) & PGD_PAE_PAGE_MASK)
316
317 /*
318 * PAE allows Base Address, P, PWT, PCD and AVL bits to be set in PGD entries.
319 * All other bits are Reserved MBZ
320 */
321 #define PGD_ALLOWED_BITS (PGD_PAE_PHYS_MASK | _PAGE_PRESENT | \
322 _PAGE_PWT | _PAGE_PCD | \
323 _PAGE_SOFTW1 | _PAGE_SOFTW2 | _PAGE_SOFTW3)
324
325 #else
326 /* No need to mask any bits for !PAE */
327 #define PGD_ALLOWED_BITS (~0ULL)
328 #endif
329
native_make_pgd(pgdval_t val)330 static inline pgd_t native_make_pgd(pgdval_t val)
331 {
332 return (pgd_t) { val & PGD_ALLOWED_BITS };
333 }
334
native_pgd_val(pgd_t pgd)335 static inline pgdval_t native_pgd_val(pgd_t pgd)
336 {
337 return pgd.pgd & PGD_ALLOWED_BITS;
338 }
339
pgd_flags(pgd_t pgd)340 static inline pgdval_t pgd_flags(pgd_t pgd)
341 {
342 return native_pgd_val(pgd) & PTE_FLAGS_MASK;
343 }
344
345 #if CONFIG_PGTABLE_LEVELS > 4
346 typedef struct { p4dval_t p4d; } p4d_t;
347
native_make_p4d(pudval_t val)348 static inline p4d_t native_make_p4d(pudval_t val)
349 {
350 return (p4d_t) { val };
351 }
352
native_p4d_val(p4d_t p4d)353 static inline p4dval_t native_p4d_val(p4d_t p4d)
354 {
355 return p4d.p4d;
356 }
357 #else
358 #include <asm-generic/pgtable-nop4d.h>
359
native_make_p4d(pudval_t val)360 static inline p4d_t native_make_p4d(pudval_t val)
361 {
362 return (p4d_t) { .pgd = native_make_pgd((pgdval_t)val) };
363 }
364
native_p4d_val(p4d_t p4d)365 static inline p4dval_t native_p4d_val(p4d_t p4d)
366 {
367 return native_pgd_val(p4d.pgd);
368 }
369 #endif
370
371 #if CONFIG_PGTABLE_LEVELS > 3
372 typedef struct { pudval_t pud; } pud_t;
373
native_make_pud(pmdval_t val)374 static inline pud_t native_make_pud(pmdval_t val)
375 {
376 return (pud_t) { val };
377 }
378
native_pud_val(pud_t pud)379 static inline pudval_t native_pud_val(pud_t pud)
380 {
381 return pud.pud;
382 }
383 #else
384 #include <asm-generic/pgtable-nopud.h>
385
native_make_pud(pudval_t val)386 static inline pud_t native_make_pud(pudval_t val)
387 {
388 return (pud_t) { .p4d.pgd = native_make_pgd(val) };
389 }
390
native_pud_val(pud_t pud)391 static inline pudval_t native_pud_val(pud_t pud)
392 {
393 return native_pgd_val(pud.p4d.pgd);
394 }
395 #endif
396
397 #if CONFIG_PGTABLE_LEVELS > 2
native_make_pmd(pmdval_t val)398 static inline pmd_t native_make_pmd(pmdval_t val)
399 {
400 return (pmd_t) { .pmd = val };
401 }
402
native_pmd_val(pmd_t pmd)403 static inline pmdval_t native_pmd_val(pmd_t pmd)
404 {
405 return pmd.pmd;
406 }
407 #else
408 #include <asm-generic/pgtable-nopmd.h>
409
native_make_pmd(pmdval_t val)410 static inline pmd_t native_make_pmd(pmdval_t val)
411 {
412 return (pmd_t) { .pud.p4d.pgd = native_make_pgd(val) };
413 }
414
native_pmd_val(pmd_t pmd)415 static inline pmdval_t native_pmd_val(pmd_t pmd)
416 {
417 return native_pgd_val(pmd.pud.p4d.pgd);
418 }
419 #endif
420
p4d_pfn_mask(p4d_t p4d)421 static inline p4dval_t p4d_pfn_mask(p4d_t p4d)
422 {
423 /* No 512 GiB huge pages yet */
424 return PTE_PFN_MASK;
425 }
426
p4d_flags_mask(p4d_t p4d)427 static inline p4dval_t p4d_flags_mask(p4d_t p4d)
428 {
429 return ~p4d_pfn_mask(p4d);
430 }
431
p4d_flags(p4d_t p4d)432 static inline p4dval_t p4d_flags(p4d_t p4d)
433 {
434 return native_p4d_val(p4d) & p4d_flags_mask(p4d);
435 }
436
pud_pfn_mask(pud_t pud)437 static inline pudval_t pud_pfn_mask(pud_t pud)
438 {
439 if (native_pud_val(pud) & _PAGE_PSE)
440 return PHYSICAL_PUD_PAGE_MASK;
441 else
442 return PTE_PFN_MASK;
443 }
444
pud_flags_mask(pud_t pud)445 static inline pudval_t pud_flags_mask(pud_t pud)
446 {
447 return ~pud_pfn_mask(pud);
448 }
449
pud_flags(pud_t pud)450 static inline pudval_t pud_flags(pud_t pud)
451 {
452 return native_pud_val(pud) & pud_flags_mask(pud);
453 }
454
pmd_pfn_mask(pmd_t pmd)455 static inline pmdval_t pmd_pfn_mask(pmd_t pmd)
456 {
457 if (native_pmd_val(pmd) & _PAGE_PSE)
458 return PHYSICAL_PMD_PAGE_MASK;
459 else
460 return PTE_PFN_MASK;
461 }
462
pmd_flags_mask(pmd_t pmd)463 static inline pmdval_t pmd_flags_mask(pmd_t pmd)
464 {
465 return ~pmd_pfn_mask(pmd);
466 }
467
pmd_flags(pmd_t pmd)468 static inline pmdval_t pmd_flags(pmd_t pmd)
469 {
470 return native_pmd_val(pmd) & pmd_flags_mask(pmd);
471 }
472
native_make_pte(pteval_t val)473 static inline pte_t native_make_pte(pteval_t val)
474 {
475 return (pte_t) { .pte = val };
476 }
477
native_pte_val(pte_t pte)478 static inline pteval_t native_pte_val(pte_t pte)
479 {
480 return pte.pte;
481 }
482
pte_flags(pte_t pte)483 static inline pteval_t pte_flags(pte_t pte)
484 {
485 return native_pte_val(pte) & PTE_FLAGS_MASK;
486 }
487
488 #define __pte2cm_idx(cb) \
489 ((((cb) >> (_PAGE_BIT_PAT - 2)) & 4) | \
490 (((cb) >> (_PAGE_BIT_PCD - 1)) & 2) | \
491 (((cb) >> _PAGE_BIT_PWT) & 1))
492 #define __cm_idx2pte(i) \
493 ((((i) & 4) << (_PAGE_BIT_PAT - 2)) | \
494 (((i) & 2) << (_PAGE_BIT_PCD - 1)) | \
495 (((i) & 1) << _PAGE_BIT_PWT))
496
497 unsigned long cachemode2protval(enum page_cache_mode pcm);
498
protval_4k_2_large(pgprotval_t val)499 static inline pgprotval_t protval_4k_2_large(pgprotval_t val)
500 {
501 return (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |
502 ((val & _PAGE_PAT) << (_PAGE_BIT_PAT_LARGE - _PAGE_BIT_PAT));
503 }
pgprot_4k_2_large(pgprot_t pgprot)504 static inline pgprot_t pgprot_4k_2_large(pgprot_t pgprot)
505 {
506 return __pgprot(protval_4k_2_large(pgprot_val(pgprot)));
507 }
protval_large_2_4k(pgprotval_t val)508 static inline pgprotval_t protval_large_2_4k(pgprotval_t val)
509 {
510 return (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |
511 ((val & _PAGE_PAT_LARGE) >>
512 (_PAGE_BIT_PAT_LARGE - _PAGE_BIT_PAT));
513 }
pgprot_large_2_4k(pgprot_t pgprot)514 static inline pgprot_t pgprot_large_2_4k(pgprot_t pgprot)
515 {
516 return __pgprot(protval_large_2_4k(pgprot_val(pgprot)));
517 }
518
519
520 typedef struct page *pgtable_t;
521
522 extern pteval_t __supported_pte_mask;
523 extern pteval_t __default_kernel_pte_mask;
524 extern void set_nx(void);
525 extern int nx_enabled;
526
527 #define pgprot_writecombine pgprot_writecombine
528 extern pgprot_t pgprot_writecombine(pgprot_t prot);
529
530 #define pgprot_writethrough pgprot_writethrough
531 extern pgprot_t pgprot_writethrough(pgprot_t prot);
532
533 /* Indicate that x86 has its own track and untrack pfn vma functions */
534 #define __HAVE_PFNMAP_TRACKING
535
536 #define __HAVE_PHYS_MEM_ACCESS_PROT
537 struct file;
538 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
539 unsigned long size, pgprot_t vma_prot);
540
541 /* Install a pte for a particular vaddr in kernel space. */
542 void set_pte_vaddr(unsigned long vaddr, pte_t pte);
543
544 #ifdef CONFIG_X86_32
545 extern void native_pagetable_init(void);
546 #else
547 #define native_pagetable_init paging_init
548 #endif
549
550 enum pg_level {
551 PG_LEVEL_NONE,
552 PG_LEVEL_4K,
553 PG_LEVEL_2M,
554 PG_LEVEL_1G,
555 PG_LEVEL_512G,
556 PG_LEVEL_NUM
557 };
558
559 #ifdef CONFIG_PROC_FS
560 extern void update_page_count(int level, unsigned long pages);
561 #else
update_page_count(int level,unsigned long pages)562 static inline void update_page_count(int level, unsigned long pages) { }
563 #endif
564
565 /*
566 * Helper function that returns the kernel pagetable entry controlling
567 * the virtual address 'address'. NULL means no pagetable entry present.
568 * NOTE: the return type is pte_t but if the pmd is PSE then we return it
569 * as a pte too.
570 */
571 extern pte_t *lookup_address(unsigned long address, unsigned int *level);
572 extern pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned long address,
573 unsigned int *level);
574 pte_t *lookup_address_in_pgd_attr(pgd_t *pgd, unsigned long address,
575 unsigned int *level, bool *nx, bool *rw);
576 extern pmd_t *lookup_pmd_address(unsigned long address);
577 extern phys_addr_t slow_virt_to_phys(void *__address);
578 extern int __init kernel_map_pages_in_pgd(pgd_t *pgd, u64 pfn,
579 unsigned long address,
580 unsigned numpages,
581 unsigned long page_flags);
582 extern int __init kernel_unmap_pages_in_pgd(pgd_t *pgd, unsigned long address,
583 unsigned long numpages);
584 #endif /* !__ASSEMBLY__ */
585
586 #endif /* _ASM_X86_PGTABLE_DEFS_H */
587