xref: /openbmc/linux/arch/arm/include/asm/arch_gicv3.h (revision 8bf0a804)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * arch/arm/include/asm/arch_gicv3.h
4  *
5  * Copyright (C) 2015 ARM Ltd.
6  */
7 #ifndef __ASM_ARCH_GICV3_H
8 #define __ASM_ARCH_GICV3_H
9 
10 #ifndef __ASSEMBLY__
11 
12 #include <linux/io.h>
13 #include <linux/io-64-nonatomic-lo-hi.h>
14 #include <asm/barrier.h>
15 #include <asm/cacheflush.h>
16 #include <asm/cp15.h>
17 
18 #define ICC_EOIR1			__ACCESS_CP15(c12, 0, c12, 1)
19 #define ICC_DIR				__ACCESS_CP15(c12, 0, c11, 1)
20 #define ICC_IAR1			__ACCESS_CP15(c12, 0, c12, 0)
21 #define ICC_SGI1R			__ACCESS_CP15_64(0, c12)
22 #define ICC_PMR				__ACCESS_CP15(c4, 0, c6, 0)
23 #define ICC_CTLR			__ACCESS_CP15(c12, 0, c12, 4)
24 #define ICC_SRE				__ACCESS_CP15(c12, 0, c12, 5)
25 #define ICC_IGRPEN1			__ACCESS_CP15(c12, 0, c12, 7)
26 #define ICC_BPR1			__ACCESS_CP15(c12, 0, c12, 3)
27 #define ICC_RPR				__ACCESS_CP15(c12, 0, c11, 3)
28 
29 #define __ICC_AP0Rx(x)			__ACCESS_CP15(c12, 0, c8, 4 | x)
30 #define ICC_AP0R0			__ICC_AP0Rx(0)
31 #define ICC_AP0R1			__ICC_AP0Rx(1)
32 #define ICC_AP0R2			__ICC_AP0Rx(2)
33 #define ICC_AP0R3			__ICC_AP0Rx(3)
34 
35 #define __ICC_AP1Rx(x)			__ACCESS_CP15(c12, 0, c9, x)
36 #define ICC_AP1R0			__ICC_AP1Rx(0)
37 #define ICC_AP1R1			__ICC_AP1Rx(1)
38 #define ICC_AP1R2			__ICC_AP1Rx(2)
39 #define ICC_AP1R3			__ICC_AP1Rx(3)
40 
41 #define CPUIF_MAP(a32, a64)			\
42 static inline void write_ ## a64(u32 val)	\
43 {						\
44 	write_sysreg(val, a32);			\
45 }						\
46 static inline u32 read_ ## a64(void)		\
47 {						\
48 	return read_sysreg(a32); 		\
49 }						\
50 
CPUIF_MAP(ICC_EOIR1,ICC_EOIR1_EL1)51 CPUIF_MAP(ICC_EOIR1, ICC_EOIR1_EL1)
52 CPUIF_MAP(ICC_PMR, ICC_PMR_EL1)
53 CPUIF_MAP(ICC_AP0R0, ICC_AP0R0_EL1)
54 CPUIF_MAP(ICC_AP0R1, ICC_AP0R1_EL1)
55 CPUIF_MAP(ICC_AP0R2, ICC_AP0R2_EL1)
56 CPUIF_MAP(ICC_AP0R3, ICC_AP0R3_EL1)
57 CPUIF_MAP(ICC_AP1R0, ICC_AP1R0_EL1)
58 CPUIF_MAP(ICC_AP1R1, ICC_AP1R1_EL1)
59 CPUIF_MAP(ICC_AP1R2, ICC_AP1R2_EL1)
60 CPUIF_MAP(ICC_AP1R3, ICC_AP1R3_EL1)
61 
62 #define read_gicreg(r)                 read_##r()
63 #define write_gicreg(v, r)             write_##r(v)
64 
65 /* Low-level accessors */
66 
67 static inline void gic_write_dir(u32 val)
68 {
69 	write_sysreg(val, ICC_DIR);
70 	isb();
71 }
72 
gic_read_iar(void)73 static inline u32 gic_read_iar(void)
74 {
75 	u32 irqstat = read_sysreg(ICC_IAR1);
76 
77 	dsb(sy);
78 
79 	return irqstat;
80 }
81 
gic_write_ctlr(u32 val)82 static inline void gic_write_ctlr(u32 val)
83 {
84 	write_sysreg(val, ICC_CTLR);
85 	isb();
86 }
87 
gic_read_ctlr(void)88 static inline u32 gic_read_ctlr(void)
89 {
90 	return read_sysreg(ICC_CTLR);
91 }
92 
gic_write_grpen1(u32 val)93 static inline void gic_write_grpen1(u32 val)
94 {
95 	write_sysreg(val, ICC_IGRPEN1);
96 	isb();
97 }
98 
gic_write_sgi1r(u64 val)99 static inline void gic_write_sgi1r(u64 val)
100 {
101 	write_sysreg(val, ICC_SGI1R);
102 }
103 
gic_read_sre(void)104 static inline u32 gic_read_sre(void)
105 {
106 	return read_sysreg(ICC_SRE);
107 }
108 
gic_write_sre(u32 val)109 static inline void gic_write_sre(u32 val)
110 {
111 	write_sysreg(val, ICC_SRE);
112 	isb();
113 }
114 
gic_write_bpr1(u32 val)115 static inline void gic_write_bpr1(u32 val)
116 {
117 	write_sysreg(val, ICC_BPR1);
118 }
119 
gic_read_pmr(void)120 static inline u32 gic_read_pmr(void)
121 {
122 	return read_sysreg(ICC_PMR);
123 }
124 
gic_write_pmr(u32 val)125 static inline void gic_write_pmr(u32 val)
126 {
127 	write_sysreg(val, ICC_PMR);
128 }
129 
gic_read_rpr(void)130 static inline u32 gic_read_rpr(void)
131 {
132 	return read_sysreg(ICC_RPR);
133 }
134 
135 /*
136  * Even in 32bit systems that use LPAE, there is no guarantee that the I/O
137  * interface provides true 64bit atomic accesses, so using strd/ldrd doesn't
138  * make much sense.
139  * Moreover, 64bit I/O emulation is extremely difficult to implement on
140  * AArch32, since the syndrome register doesn't provide any information for
141  * them.
142  * Consequently, the following IO helpers use 32bit accesses.
143  */
__gic_writeq_nonatomic(u64 val,volatile void __iomem * addr)144 static inline void __gic_writeq_nonatomic(u64 val, volatile void __iomem *addr)
145 {
146 	writel_relaxed((u32)val, addr);
147 	writel_relaxed((u32)(val >> 32), addr + 4);
148 }
149 
__gic_readq_nonatomic(const volatile void __iomem * addr)150 static inline u64 __gic_readq_nonatomic(const volatile void __iomem *addr)
151 {
152 	u64 val;
153 
154 	val = readl_relaxed(addr);
155 	val |= (u64)readl_relaxed(addr + 4) << 32;
156 	return val;
157 }
158 
159 #define gic_flush_dcache_to_poc(a,l)    __cpuc_flush_dcache_area((a), (l))
160 
161 /*
162  *  GICD_IROUTERn, contain the affinity values associated to each interrupt.
163  *  The upper-word (aff3) will always be 0, so there is no need for a lock.
164  */
165 #define gic_write_irouter(v, c)		__gic_writeq_nonatomic(v, c)
166 
167 /*
168  * GICR_TYPER is an ID register and doesn't need atomicity.
169  */
170 #define gic_read_typer(c)		__gic_readq_nonatomic(c)
171 
172 /*
173  * GITS_BASER - hi and lo bits may be accessed independently.
174  */
175 #define gits_read_baser(c)		__gic_readq_nonatomic(c)
176 #define gits_write_baser(v, c)		__gic_writeq_nonatomic(v, c)
177 
178 /*
179  * GICR_PENDBASER and GICR_PROPBASE are changed with LPIs disabled, so they
180  * won't be being used during any updates and can be changed non-atomically
181  */
182 #define gicr_read_propbaser(c)		__gic_readq_nonatomic(c)
183 #define gicr_write_propbaser(v, c)	__gic_writeq_nonatomic(v, c)
184 #define gicr_read_pendbaser(c)		__gic_readq_nonatomic(c)
185 #define gicr_write_pendbaser(v, c)	__gic_writeq_nonatomic(v, c)
186 
187 /*
188  * GICR_xLPIR - only the lower bits are significant
189  */
190 #define gic_read_lpir(c)		readl_relaxed(c)
191 #define gic_write_lpir(v, c)		writel_relaxed(lower_32_bits(v), c)
192 
193 /*
194  * GITS_TYPER is an ID register and doesn't need atomicity.
195  */
196 #define gits_read_typer(c)		__gic_readq_nonatomic(c)
197 
198 /*
199  * GITS_CBASER - hi and lo bits may be accessed independently.
200  */
201 #define gits_read_cbaser(c)		__gic_readq_nonatomic(c)
202 #define gits_write_cbaser(v, c)		__gic_writeq_nonatomic(v, c)
203 
204 /*
205  * GITS_CWRITER - hi and lo bits may be accessed independently.
206  */
207 #define gits_write_cwriter(v, c)	__gic_writeq_nonatomic(v, c)
208 
209 /*
210  * GICR_VPROPBASER - hi and lo bits may be accessed independently.
211  */
212 #define gicr_read_vpropbaser(c)		__gic_readq_nonatomic(c)
213 #define gicr_write_vpropbaser(v, c)	__gic_writeq_nonatomic(v, c)
214 
215 /*
216  * GICR_VPENDBASER - the Valid bit must be cleared before changing
217  * anything else.
218  */
gicr_write_vpendbaser(u64 val,void __iomem * addr)219 static inline void gicr_write_vpendbaser(u64 val, void __iomem *addr)
220 {
221 	u32 tmp;
222 
223 	tmp = readl_relaxed(addr + 4);
224 	if (tmp & (GICR_VPENDBASER_Valid >> 32)) {
225 		tmp &= ~(GICR_VPENDBASER_Valid >> 32);
226 		writel_relaxed(tmp, addr + 4);
227 	}
228 
229 	/*
230 	 * Use the fact that __gic_writeq_nonatomic writes the second
231 	 * half of the 64bit quantity after the first.
232 	 */
233 	__gic_writeq_nonatomic(val, addr);
234 }
235 
236 #define gicr_read_vpendbaser(c)		__gic_readq_nonatomic(c)
237 
gic_prio_masking_enabled(void)238 static inline bool gic_prio_masking_enabled(void)
239 {
240 	return false;
241 }
242 
gic_pmr_mask_irqs(void)243 static inline void gic_pmr_mask_irqs(void)
244 {
245 	/* Should not get called. */
246 	WARN_ON_ONCE(true);
247 }
248 
gic_arch_enable_irqs(void)249 static inline void gic_arch_enable_irqs(void)
250 {
251 	/* Should not get called. */
252 	WARN_ON_ONCE(true);
253 }
254 
gic_has_relaxed_pmr_sync(void)255 static inline bool gic_has_relaxed_pmr_sync(void)
256 {
257 	return false;
258 }
259 
260 #endif /* !__ASSEMBLY__ */
261 #endif /* !__ASM_ARCH_GICV3_H */
262