xref: /openbmc/u-boot/drivers/gpio/mscc_sgpio.c (revision 77c07e7e)
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3  * Microsemi SoCs serial gpio driver
4  *
5  * Author: <lars.povlsen@microchip.com>
6  *
7  * Copyright (c) 2018 Microsemi Corporation
8  */
9 
10 #include <common.h>
11 #include <dm.h>
12 #include <asm/gpio.h>
13 #include <asm/io.h>
14 #include <errno.h>
15 #include <clk.h>
16 
17 #define MSCC_SGPIOS_PER_BANK	32
18 #define MSCC_SGPIO_BANK_DEPTH	4
19 
20 enum {
21 	REG_INPUT_DATA,
22 	REG_PORT_CONFIG,
23 	REG_PORT_ENABLE,
24 	REG_SIO_CONFIG,
25 	REG_SIO_CLOCK,
26 	MAXREG
27 };
28 
29 struct mscc_sgpio_bf {
30 	u8 beg;
31 	u8 end;
32 };
33 
34 struct mscc_sgpio_props {
35 	u8 regoff[MAXREG];
36 	struct mscc_sgpio_bf auto_repeat;
37 	struct mscc_sgpio_bf port_width;
38 	struct mscc_sgpio_bf clk_freq;
39 	struct mscc_sgpio_bf bit_source;
40 };
41 
42 #define __M(bf)		GENMASK((bf).end, (bf).beg)
43 #define __F(bf, x)	(__M(bf) & ((x) << (bf).beg))
44 #define __X(bf, x)	(((x) >> (bf).beg) & GENMASK(((bf).end - (bf).beg), 0))
45 
46 #define MSCC_M_CFG_SIO_AUTO_REPEAT(p)		BIT(p->props->auto_repeat.beg)
47 #define MSCC_F_CFG_SIO_PORT_WIDTH(p, x)		__F(p->props->port_width, x)
48 #define MSCC_M_CFG_SIO_PORT_WIDTH(p)		__M(p->props->port_width)
49 #define MSCC_F_CLOCK_SIO_CLK_FREQ(p, x)		__F(p->props->clk_freq, x)
50 #define MSCC_M_CLOCK_SIO_CLK_FREQ(p)		__M(p->props->clk_freq)
51 #define MSCC_F_PORT_CFG_BIT_SOURCE(p, x)	__F(p->props->bit_source, x)
52 #define MSCC_X_PORT_CFG_BIT_SOURCE(p, x)	__X(p->props->bit_source, x)
53 
54 const struct mscc_sgpio_props props_luton = {
55 	.regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b },
56 	.auto_repeat = { 5, 5 },
57 	.port_width  = { 2, 3 },
58 	.clk_freq    = { 0, 11 },
59 	.bit_source  = { 0, 11 },
60 };
61 
62 const struct mscc_sgpio_props props_ocelot = {
63 	.regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 },
64 	.auto_repeat = { 10, 10 },
65 	.port_width  = {  7, 8  },
66 	.clk_freq    = {  8, 19 },
67 	.bit_source  = { 12, 23 },
68 };
69 
70 struct mscc_sgpio_priv {
71 	u32 bitcount;
72 	u32 ports;
73 	u32 clock;
74 	u32 mode[MSCC_SGPIOS_PER_BANK];
75 	u32 __iomem *regs;
76 	const struct mscc_sgpio_props *props;
77 };
78 
sgpio_readl(struct mscc_sgpio_priv * priv,u32 rno,u32 off)79 static inline u32 sgpio_readl(struct mscc_sgpio_priv *priv, u32 rno, u32 off)
80 {
81 	u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
82 
83 	return readl(reg);
84 }
85 
sgpio_writel(struct mscc_sgpio_priv * priv,u32 val,u32 rno,u32 off)86 static inline void sgpio_writel(struct mscc_sgpio_priv *priv,
87 				u32 val, u32 rno, u32 off)
88 {
89 	u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
90 
91 	writel(val, reg);
92 }
93 
sgpio_clrsetbits(struct mscc_sgpio_priv * priv,u32 rno,u32 off,u32 clear,u32 set)94 static void sgpio_clrsetbits(struct mscc_sgpio_priv *priv,
95 			     u32 rno, u32 off, u32 clear, u32 set)
96 {
97 	u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
98 
99 	clrsetbits_le32(reg, clear, set);
100 }
101 
mscc_sgpio_direction_input(struct udevice * dev,unsigned int gpio)102 static int mscc_sgpio_direction_input(struct udevice *dev, unsigned int gpio)
103 {
104 	struct mscc_sgpio_priv *priv = dev_get_priv(dev);
105 
106 	u32 port = gpio % MSCC_SGPIOS_PER_BANK;
107 	u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
108 
109 	priv->mode[port] |= BIT(bit);
110 
111 	return 0;
112 }
113 
mscc_sgpio_direction_output(struct udevice * dev,unsigned int gpio,int value)114 static int mscc_sgpio_direction_output(struct udevice *dev,
115 				       unsigned int gpio, int value)
116 {
117 	struct mscc_sgpio_priv *priv = dev_get_priv(dev);
118 	u32 port = gpio % MSCC_SGPIOS_PER_BANK;
119 	u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
120 	u32 mask = 3 << (3 * bit);
121 
122 	debug("set: port %d, bit %d, mask 0x%08x, value %d\n",
123 	      port, bit, mask, value);
124 
125 	value = (value & 3) << (3 * bit);
126 	sgpio_clrsetbits(priv, REG_PORT_CONFIG, port,
127 			 MSCC_F_PORT_CFG_BIT_SOURCE(priv, mask),
128 			 MSCC_F_PORT_CFG_BIT_SOURCE(priv, value));
129 	clrbits_le32(&priv->mode[port], BIT(bit));
130 
131 	return 0;
132 }
133 
mscc_sgpio_get_function(struct udevice * dev,unsigned int gpio)134 static int mscc_sgpio_get_function(struct udevice *dev, unsigned int gpio)
135 {
136 	struct mscc_sgpio_priv *priv = dev_get_priv(dev);
137 	u32 port = gpio % MSCC_SGPIOS_PER_BANK;
138 	u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
139 	u32 val = priv->mode[port] & BIT(bit);
140 
141 	if (val)
142 		return GPIOF_INPUT;
143 	else
144 		return GPIOF_OUTPUT;
145 }
146 
mscc_sgpio_set_value(struct udevice * dev,unsigned int gpio,int value)147 static int mscc_sgpio_set_value(struct udevice *dev,
148 				unsigned int gpio, int value)
149 {
150 	return mscc_sgpio_direction_output(dev, gpio, value);
151 }
152 
mscc_sgpio_get_value(struct udevice * dev,unsigned int gpio)153 static int mscc_sgpio_get_value(struct udevice *dev, unsigned int gpio)
154 {
155 	struct mscc_sgpio_priv *priv = dev_get_priv(dev);
156 	u32 port = gpio % MSCC_SGPIOS_PER_BANK;
157 	u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
158 	int ret;
159 
160 	if (mscc_sgpio_get_function(dev, gpio) == GPIOF_INPUT) {
161 		ret = !!(sgpio_readl(priv, REG_INPUT_DATA, bit) & BIT(port));
162 	} else {
163 		u32 portval = sgpio_readl(priv, REG_PORT_CONFIG, port);
164 
165 		ret = MSCC_X_PORT_CFG_BIT_SOURCE(priv, portval);
166 		ret = !!(ret & (3 << (3 * bit)));
167 	}
168 
169 	debug("get: gpio %d, port %d, bit %d, value %d\n",
170 	      gpio, port, bit, ret);
171 	return ret;
172 }
173 
mscc_sgpio_get_count(struct udevice * dev)174 static int mscc_sgpio_get_count(struct udevice *dev)
175 {
176 	struct ofnode_phandle_args args;
177 	int count = 0, i = 0, ret;
178 
179 	ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3, i, &args);
180 	while (ret != -ENOENT) {
181 		count += args.args[2];
182 		ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
183 						 ++i, &args);
184 	}
185 	return count;
186 }
187 
mscc_sgpio_probe(struct udevice * dev)188 static int mscc_sgpio_probe(struct udevice *dev)
189 {
190 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
191 	struct mscc_sgpio_priv *priv = dev_get_priv(dev);
192 	int err, div_clock = 0, port;
193 	u32 val;
194 	struct clk clk;
195 
196 	err = clk_get_by_index(dev, 0, &clk);
197 	if (!err) {
198 		err = clk_get_rate(&clk);
199 		if (IS_ERR_VALUE(err)) {
200 			dev_err(dev, "Invalid clk rate\n");
201 			return -EINVAL;
202 		}
203 		div_clock = err;
204 	} else {
205 		dev_err(dev, "Failed to get clock\n");
206 		return err;
207 	}
208 
209 	priv->props = (const struct mscc_sgpio_props *)dev_get_driver_data(dev);
210 	priv->ports = dev_read_u32_default(dev, "mscc,sgpio-ports", 0xFFFFFFFF);
211 	priv->clock = dev_read_u32_default(dev, "mscc,sgpio-frequency",
212 					   12500000);
213 	if (priv->clock <= 0 || priv->clock > div_clock) {
214 		dev_err(dev, "Invalid frequency %d\n", priv->clock);
215 		return -EINVAL;
216 	}
217 
218 	uc_priv->gpio_count = mscc_sgpio_get_count(dev);
219 	uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios",
220 						   uc_priv->gpio_count);
221 	if (uc_priv->gpio_count < 1 || uc_priv->gpio_count >
222 	    (4 * MSCC_SGPIOS_PER_BANK)) {
223 		dev_err(dev, "Invalid gpio count %d\n", uc_priv->gpio_count);
224 		return -EINVAL;
225 	}
226 	priv->bitcount = DIV_ROUND_UP(uc_priv->gpio_count,
227 				      MSCC_SGPIOS_PER_BANK);
228 	debug("probe: gpios = %d, bit-count = %d\n",
229 	      uc_priv->gpio_count, priv->bitcount);
230 
231 	priv->regs = (u32 __iomem *)dev_read_addr(dev);
232 	uc_priv->bank_name = "sgpio";
233 
234 	sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0,
235 			 MSCC_M_CFG_SIO_PORT_WIDTH(priv),
236 			 MSCC_F_CFG_SIO_PORT_WIDTH(priv, priv->bitcount - 1) |
237 			 MSCC_M_CFG_SIO_AUTO_REPEAT(priv));
238 	val = div_clock / priv->clock;
239 	debug("probe: div-clock = %d KHz, freq = %d KHz, div = %d\n",
240 	      div_clock / 1000, priv->clock / 1000, val);
241 	sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0,
242 			 MSCC_M_CLOCK_SIO_CLK_FREQ(priv),
243 			 MSCC_F_CLOCK_SIO_CLK_FREQ(priv, val));
244 
245 	for (port = 0; port < 32; port++)
246 		sgpio_writel(priv, 0, REG_PORT_CONFIG, port);
247 	sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0);
248 
249 	debug("probe: sgpio regs = %p\n", priv->regs);
250 
251 	return 0;
252 }
253 
254 static const struct dm_gpio_ops mscc_sgpio_ops = {
255 	.direction_input	= mscc_sgpio_direction_input,
256 	.direction_output	= mscc_sgpio_direction_output,
257 	.get_function		= mscc_sgpio_get_function,
258 	.get_value		= mscc_sgpio_get_value,
259 	.set_value		= mscc_sgpio_set_value,
260 };
261 
262 static const struct udevice_id mscc_sgpio_ids[] = {
263 	{ .compatible = "mscc,luton-sgpio", .data = (ulong)&props_luton },
264 	{ .compatible = "mscc,ocelot-sgpio", .data = (ulong)&props_ocelot },
265 	{ }
266 };
267 
268 U_BOOT_DRIVER(gpio_mscc_sgpio) = {
269 	.name			= "mscc-sgpio",
270 	.id			= UCLASS_GPIO,
271 	.of_match		= mscc_sgpio_ids,
272 	.ops			= &mscc_sgpio_ops,
273 	.probe			= mscc_sgpio_probe,
274 	.priv_auto_alloc_size	= sizeof(struct mscc_sgpio_priv),
275 };
276