1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DML32_DISPLAY_MODE_VBA_H__ 27 #define __DML32_DISPLAY_MODE_VBA_H__ 28 29 #include "../display_mode_enums.h" 30 31 // To enable a lot of debug msg 32 //#define __DML_VBA_DEBUG__ 33 // For DML-C changes that hasn't been propagated to VBA yet 34 //#define __DML_VBA_ALLOW_DELTA__ 35 36 // Move these to ip parameters/constant 37 // At which vstartup the DML start to try if the mode can be supported 38 #define __DML_VBA_MIN_VSTARTUP__ 9 39 40 // Delay in DCFCLK from ARB to DET (1st num is ARB to SDPIF, 2nd number is SDPIF to DET) 41 #define __DML_ARB_TO_RET_DELAY__ 7 + 95 42 43 // fudge factor for min dcfclk calclation 44 #define __DML_MIN_DCFCLK_FACTOR__ 1.15 45 46 // Prefetch schedule max vratio 47 #define __DML_MAX_VRATIO_PRE__ 7.9 48 #define __DML_MAX_BW_RATIO_PRE__ 4.0 49 50 #define __DML_VBA_MAX_DST_Y_PRE__ 63.75 51 52 #define BPP_INVALID 0 53 #define BPP_BLENDED_PIPE 0xffffffff 54 55 #define MEM_STROBE_FREQ_MHZ 1600 56 #define DCFCLK_FREQ_EXTRA_PREFETCH_REQ_MHZ 300 57 #define MEM_STROBE_MAX_DELIVERY_TIME_US 60.0 58 59 struct display_mode_lib; 60 61 void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib); 62 void dml32_recalculate(struct display_mode_lib *mode_lib); 63 64 #endif 65