1 /* SPDX-License-Identifier: GPL-2.0 */
2
3 #ifndef _ASM_X86_NOSPEC_BRANCH_H_
4 #define _ASM_X86_NOSPEC_BRANCH_H_
5
6 #include <linux/static_key.h>
7 #include <linux/objtool.h>
8 #include <linux/linkage.h>
9
10 #include <asm/alternative.h>
11 #include <asm/cpufeatures.h>
12 #include <asm/msr-index.h>
13 #include <asm/unwind_hints.h>
14 #include <asm/percpu.h>
15 #include <asm/current.h>
16
17 /*
18 * Call depth tracking for Intel SKL CPUs to address the RSB underflow
19 * issue in software.
20 *
21 * The tracking does not use a counter. It uses uses arithmetic shift
22 * right on call entry and logical shift left on return.
23 *
24 * The depth tracking variable is initialized to 0x8000.... when the call
25 * depth is zero. The arithmetic shift right sign extends the MSB and
26 * saturates after the 12th call. The shift count is 5 for both directions
27 * so the tracking covers 12 nested calls.
28 *
29 * Call
30 * 0: 0x8000000000000000 0x0000000000000000
31 * 1: 0xfc00000000000000 0xf000000000000000
32 * ...
33 * 11: 0xfffffffffffffff8 0xfffffffffffffc00
34 * 12: 0xffffffffffffffff 0xffffffffffffffe0
35 *
36 * After a return buffer fill the depth is credited 12 calls before the
37 * next stuffing has to take place.
38 *
39 * There is a inaccuracy for situations like this:
40 *
41 * 10 calls
42 * 5 returns
43 * 3 calls
44 * 4 returns
45 * 3 calls
46 * ....
47 *
48 * The shift count might cause this to be off by one in either direction,
49 * but there is still a cushion vs. the RSB depth. The algorithm does not
50 * claim to be perfect and it can be speculated around by the CPU, but it
51 * is considered that it obfuscates the problem enough to make exploitation
52 * extremly difficult.
53 */
54 #define RET_DEPTH_SHIFT 5
55 #define RSB_RET_STUFF_LOOPS 16
56 #define RET_DEPTH_INIT 0x8000000000000000ULL
57 #define RET_DEPTH_INIT_FROM_CALL 0xfc00000000000000ULL
58 #define RET_DEPTH_CREDIT 0xffffffffffffffffULL
59
60 #ifdef CONFIG_CALL_THUNKS_DEBUG
61 # define CALL_THUNKS_DEBUG_INC_CALLS \
62 incq %gs:__x86_call_count;
63 # define CALL_THUNKS_DEBUG_INC_RETS \
64 incq %gs:__x86_ret_count;
65 # define CALL_THUNKS_DEBUG_INC_STUFFS \
66 incq %gs:__x86_stuffs_count;
67 # define CALL_THUNKS_DEBUG_INC_CTXSW \
68 incq %gs:__x86_ctxsw_count;
69 #else
70 # define CALL_THUNKS_DEBUG_INC_CALLS
71 # define CALL_THUNKS_DEBUG_INC_RETS
72 # define CALL_THUNKS_DEBUG_INC_STUFFS
73 # define CALL_THUNKS_DEBUG_INC_CTXSW
74 #endif
75
76 #if defined(CONFIG_CALL_DEPTH_TRACKING) && !defined(COMPILE_OFFSETS)
77
78 #include <asm/asm-offsets.h>
79
80 #define CREDIT_CALL_DEPTH \
81 movq $-1, PER_CPU_VAR(pcpu_hot + X86_call_depth);
82
83 #define ASM_CREDIT_CALL_DEPTH \
84 movq $-1, PER_CPU_VAR(pcpu_hot + X86_call_depth);
85
86 #define RESET_CALL_DEPTH \
87 xor %eax, %eax; \
88 bts $63, %rax; \
89 movq %rax, PER_CPU_VAR(pcpu_hot + X86_call_depth);
90
91 #define RESET_CALL_DEPTH_FROM_CALL \
92 movb $0xfc, %al; \
93 shl $56, %rax; \
94 movq %rax, PER_CPU_VAR(pcpu_hot + X86_call_depth); \
95 CALL_THUNKS_DEBUG_INC_CALLS
96
97 #define INCREMENT_CALL_DEPTH \
98 sarq $5, %gs:pcpu_hot + X86_call_depth; \
99 CALL_THUNKS_DEBUG_INC_CALLS
100
101 #define ASM_INCREMENT_CALL_DEPTH \
102 sarq $5, PER_CPU_VAR(pcpu_hot + X86_call_depth); \
103 CALL_THUNKS_DEBUG_INC_CALLS
104
105 #else
106 #define CREDIT_CALL_DEPTH
107 #define ASM_CREDIT_CALL_DEPTH
108 #define RESET_CALL_DEPTH
109 #define INCREMENT_CALL_DEPTH
110 #define ASM_INCREMENT_CALL_DEPTH
111 #define RESET_CALL_DEPTH_FROM_CALL
112 #endif
113
114 /*
115 * Fill the CPU return stack buffer.
116 *
117 * Each entry in the RSB, if used for a speculative 'ret', contains an
118 * infinite 'pause; lfence; jmp' loop to capture speculative execution.
119 *
120 * This is required in various cases for retpoline and IBRS-based
121 * mitigations for the Spectre variant 2 vulnerability. Sometimes to
122 * eliminate potentially bogus entries from the RSB, and sometimes
123 * purely to ensure that it doesn't get empty, which on some CPUs would
124 * allow predictions from other (unwanted!) sources to be used.
125 *
126 * We define a CPP macro such that it can be used from both .S files and
127 * inline assembly. It's possible to do a .macro and then include that
128 * from C via asm(".include <asm/nospec-branch.h>") but let's not go there.
129 */
130
131 #define RETPOLINE_THUNK_SIZE 32
132 #define RSB_CLEAR_LOOPS 32 /* To forcibly overwrite all entries */
133
134 /*
135 * Common helper for __FILL_RETURN_BUFFER and __FILL_ONE_RETURN.
136 */
137 #define __FILL_RETURN_SLOT \
138 ANNOTATE_INTRA_FUNCTION_CALL; \
139 call 772f; \
140 int3; \
141 772:
142
143 /*
144 * Stuff the entire RSB.
145 *
146 * Google experimented with loop-unrolling and this turned out to be
147 * the optimal version - two calls, each with their own speculation
148 * trap should their return address end up getting used, in a loop.
149 */
150 #ifdef CONFIG_X86_64
151 #define __FILL_RETURN_BUFFER(reg, nr) \
152 mov $(nr/2), reg; \
153 771: \
154 __FILL_RETURN_SLOT \
155 __FILL_RETURN_SLOT \
156 add $(BITS_PER_LONG/8) * 2, %_ASM_SP; \
157 dec reg; \
158 jnz 771b; \
159 /* barrier for jnz misprediction */ \
160 lfence; \
161 ASM_CREDIT_CALL_DEPTH \
162 CALL_THUNKS_DEBUG_INC_CTXSW
163 #else
164 /*
165 * i386 doesn't unconditionally have LFENCE, as such it can't
166 * do a loop.
167 */
168 #define __FILL_RETURN_BUFFER(reg, nr) \
169 .rept nr; \
170 __FILL_RETURN_SLOT; \
171 .endr; \
172 add $(BITS_PER_LONG/8) * nr, %_ASM_SP;
173 #endif
174
175 /*
176 * Stuff a single RSB slot.
177 *
178 * To mitigate Post-Barrier RSB speculation, one CALL instruction must be
179 * forced to retire before letting a RET instruction execute.
180 *
181 * On PBRSB-vulnerable CPUs, it is not safe for a RET to be executed
182 * before this point.
183 */
184 #define __FILL_ONE_RETURN \
185 __FILL_RETURN_SLOT \
186 add $(BITS_PER_LONG/8), %_ASM_SP; \
187 lfence;
188
189 #ifdef __ASSEMBLY__
190
191 /*
192 * This should be used immediately before an indirect jump/call. It tells
193 * objtool the subsequent indirect jump/call is vouched safe for retpoline
194 * builds.
195 */
196 .macro ANNOTATE_RETPOLINE_SAFE
197 .Lhere_\@:
198 .pushsection .discard.retpoline_safe
199 .long .Lhere_\@
200 .popsection
201 .endm
202
203 /*
204 * (ab)use RETPOLINE_SAFE on RET to annotate away 'bare' RET instructions
205 * vs RETBleed validation.
206 */
207 #define ANNOTATE_UNRET_SAFE ANNOTATE_RETPOLINE_SAFE
208
209 /*
210 * Abuse ANNOTATE_RETPOLINE_SAFE on a NOP to indicate UNRET_END, should
211 * eventually turn into it's own annotation.
212 */
213 .macro VALIDATE_UNRET_END
214 #if defined(CONFIG_NOINSTR_VALIDATION) && \
215 (defined(CONFIG_CPU_UNRET_ENTRY) || defined(CONFIG_CPU_SRSO))
216 ANNOTATE_RETPOLINE_SAFE
217 nop
218 #endif
219 .endm
220
221 /*
222 * Emits a conditional CS prefix that is compatible with
223 * -mindirect-branch-cs-prefix.
224 */
225 .macro __CS_PREFIX reg:req
226 .irp rs,r8,r9,r10,r11,r12,r13,r14,r15
227 .ifc \reg,\rs
228 .byte 0x2e
229 .endif
230 .endr
231 .endm
232
233 /*
234 * JMP_NOSPEC and CALL_NOSPEC macros can be used instead of a simple
235 * indirect jmp/call which may be susceptible to the Spectre variant 2
236 * attack.
237 *
238 * NOTE: these do not take kCFI into account and are thus not comparable to C
239 * indirect calls, take care when using. The target of these should be an ENDBR
240 * instruction irrespective of kCFI.
241 */
242 .macro JMP_NOSPEC reg:req
243 #ifdef CONFIG_RETPOLINE
244 __CS_PREFIX \reg
245 jmp __x86_indirect_thunk_\reg
246 #else
247 jmp *%\reg
248 int3
249 #endif
250 .endm
251
252 .macro CALL_NOSPEC reg:req
253 #ifdef CONFIG_RETPOLINE
254 __CS_PREFIX \reg
255 call __x86_indirect_thunk_\reg
256 #else
257 call *%\reg
258 #endif
259 .endm
260
261 /*
262 * A simpler FILL_RETURN_BUFFER macro. Don't make people use the CPP
263 * monstrosity above, manually.
264 */
265 .macro FILL_RETURN_BUFFER reg:req nr:req ftr:req ftr2=ALT_NOT(X86_FEATURE_ALWAYS)
266 ALTERNATIVE_2 "jmp .Lskip_rsb_\@", \
267 __stringify(__FILL_RETURN_BUFFER(\reg,\nr)), \ftr, \
268 __stringify(nop;nop;__FILL_ONE_RETURN), \ftr2
269
270 .Lskip_rsb_\@:
271 .endm
272
273 /*
274 * The CALL to srso_alias_untrain_ret() must be patched in directly at
275 * the spot where untraining must be done, ie., srso_alias_untrain_ret()
276 * must be the target of a CALL instruction instead of indirectly
277 * jumping to a wrapper which then calls it. Therefore, this macro is
278 * called outside of __UNTRAIN_RET below, for the time being, before the
279 * kernel can support nested alternatives with arbitrary nesting.
280 */
281 .macro CALL_UNTRAIN_RET
282 #if defined(CONFIG_CPU_UNRET_ENTRY) || defined(CONFIG_CPU_SRSO)
283 ALTERNATIVE_2 "", "call entry_untrain_ret", X86_FEATURE_UNRET, \
284 "call srso_alias_untrain_ret", X86_FEATURE_SRSO_ALIAS
285 #endif
286 .endm
287
288 /*
289 * Mitigate RETBleed for AMD/Hygon Zen uarch. Requires KERNEL CR3 because the
290 * return thunk isn't mapped into the userspace tables (then again, AMD
291 * typically has NO_MELTDOWN).
292 *
293 * While retbleed_untrain_ret() doesn't clobber anything but requires stack,
294 * entry_ibpb() will clobber AX, CX, DX.
295 *
296 * As such, this must be placed after every *SWITCH_TO_KERNEL_CR3 at a point
297 * where we have a stack but before any RET instruction.
298 */
299 .macro __UNTRAIN_RET ibpb_feature, call_depth_insns
300 #if defined(CONFIG_RETHUNK) || defined(CONFIG_CPU_IBPB_ENTRY)
301 VALIDATE_UNRET_END
302 CALL_UNTRAIN_RET
303 ALTERNATIVE_2 "", \
304 "call entry_ibpb", \ibpb_feature, \
305 __stringify(\call_depth_insns), X86_FEATURE_CALL_DEPTH
306 #endif
307 .endm
308
309 #define UNTRAIN_RET \
310 __UNTRAIN_RET X86_FEATURE_ENTRY_IBPB, __stringify(RESET_CALL_DEPTH)
311
312 #define UNTRAIN_RET_VM \
313 __UNTRAIN_RET X86_FEATURE_IBPB_ON_VMEXIT, __stringify(RESET_CALL_DEPTH)
314
315 #define UNTRAIN_RET_FROM_CALL \
316 __UNTRAIN_RET X86_FEATURE_ENTRY_IBPB, __stringify(RESET_CALL_DEPTH_FROM_CALL)
317
318
319 .macro CALL_DEPTH_ACCOUNT
320 #ifdef CONFIG_CALL_DEPTH_TRACKING
321 ALTERNATIVE "", \
322 __stringify(ASM_INCREMENT_CALL_DEPTH), X86_FEATURE_CALL_DEPTH
323 #endif
324 .endm
325
326 /*
327 * Macro to execute VERW instruction that mitigate transient data sampling
328 * attacks such as MDS. On affected systems a microcode update overloaded VERW
329 * instruction to also clear the CPU buffers. VERW clobbers CFLAGS.ZF.
330 *
331 * Note: Only the memory operand variant of VERW clears the CPU buffers.
332 */
333 .macro CLEAR_CPU_BUFFERS
334 #ifdef CONFIG_X86_64
335 ALTERNATIVE "", "verw mds_verw_sel(%rip)", X86_FEATURE_CLEAR_CPU_BUF
336 #else
337 /*
338 * In 32bit mode, the memory operand must be a %cs reference. The data
339 * segments may not be usable (vm86 mode), and the stack segment may not
340 * be flat (ESPFIX32).
341 */
342 ALTERNATIVE "", "verw %cs:mds_verw_sel", X86_FEATURE_CLEAR_CPU_BUF
343 #endif
344 .endm
345
346 #ifdef CONFIG_X86_64
347 .macro CLEAR_BRANCH_HISTORY
348 ALTERNATIVE "", "call clear_bhb_loop", X86_FEATURE_CLEAR_BHB_LOOP
349 .endm
350
351 .macro CLEAR_BRANCH_HISTORY_VMEXIT
352 ALTERNATIVE "", "call clear_bhb_loop", X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT
353 .endm
354 #else
355 #define CLEAR_BRANCH_HISTORY
356 #define CLEAR_BRANCH_HISTORY_VMEXIT
357 #endif
358
359 #else /* __ASSEMBLY__ */
360
361 #define ANNOTATE_RETPOLINE_SAFE \
362 "999:\n\t" \
363 ".pushsection .discard.retpoline_safe\n\t" \
364 ".long 999b\n\t" \
365 ".popsection\n\t"
366
367 #define ITS_THUNK_SIZE 64
368
369 typedef u8 retpoline_thunk_t[RETPOLINE_THUNK_SIZE];
370 typedef u8 its_thunk_t[ITS_THUNK_SIZE];
371 extern retpoline_thunk_t __x86_indirect_thunk_array[];
372 extern retpoline_thunk_t __x86_indirect_call_thunk_array[];
373 extern retpoline_thunk_t __x86_indirect_jump_thunk_array[];
374 extern its_thunk_t __x86_indirect_its_thunk_array[];
375
376 #ifdef CONFIG_RETHUNK
377 extern void __x86_return_thunk(void);
378 #else
__x86_return_thunk(void)379 static inline void __x86_return_thunk(void) {}
380 #endif
381
382 #ifdef CONFIG_CPU_UNRET_ENTRY
383 extern void retbleed_return_thunk(void);
384 #else
retbleed_return_thunk(void)385 static inline void retbleed_return_thunk(void) {}
386 #endif
387
388 extern void srso_alias_untrain_ret(void);
389
390 #ifdef CONFIG_CPU_SRSO
391 extern void srso_return_thunk(void);
392 extern void srso_alias_return_thunk(void);
393 #else
srso_return_thunk(void)394 static inline void srso_return_thunk(void) {}
srso_alias_return_thunk(void)395 static inline void srso_alias_return_thunk(void) {}
396 #endif
397
398 #ifdef CONFIG_MITIGATION_ITS
399 extern void its_return_thunk(void);
400 #else
its_return_thunk(void)401 static inline void its_return_thunk(void) {}
402 #endif
403
404 extern void retbleed_return_thunk(void);
405 extern void srso_return_thunk(void);
406 extern void srso_alias_return_thunk(void);
407
408 extern void retbleed_untrain_ret(void);
409 extern void srso_untrain_ret(void);
410 extern void srso_alias_untrain_ret(void);
411
412 extern void entry_untrain_ret(void);
413 extern void entry_ibpb(void);
414
415 #ifdef CONFIG_X86_64
416 extern void clear_bhb_loop(void);
417 #endif
418
419 extern void (*x86_return_thunk)(void);
420
421 #ifdef CONFIG_CALL_DEPTH_TRACKING
422 extern void __x86_return_skl(void);
423
424 #define CALL_DEPTH_ACCOUNT \
425 ALTERNATIVE("", \
426 __stringify(INCREMENT_CALL_DEPTH), \
427 X86_FEATURE_CALL_DEPTH)
428
429 #ifdef CONFIG_CALL_THUNKS_DEBUG
430 DECLARE_PER_CPU(u64, __x86_call_count);
431 DECLARE_PER_CPU(u64, __x86_ret_count);
432 DECLARE_PER_CPU(u64, __x86_stuffs_count);
433 DECLARE_PER_CPU(u64, __x86_ctxsw_count);
434 #endif
435 #else
436
437 #define CALL_DEPTH_ACCOUNT ""
438
439 #endif
440
441 #ifdef CONFIG_RETPOLINE
442
443 #define GEN(reg) \
444 extern retpoline_thunk_t __x86_indirect_thunk_ ## reg;
445 #include <asm/GEN-for-each-reg.h>
446 #undef GEN
447
448 #define GEN(reg) \
449 extern retpoline_thunk_t __x86_indirect_call_thunk_ ## reg;
450 #include <asm/GEN-for-each-reg.h>
451 #undef GEN
452
453 #define GEN(reg) \
454 extern retpoline_thunk_t __x86_indirect_jump_thunk_ ## reg;
455 #include <asm/GEN-for-each-reg.h>
456 #undef GEN
457
458 #ifdef CONFIG_X86_64
459
460 /*
461 * Emits a conditional CS prefix that is compatible with
462 * -mindirect-branch-cs-prefix.
463 */
464 #define __CS_PREFIX(reg) \
465 ".irp rs,r8,r9,r10,r11,r12,r13,r14,r15\n" \
466 ".ifc \\rs," reg "\n" \
467 ".byte 0x2e\n" \
468 ".endif\n" \
469 ".endr\n"
470
471 /*
472 * Inline asm uses the %V modifier which is only in newer GCC
473 * which is ensured when CONFIG_RETPOLINE is defined.
474 */
475 #define CALL_NOSPEC __CS_PREFIX("%V[thunk_target]") \
476 "call __x86_indirect_thunk_%V[thunk_target]\n"
477
478 # define THUNK_TARGET(addr) [thunk_target] "r" (addr)
479
480 #else /* CONFIG_X86_32 */
481 /*
482 * For i386 we use the original ret-equivalent retpoline, because
483 * otherwise we'll run out of registers. We don't care about CET
484 * here, anyway.
485 */
486 # define CALL_NOSPEC \
487 ALTERNATIVE_2( \
488 ANNOTATE_RETPOLINE_SAFE \
489 "call *%[thunk_target]\n", \
490 " jmp 904f;\n" \
491 " .align 16\n" \
492 "901: call 903f;\n" \
493 "902: pause;\n" \
494 " lfence;\n" \
495 " jmp 902b;\n" \
496 " .align 16\n" \
497 "903: lea 4(%%esp), %%esp;\n" \
498 " pushl %[thunk_target];\n" \
499 " ret;\n" \
500 " .align 16\n" \
501 "904: call 901b;\n", \
502 X86_FEATURE_RETPOLINE, \
503 "lfence;\n" \
504 ANNOTATE_RETPOLINE_SAFE \
505 "call *%[thunk_target]\n", \
506 X86_FEATURE_RETPOLINE_LFENCE)
507
508 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
509 #endif
510 #else /* No retpoline for C / inline asm */
511 # define CALL_NOSPEC "call *%[thunk_target]\n"
512 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
513 #endif
514
515 /* The Spectre V2 mitigation variants */
516 enum spectre_v2_mitigation {
517 SPECTRE_V2_NONE,
518 SPECTRE_V2_RETPOLINE,
519 SPECTRE_V2_LFENCE,
520 SPECTRE_V2_EIBRS,
521 SPECTRE_V2_EIBRS_RETPOLINE,
522 SPECTRE_V2_EIBRS_LFENCE,
523 SPECTRE_V2_IBRS,
524 };
525
526 /* The indirect branch speculation control variants */
527 enum spectre_v2_user_mitigation {
528 SPECTRE_V2_USER_NONE,
529 SPECTRE_V2_USER_STRICT,
530 SPECTRE_V2_USER_STRICT_PREFERRED,
531 SPECTRE_V2_USER_PRCTL,
532 SPECTRE_V2_USER_SECCOMP,
533 };
534
535 /* The Speculative Store Bypass disable variants */
536 enum ssb_mitigation {
537 SPEC_STORE_BYPASS_NONE,
538 SPEC_STORE_BYPASS_DISABLE,
539 SPEC_STORE_BYPASS_PRCTL,
540 SPEC_STORE_BYPASS_SECCOMP,
541 };
542
543 static __always_inline
alternative_msr_write(unsigned int msr,u64 val,unsigned int feature)544 void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature)
545 {
546 asm volatile(ALTERNATIVE("", "wrmsr", %c[feature])
547 : : "c" (msr),
548 "a" ((u32)val),
549 "d" ((u32)(val >> 32)),
550 [feature] "i" (feature)
551 : "memory");
552 }
553
554 extern u64 x86_pred_cmd;
555
indirect_branch_prediction_barrier(void)556 static inline void indirect_branch_prediction_barrier(void)
557 {
558 alternative_msr_write(MSR_IA32_PRED_CMD, x86_pred_cmd, X86_FEATURE_USE_IBPB);
559 }
560
561 /* The Intel SPEC CTRL MSR base value cache */
562 extern u64 x86_spec_ctrl_base;
563 DECLARE_PER_CPU(u64, x86_spec_ctrl_current);
564 extern void update_spec_ctrl_cond(u64 val);
565 extern u64 spec_ctrl_current(void);
566
567 /*
568 * With retpoline, we must use IBRS to restrict branch prediction
569 * before calling into firmware.
570 *
571 * (Implemented as CPP macros due to header hell.)
572 */
573 #define firmware_restrict_branch_speculation_start() \
574 do { \
575 preempt_disable(); \
576 alternative_msr_write(MSR_IA32_SPEC_CTRL, \
577 spec_ctrl_current() | SPEC_CTRL_IBRS, \
578 X86_FEATURE_USE_IBRS_FW); \
579 alternative_msr_write(MSR_IA32_PRED_CMD, PRED_CMD_IBPB, \
580 X86_FEATURE_USE_IBPB_FW); \
581 } while (0)
582
583 #define firmware_restrict_branch_speculation_end() \
584 do { \
585 alternative_msr_write(MSR_IA32_SPEC_CTRL, \
586 spec_ctrl_current(), \
587 X86_FEATURE_USE_IBRS_FW); \
588 preempt_enable(); \
589 } while (0)
590
591 DECLARE_STATIC_KEY_FALSE(switch_to_cond_stibp);
592 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
593 DECLARE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
594
595 DECLARE_STATIC_KEY_FALSE(mds_idle_clear);
596
597 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush);
598
599 DECLARE_STATIC_KEY_FALSE(mmio_stale_data_clear);
600
601 extern u16 mds_verw_sel;
602
603 #include <asm/segment.h>
604
605 /**
606 * mds_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
607 *
608 * This uses the otherwise unused and obsolete VERW instruction in
609 * combination with microcode which triggers a CPU buffer flush when the
610 * instruction is executed.
611 */
mds_clear_cpu_buffers(void)612 static __always_inline void mds_clear_cpu_buffers(void)
613 {
614 static const u16 ds = __KERNEL_DS;
615
616 /*
617 * Has to be the memory-operand variant because only that
618 * guarantees the CPU buffer flush functionality according to
619 * documentation. The register-operand variant does not.
620 * Works with any segment selector, but a valid writable
621 * data segment is the fastest variant.
622 *
623 * "cc" clobber is required because VERW modifies ZF.
624 */
625 asm volatile("verw %[ds]" : : [ds] "m" (ds) : "cc");
626 }
627
628 /**
629 * mds_idle_clear_cpu_buffers - Mitigation for MDS vulnerability
630 *
631 * Clear CPU buffers if the corresponding static key is enabled
632 */
mds_idle_clear_cpu_buffers(void)633 static __always_inline void mds_idle_clear_cpu_buffers(void)
634 {
635 if (static_branch_likely(&mds_idle_clear))
636 mds_clear_cpu_buffers();
637 }
638
639 #endif /* __ASSEMBLY__ */
640
641 #endif /* _ASM_X86_NOSPEC_BRANCH_H_ */
642