1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright (C) 2017-2018 Intel Corporation <www.intel.com> 4 * 5 */ 6 7 #ifndef __CONFIG_SOCFGPA_STRATIX10_H__ 8 #define __CONFIG_SOCFGPA_STRATIX10_H__ 9 10 #include <asm/arch/base_addr_s10.h> 11 #include <asm/arch/handoff_s10.h> 12 13 /* 14 * U-Boot general configurations 15 */ 16 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 17 #define CONFIG_LOADADDR 0x2000000 18 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 19 #define CONFIG_REMAKE_ELF 20 /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */ 21 #define CPU_RELEASE_ADDR 0xFFD12210 22 #define CONFIG_SYS_CACHELINE_SIZE 64 23 #define CONFIG_SYS_MEM_RESERVE_SECURE 0 /* using OCRAM, not DDR */ 24 25 /* 26 * U-Boot console configurations 27 */ 28 #define CONFIG_SYS_MAXARGS 64 29 #define CONFIG_SYS_CBSIZE 2048 30 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 31 sizeof(CONFIG_SYS_PROMPT) + 16) 32 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 33 34 /* Extend size of kernel image for uncompression */ 35 #define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024) 36 37 /* 38 * U-Boot run time memory configurations 39 */ 40 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 41 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 42 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \ 43 + CONFIG_SYS_INIT_RAM_SIZE \ 44 - S10_HANDOFF_SIZE) 45 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR) 46 #define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) 47 48 /* 49 * U-Boot environment configurations 50 */ 51 #define CONFIG_ENV_SIZE 0x1000 52 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ 53 #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ 54 55 /* 56 * QSPI support 57 */ 58 #ifdef CONFIG_CADENCE_QSPI 59 /* Enable it if you want to use dual-stacked mode */ 60 /*#define CONFIG_QSPI_RBF_ADDR 0x720000*/ 61 62 /* Flash device info */ 63 64 /*#define CONFIG_ENV_IS_IN_SPI_FLASH*/ 65 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH 66 #undef CONFIG_ENV_OFFSET 67 #undef CONFIG_ENV_SIZE 68 #define CONFIG_ENV_OFFSET 0x710000 69 #define CONFIG_ENV_SIZE (4 * 1024) 70 #define CONFIG_ENV_SECT_SIZE (4 * 1024) 71 #endif /* CONFIG_ENV_IS_IN_SPI_FLASH */ 72 73 #ifndef CONFIG_SPL_BUILD 74 #define CONFIG_MTD_DEVICE 75 #define CONFIG_MTD_PARTITIONS 76 #define MTDIDS_DEFAULT "nor0=ff705000.spi.0" 77 #endif /* CONFIG_SPL_BUILD */ 78 79 #ifndef __ASSEMBLY__ 80 unsigned int cm_get_qspi_controller_clk_hz(void); 81 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 82 #endif 83 84 #endif /* CONFIG_CADENCE_QSPI */ 85 86 /* 87 * Boot arguments passed to the boot command. The value of 88 * CONFIG_BOOTARGS goes into the environment value "bootargs". 89 * Do note the value will override also the chosen node in FDT blob. 90 */ 91 #define CONFIG_BOOTARGS "earlycon" 92 #define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \ 93 "run mmcboot" 94 95 #define CONFIG_EXTRA_ENV_SETTINGS \ 96 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ 97 "bootfile=Image\0" \ 98 "fdt_addr=8000000\0" \ 99 "fdtimage=socfpga_stratix10_socdk.dtb\0" \ 100 "mmcroot=/dev/mmcblk0p2\0" \ 101 "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ 102 " root=${mmcroot} rw rootwait;" \ 103 "booti ${loadaddr} - ${fdt_addr}\0" \ 104 "mmcload=mmc rescan;" \ 105 "load mmc 0:1 ${loadaddr} ${bootfile};" \ 106 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ 107 "linux_qspi_enable=if sf probe; then " \ 108 "echo Enabling QSPI at Linux DTB...;" \ 109 "fdt addr ${fdt_addr}; fdt resize;" \ 110 "fdt set /soc/spi@ff8d2000 status okay;" \ 111 "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \ 112 " ${qspi_clock}; fi; \0" \ 113 "scriptaddr=0x02100000\0" \ 114 "scriptfile=u-boot.scr\0" \ 115 "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \ 116 "then source ${scriptaddr}; fi\0" 117 118 /* 119 * Generic Interrupt Controller Definitions 120 */ 121 #define CONFIG_GICV2 122 123 /* 124 * External memory configurations 125 */ 126 #define PHYS_SDRAM_1 0x0 127 #define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) 128 #define CONFIG_SYS_SDRAM_BASE 0 129 #define CONFIG_SYS_MEMTEST_START 0 130 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - 0x200000 131 132 /* 133 * SDRAM controller 134 */ 135 #define CONFIG_ALTERA_SDRAM 136 137 /* 138 * Serial / UART configurations 139 */ 140 #define CONFIG_SYS_NS16550_CLK 100000000 141 #define CONFIG_SYS_NS16550_MEM32 142 143 /* 144 * Timer & watchdog configurations 145 */ 146 #define COUNTER_FREQUENCY 400000000 147 148 /* 149 * SDMMC configurations 150 */ 151 #ifdef CONFIG_CMD_MMC 152 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 153 #endif 154 /* 155 * Flash configurations 156 */ 157 #define CONFIG_SYS_MAX_FLASH_BANKS 1 158 159 /* Ethernet on SoC (EMAC) */ 160 #if defined(CONFIG_CMD_NET) 161 #define CONFIG_DW_ALTDESCRIPTOR 162 #endif /* CONFIG_CMD_NET */ 163 164 /* 165 * L4 Watchdog 166 */ 167 #ifdef CONFIG_SPL_BUILD 168 #define CONFIG_HW_WATCHDOG 169 #define CONFIG_DESIGNWARE_WATCHDOG 170 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 171 #ifndef __ASSEMBLY__ 172 unsigned int cm_get_l4_sys_free_clk_hz(void); 173 #define CONFIG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000) 174 #endif 175 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 3000 176 #endif 177 178 /* 179 * SPL memory layout 180 * 181 * On chip RAM 182 * 0xFFE0_0000 ...... Start of OCRAM 183 * SPL code, rwdata 184 * empty space 185 * 0xFFEx_xxxx ...... Top of stack (grows down) 186 * 0xFFEy_yyyy ...... Global Data 187 * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN) 188 * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB) 189 * 0xFFE3_FFFF ...... End of OCRAM 190 * 191 * SDRAM 192 * 0x0000_0000 ...... Start of SDRAM_1 193 * unused / empty space for image loading 194 * Size 64MB ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE) 195 * Size 1MB ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE) 196 * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB) 197 * 198 */ 199 #define CONFIG_SPL_TARGET "spl/u-boot-spl.hex" 200 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 201 #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE 202 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 203 #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ 204 #define CONFIG_SPL_BSS_START_ADDR (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \ 205 - CONFIG_SPL_BSS_MAX_SIZE) 206 #define CONFIG_SYS_SPL_MALLOC_SIZE (CONFIG_SYS_MALLOC_LEN) 207 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR \ 208 - CONFIG_SYS_SPL_MALLOC_SIZE) 209 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x3C00000 210 211 /* SPL SDMMC boot support */ 212 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 213 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 214 215 #endif /* __CONFIG_H */ 216