1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2018 NXP 4 */ 5 6 #ifndef __ASM_ARCH_IMX8_REGS_H__ 7 #define __ASM_ARCH_IMX8_REGS_H__ 8 9 #define LPUART_BASE 0x5A060000 10 11 #define GPT1_BASE_ADDR 0x5D140000 12 #define SCU_LPUART_BASE 0x33220000 13 #define GPIO1_BASE_ADDR 0x5D080000 14 #define GPIO2_BASE_ADDR 0x5D090000 15 #define GPIO3_BASE_ADDR 0x5D0A0000 16 #define GPIO4_BASE_ADDR 0x5D0B0000 17 #define GPIO5_BASE_ADDR 0x5D0C0000 18 #define GPIO6_BASE_ADDR 0x5D0D0000 19 #define GPIO7_BASE_ADDR 0x5D0E0000 20 #define GPIO8_BASE_ADDR 0x5D0F0000 21 #define LPI2C1_BASE_ADDR 0x5A800000 22 #define LPI2C2_BASE_ADDR 0x5A810000 23 #define LPI2C3_BASE_ADDR 0x5A820000 24 #define LPI2C4_BASE_ADDR 0x5A830000 25 #define LPI2C5_BASE_ADDR 0x5A840000 26 27 #ifdef CONFIG_IMX8QXP 28 #define LVDS0_PHYCTRL_BASE 0x56221000 29 #define LVDS1_PHYCTRL_BASE 0x56241000 30 #define MIPI0_SS_BASE 0x56220000 31 #define MIPI1_SS_BASE 0x56240000 32 #endif 33 34 #define APBH_DMA_ARB_BASE_ADDR 0x5B810000 35 #define APBH_DMA_ARB_END_ADDR 0x5B81FFFF 36 #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR 37 38 #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) 39 #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) 40 41 #define PASS_OVER_INFO_ADDR 0x0010fe00 42 43 #define USB_BASE_ADDR 0x5b0d0000 44 #define USB_PHY0_BASE_ADDR 0x5b100000 45 46 #endif /* __ASM_ARCH_IMX8_REGS_H__ */ 47