1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  *
4  * Parts of this file are based on Ralink's 2.6.21 BSP
5  *
6  * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
7  * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8  * Copyright (C) 2013 John Crispin <john@phrozen.org>
9  */
10 
11 #ifndef _RT305X_REGS_H_
12 #define _RT305X_REGS_H_
13 
14 extern enum ralink_soc_type ralink_soc;
15 
soc_is_rt3050(void)16 static inline int soc_is_rt3050(void)
17 {
18 	return ralink_soc == RT305X_SOC_RT3050;
19 }
20 
soc_is_rt3052(void)21 static inline int soc_is_rt3052(void)
22 {
23 	return ralink_soc == RT305X_SOC_RT3052;
24 }
25 
soc_is_rt305x(void)26 static inline int soc_is_rt305x(void)
27 {
28 	return soc_is_rt3050() || soc_is_rt3052();
29 }
30 
soc_is_rt3350(void)31 static inline int soc_is_rt3350(void)
32 {
33 	return ralink_soc == RT305X_SOC_RT3350;
34 }
35 
soc_is_rt3352(void)36 static inline int soc_is_rt3352(void)
37 {
38 	return ralink_soc == RT305X_SOC_RT3352;
39 }
40 
soc_is_rt5350(void)41 static inline int soc_is_rt5350(void)
42 {
43 	return ralink_soc == RT305X_SOC_RT5350;
44 }
45 
46 #define IOMEM(x)			((void __iomem *)(KSEG1ADDR(x)))
47 #define RT305X_SYSC_BASE		IOMEM(0x10000000)
48 
49 #define SYSC_REG_CHIP_NAME0		0x00
50 #define SYSC_REG_CHIP_NAME1		0x04
51 #define SYSC_REG_CHIP_ID		0x0c
52 #define SYSC_REG_SYSTEM_CONFIG		0x10
53 
54 #define RT3052_CHIP_NAME0		0x30335452
55 #define RT3052_CHIP_NAME1		0x20203235
56 
57 #define RT3350_CHIP_NAME0		0x33335452
58 #define RT3350_CHIP_NAME1		0x20203035
59 
60 #define RT3352_CHIP_NAME0		0x33335452
61 #define RT3352_CHIP_NAME1		0x20203235
62 
63 #define RT5350_CHIP_NAME0		0x33355452
64 #define RT5350_CHIP_NAME1		0x20203035
65 
66 #define CHIP_ID_ID_MASK			0xff
67 #define CHIP_ID_ID_SHIFT		8
68 #define CHIP_ID_REV_MASK		0xff
69 
70 #define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT	2
71 #define RT305X_SYSCFG_SRAM_CS0_MODE_WDT		0x1
72 
73 #define RT5350_SYSCFG0_DRAM_SIZE_SHIFT  12
74 #define RT5350_SYSCFG0_DRAM_SIZE_MASK   7
75 #define RT5350_SYSCFG0_DRAM_SIZE_2M     0
76 #define RT5350_SYSCFG0_DRAM_SIZE_8M     1
77 #define RT5350_SYSCFG0_DRAM_SIZE_16M    2
78 #define RT5350_SYSCFG0_DRAM_SIZE_32M    3
79 #define RT5350_SYSCFG0_DRAM_SIZE_64M    4
80 
81 /* multi function gpio pins */
82 #define RT305X_GPIO_I2C_SD		1
83 #define RT305X_GPIO_I2C_SCLK		2
84 #define RT305X_GPIO_SPI_EN		3
85 #define RT305X_GPIO_SPI_CLK		4
86 /* GPIO 7-14 is shared between UART0, PCM  and I2S interfaces */
87 #define RT305X_GPIO_7			7
88 #define RT305X_GPIO_10			10
89 #define RT305X_GPIO_14			14
90 #define RT305X_GPIO_UART1_TXD		15
91 #define RT305X_GPIO_UART1_RXD		16
92 #define RT305X_GPIO_JTAG_TDO		17
93 #define RT305X_GPIO_JTAG_TDI		18
94 #define RT305X_GPIO_MDIO_MDC		22
95 #define RT305X_GPIO_MDIO_MDIO		23
96 #define RT305X_GPIO_SDRAM_MD16		24
97 #define RT305X_GPIO_SDRAM_MD31		39
98 #define RT305X_GPIO_GE0_TXD0		40
99 #define RT305X_GPIO_GE0_RXCLK		51
100 
101 #define RT3352_SYSC_REG_SYSCFG0		0x010
102 #define RT3352_SYSC_REG_SYSCFG1         0x014
103 #define RT3352_SYSC_REG_RSTCTRL         0x034
104 #define RT3352_SYSC_REG_USB_PS          0x05c
105 
106 #define RT3352_RSTCTRL_UHST		BIT(22)
107 #define RT3352_RSTCTRL_UDEV		BIT(25)
108 #define RT3352_SYSCFG1_USB0_HOST_MODE	BIT(10)
109 
110 #define RT305X_SDRAM_BASE		0x00000000
111 #define RT305X_MEM_SIZE_MIN		2
112 #define RT305X_MEM_SIZE_MAX		64
113 #define RT3352_MEM_SIZE_MIN		2
114 #define RT3352_MEM_SIZE_MAX		256
115 
116 #endif
117